ALC882 Series

7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC

DATASHEET

Rev. 1.5
04 October 2005
Track ID: JATR-1076-21
 ALC882 Series
Datasheet

COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.

TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek
ALC882 Series Audio Codec ICs.

Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY
Revision Release Date Summary
1.0 2005/01/27 First release.
1.1 2005/03/25 Change to package/version ID (see page 6).
Change to .Ordering Information, page 73.
1.2 2005/05/24 Add Port Information to pin assignments figure (see Figure 3, page 6).
Expand section 10 Application Notes, page 67.
Add ALC882DTS-LF version (see Ordering Information, page 73).
1.3 2005/08/04 Delete ‘DVD Contents protection’ in ‘General Description’, page 1.
1.4 2005/09/01 Update ordering information (see Table 80, on page 73).
1.5 2005/10/04 Update Table 75, page 62.

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Table of Contents
1. General Description .................................................................................................... 1

2. Features ........................................................................................................................ 2
2.1. HARDWARE FEATURES .....................................................................................................................2
2.2. SOFTWARE FEATURES ......................................................................................................................3

3. System Applications .................................................................................................... 3

4. Block Diagram ............................................................................................................. 4

4.1. ANALOG INPUT/OUTPUT UNIT .........................................................................................................5

5. Pin Assignments........................................................................................................... 6
5.1. LEAD (PB)-FREE PACKAGE AND VERSION IDENTIFICATION .............................................................6

6. Pin Descriptions........................................................................................................... 7
6.1. DIGITAL I/O PINS .............................................................................................................................7
6.2. ANALOG I/O PINS .............................................................................................................................7
6.3. FILTER/REFERENCE ..........................................................................................................................8
6.4. POWER/GROUND ..............................................................................................................................8

7. High Definition Audio Link Protocol ........................................................................ 9

7.1. LINK SIGNALS ..................................................................................................................................9
7.1.1. Signal Definitions .................................................................................................................................................10
7.1.2. Signaling Topology ............................................................................................................................................... 11
7.2. FRAME COMPOSITION.....................................................................................................................12
7.2.1. Outbound Frame – Single SDO............................................................................................................................12
7.2.2. Outbound Frame – Multiple SDO ........................................................................................................................13
7.2.3. Inbound Frame – Single SDI ................................................................................................................................14
7.2.4. Inbound Frame – Multiple SDI ............................................................................................................................15
7.2.5. Variable Sample Rates..........................................................................................................................................15
7.3. RESET AND INITIALIZATION............................................................................................................18
7.3.1. Link Reset .............................................................................................................................................................18
7.3.2. Codec Reset ..........................................................................................................................................................19
7.3.3. Codec Initialization Sequence ..............................................................................................................................20

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7.4. VERB AND RESPONSE FORMAT .......................................................................................................20

7.4.1. Command Verb Format ........................................................................................................................................20
7.4.2. Response Format..................................................................................................................................................21
7.5. POWER MANAGEMENT ...................................................................................................................21

8. Supported Verbs and Parameters............................................................................ 23

8.1. VERB – GET PARAMETERS (VERB ID=F00H) .................................................................................23
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................23
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................23
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................24
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ...........................................................24
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................25
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................25
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................26
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................27
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................28
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................29
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................29
8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................30
8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................30
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) .......................................................30
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ...............................................................31
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...................................................31
8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................32
8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .....................................................................32
8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................33
8.5. VERB – GET PROCESSING STATE (VERB ID=F03H)........................................................................37
8.6. VERB – SET PROCESSING STATE (VERB ID=703H) ........................................................................37
8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................38
8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H)............................................................................38
8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH).................................................................39
8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H) ..................................................................39
8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................40
8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H).................................................................................42
8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH)........................................................................43
8.14. VERB – SET CONVERTER FORMAT (VERB ID=2H) .........................................................................44
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8.15. VERB – GET POWER STATE (VERB ID=F05H)................................................................................45

8.16. VERB – SET POWER STATE (VERB ID=705H).................................................................................46
8.17. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................46
8.18. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................47
8.19. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................47
8.20. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................48
8.21. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................49
8.22. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................49
8.23. VERB – GET PIN SENSE (VERB ID=F09H) ......................................................................................50
8.24. VERB – EXECUTE PIN SENSE (VERB ID=709H) ..............................................................................50
8.25. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ...........................................................51
8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
BYTES 0, 1, 2, 3).............................................................................................................................51
8.27. VERB – GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................52
8.28. VERB – SET BEEP GENERATOR (VERB ID=70AH) ........................................................................52
8.29. VERB – GET GPIO DATA (VERB ID= F15H) ..................................................................................53
8.30. VERB – SET GPIO DATA (VERB ID= 715H) ...................................................................................53
8.31. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).....................................................................54
8.32. VERB – SET GPIO ENABLE MASK (VERB ID=716H)......................................................................54
8.33. VERB – GET GPIO DIRECTION (VERB ID=F17H)...........................................................................55
8.34. VERB – SET GPIO DIRECTION (VERB ID=717H)............................................................................55
8.35. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ...........................56
8.36. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ............................56
8.37. VERB – FUNCTION RESET (VERB ID=7FFH) ..................................................................................57
8.38. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) ..............57
8.39. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................59
8.40. GET/SET VOLUME KNOB WIDGET (NID=21H) (VERB ID= F0FH/70FH)......................................60

9. Electrical Characteristics ......................................................................................... 61

9.1. DC CHARACTERISTICS ...................................................................................................................61
9.1.1. Absolute Maximum Ratings ..................................................................................................................................61
9.1.2. Threshold Voltage .................................................................................................................................................61
9.1.3. Digital Filter Characteristics ...............................................................................................................................62
9.1.4. S/PDIF Input/Output Characteristics...................................................................................................................62
9.2. AC CHARACTERISTICS ...................................................................................................................63
9.2.1. Link Reset and Initialization Timing.....................................................................................................................63

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9.2.2. Link Timing Parameters at the Codec ..................................................................................................................64

9.2.3. S/PDIF Output and Input Timing .........................................................................................................................65
9.2.4. Test Mode..............................................................................................................................................................65
9.3. ANALOG PERFORMANCE ................................................................................................................66

10. Application Notes ...................................................................................................... 67

10.1. STANDARD APPLICATION CIRCUIT .................................................................................................67
10.2. VOLUME CONTROL BY EXTERNAL VARIABLE RESISTOR................................................................70
10.3. VOLUME CONTROL BY GPIO0/GPIO1...........................................................................................70

11. Mechanical Dimensions ............................................................................................ 71

11.1. MECHANICAL DIMENSIONS NOTES.................................................................................................72

12. Ordering Information ............................................................................................... 73

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List of Tables
Table 1. Digital I/O Pins ...........................................................................................................................7
Table 2. Analog I/O Pins...........................................................................................................................7
Table 3. Filter/Reference...........................................................................................................................8
Table 4. Power/Ground .............................................................................................................................8
Table 5. Link Signal Definitions.............................................................................................................10
Table 6. HDA Signal Definitions............................................................................................................10
Table 7. Defined Sample Rate and Transmission Rate...........................................................................16
Table 8. 48kHz Variable Rate of Delivery Timing .................................................................................16
Table 9. 44.1kHz Variable Rate of Delivery Timing ..............................................................................17
Table 10. 40-Bit Commands in 4-Bit Verb Format...................................................................................20
Table 11. 40-Bit Commands in 12-Bit Verb Format.................................................................................20
Table 12. Solicited Response Format .......................................................................................................21
Table 13. Unsolicited Response Format ...................................................................................................21
Table 14. System Power State Definitions ...............................................................................................21
Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h ..................................................................22
Table 16. Powered Down Conditions .......................................................................................................22
Table 17. Verb – Get Parameters (Verb ID=F00h) ...................................................................................23
Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) ...................................................23
Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................23
Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................24
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................24
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................25
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................25
Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................26
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................27
Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................28
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....29
Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...29
Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................30
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................30
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..............................30
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ......................................31
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) .........................31

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Table 34. Verb – Get Connection Select Control (Verb ID=F01h)...........................................................32

Table 35. Verb – Set Connection Select (Verb ID=701h) .........................................................................32
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)..................................................................33
Table 37. Verb – Get Processing State (Verb ID=F03h) ...........................................................................37
Table 38. Verb – Set Processing State (Verb ID=703h)............................................................................37
Table 39. Verb – Get Coefficient Index (Verb ID=Dh).............................................................................38
Table 40. Verb – Set Coefficient Index (Verb ID=5h) ..............................................................................38
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch).....................................................................39
Table 42. Verb – Set Processing Coefficient (Verb ID=4h)......................................................................39
Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) ................................................................................40
Table 44. Verb – Set Amplifier Gain (Verb ID=3h)..................................................................................42
Table 45. Verb – Get Converter Format (Verb ID=Ah) ............................................................................43
Table 46. Verb – Set Converter Format (Verb ID=2h)..............................................................................44
Table 47. Verb – Get Power State (Verb ID=F05h) ..................................................................................45
Table 48. Verb – Set Power State (Verb ID=705h) ...................................................................................46
Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h)...........................................................47
Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) ......................................................................47
Table 51. Verb – Set Pin Widget Control (Verb ID=707h) .......................................................................48
Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h) .....................................................49
Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) ......................................................49
Table 54. Verb – Get Pin Sense (Verb ID=F09h)......................................................................................50
Table 55. Verb – Execute Pin Sense (Verb ID=709h)...............................................................................50
Table 56. Verb – Get Configuration Default (Verb ID=F1Ch) .................................................................51
Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) ............................................................51
Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah).........................................................................52
Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah)..........................................................................52
Table 60. Verb – Get GPIO Data (Verb ID= F15h) ..................................................................................53
Table 61. Verb – Set GPIO Data (Verb ID= 715h) ...................................................................................53
Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h) .....................................................................54
Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h).......................................................................54
Table 64. Verb – Get GPIO Direction (Verb ID=F17h)............................................................................55
Table 65. Verb – Set GPIO Direction (Verb ID=717h).............................................................................55
Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) ..................................56
Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) ...................................56

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Table 68. Verb – Function Reset (Verb ID=7FFh)....................................................................................57

Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh) ........................57
Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................59
Table 71. Get/Set Volume Knob Widget (NID=21h) (Verb ID= F0Fh/70Fh) ..........................................60
Table 72. Absolute Maximum Ratings .....................................................................................................61
Table 73. Threshold Voltage .....................................................................................................................61
Table 74. Digital Filter Characteristics .....................................................................................................62
Table 75. S/PDIF Input/Output Characteristics ........................................................................................62
Table 76. Link Reset and Initialization Timing ........................................................................................63
Table 77. Link Timing Parameters at the Codec.......................................................................................64
Table 78. S/PDIF Output and Input Timing..............................................................................................65
Table 79. Analog Performance .................................................................................................................66
Table 80. Ordering Information ................................................................................................................73

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List of Figures
Figure 1. Block Diagram ..........................................................................................................................4
Figure 2. Analog Input/Output Unit .........................................................................................................5
Figure 3. Pin Assignments ........................................................................................................................6
Figure 4. HDA Link Protocol ...................................................................................................................9
Figure 5. Bit Timing ...............................................................................................................................10
Figure 6. Signaling Topology .................................................................................................................11
Figure 7. SDO Outbound Frame.............................................................................................................12
Figure 8. SDO Stream Tag is Indicated in SYNC ..................................................................................12
Figure 9. Stripped Stream on Multiple SDO ..........................................................................................13
Figure 10. SDI Inbound Stream................................................................................................................14
Figure 11. SDI Stream Tag and Data ........................................................................................................14
Figure 12. Codec Transmits Data Over Multiple SDI ..............................................................................15
Figure 13. Link Reset Timing...................................................................................................................19
Figure 14. Codec Initialization Sequence.................................................................................................20
Figure 15. Link Reset and Initialization Timing.......................................................................................63
Figure 16. Link Signals Timing ................................................................................................................64
Figure 17. Output and Input Timing .........................................................................................................65
Figure 18. Filter Connection.....................................................................................................................67
Figure 19. IO Connection .........................................................................................................................68
Figure 20. On board Front Panel Header & Front I/O Module Connection.............................................69
Figure 21. Volume Control by External Variable Resistor .......................................................................70
Figure 22. Volume Control by GPIO0 and GPIO1...................................................................................70

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1. General Description
The ALC882 series* 7.1+2 Channel High Definition Audio codecs with UAA (Universal Audio
Architecture), featuring five 24-bit stereo DACs and three 20-bit stereo ADCs, are designed for high
performance multimedia PC systems. The ALC882 series incorporates proprietary converter technology
to achieve over 100dB Signal-to-Noise ratio playback quality; easily meeting PC2001 requirements and
also bringing PC sound quality closer to consumer electronic devices.

The ALC882 series provides 10 channels of DAC that simultaneously support 7.1 sound playback, plus 2
channels of independent stereo sound output (multiple streaming) through the Front-Out-Left and
Front-Out-Right channels. Flexible mixing, mute, and fine gain control functions provide a complete
integrated audio solution for next generation multimedia PCs.

The DACs (with a highest sampling frequency of 192kHz) are applicable for DVD-Audio, previously
only implemented in high-end consumer electronics, and now achieved by PCs with the ALC882 series
inside. The ALC882 series also integrate three stereo ADCs that can support a microphone array with
Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology
simultaneously, significantly improving recording quality for conference calls. With this feature (3 stereo
ADCs), the ALC882 series can provide high-quality audio using S/PDIF to output analog data, or for
multiple-source recording applications.

All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog
output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched
depending on the connected device type.

The ALC882 series supports 16/20/24/32-bit S/PDIF input and output functions for both consumer mode
and professional mode, offering easy connection of PCs to high quality consumer electronic products such
as AC-3 decoders/speakers, and mini disk devices.

The ALC882 series supports host/soft audio from the Intel ICH6/ICH7 chipset, and also from any other
HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent
software utilities such as Karaoke mode, environment emulation, software equalizer, HRTF 3D positional
audio, optional DTS Connect™, and optional Dolby® Digital Live, Home Theatre, and Master Studio
programs, the ALC882 series provides an excellent entertainment package and game experience for PC
users.
*Note: The ALC882 series covers all products listed in section 12 Ordering Information, page 73.

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2. Features
2.1. Hardware Features
„ High-performance DACs with 103dB SNR are ideal for Dolby® Master Studio
„ ADCs with 90dBA SNR
„ Meets performance requirements for audio on PC2001 systems
„ 10 DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels of
independent stereo sound output (multiple streaming) through the Front-Out-Left and
Front-Out-Right channels
„ 3 stereo ADCs support 16/20-bit PCM format, two for microphone array, one for legacy mixer
recording
„ All DACs supports 44.1K/48K/96K/192kHz sample rate
„ All ADCs support 44.1K/48K/96K sample rate
„ Applicable for DVD-Audio solutions
„ 16/20/24-bit S/PDIF-OUT supports 44.1K/48K/96/192kHz sample rate
„ 16/20/24-bit S/PDIF-IN supports 44.1K/48K/96/192kHz sample rate
„ Up to four channels of microphone input are supported for AEC/BF application
„ High-quality analog differential CD input
„ Supports external PCBEEP input and built-in digital BEEP generator
„ Software selectable 2.5V/3.75V VREFOUT
„ Six VREFOUTs are supported by default, with additional four VREFOUTs available by sharing
unused analog I/O pins
„ Two jack detection pins each designed to detect up to 4 jacks
„ Reserve analog mixer architecture for backward compatibility with AC'97
„ Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain
„ All analog jacks are stereo input and output re-tasking for analog plug & play
„ Built-in headphone amplifiers for each re-tasking jack
„ Supports both analog DC volume control and GPI digital volume control
„ 2 GPIOs (General Purpose Input/Output) for customized applications
„ Optional EAPD (External Amplifier Power Down) is supported
„ Power support: Digital: 3.3V; Analog: 5.0V (Minimum AVDD is 3.6V)
„ Power management and enhanced power saving features
„ 48-pin LQFP lead (Pb)-free package

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2.2. Software Features

„ Meets Microsoft WHQL/WLP 2.0 audio requirements
„ EAX™ 1.0 & 2.0 compatible
„ Direct Sound 3D™ compatible
„ A3D™ compatible
„ I3DL2 compatible
„ HRTF 3D Positional Audio
„ Emulation of 26 sound environments to enhance gaming experience
„ 10 Software Equalizer Bands
„ Voice Cancellation and Key Shifting in Karaoke mode
„ Realtek Media Player
„ Enhanced Configuration Panel and device sensing wizard to improve user experience
„ Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS) and Beam Forming (BF)
technology for voice application
„ ALC882D features Dolby® Digital Live output for consumer equipment
„ ALC882H features Dolby® Home Theater software
„ ALC882M features Dolby® Master Studio software
„ ALC882DTS features DTS® Connect™ software

3. System Applications
„ Multimedia PCs
„ 3D PC games
„ Information appliances (IA)
„ Voice recognition
„ Audio conferencing

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 4.
25h 26h
Front
PCM-5 SRC DAC M VOL Fout Surr
CLfe
M SideSurr 17h
Fout
05h 0Fh M I/O SIDESURR(Port-H)
Boost
PCM-4 SRC DAC M VOL SideSurr
M Front
Surr
CLfe
04h 0Eh SideSurr 16h
SRC DAC M CLfe Fout
PCM-3 VOL M
Boost
I/O CEN/LFE(Port-G)
M
03h 0Dh Front
Surr
PCM-2 SRC DAC M VOL Surr CLfe
SideSurr 15h
M Fout
M I/O SURR(Port-A)
02h 0Ch Boost
PCM-1 SRC DAC M VOL Front Front
Surr
M
Block Diagram

CLfe
SideSurr 14h
Fout
VOL M M

7.1+2 Channel High Definition Audio Codec

Boost
I/O FRONT(Port-D)
VOL M
VOL M
Digital Interface 0Bh
VOL M BEEP Gen BEEP-IN 1Dh
VOL M
VOL M

Figure 1.
1 VOL M CD-IN 1Ch
VOL M Front
Surr
VOL M CLfe
SideSurr

4
Parameters Fout
1Bh
VOL M M
Boost
I/O LINE2(Port-E)
M
M Front
09h M Surr
M CLfe
M SideSurr 1Ah
SRC ADC VOL M M 22h Fout
M M
M I/O LINE1(Port-C)
M Boost
M
M
Front
M Surr
M CLfe

Block Diagram
M SideSurr 19h
08h M Fout
M M I/O
SRC ADC VOL M M Boost MIC2(Port-F)
M
M 23h
M Front
M Surr
M CLfe
SideSurr 18h
M Fout
M M
M I/O MIC1(Port-B)
07h M Boost
M
SRC ADC VOL M M
M
M
M 24h
M
M

06h
S/PDIF-OUT
S/PDIF-OUT 1Eh
0Ah
S/PDIF-IN S/PDIF-IN 1Fh

Volume Up/Down

Track ID: JATR-1076-21

Knob Mute 21h
Datasheet

Rev. 1.5
ALC882 Series
 ALC882 Series
Datasheet

4.1. Analog Input/Output Unit

Pin Complex widgets NID=14h~1Bh are re-tasking IO.

A Left
R
R
EN_OBUF EN_AMP Right
Output_Signal_Left
Output_Signal_Right EN_OBUF

Input_Signal_Left
Input_Signal_Right EN_IBUF

Figure 2. Analog Input/Output Unit

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 ALC882 Series
Datasheet

5. Pin Assignments

36 35 34 33 32 31 30 29 28 27 26 25
PIN37-VREFO-R 37 24 LINE1-R (PORT-C-R)
AVDD2 38 23 LINE1-L (PORT-C-L)
(PORT-A-L) SURR-OUT-L 39 22 MIC1-R (PORT-B-R)
JDREF 40 21 MIC1-L (PORT-B-L)
(PORT-A-R) SURR-OUT-R 41 20 CD-R
AVSS2 ALC882 Series 19
42 CD-GND
(PORT-G-L) CEN-OUT 43 18 CD-L
(PORT-G-R) LFE-OUT 44 17 MIC2-R (PORT-F-R)
(PORT-H-L) SIDESURR-OUT-L 45 LLLLLLL TXXXVV 16 MIC2-L (PORT-F-L)
(PORT-H-R) SIDESURR-OUT-R 46 15 LINE2-R (PORT-E-R)
SPDIFI/EAPD 47 14 LINE2-L (PORT-E-L)
SPDIFO 48 13 Sense A (JD1)
1 2 3 4 5 6 7 8 9 10 11 12 2
0

Figure 3. Pin Assignments

5.1. Lead (Pb)-Free Package and Version Identification

Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 3. The version number
is shown in the location marked ‘VV’.

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Datasheet

6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Name Type Pin No. Description Characteristic Definition
RESET# I 11 H/W reset TTL input, VIL=1.0V, VIH=2.0V
SYNC I 10 Sample Sync (48kHz) Schmitt trigger input, VIL=1.0V, VIH=2.0V
BITCLK I 6 24MHz Bit clock input Schmitt trigger input, VIL=1.0V, VIH=2.0V
SDATA-OUT I 5 Serial TDM data input TTL input, VIL=1.0V, VIH=2.0V
SDATA-IN O 8 Serial TDM data output TTL output, VOH=0.9*DVDD, VOL=0.1*DVDD
SPDIFI / I/O 47 S/PDIF Input / Schmitt input (VIL=1.45V, VIH=1.85V) /
EAPD Signal to power down ext. amp TTL output
SPDIFO O 48 S/PDIF output TTL output has 12mA@75Ω driving capability.
GPIO0 I/O 2 General Purpose Input/Output 0 Schmitt input/output, VIL=1.45V, VIH=1.85V
GPIO1 I/O 3 General Purpose Input/Output 1 Schmitt input/output, VIL=1.45V, VIH=1.85V
Total: 9 Pins

6.2. Analog I/O Pins

Table 2. Analog I/O Pins
Name Type Pin No. Description Characteristic Definition
LINE2-L IO 14 2nd line input left channel Analog input/output, default is input (JACK-E)
nd
LINE2-R IO 15 2 line input right channel Analog input/output, default is input (JACK -E)
MIC2-L IO 16 2nd stereo microphone input Analog input/output, default is input (JACK -F)
left channel
MIC2-R IO 17 2nd stereo microphone input Analog input/output, default is input (JACK -F)
right channel
CD-L I 18 CD input left channel Analog input, 1.6Vrms of full scale input
CD-G I 19 CD input reference ground Analog input, 1.6Vrms of full scale input
CD-R I 20 CD input right channel Analog input, 1.6Vrms of full scale input
st
MIC1-L IO 21 1 stereo microphone input Analog input/output, default is input (JACK -B)
left channel
MIC1-R IO 22 1st stereo microphone input Analog input/output, default is input (JACK -B)
right channel
LINE1-L IO 23 1st line input left channel Analog input/output, default is input (JACK -C)
st
LINE1-R IO 24 1 line input right channel Analog input/output, default is input (JACK -C)
PCBEEP I 12 External PCBEEP input Analog input, 1.6Vrms of full scale input
FRONT- IO 35 Front output left channel Analog output (JACK -D)
OUT-L
FRONT- IO 36 Front output right channel Analog output (JACK -D)
OUT-R
SURR-OUT-L IO 39 Surround out left channel Analog output (JACK -A)
SURR-OUT-R IO 41 Surround out right channel Analog output (JACK -A)

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Name Type Pin No. Description Characteristic Definition
CEN-OUT O 43 Center output Analog output (JACK -G)
LFE-OUT O 44 Low Frequency output Analog output (JACK -G)
SIDESURR- O 45 Side Surround output left Analog output (JACK -H)
OUT-L channel
SIDESURR- O 46 Side Surround output right Analog output (JACK -H)
OUT-R channel
Sense A I 13 Jack Detect pin l Jack resistor network input 1
Sense B I 34 Jack Detect pin 2 Jack resistor network input 2
DCVOL I 33 DC sense for volume Analog DC input for external volume control
control
Total: 23 Pins

6.3. Filter/Reference
Table 3. Filter/Reference
Name Type Pin No. Description Characteristic Definition
VREF - 27 2.5V Reference voltage 10uf capacitor to analog ground
MIC1-VREFO-L O 28 Bias voltage for MIC1 jack 2.5V/3.75Vreference voltage
LINE1-VREFO O 29 Bias voltage for LINE1 jack 2.5V/3.75Vreference voltage
MIC2-VREFO O 30 Bias voltage for MIC2 jack 2.5V/3.75Vreference voltage
LINE2-VREFO O 31 Bias voltage for LINE2 jack 2.5V/3.75Vreference voltage
MIC1-VREFO-R O 32 Bias voltage for MIC1 jack or 2.5V/3.75Vreference voltage
(PIN32-VREFO) software select specific jack
LINE1-VREFO-R O 37 Bias voltage for LINE1 jack or 2.5V/3.75Vreference voltage
(PIN37-VREFO) software select specific jack
JDREF - 40 Reference resistor for Jack 20K, 1% external resistor to analog ground
detection
Total: 8 Pins

6.4. Power/Ground
Table 4. Power/Ground
Name Type Pin No Description Characteristic Definition
AVDD1 I 25 Analog VDD (5V or 3.3V) Analog power for mixer and amplifier
AVSS1 I 26 Analog GND Analog ground for mixer and amplifier
AVDD2 I 38 Analog VDD (5V or 3.3V) Analog power for DACs and ADCs
AVSS2 I 42 Analog GND Analog ground for DACs and ADCs
DVDD1 I 1 Digital VDD (3.3V) Digital power
DVSS1 I 4 Digital GND Digital ground
DVDD2 I 9 Digital VDD (3.3V) Digital power
DVSS2 I 7 Digital GND Digital ground
Total: 8 Pins

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Datasheet

7. High Definition Audio Link Protocol

7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.

Previous Frame Tframe_sync = 20.833 µs (48KHz)

Next Frame

BCLK

Frame SYNC= 8 BCLK Stream 'A' Tag Stream 'B' Tag

(Here 'A' = 5) (Here 'B' = 6)
SYNC

SDO Command Stream Stream 'A' Data Stream 'B' Data

(40-bit data)

SDI Stream
Response Stream 'C' Tag Stream 'C' Data
(36-bit data) (n bytes + 10-bit data)

RST#

Figure 4. HDA Link Protocol

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Datasheet

7.1.1. Signal Definitions

Table 5. Link Signal Definitions
Item Description
BCLK 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.
SYNC 48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported.
SDI Serial data input signal driven by the codec. It is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST# Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.

Table 6. HDA Signal Definitions

Signal Name Source Controller Type Description
BCLK Controller Output Global 24.0MHz bit clock
SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal
SDO Controller Output Serial data output from controller
SDI Codec/Controller Input/Output Serial data input from codec. Weakly pulled down by the
controller
RST# Controller Output Global active low reset signal

BCLK

SYNC 8-Bit Frame SYNC

Start of Frame

SDO 7 6 5 4 3 2 1 0 999 998 997 996 995 994 993 992 991 990

SDI 3 2 1 0 499 498 497 496 495 494

Codec samples SDO at both rising and falling edge of BCLK

Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing

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7.1.2. Signaling Topology

The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.

Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 12 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.

The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC882
series is designed to receive a single SDO stream.

SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA SDI1
Controller SDI0
SDO1
SDO0
SYNC
BCLK
RST#
SYNC

SYNC

SYNC

SYNC
SDO0

SDO0
SDO1

SDO0
BCLK

SDO0
SDO1
RST#
BCLK

BCLK

BCLK
S DI0

SDI0
RST#
SDI0

SDI0
SDI1

SDI1
SDI2
RST#

RST#

...
Codec 0 Codec 1 Codec 2 Codec N

Single SDO Two SDOs Single SDO Two SDOs

Single SDI Single SDI Two SDIs Multiple SDIs
Figure 6. Signaling Topology

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7.2. Frame Composition

7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-Bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry
96kHz samples (Figure 7).

For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-Bit preamble and 4-Bit stream ID (Figure 8).

To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.

Previous Frame
A 48kHz Frame is composed of Command stream and multiple Data streams Next Frame

Frame SYNC Stream 'A' Tag Stream 'X' Tag

SYNC (Here 'A' = 5) (Here 'X' = 6)

SDO Command Stream Stream 'A' Data Stream 'X' Data 0s

Null Field Padded at the

Sample Block(s) One or multiple blocks in a stream end of Frame

.. For 48kHz rate, only Block1 is included

Block 1 Block 2 Block Y For 96kHz rate, Block1 includes (N)th time of samples, Block2
.
includes (N+1)th time of samples
..
Sample 1 Sample 2 Sample Z Z channels of PCM Sample
.

msb ... lsb msb first in a sample

Figure 7. SDO Outbound Frame

BCLK
Stream Tag
msb lsb
SYNC 1010

Preamble Stream=10 Data of Stream 10

(4-Bit) (4-Bit)
ms b

SDO 7 6 5 4 3 2 1 0

Previous Stream

Figure 8. SDO Stream Tag is Indicated in SYNC

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7.2.2. Outbound Frame – Multiple SDO

The HDA controller allows two SDO signals to be used to strip outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Strip Control’ bit in the controller’s Output Stream Control Register to initiate a
specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.

SDO1 is for transmitting a stripped stream. The codec does not support multiple SDOs connected to
SDO0.

To guarantee all codecs can determine their corresponding stream, the command stream is not stripped. It
is always transmitted on SDO0, and copied on SDO1.

Stream 'A' Tag Stream 'X' Tag Stream 'Y' Tag

SYNC

Frame SYNC
Stream 'A' to Codec A
SDO0 Command Stream ... Stream 'X' to Codec X Stream 'Y' to Codec Y

Dn Dn-2

SDO1 Command Stream ... 0s 0s

D Dn-3 . . .
n-1
Stream A is "bit-stripped" on SDO0 and SDO1

Command Stream is unchanged, not stripped

Figure 9. Stripped Stream on Multiple SDO

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7.2.3. Inbound Frame – Single SDI

An Inbound Frame – Single SDI is composed of one 36-Bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10).

The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-Bit stream tag, one 6-Bit data length, and n-Bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 11).

Previous Frame A 48kHz Frame is Composed of a Response Stream and Multiple Data streams Next Frame

Frame SYNC

SYNC

SDI Response Stream Stream 'A' Stream 'X' 0s

Null Field Padded at the end of Frame

Stream Tag Sample Block(s)

For 48kHz rate, only Block1 is included

Block 1 Block 2 ... Block Y Null Pad For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples

Sample 1 Sample 2 ... Sample Z Z channels of PCM Sample

msb ... lsb msb first in a sample

Figure 10. SDI Inbound Stream

BCLK

Stream Tag Data Length in Bytes n-Bit Sample Block Null Pad Next Stream

SDI B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Dn-1 Dn-2 D0 0 0 0 0

(Data Length in Bytes *8)-Bit

A Complete Stream
Figure 11. SDI Stream Tag and Data

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7.2.4. Inbound Frame – Multiple SDI

A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.

SYNC

Frame SYNC
Stream 'A'
SDI 0 Response Stream Tag A Data A Stream 'X' Stream 'Y'

Stream 'B'
SDI 1 Response Stream Tag B Data B 0s 0s

Codec drives SDI0 and SDI1 Stream A, B, X, and Y are independent and have separate IDs

Figure 12. Codec Transmits Data Over Multiple SDI

7.2.5. Variable Sample Rates

The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.

The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 16, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.

Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 16, shows the delivery cadence
of variable rates based on 48kHz.

The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames. The cadence
“12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)”
interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term
frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this
cadence AND interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain
n sample blocks in the non-empty frame AND interleave an empty frame between non-empty
frames (Table 9, page 17).

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Table 7. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base 44.1kHz Base
1/6 8kHz (1 sample block every 6 frames)
1/4 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames)
1/3 16kHz (1 sample block every 3 frames)
1/2 22.05kHz (1 sample block every 2 frames)
2/3 32kHz (2 sample blocks every 3 frames)
1 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame)
2 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame)
4 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)

Table 8. 48kHz Variable Rate of Delivery Timing

Rate Delivery Cadence Description
8kHz YNNNNN (repeat) One sample block is transmitted in every 6 frames
12kHz YNNN (repeat) One sample block is transmitted in every 4 frames
16kHz YNN (repeat) One sample block is transmitted in every 3 frames
32kHz Y2NN (repeat) One sample block is transmitted in every 6 frames
48kHz Y (repeat) One sample block is transmitted in every 6 frames
96kHz Y2 (repeat) Two sample blocks are transmitted in each frame
192kHz Y4 (repeat) Four sample blocks are transmitted in each frame
N: No sample block in a frame
Y: One sample block in a frame
Yx: X sample blocks in a frame

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Table 9. 44.1kHz Variable Rate of Delivery Timing
Rate Delivery Cadence
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)

11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN

{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN

{ - } =NNNN

22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN

{11}=YNYNYNYNYNYNYNYNYNYNYN

{ - }=NN

44.1kHz 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.

88.2kHz 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.

174.4kHz 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.

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7.3. Reset and Initialization

There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (for example, hot docking a codec to an HDA system)

7.3.1. Link Reset

A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 13, page 19, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)

Enter ‘Link Reset’:

n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset

o As the controller completes the current frame, it does not signal the normal 8-Bit frame SYNC at the
end of the frame

p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low

q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state

r All link signals driven by controller and codecs should be tri-state by internal pull low resistors

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Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)

t Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µs provides time for the codec PLL to stabilize)

u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC

v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
Previous Frame 4 BCLK 4 BCLK Link in Reset >=100 usec >= 4 BCLK Initialization Sequence

BCLK

Normal Frame Normal Frame

SYNC SYNC is absent Driven Low Pulled Low SYNC
2 8

SDOs Driven Low Pulled Low

Wake Event
SDIs Driven Low Pulled Low
9

RST# Pulled Low

1 3 4 5 6 7

Figure 13. Link Reset Timing

7.3.2. Codec Reset

A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.

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7.3.3. Codec Initialization Sequence

n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller

o The codec will stop driving the SDI during this turnaround period

pqrs The controller drives SDI to assign a CAD to the codec

t The controller releases the SDI after the CAD has been assigned

u Normal operation state

Exit from Reset Connection Frame Turnaround Frame Address Frame

(Non-48kHz Frame) (Non-48kHz Frame) Normal Operation

BCLK

Frame SYNC Frame SYNC Frame SYNC

SYNC

4 5 6 Response
SDIx
SD0 SD1 SD14
1 2 3 7 8
RST#
Codec Codec Controller Drives SDIx Controller Codec Drives SDIx
Drives SDIx Turnaround Turnaround
(477 BCLK (477 BCLK
Max.) Max.)

Figure 14. Codec Initialization Sequence

7.4. Verb and Response Format

7.4.1. Command Verb Format
There are two types of verbs: one with 4-Bit identifiers (4-Bit verbs) and 16-Bits of data, the other with
12-Bit identifiers (12-Bit verbs) and 8-Bits of data. Table 10 shows the 4-Bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-Bit verb structure that gets and
controls parameters in the codec.

Table 10. 40-Bit Commands in 4-Bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:16] Bit [15:0]
Reserved Codec Address Node ID Verb ID Payload

Table 11. 40-Bit Commands in 12-Bit Verb Format

Bit [39:32] Bit [31:28] Bit [27:20] Bit [19:8] Bit [7:0]
Reserved Codec Address Node ID Verb ID Payload

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7.4.2. Response Format

There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-Bit Response is interpreted by
software, opaque to the controller.

Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.

Table 12. Solicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:0]
Valid Unsol=0 Reserved Response

Table 13. Unsolicited Response Format

Bit [35] Bit [34] Bit [33:32] Bit [31:28] Bit [27:0]
Valid Unsol=1 Reserved Tag Response
Note: The response stream in the link protocol is 36-Bits wide. The response is placed in the lower
32-bit field. Bit-35 is a ‘Valid’ bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that
an unsolicited response was sent.

7.5. Power Management

The ALC882 series does not support Wake-Up events when in low power mode. All power management
state changes in widgets are driven by software. Table 14 shows the System Power State Definitions.

In the ALC882 series, all the widgets, including output/input converters, support power control. Software
may have various power states depending on system configuration. Table 15 indicates those nodes that
support power management. To simplify power control, software can configure whole codec power states
through the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no
individual power control to supply fine-grained power control.

Table 14. System Power State Definitions

Power States Definitions
D0 All power on. Individual DACs and ADCs can be powered up or down as required
D1 All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference
stays up
D2 All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference is off (D1 + analog reference off)
D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained
D3 (Cold) All power removed. State lost

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Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h
Item Description D0 D1 D2 D3 Link Reset
Audio Function LINK Response Normal Normal Normal PD PD
(NID=01h) Front DAC Normal PD PD PD PD
Surr DAC) Normal PD PD PD PD
Cen/Lfe DAC Normal PD PD PD PD
Side DAC Normal PD PD PD PD
Fout DAC Normal PD PD PD PD
MIC ADC Normal PD PD PD PD
LINE ADC Normal PD PD PD PD
MIX ADC Normal PD PD PD PD
All Headphone Drivers Normal Normal PD PD Normal
All Mixers Normal Normal PD PD Normal
All Reference Normal Normal PD PD Normal
Note: PD=Powered Down

Table 16. Powered Down Conditions

Condition Description
LINK Response powered down Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with
pulled low 47K resistors internally. S/PDIF-IN is also floated. Detection of
‘Link Reset Entry’ and ‘Link Reset Exit’ sequences are supported. All
states are maintained if DVDD is supplied
Front DAC powered down Analog block and digital filter are powered down
Surr DAC powered down Analog block and digital filter are powered down
CEN/LFE DAC powered down Analog block and digital filter are powered down
SIDESURR DAC powered down Analog block and digital filter are powered down
Fout DAC powered down Analog block and digital filter are powered down
MIC ADC powered down Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
LINE ADC powered down Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
MIX ADC powered down Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
Headphone Driver powered down All headphone drivers are powered down
Mixers powered down All internal mixer widgets are powered down. The DC reference and
VREFOUTx at individual pin complexes are still alive
Reference power down All internal references, DC reference, and VREFOUTx at individual pin
complexes are off

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8. Supported Verbs and Parameters

This section describes the Verbs and Parameters supported by various widgets in the ALC882 series. If a
verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’.

8.1. Verb – Get Parameters (Verb ID=F00h)

The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget,
some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
page 20, to get detailed information about supported parameters.

Table 17. Verb – Get Parameters (Verb ID=F00h)

Get Parameter Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=00h Verb ID=F00h Parameter ID[7:0] 32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.

8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)

Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit Description
31:16 Vendor ID=10ECh (Realtek’s PCI vendor ID)
15:0 Device ID=0882h
Note: The Root Node (NID=00h) supports this parameter.

8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)

Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit Description
31:24 Reserved. Read as 0’s
23:20 MajRev. The major version number (in decimal) of the HDA Spec to which the ALC882 series is fully
compliant
19:16 MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC882 series is fully
compliant
15:8 Revision ID. The vendor’s revision number.
00h is for the first silicon version, 01h is for the second version, etc.
7:0 Stepping ID. The vendor’s stepping number within the given Revision ID
Note: The Root Node (NID=00h in the ALC882 series) supports this parameter.

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8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h,

Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.

For function group nodes, it provides the total number of widgets associated with this function node.

Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit Description
31:24 Reserved. Read as 0’s
23:16 Starting Node Number
The starting node number in the sequential widgets
15:8 Reserved. Read as 0’s
7:0 Total Number of Nodes
For a root node, the total number of function groups in the root node
For a function group, the total number of widget nodes in the function group

8.1.4. Parameter – Function Group Type (Verb ID=F00h,

Parameter ID=05h)
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit Description
31:8 Reserved. Read as 0’s
7:0 Function Group Type
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
Note: The Audio Function Group (NID=01h) supports this parameter.

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8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h,

Parameter ID=08h)
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit Description
31:17 Reserved. Read as 0’s
16 Beep Generator
A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group
15:12 Reserved. Read as 0’s
11:8 Input Delay
7:4 Reserved. Read as 0’s
3:0 Output Delay
Note: The Audio Function Group (NID=01h) supports this parameter.

8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h,

Parameter ID=09h)
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit Description
31:24 Reserved. Read as 0’s
23:20 Widget Type
0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex
5h: Power Widget 6h: Volume Knob Widget 7h~Eh: Reserved Fh: Vendor defined audio widget
19:16 Delay. Samples delayed between the HDA link and widgets
15:11 Reserved. Read as 0’s
10 Power Control
0: Power state control is not supported on this widget
1: Power state is supported on this widget
9 Digital
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
8 ConnList. Connection List
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
7 UnsolCap. Unsolicited Capable
0: Unsolicited response is not supported
1: Unsolicited response is supported
6 ProcWidget. Processing Widget
0: No processing control
1: Processing control is supported
5 Reserved. Read as 0
4 Format Override
3 AmpParOvr, AMP Param Override

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Codec Response Format
Bit Description
2 OutAmpPre. Out AMP Present
1 InAmpPre. In AMP Present
0 Stereo
0: Mono Widget
1: Stereo Widget

8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h,

Parameter ID=0Ah)
Parameter in audio function provides default information about formats. Individual converters have their
own parameters to provide supported formats if their ‘Format Override’ bit is set.

Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit Description
31:21 Reserved. Read as 0’s
20 B32. 32-Bit audio format support
0: Not supported
1: Supported
19 B24. 24-bit audio format support
0: Not supported
1: Supported
18 B20. 20-bit audio format support
0: Not supported
1: Supported
17 B16. 16-bit audio format support
0: Not supported
1: Supported
16 B8. 24-bit audio format support
0: Not supported
1: Supported
15:12 Reserved. Read as 0’s
11 R12. 384kHz (=8*48kHz) rate support
0: Not supported
1: Supported
10 R11. 192kHz (=4*48kHz) rate support
0: Not supported
1: Supported
9 R10. 176.4kHz (=4*44.1kHz) rate support
0: Not supported
1: Supported
8 R9. 96kHz (=2*48kHz) rate support
0: Not supported
1: Supported

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Codec Response Format
Bit Description
7 R8. 88.2kHz (=2*44.1kHz) rate support
0: Not supported
1: Supported
6 R7. 48kHz rate support
0: Not supported
1: Supported
5 R6. 44.1kHz rate support
0: Not supported
1: Supported
4 R5. 32kHz (=2/3*48kHz) rate support
0: Not supported
1: Supported
3 R4. 22.05kHz (=1/2*44.1kHz) rate support
0: Not supported
1: Supported
2 R3. 16kHz (=1/3*48kHz) rate support
0: Not supported
1: Supported
1 R2. 11.025kHz (=1/4*44.1kHz) rate support
0: Not supported
1: Supported
0 R1. 8kHz (=1/6*48kHz) rate support
0: Not supported
1: Supported

8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h,

Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit Description
31:3 Reserved. Read as 0’s
2 AC3
0: Not supported
1: Supported
1 Float32
0: Not supported
1: Supported
0 PCM
0: Not supported
1: Supported
Note: Input converters and output converters support this parameter.

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8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)

The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.

Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)

Codec Response Format
Bit Description
31:16 Reserved. Read as 0’s
15:8 VREF Control Capability
‘1’ in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of
AVDD.
7:6 5 4 3 2 1 0
Reserved 100% 80% Reserved Ground 50% Hi-Z
7 L-R Swap. Indicates the capability of swapping the left and rights
6 Balanced I/O Pin
‘1’ indicates this pin complex has balanced pins
5 Input Capable
‘1’ indicates this pin complex supports input
4 Output Capable
‘1’ indicates this pin complex supports output
3 Headphone Drive Capable
‘1’ indicates this pin complex has an amplifier to drive a headphone
2 Presence Detect Capable
‘1’ indicates this pin complex can detect whether there is anything plugged in
1 Trigger Required
‘1’ indicates whether a software trigger is required for an impedance measurement
0 Impedance Sense Capable
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type
Note: Only Pin Complex widgets support this parameter.

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8.1.10. Parameter – Amplifier Capabilities

(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.

Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit Description
31 (Input) Mute Capable
30:23 Reserved. Read as 0
22:16 Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
15 Reserved. Read as 0
14:8 Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
7 Reserved. Read as 0
6:0 Offset
Indicates which step is 0dB

8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output

Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.

Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit Description
31 (Output) Mute Capable
30:23 Reserved. Read as 0
22:16 Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
15 Reserved. Read as 0
14:8 Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
7 Reserved. Read as 0
6:0 Offset. Indicates which step is 0dB

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8.1.12. Parameter – Connect List Length (Verb ID=F00h,

Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.

Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit Description
31:8 Reserved. Read as 0
7 Short Form
0: Short Form
1: Long Form
6:0 Connect List Length
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (Not a MUX widget)

8.1.13. Parameter – Supported Power States (Verb ID=F00h,

Parameter ID=0Fh)
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit Description
31:4 Reserved. Read as 0’s
3 D3Sup
1: Power state D3 is supported
2 D2Sup
1: Power state D2 is supported
1 D1Sup
1: Power state D1 is supported
0 D0Sup
1: Power state D0 is supported

8.1.14. Parameter – Processing Capabilities (Verb ID=F00h,

Parameter ID=10h)
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit Description
31:16 Reserved. Read as 0’s
15:8 NumCoeff. Number of Coefficient
7:1 Reserved. Read as 0’s
0 Benign
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant

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8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h,

Parameter ID=11h)
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit Description
31 GPIWake=0
The ALC882 series does not support GPIO wake up function
30 GPIUnsol=1
The ALC882 series supports GPIO unsolicited response
29:24 Reserved. Read as 0’s
23:16 NumGPIs=00h
No GPI pin is supported
15:8 NumGPOs=00h
No GPO pin is supported
7:0 NumGPIOs=02h
Two GPIO pins are supported

8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h,

Parameter ID=13h)
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit Description
31:8 Reserved. Read as 0’s
7 Delta
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
6:0 NumSteps
The number of steps in the range of the Volume Control Knob

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8.2. Verb – Get Connection Select Control (Verb ID=F01h)

Table 34. Verb – Get Connection Select Control (Verb ID=F01h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F01h 0’s Bit[7:0] are Connection Index

Codec Response for Analog Port-A/B/C/D/E/F/G/H

Bit Description
31:8 0’s
7:0 Connection Index currently Set (Default value is 00h)
00h: Sum Widget NID=0Ch
01h: Sum Widget NID=0Dh
02h: Sum Widget NID=0Eh
03h: Sum Widget NID=0Fh
04h: Sum Widget NID=26h
Other: Reserved

Codec Response for Digital Pin S/PDIF-OUT

Bit Description
31:8 0’s
7:0 Connection Index currently Set (Default value is 00h)
00h: Digital Converter (S/PDIF-OUT)
01h: Pin Widget (S/PDIF-IN)
Other: Reserved

Codec Response for other NID

Bit Description
31:0 Not supported (returns 00000000h)

8.3. Verb – Set Connection Select (Verb ID=701h)

Table 35. Verb – Set Connection Select (Verb ID=701h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=701h Select Index [7:0] 0’s for all nodes

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8.4. Verb – Get Connection List Entry (Verb ID=F02h)

Table 36. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F02h Offset Index - N[7:0] 32-bit Response

Codec Response for NID=07h (MIC ADC)

Bit Description
31:8 Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0 Connection List Entry (N)
Returns 24h (Sum Widget) for N=0~3
Returns 00h for N>3

Codec Response for NID=08h (LINE ADC)

Bit Description
31:8 Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0 Connection List Entry (N)
Returns 23h (Sum Widget) for N=0~3
Returns 00h for N>3

Codec Response for NID=09h (MIX ADC)

Bit Description
15:8 Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0 Connection List Entry (N)
Returns 22h (Sum Widget) for N=0~3
Returns 00h for N>3

Codec Response for NID=0Ah (S/PDIF-IN Converter)

Bit Description
31:8 Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0 Connection List Entry (N)
Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3
Returns 00h for N>3

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Codec Response for NID=0Bh (Mixer)
Bit Description
31:24 Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
23:16 Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 00h for N>7
15:8 Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
7:0 Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11

Codec Response for NID=0Ch (Front Sum)

Bit Description
31:24 Connection List Entry (N)
Returns 00h
23:16 Connection List Entry (N+2)
Returns 00h
15:8 Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0 Connection List Entry (N)
Returns 02h (Front DAC) for N=0~3
Returns 00h for N>3

Codec Response for NID=0Dh (Surround Sum)

Bit Description
31:24 Connection List Entry (N)
Returns 00h
23:16 Connection List Entry (N+2)
Returns 00h
15:8 Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3

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Codec Response for NID=0Dh (Surround Sum)
Bit Description
7:0 Connection List Entry (N)
Returns 03h (Surround DAC) for N=0~3.
Returns 00h for N>3.

Codec Response for NID=0Eh (Cen/Lfe Sum)

Bit Description
31:24 Connection List Entry (N)
Returns 00h
23:16 Connection List Entry (N+2)
Returns 00h
15:8 Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0 Connection List Entry (N)
Returns 04h (Cen/Lfe DAC) for N=0~3
Returns 00h for N>3

Codec Response for NID=0Fh (Side-Surr Sum)

Bit Description
31:24 Connection List Entry (N)
Returns 00h
23:16 Connection List Entry (N+2)
Returns 00h
15:8 Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0 Connection List Entry (N)
Returns 05h (Front DAC) for N=0~3
Returns 00h for N>3

Codec Response for NID=26h (Fout Sum)

Bit Description
31:24 Connection List Entry (N)
Returns 00h
23:16 Connection List Entry (N+2)
Returns 00h
15:8 Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3

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Codec Response for NID=26h (Fout Sum)
Bit Description
7:0 Connection List Entry (N)
Returns 25h (Fout1 DAC) for N=0~3
Returns 00h for N>3

Codec Response for NID=14h~1Bh (Port-A to port-H)

Bit Description
31:24 Connection List Entry (N+3)
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3
Returns 00h for n>3
23:16 Connection List Entry (N+2)
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3
Returns 00h for N>3
15:8 Connection List Entry (N+1)
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3
Returns 00h for N>3
7:0 Connection List Entry (N)
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3
Returns 26h (Sum Widget NID=26h) for N=4~7
Returns 00h for N>7

Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT)

Bit Description
31:16 Connection List Entry (N+3) and (N+2)
Returns 0000h
15:8 Connection List Entry (N+1)
Returns 1Fh (Pin Widget S/PDIF-IN) for N=0~3
Returns 00h for N>3
7:0 Connection List Entry (N)
Returns 06h (S/PDIF-OUT converter) for N=0~3
Returns 00h for N>3

Codec Response for NID= 22h/23h/24h (Sum Widget before MIX/LINE/MIC ADCs)
Bit Description
31:24 Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
23:16 Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 0Bh (Sum Widget) for N=8~11
Returns 00h for N>11

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 ALC882 Series
Datasheet
Codec Response for NID= 22h/23h/24h (Sum Widget before MIX/LINE/MIC ADCs)
Bit Description
15:8 Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
7:0 Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11

Codec Response for Other NID

Bit Description
31:0 Not supported (returns 00000000h)

8.5. Verb – Get Processing State (Verb ID=F03h)

Table 37. Verb – Get Processing State (Verb ID=F03h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F03h 0’s 32-bit response

Codec Response for All NID

Bit Description
31:0 Not supported (returns 00000000h)

8.6. Verb – Set Processing State (Verb ID=703h)

Table 38. Verb – Set Processing State (Verb ID=703h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=703h Processing State [7:0] 0’s for all nodes

Codec Response for All NID

Bit Description
31:0 0’s

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 ALC882 Series
Datasheet

8.7. Verb – Get Coefficient Index (Verb ID=Dh)

Table 39. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=Dh 0’s Bit [15:0] are Coefficient Index

Codec Response for NID=20h (Realtek Defined Hidden Registers)

Bit Description
31:16 Reserved. Read as 0’s
15:0 Coefficient Index

Codec Response for Other NID

Bit Description
31:0 Not supported (returns 00000000h)

8.8. Verb – Set Coefficient Index (Verb ID=5h)

Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=5h Coefficient Index [15:0] 0’s for all nodes

Codec Response for All NID

Bit Description
31:0 0’s

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 ALC882 Series
Datasheet

8.9. Verb – Get Processing Coefficient (Verb ID=Ch)

Table 41. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=Ch 0’s Processing Coefficient [15:0]

Codec Response for NID=20h (Realtek Defined Hidden Registers)

Bit Description
31:16 Reserved. Read as 0’s
15:0 Processing Coefficient

Codec Response for Other NID

Bit Description
31:0 Not supported (returns 00000000h)

8.10. Verb – Set Processing Coefficient (Verb ID=4h)

Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=4h Coefficient [15:0] 0’s for all nodes

Codec Response for All NID

Bit Description
31:0 0’s

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 ALC882 Series
Datasheet

8.11. Verb – Get Amplifier Gain (Verb ID=Bh)

This verb is used to get gain/attenuation settings from each widget.

Table 43. Verb – Get Amplifier Gain (Verb ID=Bh)

Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=Bh ‘Get’ payload [15:0] Bit[7:0] are responsible for ‘Get’

‘Get’ Payload in Command Bit[15:0]

Bit Description
15 Get Input/Output
0: Input amplifier gain is requested
1: Output amplifier gain is requested
14 Reserved. Read as 0.
13 Get Left/Right
0: Right amplifier gain is requested
1: Left amplifier gain is requested
12:4 Reserved. Read as 0’s
3:0 Index[3:0] for Input Source
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored

Codec Response for NID=07h (MIC ADC), 08h(LINE ADC) and 09h (MIX ADC)
Bit Description
31:8 0’s
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the
volume from –16.5B~+30dB in 1.5dB steps
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)

Codec Response for NID=0Bh (MIXER Sum Widget)

Bit Description
31:8 0’s
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute 1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the
volume from –34.5dB~+12dB in 1.5dB steps
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)

7.1+2 Channel High Definition Audio Codec 40 Track ID: JATR-1076-21 Rev. 1.5
 ALC882 Series
Datasheet
Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/Lfe, SIDESURR Sum)
Bit Description
31:8 0’s
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. (No Input Amplifier Gain)
Bit-15 is 1 in ‘Get Amplifier Gain’:Output Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the
volume from –46.5dB~0dB in 1.5dB steps

Codec Response for NID=14h~1Bh (Pin Complex: Front/Surr/CenLfe/SIDESURR/MIC1/MIC2/LINE1/LINE2)

Bit Description
31:8 0’s
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute, 0:Unmute, 1:Mute
(NID=14h~1Bh,Default=1)
6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0’s
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain)

Codec Response to Other NID

Bit Description
31:0 Not supported (returns 00000000h)

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 ALC882 Series
Datasheet

8.12. Verb – Set Amplifier Gain (Verb ID=3h)

This verb is used to set amplifier gain/attenuation in each widget.

Table 44. Verb – Set Amplifier Gain (Verb ID=3h)

Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=3h ‘Set’ payload [7:0] 0’s for all nodes

‘Set’ Payload in Command Bit[15:0]

Bit Description
15 Set Output Amp
1 indicates output amplifier gain will be set
14 Set Input Amp
1 indicates input amplifier gain will be set
13 Set Left Amp
1 indicates left amplifier gain will be set
12 Set Right Amp
1 indicates right amplifier gain will be set
11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets)
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is
not set
7 Mute
0: Unmute
1: Mute (-∞ gain)
6:0 Gain[6:0]
A 7-bit step value specifying the amplifier gain

7.1+2 Channel High Definition Audio Codec 42 Track ID: JATR-1076-21 Rev. 1.5
 ALC882 Series
Datasheet

8.13. Verb – Get Converter Format (Verb ID=Ah)

Table 45. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=Ah 0’s Bit[15:0] are converter format

Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/Lfe, Side-Surr, Fout DAC, S/PDIF-OUT).
Codec Response for NID=07h~0Ah (Input Converters: MIC, LINE, UIO1, UIO2, MIX DAC, and S/PDIF-IN)
Bit Description
31:16 Reserved. Read as 0
15 Stream Type (TYPE)
0: PCM
1: Non-PCM
14 Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11 Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
10:8 Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8
The ALC882 series does not support Divisor. Always read as 000b
7 Reserved. Read as 0.
6:4 Bits per Sample (BITS)
000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: reserved
3:0 Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels ….. 15: 16 channels

Codec Response for other NID

Bit Description
31:0 Not supported (returns 00000000h)

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 ALC882 Series
Datasheet

8.14. Verb – Set Converter Format (Verb ID=2h)

Table 46. Verb – Set Converter Format (Verb ID=2h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=2h Set format [15:0] 0’s for all nodes

‘Set’ Payload in Command Bit[15:0]

Bit Description
31:16 Reserved. Read as 0
15 Stream Type (TYPE)
0: PCM
1: Non-PCM
14 Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11 Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
10:8 Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8
7 Reserved. Read as 0
6:4 Bits per Sample (BITS)
000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0 Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels …..… 15: 16 channels

7.1+2 Channel High Definition Audio Codec 44 Track ID: JATR-1076-21 Rev. 1.5
 ALC882 Series
Datasheet

8.15. Verb – Get Power State (Verb ID=F05h)

Table 47. Verb – Get Power State (Verb ID=F05h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=Ah 0’s Power State [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:6 Reserved. Read as 0’s
5:4 PS-Act. Actual Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set
3:2 Reserved. Read as 0’s
1:0 PS-Set, Set Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Set controls the current power setting of the referenced node

Codec Response for other NID

Bit Description
31:0 Not supported (returns 00000000h)

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 ALC882 Series
Datasheet

8.16. Verb – Set Power State (Verb ID=705h)

Table 48. Verb – Set Power State (Verb ID=705h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=705h Power State [7:0] 0’s for all nodes

‘Power State’ in Command Bit[7:0]

Bit Description
7:6 Reserved. Read as 0’s
5:4 PS-Act. Actual Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node.
3:2 Reserved. Read as 0’s
1:0 PS-Set. Set Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3

8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)

Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F06h 0’s Stream & Channel [7:0]

Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/Lfe, Side-Surr, Fout DAC, S/PDIF-OUT)
Codec Response for NID=07h~0Ah (Input Converters: MIC ADC, LINE ADC, MIX DAC, and S/PDIF-IN)
Bit Description
31:8 Reserved. Read as 0’s
7:4 Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
3:0 Channel[3:0]
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel

Codec Response for other NID

Bit Description
31:0 Not supported (returns 00000000h)

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 ALC882 Series
Datasheet

8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)

Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=706h Stream & Channel [7:0] 0’s for all nodes

‘Stream and Channel’ in Command Bit[7:0]

Bit Description
31:8 Reserved. Read as 0’s
7:4 Set Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
1:0 Set Channel[3:0]
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel
Note: This verb assigns stream and channel for output converters (NID=02h~06h, 25h) and input converters
(NID=07h~0Ah). Other widgets will ignore this verb.

8.19. Verb – Get Pin Widget Control (Verb ID=F07h)

Table 50. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F07h 0’s Pin Control [7:0]

Codec Response for NID=14h~1Bh

(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit Description
31:1 Reserved. Read as 0’s
7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
0: Disabled
1: Enabled
6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
0: Disabled
1: Enabled
5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4: Reserved

7.1+2 Channel High Definition Audio Codec 47 Track ID: JATR-1076-21 Rev. 1.5
 ALC882 Series
Datasheet
Codec Response for NID=14h~1Bh
(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit Description
2:0 VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved

Codec Response for other NID

Bit Description
31:0 Not supported (returns 00000000h)

8.20. Verb – Set Pin Widget Control (Verb ID=707h)

Table 51. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=707h Pin Control [7:0] 0’s for all nodes

‘Pin Control’ in command [7:0]: (Pin: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, and LINE2)
Bit Description
31:1 Reserved. Read as 0’s
7 H-Phn Enable
0: Disabled
1: Enabled
6 Out Enable
0: Disabled
1: Enabled
5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4: Reserved
2:0 VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD)
101b: 100% of AVDD
110b~111b: Reserved

7.1+2 Channel High Definition Audio Codec 48 Track ID: JATR-1076-21 Rev. 1.5
 ALC882 Series
Datasheet

8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)

Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.

Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h)

Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID= F08h 0’s 32-bit Response

Codec Response for NID=01h (GPIO), 0Ah (S/PDIF-IN), 14h~1Bh (Port), 21h (Volume in Step)
Bit Description
31:8 Reserved. Read as 0’s
7 Unsolicited Response is Enabled
0: Disabled
1: Enabled
6:4 Reserved. Read as 0’s
3:0 Assigned Tag for Unsolicited Response
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses

Codec Response for other NID

Bit Description
31:0 Not supported (returns 00000000h)

8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)

Enable a widget to generate an unsolicited response.

Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h)

Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=708h EnableUnsol [7:0] 0’s for all nodes

‘EnableUnsol’ in Command Bit[7:0]

Bit Description
31:8 Reserved. Read as 0’s
7 Enable Unsolicited Response
0: Disable
1: Enable
6:4 Reserved. Read as 0’s
3:0 Tag for Unsolicited Response
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses

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 ALC882 Series
Datasheet

8.23. Verb – Get Pin Sense (Verb ID=F09h)

Returns the Presence Detect status and the impedance of a device attached to the pin.

Table 54. Verb – Get Pin Sense (Verb ID=F09h)

Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID= F09h 0’s 32-bit Response

Codec Response for NID = 14h~1Bh, 1Eh, 1Fh

Bit Description
31 Presence Detect Status
0: No device is attached to the pin
1: Device is attached to the pin
30:0 Measured Impedance
0x7FFFFFFF or 0xFFFFFFFF: Valid sense is not available or busy

Codec Response for other NID

Bit Description
31:0 Not supported (returns 00000000h)

8.24. Verb – Execute Pin Sense (Verb ID=709h)

Table 55. Verb – Execute Pin Sense (Verb ID=709h)
Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID= 709h Right Channel[0] 0’s for all nodes

‘Payload’ in Command Bit[7:0]

Bit Description
7:1 Reserved. Read as 0’s
0 Right (Ring) Channel Select
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)

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 ALC882 Series
Datasheet

8.25. Verb – Get Configuration Default (Verb ID=F1Ch)

Read the 32-bit sticky register for each Pin Widget configured by software.

Table 56. Verb – Get Configuration Default (Verb ID=F1Ch)

Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID= F1Ch 0’s 32-bit Response

Codec Response for NID=14h, 15h, 16h, 17h, 18h, 19h, 1Ah, 1Bh, 1Eh, and 1Fh
Bit Description
31:0 32-bit configuration information for each pin widget
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).

8.26. Verb – Set Configuration Default Bytes 0, 1, 2, 3

(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.

Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3

(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=71Ch, Label [7:0] 0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb.

Codec Response for All NID

Bit Description
31:0 0’s

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Datasheet

8.27. Verb – Get BEEP Generator (Verb ID=F0Ah)

Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID= F1Bh 0’s Divider [7:0]

‘Response’ for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:0 Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input

Codec Response for Other NID

Bit Description
31:0 0’s

8.28. Verb – Set BEEP Generator (Verb ID=70Ah)

Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=71Bh Divider [7:0] 0’s for all nodes

‘Divider’ in Set Command

Bit Description
31:8 Reserved
7:0 Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for All NID

Bit Description
31:0 0’s

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Datasheet

8.29. Verb – Get GPIO Data (Verb ID= F15h)

Table 60. Verb – Get GPIO Data (Verb ID= F15h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F15h 0’s 32-bit Response

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Data. Not supported in the ALC882 series
1:0 GPIO[1:0] Data
The value written (output) or sensed (input) on the corresponding pin if it is enabled

Codec Response for Other NID

Bit Description
31:0 0’s

8.30. Verb – Set GPIO Data (Verb ID= 715h)

Table 61. Verb – Set GPIO Data (Verb ID= 715h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=715h Data [7:0] 0’s for all nodes

‘Data’ in Set command for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] output Data. Not supported in the ALC882 series
1:0 GPIO[1:0] Output Data
The value written determines the value driven on a pin that is configured as an output pin

Codec Response for All NID

Bit Description
31:0 0’s

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8.31. Verb – Get GPIO Enable Mask (Verb ID=F16h)

Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F16h 0’s EnableMask [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 Reserved
1:0 GPIO[1:0] Enable mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description
31:0 0’s

8.32. Verb – Set GPIO Enable Mask (Verb ID=716h)

Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=716h Enable Mask [7:0] 0’s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Enable Mask. Not supported in the ALC882 series
1:0 GPIO[1:0] Enable Mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for All NID

Bit Description
31:0 0’s

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8.33. Verb – Get GPIO Direction (Verb ID=F17h)

Table 64. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F17h 0’s Direction [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Direction Control. Not supported in the ALC882 series
1:0 GPIO[1:0] Direction Control
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description
31:0 0’s

8.34. Verb – Set GPIO Direction (Verb ID=717h)

Table 65. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=717h Direction [7:0] 0’s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Direction Control. Not supported in the ALC882 series
1:0 GPIO[1:0] Direction Control
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description
31:0 0’s

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8.35. Verb – Get GPIO Unsolicited Response Enable Mask

(Verb ID=F19h)
Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F19h 0’s UnsolEnable [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC882 series
1:0 GPIO[1:0] Unsolicited Enable mask
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit Description
31:0 0’s

8.36. Verb – Set GPIO Unsolicited Response Enable Mask

(Verb ID=719h)
Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=719h UnsolEnable [7:0] 0’s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit Description
31:8 Reserved
7:2 GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC882 series
1:0 GPIO[1:0] Unsolicited Enable Mask
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’ and Verb-‘Unsolicited
Response’ for NID=01h are enabled.

Codec Response for Other NID

Bit Description
31:0 0’s

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8.37. Verb – Function Reset (Verb ID=7FFh)

Table 68. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H) Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=01h Verb ID=7FFh 0’s 0’s

Codec Response
Bit Description
31:0 Reserved. Read as 0’s
Note: The Function Reset command causes all widgets in the ALC882 series to return to their power on default state.

8.38. Verb – Get Digital Converter Control 1 & Control 2 (Verb

ID= F0Dh, F0Eh)
Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F0Dh/ 0’s Bit[31:16]=0’s, Bit[15:0] are SIC bit
F0Eh

NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
31:16 Read as 0’s
15 Reserved. Read as 0’s
14:8 CC[6:0] (Category Code)
7 LEVEL (Generation Level)
6 PRO (Professional or Consumer format)
0: Consumer format
1: Professional format
5 /AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
4 COPY (Copyright)
0: Asserted
1: Not asserted
3 PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
2 VCFG for Validity Control (control V bit and data in Sub-Frame)
1 V for Validity Control (control V bit and data in Sub-Frame)

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NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
0 Digital Enable. DigEn
0: OFF
1: ON

NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Dh)’

NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Eh)’
Bit Description (part of S/PDIF-IN Channel Status)
31:16 Reserved. Read as 0’s
15 Reserved. Read as 0’s
14:8 CC[6:0] (Category Code)
7 LEVEL (Generation Level)
6 PRO (Professional or Consumer format)
0: Consumer format
1: Professional format
5 /AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
4 COPY (Copyright)
0: Asserted
1: Not asserted
3 PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
2 Reserved
1 In‘V’alid. V bit in sub-frame of S/PDIF-IN
0: Data X and Y are valid, or S/PDIF-IN is not locked
1: At least one of data X and Y is invalid
0 Digital Enable. DigEn
0: OFF
1: ON

Codec Response for Other NID

Bit Description
31:0 0’s

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8.39. Verb – Set Digital Converter Control 1 & Control 2

(Verb ID=70Dh, 70Eh)
Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Xh, Set Control 1) Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=70Dh SIC [7:0] 0’s

Set Command Format (Verb ID=70Yh, Set Control 2) Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=70Eh SIC [15:8] 0’s

‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT)

Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
7 LEVEL (Generation Level)
6 PRO (Professional or Consumer format)
0: Consumer format
1: Professional format
5 /AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
4 COPY (Copyright)
0: Asserted
1: Not asserted
3 PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
2 VCFG for Validity Control (control V bit and data in Sub-Frame)
1 V for Validity Control (control V bit and data in Sub-Frame)
0 Digital Enable. DigEn
0: OFF
1: ON

‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT)

Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
7 Reserved. Read as 0’s
6:0 CC[6:0] (Category Code)

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‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN)
Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
7:1 Reserved
0 Digital Enable. DigEn
0: OFF
1: ON

‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN)

Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
7:0 Reserved. Read as 0’s
Note: Other widgets will ignore this verb.

8.40. Get/Set Volume Knob Widget (NID=21h)

(Verb ID= F0Fh/70Fh)
Table 71. Get/Set Volume Knob Widget (NID=21h) (Verb ID= F0Fh/70Fh)
Get Command Format Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=F0Fh 0’s Bit[31:8]=0’s, Bit[7:0] is volume

Codec Response for NID=21h (Volume Knob Widget)

Bit Description
31:8 Reserved
7 Direct
0: The volume generated by an external HW volume control will be sent by unsolicited
response. Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
6:0 Volume in steps

Set Command Format (Verb ID=70Yh, Set Control 2) Codec Response Format
Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0]
CAd=X Node ID=Xh Verb ID=70Fh Bit[7] is ‘Direct’ control 0’s

‘Payload’ in Set Command for NID=21h (Volume Knob Widget)

Bit Description
31:8 Reserved
7 Direct
0: The volume generated by an external HW volume control will be sent by unsolicited
response. Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
6:0 Reserved
Note: Other nodes will ignore this verb.

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9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 72. Absolute Maximum Ratings
Parameter Symbol Minimum Typical Maximum Units
Power Supplies:
Digital DVDD 3.0 3.3 3.6 V
Analog AVDD 3.6 5.0 5.5 V
o
Ambient Operating Ta 0 - +70 C
Temperature
o
Storage Temperature Ts +125 C
ESD (Electrostatic Discharge)
Susceptibility Voltage
All Pins 4500V

9.1.2. Threshold Voltage

DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.

Table 73. Threshold Voltage

Parameter Symbol Minimum Typical Maximum Units
Input Voltage Range Vin -0.30 - DVDD +0.30 V
Low Level Input Voltage VIL - - 0.30*DVDD V
(BCLK, RST#, SDO, SYNC, SDI) (1.00)
High Level Input Voltage VIH 0.65* DVDD - - V
(BCLK, RST#, SDO, SYNC, SDI) (2.00)
Low Level Input Voltage VIL - - 0.44*DVDD V
(S/PDIF-IN/OUT, GPIOs) (1.45)
High Level Input Voltage VIH 0.56* DVDD - - V
(S/PDIF-IN/OUT, GPIOs) (1.85)
High Level Output Voltage VOH 0.9*DVDD - V
Low Level Output Voltage VOL - - 0.1*DVDD V
Input Leakage Current - -10 - 10 µA
Output Leakage Current (Hi-Z) - -10 - 10 µA
Output Buffer Drive Current - - 5 - mA
Internal Pull Up Resistance - - 50k - Ω

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9.1.3. Digital Filter Characteristics

Table 74. Digital Filter Characteristics
Filter Symbol Minimum Typical Maximum Units
ADC Lowpass Filter Passband 0 - 19.2 kHz
Stopband 28.8 kHz
Stopband Rejection -76.0 dB
Passband ±0.20 dB
Frequency Response
DAC Lowpass Filter Passband 0 - 19.2 kHz
Stopband 28.8 kHz
Stopband Rejection -78.5 dB
Passband ±0.20 dB
Frequency Response

9.1.4. S/PDIF Input/Output Characteristics

DVDD= 3.3V, Tambient=25°C, with 75Ω external load.

Table 75. S/PDIF Input/Output Characteristics

Parameter Symbol Minimum Typical Maximum Units
S/PDIF-OUT High Level Output VOH 3.0 3.3 - V
S/PDIF-OUT Low Level Output VOL - 0 0.3 V
S/PDIF-IN High Level Input VIH 1.85 - - V
S/PDIF-IN Low Level Input VIL - - 1.45 V
S/PDIF-IN Bias Level Vt - 1.5 - V

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9.2. AC Characteristics
9.2.1. Link Reset and Initialization Timing
Table 76. Link Reset and Initialization Timing
Parameter Symbol Minimum Typical Maximum Units
RESET# Active Low Pulse Width TRST 1.0 - - µs
RESET# Inactive to BCLK TPLL 20 - - µs
Startup delay for PLL ready time
SDI Initialization Request TFRAME - - 1 Frame Time

Initialization
4 BCLK 4 BCLK >= 4 BCLK Sequence

BCLK

Normal Frame
SYNC SYNC

SDO

Initialization
SDI Request

RESET#
TRST
TPLL T FRAME

Figure 15. Link Reset and Initialization Timing

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9.2.2. Link Timing Parameters at the Codec

Table 77. Link Timing Parameters at the Codec
Parameter Symbol Minimum Typical Maximum Units
BCLK Frequency - 24.0 - MHz
BCLK Period Tcycle - 41.67 - ns
BCLK Jitter Tjitter - - 2.0 ns
BCLK High Pulse Width Thigh 18.75 - 22.91 ns
(45%) (55%) (%)
BCLK Low Pulse Width Tlow 18.75 - 22.91 ns
(45%) (55%) (%)
SDO Setup Time at Both Rising Tsetup 2.1 - - ns
and Falling Edge of BCLK
SDO Hold Time at Both Rising and Thold 2.1 - - ns
Falling Edge of BCLK
SDI Valid Time After Rising Edge Ttco - 7.5 8.0 ns
of BCLK (1: 50pF external load)
SDI Flight Time Tflight - 2.0 - ns

T_cycle
T_high
V IH
BCLK VT
V IL

T_low
T_setup T_hold

SDO

T_tco
VOH

SDI
VOL

T_flight

Figure 16. Link Signals Timing

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9.2.3. S/PDIF Output and Input Timing

Table 78. S/PDIF Output and Input Timing
Parameter Symbol Minimum Typical Maximum Units
S/PDIF-OUT Frequency *1 - - 6.144 - MHz
S/PDIF-OUT Period *1 Tcycle - 162.8 - ns
S/PDIF-OUT Jitter Tjitter - - 4 ns
S/PDIF-OUT High Level Width THigh 78.1 (48%) 81.4 (50%) 84.6 (52%) ns (%)
*1

S/PDIF-OUT Low Level Width*1 TLow 78.1 (48%) 81.4 (50%) 84.6 (52%) ns (%)
S/PDIF-OUT Rising Time Trise - 2.0 - ns
S/PDIF-OUT Falling Time Tfall - 2.0 - ns
S/PDIF-IN Period *2 Tcycle - 162.8 - ns
S/PDIF-IN Jitter Tjitter - - 10 ns
*2
S/PDIF-IN High Level Width THigh 73.2 (45%) 81.4 (50%) 89.5 (55%) ns (%)
S/PDIF-IN Low Level Width*2 TLow 73.2 (45%) 81.4 (50%) 89.5 (55%) ns (%)
*1: Bit parameters for 48kHz sample rate of S/PDIF-OUT
*2: Bit parameters for 48kHz sample rate of S/PDIF-IN

Tcycle
Thigh Tlow
VOH
VIH
Vt
VIL
V OL

Trise T fall
Figure 17. Output and Input Timing

9.2.4. Test Mode

The ALC882 series does not support codec test mode or Automatic Test Equipment (ATE) mode.

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9.3. Analog Performance

Standard Test Conditions • Tambient=25 oC, DVDD=3.3V ±5%, AVDD=5.0V±5%
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz,
0dB attenuation
Table 79. Analog Performance
Parameter Min Typical Max Units
Full Scale Input Voltage
All Inputs (gain=0dB) - 1.6 - Vrms
All ADC - 1.1 - Vrms
Full Scale Output Voltage
All DAC - 1.2 1.5 Vrms
S/N (A Weighted)
Analog Inputs to Outputs - 95 100 dB FSA
All ADC - 90 - dB FSA
All DAC - 101 104 dB FSA
THD+N
Analog Inputs to Outputs - -90 - dB FS
ADC - -82 - dB FS
All DAC - -90 - dB FS
Frequency Response
Mixers 10 - 22,000 Hz
ADC, DAC 16 - 19,200 Hz
Power Supply Rejection - -40 - dB
Total Out-of-Band Noise (28.8kHz~100kHz) - -60 - dB
Amplifier Gain Step - 1.5 - dB
Crosstalk Between Input Channels - -80 dB
Input Impedance (gain=0dB) 47 KΩ
Output Impedance
Amplified Output 1 Ω
Non-amplified Output 100 Ω
Digital Power Supply Current (normal operation)
DVDD=3.3V - 35 - mA
Digital Power Supply Current (power down mode)
DVDD=3.3V - - 600 µA
Analog Power Supply Current (normal operation)
AVDD=5.0V - 68 - mA
Analog Power Supply Current (power down mode)
AVDD=5.0V - - 600 µA
VREFOUTx Output Voltage 2.25 2.50 3.75 V
VREFOUTx Output Current 5 mA

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10. Application Notes

10.1. Standard Application Circuit
Please contact Realtek for the latest application circuits. To get the best compatibility in hardware design
and software driver, any modification should be confirmed by Realtek. Realtek may update the latest
application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.

+5VA

R3

Ext.Volume Control
VAR 10K

MIC1-VREFO-R
External Volume Control
LINE2-VREFO

Ext.Volume Control MIC2-VREFO

LINE1-VREFO +12V
+5VA
SIDESURR-JD R7 5.1K,1% Sense B MIC1-VREFO-L U1
LM7805CT/200mA L1 FERB
CEN-JD R6 10K,1% +5VA 3
OUT IN
1

FRONT-IO-SENSE R42 0 FRONT-L C1

C7 10u C8 +
FRONT-R + + C2
+10u
10u +10u
Reserved for 100dB SNR
+5VA U6

C26

1u
37 24 LINE1-R
VRDA LINE1-R
38 23 LINE1-L
AVDD2 LINE1-L
SURR-L 39 22 MIC1-R
C15 + SURR-L MIC1-R
R41 20K,1% 40 21 MIC1-L CD-IN Header
10u JDREF MIC1-L
SURR-R 41 20 C17 1u
SURR-R CD-R 4 J1
42 19 C20 1u 3
AVSS2 CD-GND 2
CEN 43
CEN
ALC882 CD-L
18 C21 1u 1

LFE 44 17 MIC2-R
LFE MIC2-R
SIDESURR-L 45 16 MIC2-L
SIDESURR-L MIC2-L
SIDESURR-R 46 15 LINE2-R
SIDESURR-R LINE2-R
47 14 LINE2-L
SPDIFI/EAPD LINE2-L
48 13 Sense A R16 5.1K,1% FRONT-JD
SPDIFO Sense A
S/PDIF-IN R13 10K,1% LINE1-JD
R12 20K,1% MIC1-JD
Split by DGND
R11 39.2K,1% SURR-JD
S/PDIF-OUT

+3.3VD
R17 47K
C30 + C29 1u
Ext. PCBEEP
10u

R48
RESET#
R19 4.7k
22
SYNC

SDIN

R22 22
BCLK

C34 DGND AGND

22P
Tied at one point only under
the codec or near the codec
SDOUT

Figure 18. Filter Connection

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Figure 19. IO Connection

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Figure 20. On board Front Panel Header & Front I/O Module Connection

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10.2. Volume Control by External Variable Resistor

The input range of DCVOL is from GND to AVDD. A 5-bit resolution ADC is used to convert the DC
level on a variable resistor into 32 steps for Volume knob use. DC level changes are reflected to software
to control the master volume.

ALC882
AVDD=5V

5-bit
Variable DCVOL (Pin 33) ADC
Resistor
Volume Code [4:0]

+5V: DCVOL=31
0V: DCVOL=0

Figure 21. Volume Control by External Variable Resistor

10.3. Volume Control by GPIO0/GPIO1

Detect Low pulses generated at GPIO0 and GPIO1 calculate the Up and Down count into 7 bits of
volume step. ‘Mute’ is also sampled to toggle the mute status. Hardware does not adjust volume. The
count value is reported via unsolicited response to software to control the master volume.

Figure 22. Volume Control by GPIO0 and GPIO1

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11. Mechanical Dimensions

L1

See the Mechanical Dimensions notes on the next page.

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11.1. Mechanical Dimensions Notes

SYMBOL
MILLIMETER INCH
MIN. TYP MAX. MIN. TYP MAX
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057 TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
c 0.09 0.20 0.004 0.008
FOOTPRINT 2.0mm
D 9.00 BSC 0.354 BSC
LEADFRAME MATERIAL
D1 7.00 BSC 0.276 BSC
APPROVE DOC. NO.
D2 5.50 0.217
VERSION 02
E 9.00 BSC 0.354 BSC
CHECK DWG NO. PKGC-065
E1 7.00BSC 0.276 BSC
DATE
E2 5.50 0.217
REALTEK SEMICONDUCTOR CORP.
b 0.17 0.20 0.27 0.007 0.008 0.011
e 0.50 BSC 0.0196 BSC
o
TH 0 3.5o 7o 0o
3.5o 7o
L 0.45 0.60 0.75 0.018 0.0236 0.030
L1 1.00 0.0393

7.1+2 Channel High Definition Audio Codec 72 Track ID: JATR-1076-21 Rev. 1.5
 ALC882 Series
Datasheet

12. Ordering Information

Table 80. Ordering Information
Part Number Description Status
ALC882-VB1-LF LQFP-48 & Lead (Pb)-Free package Production
ALC882D-LF ALC882-VB1-LF + Dolby® Digital Live (software feature) Production
ALC882H-LF ALC882-VB1-LF + Dolby® Home Theater (software feature) Production
ALC882M-LF ALC882-VB1-LF + Dolby® Master Studio (software feature) Production
ALC882DTS-LF ALC882-VB1-LF + DTS® CONNECT™ (software feature) Production
Note 1: See page 6 for lead (Pb)-free package and version identification.
Note 2: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact
Realtek sales representatives or agents.

Realtek Semiconductor Corp.

Headquarters
No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw

7.1+2 Channel High Definition Audio Codec 73 Track ID: JATR-1076-21 Rev. 1.5