Risc-V Processor Verification: Processors For The Connected World
Risc-V Processor Verification: Processors For The Connected World
Software
Processor Modeling SDK Synthesis RTL Synthesis Verification
analysis
Application(s)/Programs(s)
C/C++ Compiler
Assembler
Linker
Codix CodAL Models Codix Cycle Accurate CA Simulator, Profiler, Debugger Codix RTL Models
Models
Codix
Microarchitecture
AUTOMATION VS. VERIFICATION
Fewer bugs - once the tool generating RTL is debugged, then certain
types of bugs no longer occur.
Verification environment generation –from the high-level IA and CA
CodAL models.
Reference model updates - as well as new RTL (which serves in
verification as DUT), reference models from IA model in C/C++ can
be generated.
Test generation - random assembler programs generator tool
integrated in Codasip Studio.
UNIQUE AUTOMATION TECHNOLOGY
Software
Processor Modeling SDK Synthesis RTL Synthesis Verification
analysis
Application(s)/Programs(s)
C/C++ Compiler
Assembler
Linker
RESULTS OK BUT
COVERAGE NOT 100%
RESULTS OK,
COVERAGE 100%
VERIFICATION Directed tests, assertions,
FINISHED coverage points
EXAMPLE: SUB-DESIGN REUSE
MISMATCHES FOUND, MODEL MUST BE FIXED (not expected, everything is debugged)
RESULTS OK BUT
COVERAGE NOT 100%
RESULTS OK,
COVERAGE 100% COPY directed tests,
VERIFICATION
assertions, coverage points
FINISHED from full design
EXAMPLE: NEW EXTENSION
MISMATCHES FOUND, MODEL MUST BE FIXED (only extension-specific parts)
GENERATE
Bk5 extended model RTL, reference model,
UVM verification environment,
64b+I+M+F+C+? ISA tests
RESULTS OK BUT
COVERAGE NOT 100%
RESULTS OK,
VERIFICATION COVERAGE 100% COPY directed tests,
assertions, coverage points
FINISHED from full design + add new
connected to extension
SUMMARY