Complementary metal–oxide–semiconductor 

(CMOS) (pronounced /ˈsiːmɒs/) is a technology for

constructing integrated circuits. CMOS technology is used in microprocessors,microcontrollers, static
RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such
as image sensors, data converters, and highly integrated transceiversfor many types of
communication. Frank Wanlass patented CMOS in 1967 (US patent 3,356,858).

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or

COS-MOS[1]). The words "complementary-symmetry" refer to the fact that the typical digital design style
with CMOS uses complementary and symmetrical pairs of p-type andn-type metal oxide semiconductor
field effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise immunity and low static power
consumption. Significant power is only drawn while the transistors in the CMOS device are switching
between on and off states. Consequently, CMOS devices do not produce as muchwaste heat as other
forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel
devices without p-channel devices. CMOS also allows a high density of logic functions on a chip. It was
primarily this reason why CMOS won the race in the eighties and became the most used technology to be
implemented in VLSI chips.

A MOSFET can be made to operate as a resistor, so the whole circuit can be made with n-channel
MOSFETs only. For many years, this made NMOS circuits much faster than comparable PMOS and
CMOS circuits, which had to use much slower p-channel transistors. It was also easier to manufacture
NMOS than CMOS, as the latter has to implement p-channel transistors in special n-wells on the p-
substrate. The major problem with NMOS (and most other logic families) is that a DC current must flow
through a logic gate even when the output is in asteady state (low in the case of NMOS). This means
static power dissipation, i.e. power drain even when the circuit is not switching. This is a similar situation
to the modern high speed, high density CMOS circuits (microprocessors etc) which also has significant
static current draw, although this is due to leakage, not bias. However, older and/or slower static CMOS
circuits used for ASICs, SRAM etc, typically have very low static power consumption.

Also, NMOS circuits are slow to transition from low to high. When transitioning from high to low, the
transistors provide low resistance, and the capacitative charge at the output drains away very quickly
(similar to discharging a capacitor through a very low resistor). But the resistance between the output and
the positive supply rail is much greater, so the low to high transition takes longer (similar to charging a
capacitor through a high value resistor). Using a resistor of lower value will speed up the process but also
increases static power dissipation. However, a better (and the most common) way to make the gates
faster is to use depletion-mode transistors instead of enhacement-modetransistors as loads. This is
called depletion-load NMOS logic.
Additionally, just like in DTL, TTL and ECL etc., the asymmetric input logic levels make NMOS circuits
somewhat susceptible to noise. These disadvantages are why the CMOS logic now has supplanted most
of these types in most high-speed digital circuits such asmicroprocessors (despite the fact that CMOS
was originally very slow).

Oxidation:-

At 900-1200 degree centigrade in a furnace.

Polysilicon:-

The silicon wafer is placed in a furnace and in presence of silane gas(SiH4) chemical vapour
decomposition of the silicon wafer takes place and a large number of silicon crystals are formed with
high dopant concentration to become a good conductor and this crystal silicons form polysilicon.
CVD = Chemical Vapor Deposition, where reactive gases collide above the wafer, and chemical
reaction products then fall onto the wafer creating a new layer.). Metal interconnects have 3-5x the
speed of polysilicon (electron mobility is higher) and less resistance. However, metals may react with
nearby materials, and may have to be encapsulated using nitrides (e.g. Si3N4 or TiN) to prevent
unwanted reactions, or partial erosion in subsequent etching procedures. This is expensive. In Upper
Metallurgy (not local interconnects) metal is always used because processing is simple: only Metal +
SiO2.

Polysilicon interconnects are used to connect Gates and other short-distance connections which have
minimal currents. Polysilicon is a very stable material that rarely interacts with nearby materials

Self-aligned:-

Gate is formed first so that it forms a mask for the formation of drain and source, thus helping in denoting
the proper position for the channel,source and drain.

Metal is not used in place of polysilicon as because the metal would melt during the metal deposition.

Ion implantation(during metal deposition and formation of n-well):-

Blasting the silicon wafer by arsenic gas to impact the atoms of As inside the silicon wafer.

Diffusion (during metal deposition and formation of n-well:-

Silicon wafer placed inside furnace with As gas and heated until As atoms diffuse inside the silicon.
Twin tub:-

This technology provides the basis for separate optimization of the nMOS and pMOS transistors,
thus making it possible for threshold voltage, body effect and the channel transconductance of both
types of transistors to be tuned independently. Generally, the starting material is a n+ or p+
substrate, with a lightly doped epitaxial layer (~1015/cm3) on top. This epitaxial layer provides the
actual substrate on which the n-well and the p-well are formed. Since two independent doping steps
are performed for the creation of the well regions, the dopant concentrations can be carefully
optimized to produce the desired device characteristics.

In the conventional n-well CMOS process, the doping of the well region is typically about one order
of magnitude higher than the substrate, which, among other effects, results in unbalanced drain
parasitics (possible latchup). The twin-tub process, below, avoids this problem. For inexpensive and
low-performance chips, one may use a heavily doped substrate and omit one well. The substrate
should be doped to about 1016/cm3, with a resistivity of about 1 Ω-cm. This allows simpler
construction, with good “Ground Potential” distribution, but the devices are not optimal and there is
a chance of latch-up if the voltages are pushed hard.

For high-performance chips, one uses a low doped substrate, 10 15/cm3, 10 Ω-cm, and then
constructs Two Wells at optimum doping levels (called Tubs in the diagram). Since the substrate is
lightly doped, there is less chance for latch-up because of the high resistivity.

Silicon-on-Insulator (SOI) CMOS Process :-

Rather than using silicon as the substrate material, an insulating substrate will improve process
characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the
creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on
an insulating substrate. The main advantages of this technology are the higher integration density
(because of the absence of well regions), complete avoidance of the latch-up problem, and lower
parasitic capacitances compared to the conventional n-well or twin-tub CMOS processes. A cross-
section of nMOS and pMOS devices in created using SOI process is shown below.