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Vlsi-Expt-5 and 6

The document contains the code for several Verilog modules: 1) A 3-bit ripple upcounter and testbench that uses D flip-flops to increment the counter value on each clock cycle. 2) A 3-bit ripple downcounter and testbench that decrements the counter value on each clock cycle. 3) A switch debouncer and testbench that filters out switch noise and outputs a clean switch signal. 4) A 4-bit ripple carry adder and testbench that adds two 4-bit numbers and outputs the sum and carry out. 5) An 8-bit adder/subtractor and testbench that can add or subtract two

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45 views6 pages

Vlsi-Expt-5 and 6

The document contains the code for several Verilog modules: 1) A 3-bit ripple upcounter and testbench that uses D flip-flops to increment the counter value on each clock cycle. 2) A 3-bit ripple downcounter and testbench that decrements the counter value on each clock cycle. 3) A switch debouncer and testbench that filters out switch noise and outputs a clean switch signal. 4) A 4-bit ripple carry adder and testbench that adds two 4-bit numbers and outputs the sum and carry out. 5) An 8-bit adder/subtractor and testbench that can add or subtract two

Uploaded by

gayathri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Ripple upcounter

module rip_up_counter(
input clk,reset,
output [2:0] q
);
tff t1(clk,reset,1,q[0]);
tff t2(~(q[0]),reset,1,q[1]);
tff t3(~(q[1]),reset,1,q[2]);
endmodule

TEST BENCH
initial begin
// Initialize Inputs
clk = 0;
reset = 1;

// Wait 100 ns for global reset to finish


#100;
reset=0;
end

always
begin
#100 clk=~clk;
end
endmodule

Ripple Down Counter

module rip_down_counter(
input clk,reset,
output [2:0] q
);

tff t1(clk,reset,1,q[0]);
tff t2((q[0]),reset,1,q[1]);
tff t3((q[1]),reset,1,q[2]);

endmodule
TEST BENCH
initial begin
// Initialize Inputs
clk = 0;
reset = 1;

// Wait 100 ns for global reset to finish


#100;
reset=0;
end

always
begin
#100 clk=~clk;
end
endmodule

SWITCH DEBOUNCER
module switch_debounce(
input in_switch,clk,
output out_switch
);
reg [17:0] count=18'b0;
reg in_state=1'b0;
always@(posedge clk)
begin
if((in_switch !=in_state) && (count<250000))
count<=count+18'b1;
else if(count==250000)
begin
in_state=in_switch;
count<=18'b1;
end
else
count<=18'b0;
end
assign out_switch=in_state;

endmodule
TEST BENCH

initial begin
in_switch = 1;
clk = 0;
#100;
end

always
begin
#20 clk=~clk;
end

endmodule

RIPPLE CARRY ADDER


module ripc_adder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] s,
output cout
);
wire [4:0] c;
genvar i;
assign c[0]=cin;
generate for(i=0;i<=3;i=i+1)
begin:loop
Fulladder f1(a[i],b[i],c[i],s[i],c[i+1]);
end
assign cout=c[4];
endgenerate

endmodule

TEST BENCH:
initial begin

a = 2;
b = 4;
cin = 1;

#100;

a = 15;
b = 1;
cin = 0;

#100;
a = 10;
b = 12;
cin = 1;

#100;

a = 8;
b = 3;
cin = 0;

#100;
a = 1;
b = 5;
cin = 1;

#100;

a = 5;
b = 9;
cin = 0;

#100;

a = 16;
b = 2;
cin = 1;

#100;

a = 3;
b = 2;
cin = 1;

end

endmodule
ADDER/SUBTRACTOR
module addsub(
input [7:0] a,
input [7:0] b,
input cin,
output cout,
output [7:0] s
);
wire [8:0] c;
wire [7:0] x;
genvar i;
assign c[0] =cin;
generate for (i=0;i<=7;i=i+1)
begin:loop
xor(x[i],b[i],cin);
Fulladder f1(a[i],x[i],c[i],s[i],c[i+1]);
end
assign cout=c[7];
endgenerate
endmodule

TEST BENCH
initial begin

a = 10;
b = 1;
cin = 0;
#100;

a = 2;
b = 4;
cin = 1;

#100;

a = 12;
b = 6;
cin = 0;

#100;

a = 16;
b = 1;
cin = 0;

#100;

a = 8;
b = 2;
cin = 1;

#100;
end
endmodule

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