Atmel 42005 8 and 16 Bit AVR Microcontrollers XMEGA E Manual

8/16-bit Atmel AVR XMEGA Microcontrollers
XMEGA E MANUAL
This document contains complete and detailed description of all modules included in the
Atmel®AVR® XMEGA® E microcontroller family. The XMEGA E is a family of low-power, high-
performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced
RISC architecture. The available XMEGA E modules described in this manual are:
 Atmel AVR CPU
 Memories
 EDMA - Enhanced direct memory access
 Event system
 System clock and clock options
 Power management and sleep modes
 Reset system
 WDT - Watchdog timer
 Interrupts and programmable multilevel interrupt controller
 PORT - I/O ports
 TC4/5 - 16-bit timer/counters
 WeX - Waveform extension
 Hi-Res - High resolution extension
 Fault - Fault extension
 RTC - Real-time counter
 TWI - Two-wire serial interface
 SPI - Serial peripheral interface
 USART - Universal synchronous and asynchronous serial receiver and transmitter
 IRCOM - Infrared communication module
 XCL - XMEGA custom logic
 CRC - Cyclic redundancy check
 ADC - Analog-to-digital converter
 DAC - Digital-to-analog converter
 AC - Analog comparator
 PDI - Program and debug interface
 Memory Programming
 Peripheral module address map
 Instruction set summary
 Manual revision history
 Table of contents
Atmel–42005E–AVR–XMEGA E–11/2014
1. About the Manual
This document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA E
microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals
and modules described in this manual may not be present in all XMEGA E devices.
For all device-specific information such as characterization data, memory sizes, modules, peripherals available and their
absolute memory addresses, refer to the device datasheets. When several instances of a peripheral exists in one device,
each instance will have a unique name. For example each port module (PORT) have unique name, such as PORTA,
PORTB, etc. Register and bit names are unique within one module instance.
For more details on applied use and code examples for peripherals and modules, refer to the Atmel AVR XMEGA
specific application notes available from http://www.atmel.com/avr.
1.1 Reading the Manual

The main sections describe the various modules and peripherals. Each section contains a short feature list and overview
describing the module. The remaining section describes the features and functions in more detail.
The register description sections list all registers and describe each register, bit and flag with their function. This includes
details on how to set up and enable various features in the module. When multiple bits are needed for a configuration
setting, these are grouped together in a bit group. The possible bit group configurations are listed for all bit groups
together with their associated Group Configuration and a short description. The Group Configuration refers to the defined
configuration name used in the Atmel AVR XMEGA assembler header files and application note source code.
The register summary sections list the internal register map for each module type.
The interrupt vector summary sections list the interrupt vectors and offset address for each module type.
1.2 Resources
A comprehensive set of development tools, application notes, and datasheets are available for download from
http://www.atmel.com/avr.
1.3 Recommended Reading

 XMEGA E device datasheets
 XMEGA application notes
This manual contains general modules and peripheral descriptions. The AVR XMEGA E device datasheets contains the
device-specific information. The XMEGA application notes and Atmel Software Framework contain example code and
show applied use of the modules and peripherals.
For new users, it is recommended to read the AVR1000 - Getting Started Writing C Code for Atmel XMEGA.
XMEGA E [MANUAL] 2
2. Overview
The AVR XMEGA E microcontrollers is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit
microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the XMEGA E devices achieve throughputs approaching one million instructions per second (MIPS) per
megahertz, allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA E devices provide the following features: in-system programmable flash; internal EEPROM and SRAM;
four-channel enhanced DMA controller (EDMA); eight-channel event system with asynchronous event support;
programmable multilevel interrupt controller; up to 26 general purpose I/O lines; 16-bit real-time counter (RTC) with
digital correction; up to three flexible, 16-bit timer/counters with capture, compare and PWM modes; up to two USARTs;
one I2C and SMBUS compatible two-wire serial interfaces (TWI); one serial peripheral interfaces (SPI); one XMEGA
custom logic (XCL) with timer/counter and logic functions; CRC module; one 16-channel, 12-bit ADC with programmable
gain, offset and gain correction, averaging, oversampling and decimation; one 2-channel, 12-bit DAC; two analog
comparators with window mode; programmable watchdog timer with separate internal oscillator; accurate internal
oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. Selected
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for on-chip debug and
programming.
The Atmel AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, EDMA controller, event system, interrupt controller, and all peripherals to continue functioning. The
power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the
next TWI, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external
crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external
crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the
asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode. The low power internal 8MHz oscillator allows
very fast start-up time, combined with low power modes.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI interface. A boot loader running in the device can use any interface to
download the application program to the flash memory. By combining an 8/16-bit RISC CPU with In-system, self-
programmable flash, the Atmel AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost
effective solution for many embedded applications.
The XMEGA E devices are supported with a full suite of program and system development tools, including C compilers,
macro assemblers, program debugger/simulators, programmers, and evaluation kits.
XMEGA E [MANUAL] 3
2.1 Block Diagram
Figure 2-1. XMEGA E Block Diagram
PR[0..1] Power Programming, debug, test

Ground External clock / Crystal pins
XTAL1 / Digital function General Purpose I/O
TOSC1 Analog function / Oscillators
XTAL2 /
TOSC2
PORT R (2) Oscillator

Circuits/
Clock
Generation
Real Time Watchdog
Counter Oscillator
EVENT ROUTING NETWORK
DATA BUS Watchdog

Timer
Event System Oscillator

DACA Controller Control VCC
Power
SRAM Supervision
POR/BOD &
PA[0..7] PORT A (8) EDMA Sleep RESET GND
Controller Controller
ACA RESET /
PDI_CLK
Prog/Debug PDI
ADCA BUS Matrix PDI_DATA
Controller
AREFA
VCC/10
OCD
Int. Refs.
Tempref
CPU Interrupt
AREFD Controller
CRC
NVM Controller
Flash EEPROM
PD[0..7] PORT D (8)
TCD5
USARTD0 DATA BUS
EVENT ROUTING NETWORK

USARTC0
TCC4:5
IRCOM
TWIC
SPIC
XCL
PORT C (8)
PC[0..7]
Note: 1. AVCC is only powering the following I/Os and analog functions:
PA0 to PA7, AREF, ADC, DAC, AC0:1, Power Supervision, tempref, VREF, and Watchdog Oscillator.
VCC is powering all other functions and I/Os.
XMEGA E [MANUAL] 4
In Table 2-1 on page 5 a feature summary for the XMEGA E family is shown, split into one feature summary column for
each sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheet
for ordering codes and memory options.
Table 2-1. XMEGA E Feature Summary Overview
Feature Details / sub-family E5
Total 32
Pins, I/O
Programmable I/O pins 26
Program memory (KB) 8 - 32
Boot memory (KB) 2-4
Memory SRAM (KB) 1-4
EEPROM (Bytes) 512
General purpose registers 4
TQFP 32A
Package
QFN /VQFN 32Z
QTouch® Sense channels 56
EDMA Controller Channels 4
Channels 8
Event System QDEC 1
Rotary 1
0.4 - 16MHz XOSC Yes

Crystal Oscillator
32.768 kHz TOSC Yes
8MHz calibrated Yes
32MHz calibrated Yes
Internal Oscillator 128MHz PLL Yes
32.768kHz calibrated Yes
32kHz ULP Yes
TC4 - 16-bit, 4 CC 1
TC5 - 16-bit, 2 CC 2
Hi-Res 1
Timer / Counter
WeX 1
FAULT 2
RTC Yes
BTC0 - 8-bit, 1 CC 1
XMEGA Custom Logic BTC1 - 8-bit, 1 CC 1
LUT, 2-input, one output 2
XMEGA E [MANUAL] 5
Feature Details / sub-family E5
USART 2
Serial Communication
SPI 1
TWI 1
CRC-16 Yes
CRC
CRC-32 Yes
Resolution (bits) 12
Oversampling extra resolution (bits) 4
Sampling speed (kbps) 300

Analog to Digital Converter (ADC)
External inputs per ADC 16
Conversion channels 1
Offset/gain error correction Yes
Averaging (samples) 1 - 1024
Resolution (bits) 12
Digital to Analog Converter (DAC)
Sampling speed (kbps) 1000
Output channels per DAC 2
Analog Comparator (AC) 2
Program and Debug Interface (PDI) PDI Yes
XMEGA E [MANUAL] 6
3. Atmel AVR CPU
3.1 Features
 8/16-bit, high-performance Atmel AVR RISC CPU
 141 instructions
 Hardware multiplier
 32x8-bit registers directly connected to the ALU
 Stack in RAM
 Stack pointer accessible in I/O memory space
 Direct addressing of up to 16MB of program memory and 16MB of data memory
 True 16/24-bit access to 16/24-bit I/O registers
 Efficient support for 8-, 16-, and 32-bit arithmetic
 Configuration change protection of system-critical features
3.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, “PMIC – Interrupts and
Programmable Multilevel Interrupt Controller” on page 132.
3.3 Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For a summary of all AVR instructions, refer to “Instruction Set Summary” on page
432. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 3-1. Block Diagram of the AVR CPU Architecture
XMEGA E MANUAL 7
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM is memory
mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for save storing of nonvolatile data in the program memory.
3.4 ALU - Arithmetic Logic Unit

The arithmetic logic unit supports arithmetic and logic operations between registers or between a constant and a register.
Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose
registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status
register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
3.4.1 Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
 Multiplication of unsigned integers
 Multiplication of signed integers
 Multiplication of a signed integer with an unsigned integer
 Multiplication of unsigned fractional numbers
 Multiplication of signed fractional numbers
 Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
XMEGA E MANUAL 8
3.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
3.6 Instruction Execution Timing

The AVR CPU is clocked by the CPU clock, clkCPU. No internal clock division is used. Figure 3-2 shows the parallel
instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file
concept. This is the basic pipelining concept used to obtain up to 1MIPS/MHz performance with high power efficiency.
Figure 3-2. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4
clkCPU
1st Instruction Fetch

1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute

3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 3-3 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two
register operands is executed and the result is stored back to the destination register.
Figure 3-3. Single Cycle ALU Operation

T1 T2 T3 T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
XMEGA E MANUAL 9
3.7 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 432. This
will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact
code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
3.8 Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
3.9 Register File

The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
 One 8-bit output operand and one 8-bit result input
 Two 8-bit output operands and one 8-bit result input
 Two 8-bit output operands and one 16-bit result input
 One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
XMEGA E MANUAL 10
Figure 3-4. AVR CPU General Purpose Working Registers
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
The register file is located in a separate address space, and so the registers are not accessible as data memory.
3.9.1 The X-, Y-, and Z-registers

Registers R26..R31 have added functions besides their general-purpose usage.
These registers can form 16-bit address pointers for addressing data memory. These three address registers are called
the X-register, Y-register, and Z-register. The Z-register can also be used as an address pointer to read from and/or write
to the flash program memory, signature rows, fuses, and lock bits.
Figure 3-5. The X-, Y-, and Z-registers
Bit (individually) 7 R27 0 7 R26 0

X-register XH XL
Bit (X-register) 15 8 7 0

Y-register YH YL
Bit (Y-register) 15 8 7 0

Z-register ZH ZL
Bit (Z-register) 15 8 7 0
The lowest register address holds the least-significant byte (LSB), and the highest register address holds the most-
significant byte (MSB). In the different addressing modes, these address registers function as fixed displacement,
automatic increment, and automatic decrement (see the “Instruction Set Summary” on page 432 for details).
XMEGA E MANUAL 11
3.10 RAMP and Extended Indirect Registers
In order to access program memory or data memory above 64KB, the address pointer must be larger than 16 bits. This is
done by concatenating one register to one of the X-, Y-, or Z-registers. This register then holds the most-significant byte
(MSB) in a 24-bit address or address pointer.
These registers are available only on devices with external bus interface and/or more than 64KB of program or data
memory space. For these devices, only the number of bits required to address the whole program and data memory
space in the device is implemented in the registers.
3.10.1 RAMPX, RAMPY, and RAMPZ Registers

The RAMPX, RAMPY, and RAMPZ registers are concatenated with the X-, Y-, and Z-registers, respectively, to enable
indirect addressing of the whole data memory space above 64KB and up to 16MB.
Figure 3-6. The Combined RAMPX + X, RAMPY + Y, and RAMPZ + Z Registers
Bit (Individually) 7 0 7 0 7 0
RAMPX XH XL
Bit (X-pointer) 23 16 15 8 7 0
RAMPY YH YL
Bit (Y-pointer) 23 16 15 8 7 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
When reading (ELPM) and writing (SPM) program memory locations above the first 128KB of the program memory,
RAMPZ is concatenated with the Z-register to form the 24-bit address. LPM is not affected by the RAMPZ setting.
3.10.2 RAMPD Register

This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB.
Together, RAMPD and the operand will form a 24-bit address.
Figure 3-7. The Combined RAMPD + K Register
Bit (Individually) 7 0 15 0
RAMPD K
Bit (D-pointer) 23 16 15 0
3.10.3 EIND - Extended Indirect Register

EIND is concatenated with the Z-register to enable indirect jump and call to locations above the first 128KB (64K words)
of the program memory.
Figure 3-8. The Combined EIND + Z Register
EIND ZH ZL
Bit (D-pointer) 23 16 15 8 7 0
XMEGA E MANUAL 12
3.11 Accessing 16-bit Registers
The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be
byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register
using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written
into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the
low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register is
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the
low byte is read. When the high byte is read, it is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing
the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an
atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
3.11.1 Accessing 24- and 32-bit Registers

For 24- and 32-bit registers, the read and write access is done in the same way as described for 16-bit registers, except
there are two temporary registers for 24-bit registers and three for 32-bit registers. The least-significant byte must be
written first when doing a write, and read first when doing a read.
3.12 Configuration Change Protection

System critical I/O register settings are protected from accidental modification. The SPM instruction is protected from
accidental execution, and the LPM instruction is protected when reading the fuses and signature row. This is handled
globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or
execution of protected instructions, are only possible after the CPU writes a signature to the CCP register. The different
signatures are described in the register description.
There are two modes of operation: one for protected I/O registers, and one for the protected instructions, SPM/LPM.
3.12.1 Sequence for Write Operation to Protected I/O Registers

1. The application code writes the signature that enable change of protected I/O registers to the CCP register.
2. Within four instruction cycles, the application code must write the appropriate data to the protected register. Most
protected registers also contain a write enable/change enable bit. This bit must be written to one in the same oper-
ation as the data are written. The protected change is immediately disabled if the CPU performs write operations to
the I/O register or data memory or if the SPM, LPM, or SLEEP instruction is executed.
3.12.2 Sequence for Execution of Protected SPM/LPM

1. The application code writes the signature for the execution of protected SPM/LPM to the CCP register.
2. Within four instruction cycles, the application code must execute the appropriate instruction. The protected change
is immediately disabled if the CPU performs write operations to the data memory or if the SLEEP instruction is
executed.
Once the correct signature is written by the CPU, interrupts will be ignored for the duration of the configuration change
enable period. Any interrupt request (including non-maskable interrupts) during the CCP period will set the
corresponding interrupt flag as normal, and the request is kept pending. After the CCP period is completed, any pending
interrupts are executed according to their level and priority. EDMA requests are still handled, but do not influence the
protected configuration change enable period. A signature written by EDMA is ignored.
XMEGA E MANUAL 13
3.13 Fuse Lock
For some system-critical features, it is possible to program a fuse to disable all changes to the associated I/O control
registers. If this is done, it will not be possible to change the registers from the user software, and the fuse can only be
reprogrammed using an external programmer. Details on this are described in the datasheet module where this feature is
available.
XMEGA E MANUAL 14
3.14 Register Descriptions
3.14.1 CCP – Configuration Change Protection Register
Bit 7 6 5 4 3 2 1 0
+0x04 CCP[7:0]
Read/Write W W W W W W R/W R/W
Initial value 0 0 0 0 0 0 0 0
 Bit 7:0 – CCP[7:0]: Configuration Change Protection Bits

The CCP register must be written with the correct signature to enable change of the protected I/O register or exe-
cution of the protected instruction for a maximum period of four CPU instruction cycles. All interrupts are ignored
during these cycles. After these cycles, interrupts will automatically be handled again by the CPU, and any pend-
ing interrupts will be executed according to their level and priority. When the protected I/O register signature is
written, CCP[0] will read as one as long as the protected feature is enabled. Similarly when the protected
SPM/LPM signature is written, CCP[1] will read as one as long as the protected feature is enabled. CCP[7:2] will
always read as zero. Table 3-1 on page 15 shows the signature for the various modes.
Table 3-1. Modes of CPU Change Protection
Signature Group configuration Description
0x9D SPM Protected SPM/LPM
0xD8 IOREG Protected IO register
3.14.2 RAMPD – Extended Direct Addressing Register

This register is concatenated with the operand for direct addressing (LDS/STS) of the whole data memory space on
devices with more than 64KB of data memory. This register is not available if the data memory, including external
memory, is less than 64KB.
Bit 7 6 5 4 3 2 1 0
+0x08 RAMPD[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
 Bit 7:0 – RAMPD[7:0]: Extended Direct Addressing Bits

These bits hold the MSB of the 24-bit address created by RAMPD and the 16-bit operand. Only the number of bits
required to address the available data memory is implemented for each device. Unused bits will always read as
zero.
3.14.3 RAMPX – Extended X-Pointer Register

This register is concatenated with the X-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. This register is not available if the data memory, including
external memory, is less than 64KB.
Bit 7 6 5 4 3 2 1 0
+0x09 RAMPX[7:0]
XMEGA E MANUAL 15
 Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address Bits
These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of
bits required to address the available data memory is implemented for each device. Unused bits will always read
as zero.
3.14.4 RAMPY – Extended Y-Pointer Register

This register is concatenated with the Y-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. This register is not available if the data memory, including
external memory, is less than 64KB.
Bit 7 6 5 4 3 2 1 0
+0x0A RAMPY[7:0]
 Bit 7:0 – RAMPY[7:0]: Extended Y-pointer Address Bits

These bits hold the MSB of the 24-bit address created by RAMPY and the 16-bit Y-register. Only the number of
bits required to address the available data memory is implemented for each device. Unused bits will always read
as zero.
3.14.5 RAMPZ – Extended Z-Pointer Register

This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. RAMPZ is concatenated with the Z-register when reading
(ELPM) program memory locations above the first 64KB and writing (SPM) program memory locations above the first
128KB of the program memory.
This register is not available if the data memory, including external memory and program memory in the device, is less
than 64KB.
Bit 7 6 5 4 3 2 1 0
+0x0B RAMPZ[7:0]
 Bit 7:0 – RAMPZ[7:0]: Extended Z-pointer Address Bits

These bits hold the MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register. Only the number of
bits required to address the available data and program memory is implemented for each device. Unused bits will
always read as zero.
3.14.6 EIND – Extended Indirect Register

This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP) and call (EICALL) to the
whole program memory space on devices with more than 128KB of program memory. The register should be used for
jumps to addresses below 128KB if ECALL/EIJMP are used, and it will not be used if CALL and IJMP commands are
used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program
memory in the device is less than 128KB.
Bit 7 6 5 4 3 2 1 0
+0x0C EIND[7:0]
XMEGA E MANUAL 16
 Bit 7:0 – EIND[7:0]: Extended Indirect Address Bits
These bits hold the MSB of the 24-bit address created by EIND and the 16-bit Z-register. Only the number of bits
required to access the available program memory is implemented for each device. Unused bits will always read as
zero.
3.14.7 SPL – Stack Pointer Register Low

The SPH and SPL stack pointer pair represent the 16-bit SP value. The SP holds the stack pointer that points to the top
of the stack. After reset, the stack pointer points to the highest internal SRAM address. To prevent corruption when
updating the stack pointer from software, a write to SPL will automatically disable interrupts for the next four instructions
or until the next I/O memory write.
Only the number of bits required to address the available data memory, including external memory, up to 64KB is
implemented for each device. Unused bits will always read as zero.
Bit 7 6 5 4 3 2 1 0
+0x0D SP[7:0]
(1)
Initial Value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Note: 1. Refer to specific device datasheets for exact size.
 Bit 7:0 – SP[7:0]: Stack Pointer Low Byte

These bits hold the LSB of the 16-bit stack pointer (SP).
3.14.8 SPH – Stack Pointer Register High
Bit 7 6 5 4 3 2 1 0
+0x0E SP[15:8]
(1)
Initial value 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Note: 1. Refer to specific device datasheets for the exact size.
 Bit 7:0 – SP[15:8]: Stack Pointer High Byte

These bits hold the MSB of the 16-bit stack pointer (SP).
3.14.9 SREG – Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. For details information about the bits in this register and how they are affected by the different instructions
see “Instruction Set Summary” on page 432.
Bit 7 6 5 4 3 2 1 0
+0x0F I T H S V N Z C
 Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set for interrupts to be enabled. If the global interrupt enable register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. This bit is not
cleared by hardware after an interrupt has occurred. This bit can be set and cleared by the application with the SEI
and CLI instructions, as described in “Instruction Set Summary” on page 432. Changing the I flag through the I/O-
register result in a one-cycle wait state on the access.
XMEGA E MANUAL 17
 Bit 6 – T: Bit Copy Storage
The bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination for the operated
bit. A bit from a register in the register file can be copied into this bit by the BST instruction, and this bit can be cop-
ied into a bit in a register in the register file by the BLD instruction.
 Bit 5 – H: Half Carry Flag
The half carry flag (H) indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic.
 Bit 4 – S: Sign Bit, S = N V
The sign bit is always an exclusive or between the negative flag, N, and the two’s complement overflow flag, V.
 Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag (V) supports two’s complement arithmetic.
 Bit 2 – N: Negative Flag
The negative flag (N) indicates a negative result in an arithmetic or logic operation.
 Bit 1 – Z: Zero Flag
The zero flag (Z) indicates a zero result in an arithmetic or logic operation.
 Bit 0 – C: Carry Flag
The carry flag (C) indicates a carry in an arithmetic or logic operation.
XMEGA E MANUAL 18
3.15 Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 Reserved – – – – – – – –
+0x01 Reserved – – – – – – – –
+0x02 Reserved – – – – – – – –
+0x03 Reserved – – – – – – – –
+0x04 CCP CCP[7:0] 15
+0x05 Reserved – – – – – – – –
+0x06 Reserved – – – – – – – –
+0x07 Reserved – – – – – – – –
+0x08 RAMPD RAMPD[7:0] 15
+0x09 RAMPX RAMPX[7:0] 15
+0x0A RAMPY RAMPY[7:0] 16
+0x0B RAMPZ RAMPZ[7:0] 16
+0x0C EIND EIND[7:0] 16
+0x0D SPL SPL[7:0] 17
+0x0E SPH SPH[7:0] 17
+0x0F SREG I T H S V N Z C 17
XMEGA E MANUAL 19
4. Memories
4.1 Features
 Flash program memory
 One linear address space
 In-system programmable
 Self-programming and boot loader support
 Application section for application code
 Application table section for application code or data storage
 Boot section for application code or bootloader code
 Separate read/write protection lock bits for all sections
 Built in fast CRC check of a selectable flash program memory section
 Data memory
 One linear address space
 Single-cycle access from CPU
 SRAM
 EEPROM
 Byte and page accessible
 Memory mapped for direct load and store
 I/O memory
 Configuration and status registers for all peripherals and modules
 Four bit-accessible general purpose registers for global variables or flags
 Bus arbitration
 Deterministic handling of priority between CPU, EDMA controller, and other bus masters
 Separate buses for SRAM, EEPROM, I/O memory, and external memory access
 Simultaneous bus access for CPU and EDMA controller
 Production signature row memory for factory programmed data
 ID for each microcontroller device type
 Serial number for each device
 Calibration bytes for factory calibrated peripherals
 User signature row
 One flash page in size
 Can be read and written from software
 Content is kept after chip erase
4.2 Overview
This section describes the different memory sections. The AVR architecture has two main memory spaces, the program
memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the
program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile
data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces
can be locked for further write and read/write operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
4.3 Flash Program Memory

All XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory
can be accessed for read and write from an external programmer through the PDI or from application software running in
the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section, as shown in Figure 4-1 on page 21. The sizes
XMEGA E MANUAL 20
of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have
different levels of protection. The store program memory (SPM) instruction, used to write to the flash from the application
software, will only operate when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 4-1. Flash Memory Sections

0x000000
Application Flash
Section
Application Table
Flash Section
End Application
Start Boot Loader
Boot Loader Flash
Section
Flashend
4.3.1 Application Section

The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
4.3.2 Application Table Section

The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
4.3.3 Boot Loader Section

While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can initiate programming when executing from this section. When
programming, the CPU is halted, waiting for the flash operation to complete. The SPM instruction can access the entire
flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot
loader lock bits. If this section is not used for boot loader software, application code can be stored here.
XMEGA E MANUAL 21
4.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions such as temperature, voltage
references, etc., refer to the device datasheet.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
4.3.5 User Signature Row

The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
4.4 Fuses and Lockbits

The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure the startup configuration and reset sources such
as brownout detector and watchdog.
The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
4.5 Data Memory

The data memory contains the I/O memory, internal SRAM, EEPROM, and external memory, if available. The data
memory is organized as one continuous memory section, as shown in Figure 4-2 on page 23.
XMEGA E MANUAL 22
Figure 4-2. Data Memory Map
Start/End
Data Memory
Address
0x0000
I/O Memory
(Up to 4KB)
0x1000
EEPROM
(Up to 1KB)
0x2000
Internal SRAM
(Up to 4KB)
I/O memory, EEPROM, and SRAM will always have the same start addresses for all XMEGA devices.
4.6 Internal SRAM

The internal SRAM always starts at hexadecimal address 0x2000. SRAM is accessed by the CPU using the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions.
4.7 EEPROM
All XMEGA devices have EEPROM for nonvolatile data storage. It is addressable in a separate memory mapped space
and accessed in normal data space. The EEPROM supports both byte and page access. EEPROM is accessible using
load and store instructions, allowing highly efficient EEPROM reading and EEPROM buffer loading. EEPROM always
starts at the hexadecimal address 0x1000.
4.8 I/O Memory

The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
4.8.1 General Purpose I/O Registers

The lowest four I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
4.9 Data Memory and Bus Arbitration

Since the data memory is organized as three separate sets of memories, the different bus masters (CPU, EDMA
controller read and EDMA controller write, etc.) can access different memory sections at the same time. See Figure 4-3
on page 24.
XMEGA E MANUAL 23
Figure 4-3. Bus Access
EDMA CPU External

programming
CH0 CH1
CH2 CH3 AVR core OCD PDI
Bus matrix
Event Interrupt
Flash CRC system controller SRAM
Power Oscillator
EEPROM management
USART control
RAM
Timer /
Non-volatile AC SPI Counter
memory
Real Time
ADC TWI Counter
XMEGA
DAC I/O Custom Logic
Peripherals and system modules
4.9.1 Bus Priority

When several masters request access to the same bus, the bus priority is in the following order (from higher to lower
priority):
1. Bus Master with ongoing access.
2. Bus Master with ongoing burst.
1. Alternating EDMA controller read and EDMA controller write when they access the same data memory
section.
3. Bus Master requesting burst access.
1. CPU has priority.
4. Bus Master requesting bus access.
1. CPU has priority.
4.10 Memory Timing

Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (EDMA), new data are available every cycle. EEPROM page load (write) takes
one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
4.11 Device ID and Revision

Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
XMEGA E MANUAL 24
4.12 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism. For details, refer to “Configuration Change
Protection” on page 13.
XMEGA E MANUAL 25
4.13 Register Description – NVM Controller
4.13.1 ADDR0 – Address Register 0

The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value, ADDR. This is used for addressing all NVM
sections for read, write, and CRC operations.
Bit 7 6 5 4 3 2 1 0
+0x00 ADDR[7:0]
 Bit 7:0 – ADDR[7:0]: Address Byte 0

This register gives the address low byte when accessing NVM locations.
Bit 7 6 5 4 3 2 1 0
+0x01 ADDR[15:8]

This register gives the address high byte when accessing NVM locations.
Bit 7 6 5 4 3 2 1 0
+0x02 ADDR[23:16]

This register gives the address extended byte when accessing NVM locations.
4.13.4 DATA0 – Data Register 0

The DATA0, DATA1, and DATA registers represent the 24-bit value, DATA. This holds data during NVM read, write, and
CRC access.
Bit 7 6 5 4 3 2 1 0
+0x04 DATA[7:0]
Initial Value 0 0 0 0 0 0 0 0
 Bit 7:0 – DATA[7:0]: Data Byte 0

This register gives the data value byte 0 when accessing NVM locations.
XMEGA E MANUAL 26
Bit 7 6 5 4 3 2 1 0
+0x05 DATA[15:8]

Bit 7 6 5 4 3 2 1 0
+0x06 DATA[23:16]

4.13.7 CMD – Command Register
Bit 7 6 5 4 3 2 1 0
+0x0A – CMD[6:0]
Read/Write R R/W R/W R/W R/W R/W R/W R/W
 Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
 Bit 6:0 – CMD[6:0]: Command
These bits define the programming commands for the flash. Bit 6 is only set for external programming commands.
See “Memory Programming” on page 411 for programming commands.
4.13.8 CTRLA – Control Register A
Bit 7 6 5 4 3 2 1 0
+0x0B – – – – – – – CMDEX
Read/Write R R R R R R R S
 Bit 7:1 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
 Bit 0 – CMDEX: Command Execute
Setting this bit will execute the command in the CMD register. This bit is protected by the configuration change
protection (CCP) mechanism. Refer to “Configuration Change Protection” on page 13 for details on the CCP.
XMEGA E MANUAL 27
4.13.9 CTRLB – Control Register B
Bit 7 6 5 4 3 2 1 0
+0x0C – – – – – – EPRM SPMLOCK
Read/Write R R R R R R R/W R/W

 Bit 1 – EPRM: EEPROM Power Reduction Mode
Setting this bit enables power saving for the EEPROM. The EEPROM will then be turned off in a manner equiva-
lent to entering sleep mode. If access is required, the bus master will be halted for a time equal to the start-up time
from idle sleep mode.
 Bit 0 – SPMLOCK: SPM Locked
This bit can be written to prevent all further self-programming. The bit is cleared at reset, and cannot be cleared
from software. This bit is protected by the configuration change protection (CCP) mechanism. Refer to “Configura-
tion Change Protection” on page 13 for details on the CCP.
4.13.10 INTCTRL – Interrupt Control Register
Bit 7 6 5 4 3 2 1 0
+0x0D – – – – SPMLVL[1:0] EELVL[1:0]
Read/Write R R R R R/W R/W R/W R/W

 Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the interrupt and select the interrupt level, as described in “PMIC – Interrupts and Programma-
ble Multilevel Interrupt Controller” on page 132. This is a level interrupt that will be triggered only when the
NVMBUSY flag in the STATUS register is set to zero. Thus, the interrupt should not be enabled before triggering
an NVM command, as the NVMBUSY flag will not be set before the NVM command is triggered. The interrupt
should be disabled in the interrupt handler.
 Bit 1:0 – EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM ready interrupt and select the interrupt level, as described in “PMIC – Interrupts
and Programmable Multilevel Interrupt Controller” on page 132. This is a level interrupt that will be triggered only
when the NVMBUSY flag in the STATUS register is set to zero. Thus, the interrupt should not be enabled before
triggering an NVM command, as the NVMNVMBUSY flag will not be set before the NVM command is triggered.
The interrupt should be disabled in the interrupt handler.
XMEGA E MANUAL 28
4.13.11 STATUS – Status Register
Bit 7 6 5 4 3 2 1 0
+0x0F NVMBUSY FBUSY – – – – EELOAD FLOAD
Read/Write R R R R R R R R
 Bit 7 – NVMBUSY: Nonvolatile Memory Busy

The NVMBUSY flag indicates if the NVM (Flash, EEPROM, lock bit) is being programmed. Once an operation is
started, this flag is set and remains set until the operation is completed. The NVMBUSY flag is automatically
cleared when the operation is finished.
 Bit 6 – FBUSY: Flash Busy
The FBUSY flag indicates if a flash programming operation is initiated. Once an operation is started, the FBUSY
flag is set and the application section cannot be accessed. The FBUSY flag is automatically cleared when the
operation is finished.
 Bit 1 – EELOAD: EEPROM Page Buffer Active Loading
The EELOAD flag indicates that the temporary EEPROM page buffer has been loaded with one or more data
bytes. It remains set until an EEPROM page write or a page buffer flush operation is executed. For more details,
see “Flash and EEPROM Programming Sequences” on page 413.
 Bit 0 – FLOAD: Flash Page Buffer Active Loading
The FLOAD flag indicates that the temporary flash page buffer has been loaded with one or more data bytes. It
remains set until an application page write, boot page write, or page buffer flush operation is executed. For more
details, see “Flash and EEPROM Programming Sequences” on page 413.
4.13.12 LOCKBITS – Lock Bit Register
Bit 7 6 5 4 3 2 1 0
+0x10 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0]
This register is a mapping of the NVM lock bits into the I/O memory space which enables direct read access from
the application software. Refer to “LOCKBITS – Lock Bit Register” on page 33 for a description.
XMEGA E MANUAL 29
4.14 Register Descriptions – Fuses and Lock Bits
4.14.1 FUSEBYTE1 – Fuse Byte 1
Bit 7 6 5 4 3 2 1 0
+0x01 WDWPER[3:0] WDPER[3:0]
 Bit 7:4 – WDWPER[3:0]: Watchdog Window Timeout Period

These fuse bits are used to set initial value of the closed window for the Watchdog Timer in Window Mode. During
reset these fuse bits are automatically written to the WPER bits Watchdog Window Mode Control Register. Refer
to “WINCTRL – Window Mode Control Register” on page 130 for details.
 Bit 3:0 – WDPER[3:0]: Watchdog Timeout Period
These fuse bits are used to set the initial value of the watchdog timeout period. During reset, these fuse bits are
automatically written to the PER bits in the watchdog control register. Refer to “CTRL – Control Register” on page
129 for details.
Bit 7 6 5 4 3 2 1 0
+0x02 – BOOTRST – – – – BODPD[1:0]
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to one
 Bit 6 – BOOTRST: Boot Loader Section Reset Vector
This fuse can be programmed so the reset vector is pointing to the first address in the boot loader flash section.
The device will then start executing from the boot loader flash section after reset.
Table 4-1. Boot Reset Fuse
BOOTRST Reset address
0 Reset vector = Boot loader reset
1 Reset vector = Application reset (address 0x0000)

one when this register is written.
 Bit 1:0 – BODPD[1:0]: BOD Operation in Power-down Mode
These fuse bits set the BOD operation mode in all sleep modes except idle mode.
For details on the BOD and BOD operation modes, refer to “Brownout Detection” on page 122.
XMEGA E MANUAL 30
Table 4-2. BOD Operation Modes in Sleep Modes
BODPD[1:0] Description
00 Reserved
01 BOD enabled in sampled mode
10 BOD enabled continuously
11 BOD disabled
Bit 7 6 5 4 3 2 1 0
+0x04 – – – RSTDISBL STARTUPTIME[1:0] WDLOCK –

 Bit: 4 – RSTDISBL: External Reset Disable
This fuse can be programmed to disable the external reset pin functionality. When this is done, pulling the reset pin
low will not cause an external reset. A reset is required before this bit will be read correctly after it is changed.
 Bit 3:2 – STARTUPTIME[1:0]: Start-up Time
These fuse bits can be used to set at a programmable timeout period from when all reset sources are released
until the internal reset is released from the delay counter. A reset is required before these bits will be read correctly
after they are changed.
The delay is timed from the 1kHz output of the ULP oscillator. Refer to “Reset Sequence” on page 121 for details.
Table 4-3. Start-up Time
STARTUPTIME[1:0] 1kHz ULP oscillator cycles
00 64
01 4
10 Reserved
11 0
 Bit 1 – WDLOCK: Watchdog Timer Lock

The WDLOCK fuse can be programmed to lock the watchdog timer configuration. When this fuse is programmed,
the watchdog timer configuration cannot be changed, and the ENABLE bit in the watchdog CTRL register is auto-
matically set at reset and cannot be cleared from the application software. The WEN bit in the watchdog WINCTRL
register is not set automatically, and needs to be set from software. A reset is required before this bit will be read
correctly after it is changed.
Table 4-4. Watchdog Timer Lock
WDLOCK Description
0 Watchdog timer locked for modifications
1 Watchdog timer not locked
XMEGA E MANUAL 31
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to one
Bit 7 6 5 4 3 2 1 0
+0x05 – – BODACT[1:0] EESAVE BODLEVEL[2:0]
Initial value 1 1 – – – – – –

 Bit 5:4 – BODACT[1:0]: BOD Operation in Active Mode
These fuse bits set the BOD operation mode when the device is in active and idle modes. For details on the BOD
and BOD operation modes, refer to “Brownout Detection” on page 122.
Table 4-5. BOD Operation Modes in Active and Idle Modes
BODACT[1:0] Description
00 Reserved
01 BOD enabled in sampled mode
10 BOD enabled continuously
11 BOD disabled
 Bit 3 – EESAVE: EEPROM Preserved through the Chip Erase

A chip erase command will normally erase the flash, EEPROM, and internal SRAM. If this fuse is programmed, the
EEPROM is not erased during chip erase. This is useful if EEPROM is used to store data independently of the
software revision.
Table 4-6. EEPROM Preserved Through Chip Erase
EESAVE Description
0 EEPROM is preserved during chip erase
1 EEPROM is erased during chip erase
Changes to the EESAVE fuse bit take effect immediately after the write timeout elapses. Hence, it is possible to
update EESAVE and perform a chip erase according to the new setting of EESAVE without leaving and reentering
programming mode.
 Bit 2:0 – BODLEVEL[2:0]: Brownout Detection Voltage Level
These fuse bits sets the BOD voltage level. Refer to “Reset Sequence” on page 121 for details. For BOD level
nominal values, see Table 9-2 on page 123.
XMEGA E MANUAL 32
Bit 7 6 5 4 3 2 1 0
+0x06 FDACT5 FDACT4 VALUE[5:0]
 Bit 7 – FDACT5: Fault Detection Action Timer/Counter 5

This fuse sets the fault detection action on Px4 and Px5 port pins during the Reset phase, which are the default
output pins for timer/counter 5 output compare channels. Table 4-7 on page 33 shows the possible settings.
 Bit 6 – FDACT4: Fault Detection Action Timer/Counter 4
This fuse sets the fault detection action on Px0 to Px3 port pins during the Reset phase, which are the default out-
put pins for timer/counter 4 output compare channels. Table 4-7 on page 33 shows the possible settings.
Table 4-7. Fault Detection Action
FDACT Description
In reset state and until a timer/counter compare channel is enabled, the port pins are forced to the value set in
0
the corresponding VALUEn fuse.
1 Default I/O pin configuration.
 Bit 5:0 – VALUE[5:0]: Port Pin n Value

These fuses select the value that will be output on the corresponding port pin when an emergency fault occurs and
if the corresponding FDACT fuse is set.
Table 4-8. Port Pin Value
VALUEn Description
0 The corresponding port pin output value is set to 1 (high level).
1 The corresponding port pin output value is set to 0 (low level).
4.14.6 LOCKBITS – Lock Bit Register
Bit 7 6 5 4 3 2 1 0
+0x07 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0]
 Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section

These lock bits control the software security level for accessing the boot loader section. The BLBB bits can only be
written to a more strict locking. Resetting the BLBB bits is possible only by executing a chip erase command.
XMEGA E MANUAL 33
Table 4-9. Boot Lock Bit for the Boot Loader Section
BLBB[1:0] Group configuration Description
11 NOLOCK No lock – no restrictions for SPM and (E)LPM accessing the boot loader section.
10 WLOCK Write lock – SPM is not allowed to write the boot loader section.
Read lock – (E)LPM executing from the application section is not allowed to
read from the boot loader section.
01 RLOCK
If the interrupt vectors are placed in the application section, interrupts are
disabled while executing from the boot loader section.
Read and write lock – SPM is not allowed to write to the boot loader section, and
(E)LPM executing from the application section is not allowed to read from the
00 RWLOCK boot loader section.
If the interrupt vectors are placed in the application section, interrupts are
disabled while executing from the boot loader section.
 Bit 5:4 – BLBA[1:0]: Boot Lock Bit Application Section

These lock bits control the software security level for accessing the application section. The BLBA bits can only be
written to a more strict locking. Resetting the BLBA bits is possible only by executing a chip erase command.
Table 4-10. Boot Lock Bit for the Application Section
BLBA[1:0] Group configuration Description
11 NOLOCK No Lock - no restrictions for SPM and (E)LPM accessing the application section.
10 WLOCK Write lock – SPM is not allowed to write the application section.
Read lock – (E)LPM executing from the boot loader section is not allowed to
read from the application section.
01 RLOCK
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
Read and write lock – SPM is not allowed to write to the application section, and
(E)LPM executing from the boot loader section is not allowed to read from the
00 RWLOCK application section.
 Bit 3:2 – BLBAT[1:0]: Boot Lock Bit Application Table Section

These lock bits control the software security level for accessing the application table section for software access.
The BLBAT bits can only be written to a more strict locking. Resetting the BLBAT bits is possible only by executing
a chip erase command.
XMEGA E MANUAL 34
Table 4-11. Boot Lock Bit for the Application Table Section
BLBAT[1:0] Group configuration Description
No lock – no restrictions for SPM and (E)LPM accessing the application table
11 NOLOCK
section.
10 WLOCK Write lock – SPM is not allowed to write the application table
Read lock – (E)LPM executing from the boot loader section is not allowed to
read from the application table section.
01 RLOCK
Read and write lock – SPM is not allowed to write to the application table
section, and (E)LPM executing from the boot loader section is not allowed to
00 RWLOCK read from the application table section.
 Bit 1:0 – LB[1:0]: Lock Bits(1)

These lock bits control the security level for the flash and EEPROM during external programming. These bits are
writable only through an external programming interface. Resetting the lock bits is possible only by executing a
chip erase command. All other access; using the TIF and OCD, is blocked if any of the Lock Bits are written to 0.
These bits do not block any software access to the memory.
Table 4-12. Lock Bit Protection Mode
LB[1:0] Group configuration Description
11 NOLOCK3 No lock – no memory locks enabled.
Write lock – programming of the flash and EEPROM is disabled for the
10 WLOCK programming interface. Fuse bits are locked for write from the programming
interface.
Read and write lock – programming and read/verification of the flash and
00 RWLOCK EEPROM are disabled for the programming interface. The lock bits and fuses
are locked for read and write from the programming interface.
Note: 1. Program the Fuse bits and Boot Lock bits before programming the Lock Bits.
XMEGA E MANUAL 35
4.15 Register Description – Production Signature Row
Note: The initial value for these registers will read as 0xFFFF if production calibration is not done.
4.15.1 RCOSC8M – Internal 8MHz Oscillator Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x00 RCOSC8M[7:0]
Initial value x x x x x x x x
 Bit 7:0 – RCOSC8M[7:0]: Internal 8MHz Oscillator Calibration Value

This byte contains the oscillator calibration value for the internal 8MHz oscillator. Calibration of the oscillator is per-
formed during production testing of the device. During reset, this value is automatically loaded into calibration
register for the 8MHz oscillator. Refer to “RC8MCAL – 8MHz Internal Oscillator Calibration Register” on page 108
for more details.
4.15.2 RCOSC32K – Internal 32.768kHz Oscillator Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x02 RCOSC32K[7:0]
 Bit 7:0 – RCOSC32K[7:0]: Internal 32.768kHz Oscillator Calibration Value

This byte contains the oscillator calibration value for the internal 32.768kHz oscillator. Calibration of the oscillator
is performed during production testing of the device. During reset, this value is automatically loaded into the cali-
bration register for the 32.768kHz oscillator. Refer to “RC32KCAL – 32kHz Oscillator Calibration Register” on page
107 for more details.
4.15.3 RCOSC32M – Internal 32MHz Oscillator Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x03 RCOSC32M[7:0]
 Bit 7:0 – RCOSC32M[7:0]: Internal 32MHz Oscillator Calibration Value

This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is
performed during production testing of the device. During reset, this value is automatically loaded into calibration
register B for the 32MHz DFLL. Refer to “CALB – DFLL Calibration Register B” on page 109 for more details.
4.15.4 RCOSC32MA – Internal 32MHz RC Oscillator Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x04 RCOSC32MA[7:0]
 Bit 7:0 – RCOSC32MA[7:0]: Internal 32MHz Oscillator Calibration Value

This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is
performed during production testing of the device. During reset, this value is automatically loaded into calibration
register A for the 32MHz DFLL. Refer to “CALA – DFLL Calibration Register A” on page 109 for more details.
XMEGA E MANUAL 36
4.15.5 LOTNUM0 – Lot Number Register 0
LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4, and LOTNUM5 contain the lot number for each device.
Together with the wafer number and wafer coordinates, this gives a serial number for the device.
Bit 7 6 5 4 3 2 1 0
+0x08 LOTNUM0[7:0]
 Bit 7:0 – LOTNUM0[7:0]: Lot Number Byte 0

This byte contains byte 0 of the lot number for the device.
Bit 7 6 5 4 3 2 1 0
+0x09 LOTNUM1[7:0]

Bit 7 6 5 4 3 2 1 0
+0x0A LOTNUM2[7:0]

4.15.8 LOTNUM3- Lot Number Register 3
Bit 7 6 5 4 3 2 1 0
+0x0B LOTNUM3[7:0]

Bit 7 6 5 4 3 2 1 0
+0x0C LOTNUM4[7:0]

XMEGA E MANUAL 37
Bit 7 6 5 4 3 2 1 0
+0x0D LOTNUM5[7:0]

4.15.11 WAFNUM – Wafer Number Register
Bit 7 6 5 4 3 2 1 0
+0x10 WAFNUM[7:0]
Initial value 0 0 0 x x x x x
 Bit 7:0 – WAFNUM[7:0]: Wafer Number

This byte contains the wafer number for each device. Together with the lot number and wafer coordinates, this
gives a serial number for the device.
4.15.12 COORDX0 – Wafer Coordinate X Register 0

COORDX0, COORDX1, COORDY0, and COORDY1 contain the wafer X and Y coordinates for each device. Together
with the lot number and wafer number, this gives a serial number for each device.
Bit 7 6 5 4 3 2 1 0
+0x12 COORDX0[7:0]
 Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 0

This byte contains byte 0 of wafer coordinate X for the device.
4.15.13 COORDX1 – Wafer Coordinate X Register 1
Bit 7 6 5 4 3 2 1 0
+0x13 COORDX1[7:0]
 Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 1

This byte contains byte 1 of wafer coordinate X for the device.
4.15.14 COORDY0 – Wafer Coordinate Y Register 0
Bit 7 6 5 4 3 2 1 0
+0x14 COORDY0[7:0]
 Bit 7:0 – COORDY0[7:0]: Wafer Coordinate Y Byte 0

This byte contains byte 0 of wafer coordinate Y for the device.
XMEGA E MANUAL 38
4.15.15 COORDY1 – Wafer Coordinate Y Register 1
Bit 7 6 5 4 3 2 1 0
+0x15 COORDY1[7:0]
 Bit 7:0 – COORDY1[7:0]: Wafer Coordinate Y Byte 1

This byte contains byte 1 of wafer coordinate Y for the device.
4.15.16 ROOMTEMP – Room Temperature Register

.
Bit 7 6 5 4 3 2 1 0
+0x1E ROOMTEMP[7:0]
 Bit 7:0 – ROOMTEMP[7:0]: Room Temperature Value

This byte contains the room temperature value.
4.15.17 HOTTEMP – Hot Temperature Register

.
Bit 7 6 5 4 3 2 1 0
+0x1F HOTTEMP[7:0]
 Bit 7:0 – HOTTEMP[7:0]: Hot Temperature Value

This byte contains the hot temperature value.
4.15.18 ADCACAL0 – ADCA Calibration Register 0

ADCACAL0 and ADCACAL1 contain the calibration value for the analog- to -digital converter A (ADCA). Calibration is
done during production testing of the device. The calibration bytes are not loaded automatically into the ADC calibration
registers, and so this must be done from software.
Bit 7 6 5 4 3 2 1 0
+0x20 ADCACAL0[7:0]
 Bit 7:0 – ADCACAL0[7:0]: ADCA Calibration Byte 0

This byte contains byte 0 of the ADCA calibration data, and must be loaded into the ADCA CALL register.
4.15.19 ADCACAL1 – ADCA Calibration Register 1
Bit 7 6 5 4 3 2 1 0
+0x21 ADCACAL1[7:0]
 Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1

This byte contains byte 1 of the ADCA calibration data.
XMEGA E MANUAL 39
4.15.20 ACACURRCAL – ACA Current Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x28 ACACURRCAL[7:0]
Initial value 0 0 0 0 x x x x
 Bit 7:0 – ACACURRCAL[7:0]: ACA Current Calibration Byte

This byte contains the ACA current source calibration value, and must be loaded into the ACA CURRCALIB
register.
4.15.21 TEMPSENSE2 – Temperature Sensor Calibration Register 2

TEMPSENSE2 and TEMPSENSE3 contain the 12-bit ADCA value from a temperature measurement done with the
internal temperature sensor. The measurement is done in production testing at room temperature, and can be used for
single- or multi-point temperature sensor calibration.
Bit 7 6 5 4 3 2 1 0
+0x2C TEMPSENSE2[7:0]
 Bit 7:0 – TEMPSENSE2[7:0]: Temperature Sensor Calibration Byte 2

This byte contains the byte 2 of the temperature measurement.
Bit 7 6 5 4 3 2 1 0
+0x2D TEMPSENSE3[7:0]

This byte contains byte 3 of the temperature measurement.

TEMPSENSE0 and TEMPSENSE1 contain the 12-bit ADCA value from a temperature measurement done with the
internal temperature sensor. The measurement is done in production testing at 85C, and can be used for single- or
multi-point temperature sensor calibration.
Bit 7 6 5 4 3 2 1 0
+0x2E TEMPSENSE0[7:0]

This byte contains the byte 0 of the temperature measurement.
XMEGA E MANUAL 40
Bit 7 6 5 4 3 2 1 0
+0x2F TEMPSENSE1[7:0]

This byte contains byte 1 of the temperature measurement.
4.15.25 DACA0OFFCAL – DACA Offset Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x30 DACA0OFFCAL[7:0]
 Bit 7:0 – DACA0OFFCAL[7:0]: DACA0 Offset Calibration Byte

This byte contains the offset calibration value for channel 0 in the digital -to -analog converter A (DACA). Calibra-
tion is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 0 offset calibration register, so this must be done from software.
4.15.26 DACA0GAINCAL – DACA Gain Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x31 DACA0GAINCAL[7:0]
 Bit 7:0 – DACA0GAINCAL[7:0]: DACA0 Gain Calibration Byte

This byte contains the gain calibration value for channel 0 in the digital -to -analog converter A (DACA). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC gain
calibration register, so this must be done from software.
4.15.27 DACA1OFFCAL – DACA Offset Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x34 DACA1OFFCAL[7:0]
 Bit 7:0 – DACA1OFFCAL[7:0]: DACA1 Offset Calibration Byte

This byte contains the offset calibration value for channel 1 in the digital- to -analog converter A (DACA). Calibra-
tion is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 1 offset calibration register, so this must be done from software.
XMEGA E MANUAL 41
4.15.28 DACA1GAINCAL – DACA Gain Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x35 DACA1GAINCAL[7:0]
 Bit 7:0 – DACA1GAINCAL[7:0]: DACA1 Gain Calibration Byte

This byte contains the gain calibration value for channel 1 in the digital -to- analog converter A (DACA). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC chan-
nel 1 gain calibration register, so this must be done from software.
4.16 Register Description – General Purpose I/O Memory
4.16.1 GPIORn – General Purpose I/O Register n
Bit 7 6 5 4 3 2 1 0
+n GPIORn[7:0]
These are general purpose registers that can be used to store data, such as global variables and flags, in the bit-
accessible I/O memory space.
4.17 Register Descriptions – MCU Control
4.17.1 DEVID0 – Device ID Register 0

DEVID0, DEVID1, and DEVID2 contain the byte identification that identifies each microcontroller device type.
For details on the actual ID, refer to the device datasheet.
Bit 7 6 5 4 3 2 1 0
+0x00 DEVID0[7:0]
 Bit 7:0 – DEVID0[7:0]: Device ID Byte 0

Byte 0 of the device ID. This byte will always be read as 0x1E. This indicates that the device is manufactured by
Atmel.
Bit 7 6 5 4 3 2 1 0
+0x01 DEVID1[7:0]
Initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
 Bit 7:0 – DEVID[7:0]: Device ID Byte 1

Byte 1 of the device ID indicates the flash size of the device.
XMEGA E MANUAL 42
Bit 7 6 5 4 3 2 1 0
+0x02 DEVID2[7:0]
Initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
 Bit 7:0 – DEVID2[7:0]: Device ID Byte 2

Byte 2 of the device ID indicates the device number.
4.17.4 REVID – Revision ID
Bit 7 6 5 4 3 2 1 0
+0x03 – – – – REVID[3:0]
Initial value 0 0 0 0 1/0 1/0 1/0 1/0

These bits are unused and reserved for future use.
 Bit 3:0 – REVID[3:0]: Revision ID
These bits contains the device revision. 0 = A, 1 = B, and so on.
4.17.5 ANAINIT – Analog Initialization Register
Bit 7 6 5 4 3 2 1 0
+0x07 – – – – STARTUPDLYD[1:0] STARTUPDLYA[1:0]

 Bit 3:2 / 1:0 – STARTUPDLYx[1:0]: Analog Start-up Delay
Setting these bits enables sequential start of the internal components used for the ADC, DAC, and analog compar-
ator with the main input/output connected to that port. When this is done, the internal components, such as voltage
reference and bias currents, are started sequentially when the module is enabled. This reduces the peak current
consumption during startup of the module. For maximum effect, the start-up delay should be set so that it is larger
than 0.5µs.
Table 4-13. Analog Start-up Delay
STARTUPDLYx Group configuration Description
00 NONE Direct startup
11 2CLK 2 * ClkPER
10 8CLK 8 * ClkPER
11 32CLK 32 * ClkPER
XMEGA E MANUAL 43
4.17.6 EVSYSLOCK – Event System Lock Register
Bit 7 6 5 4 3 2 1 0
+0x08 – – – EVSYS1LOCK – – – EVSYS0LOCK
Read/Write R R R R/W R R R R/W

 Bit 4 – EVSYS1LOCK: Event System Channel 4-7 Lock
Setting this bit will lock all registers in the event system related to event channels 4 to 7against for further modifica-
tion. The following registers in the event system are locked: CH4MUX, CH4CTRL, CH5MUX, CH5CTRL,
CH6MUX, CH6CTRL, CH7MUX, and CH7CTRL. This bit is protected by the configuration change protection
mechanism. For details, refer to “Configuration Change Protection” on page 13.
 Bit 0 – EVSYS0LOCK: Event System Channel 0-3 Lock
Setting this bit will lock all registers in the event system related to event channels 0 to 3 for against further modifi-
cation. The following registers in the event system are locked: CH0MUX, CH0CTRL, CH1MUX, CH1CTRL,
CH2MUX, CH2CTRL, CH3MUX, and CH3CTRL. This bit is protected by the configuration change protection
mechanism. For details, refer to “Configuration Change Protection” on page 13.
4.17.7 WEXLOCK – Waveform Extension Lock Register
Bit 7 6 5 4 3 2 1 0
+0x09 – – – – – – – WEXCLOCK
Read/Write R R R R R R R R/W

 Bit 0 – WEXCLOCK: Waveform Extension Port C Lock
Setting this bit will lock all protected registers in the WEX module extension on port C, against further modification.
This bit is protected by the configuration change protection mechanism.
For details, refer to “Configuration Change Protection” on page 13.
XMEGA E MANUAL 44
4.17.8 FAULTLOCK – Fault Extension Lock Register
Bit 7 6 5 4 3 2 1 0
+0x03 – – – – – – FAULTC5LOCK FAULTC4LOCK

 Bit 1 – FAULTC5LOCK: Fault Lock for Timer/Counter 5 on Port C
Setting this bit will lock all protected registers in the FAULT module extension on port C of the timer/counter 5,
against further modification. This bit is protected by the configuration change protection mechanism.
For details refer to “Configuration Change Protection” on page 13.
 Bit 0 – FAULTC4LOCK: Fault Lock for Timer/Counter 4 on Port C
Setting this bit will lock all protected registers in the FAULT module extension on port C of the timer/counter 4,
against further modification. This bit is protected by the configuration change protection mechanism.
For details refer to “Configuration Change Protection” on page 13.
XMEGA E MANUAL 45
4.18 Register Summary – NVM Controller
+0x00 ADDR0 Address Byte 0 26

+0x01 ADDR1 Address Byte 1 26
+0x02 ADDR2 Address byte 2 26
+0x03 Reserved - - - - - - - -
+0x04 DATA0 Data byte 0 26
+0x07 Reserved - - - - - - - -
+0x08 Reserved - - - - - - - -
+0x09 Reserved - - - - - - - -
+0x0A CMD - CMD[6:0] 27
+0x0B CTRLA - - - - - - - CMDEX 27
+0x0C CTRLB - - - - - - EPRM SPMLOCK 28
+0x0D INTCTRL - - - - SPMLVL[1:0] EELVL[1:0] 28
+0x0E Reserved - - - - - - - -
+0x0F STATUS NVMBUSY FBUSY - - - - EELOAD FLOAD 29
+0x10 LOCKBITS BLBB1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] 29
4.19 Register Summary – Fuses and Lockbits

+0x00 Reserved - - - - - - - -
+0x01 FUSEBYTE1 WDWPER[3:0] WDPER[3:0] 30
+0x02 FUSEBYTE2 - BOOTRST - - - - BODPD[1:0] 30
+0x03 Reserved - - - - - - - -
+0x04 FUSEBYTE4 - - - RSTDISBL STARTUPTIME[1:0] WDLOCK - 31
+0x05 FUSEBYTE5 - - BODACT[1:0] EESAVE BODLEVEL[2:0] 32
+0x06 FUSEBYTE6 FDACT5 FDACT4 VALUE[5:0] 33
+0x07 LOCKBITS BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] 33
4.20 Register Summary – Production Signature Row

Address Auto Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Page
+0x00 YES RCOSC8M RCOSC8M[7:0] 36

+0x01 Reserved - - - - - - - -
+0x02 YES RCOSC32K RCOSC32K[7:0] 36
+0x03 YES RCOSC32M RCOSC32M[7:0] 36
+0x04 YES RCOSC32MA RCOSC32MA[7:0] 36
+0x05 Reserved - - - - - - - -
+0x06 Reserved - - - - - - - -
+0x07 Reserved - - - - - - - -
+0x08 NO LOTNUM0 LOTNUM0 [7:0] 37
+0x09 NO LOTNUM1 LOTNUM1 [7:0] 37
XMEGA E MANUAL 46
+0x0A NO LOTNUM2 LOTNUM2 [7:0] 37

+0x0B NO LOTNUM3 LOTNUM3 [7:0] 37
+0x0C NO LOTNUM4 LOTNUM4 [7:0] 37
+0x0D NO LOTNUM5 LOTNUM5 [7:0] 38
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
+0x10 NO WAFNUM WAFNUM [7:0] 38
+0x11 Reserved - - - - - - - -
+0x12 NO COORDX0 COORDX0 [7:0] 38
+0x13 NO COORDX1 COORDX1 [7:0] 38
+0x14 NO COORDY0 COORDY0 [7:0] 38
+0x15 NO COORDY1 COORDY1 [7:0] 39
+0x16 Reserved - - - - - - - -
+0x17 Reserved - - - - - - - -
+0x18 Reserved - - - - - - - -
+0x19 Reserved - - - - - - - -
+0x1A Reserved - - - - - - - -
+0x1B Reserved - - - - - - - -
+0x1C Reserved - - - - - - - -
+0x1D Reserved - - - - - - - -
+0x1E NO ROOMTEMP ROOMTEMP[7:0] 39
+0x1F NO HOTTEMP HOTTEMP[7:0] 39
+0x20 NO ADCACAL0 ADCACAL0[7:0] 39
+0x21 NO ADCACAL1 ADCACAL1[7:0] 39
+0x22 Reserved - - - - - - - -
+0x23 Reserved - - - - - - - -
+0x24 Reserved - - - - - - - -
+0x25 Reserved - - - - - - - -
+0x26 Reserved - - - - - - - -
+0x27 Reserved - - - - - - - -
+0x28 NO ACACURRCAL ACACURRCAL[7:0] 40
+0x29 Reserved - - - - - - - -
+0x2A Reserved - - - - - - - -
+0x2B Reserved - - - - - - - -
+0x2C NO TEMPSENSE2 TEMPSENSE2[7:0] 40
+0x2D NO TEMPSENSE3 - - - - TEMPSENSE3[11:8] 40
+0x2E NO TEMPSENSE0 TEMPSENSE0[7:0] 40
+0x2F NO TEMPSENSE1 - - - - TEMPSENSE1[11:8] 41
+0x30 NO DACA0OFFCAL DACA0OFFCAL[7:0] 41
+0x31 NO DACA0GAINCAL DACA0GAINCAL[1:0] 41
+0x32 Reserved - - - - - - - -
+0x33 Reserved - - - - - - - -
XMEGA E MANUAL 47
+0x34 NO DACA1OFFCAL DACA1OFFCAL[7:0] 41

+0x35 NO DACA1GAINCAL DACA1GAINCAL[7:0] 42
+0x36 Reserved - - - - - - - -
+0x37 Reserved - - - - - - - -
+0x38 Reserved - - - - - - - -
+0x39 Reserved - - - - - - - -
+0x3A Reserved - - - - - - - -
+0x3B Reserved - - - - - - - -
+0x3C Reserved - - - - - - - -
+0x3D Reserved - - - - - - - -
+0x3E Reserved - - - - - - - -
+0x3F Reserved - - - - - - - -
XMEGA E MANUAL 48
4.21 Register Summary – General Purpose I/O Registers
+0x00 GPIOR0 GPIOR0[7:0] 42

+0x04 Reserved - - - - - - - -
+0x05 Reserved - - - - - - - -
+0x06 Reserved - - - - - - - -
+0x07 Reserved - - - - - - - -
+0x08 Reserved - - - - - - - -
+0x09 Reserved - - - - - - - -
+0x0A Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
4.22 Register Summary – MCU Control

+0x00 DEVID0 DEVID0[7:0] 42

+0x03 REVID - - - - REVID[7:0] 43
+0x04 Reserved - - - - - - - -
+0x05 Reserved - - - - - - - -
+0x06 Reserved - - - - - - - -
+0x07 ANAINIT - - - - STARTUPDLYD[1:0] STARTUPDLYA[1:0] 43
+0x08 EVSYSLOC - - - EVSYS1LOCK - - - EVSYS0LOCK 44
+0x09 WEXLOCK - - - - - - - WEXCLOCK 44
+0x0A FAULTLOCK - - - - - - FAULTC5LOC FAULTC4LOC 45
+0x0B Reserved - - - - - - - -
4.23 Interrupt Vector Summary
Table 4-14. NVM Interrupt vectors and their word offset address from NVM controller interrupt base.
Offset Source Interrupt description
0x00 EE_vect Nonvolatile memory EEPROM interrupt vector
0x02 SPM_vect Nonvolatile memory SPM interrupt vector
XMEGA E MANUAL 49
5. EDMA – Enhanced Direct Memory Access
5.1 Features
 The EDMA Controller allows data transfers with minimal CPU intervention
 From data memory to data memory
 From data memory to peripheral
 From peripheral to data memory
 From peripheral to peripheral
 Four peripheral EDMA channels with separate:
 Transfer triggers
 Interrupt vectors
 Addressing modes
 Data match
 Up to two standard EDMA with separate:
 Transfer triggers
 Interrupt vectors
 Addressing modes
 Data search
 Programmable channel priority
 From 1 byte to 128KB of data in a single transaction
 Up to 64K block transfer with repeat
 1 or 2 bytes burst transfers
 Multiple addressing modes
 Static
 Increment
 Optional reload of source and destination address at the end of each
 Burst
 Block
 Transaction
 Optional Interrupt on end of transaction
 Optional connection to CRC Generator module for CRC on EDMA data
5.2 Overview
The enhanced direct memory access (EDMA) controller can transfer data between memories and peripherals, and thus
off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four EDMA channels enable up to four independent and parallel transfers.
The EDMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the EDMA controller can handle automatic transfer of data to/from
communication modules. The EDMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1 or 2 bytes. They build block transfers of configurable size from 1 byte to
64KB. Repeat option can be used to repeat once each block transfer for single transactions up to 128KB. Source and
destination addressing can be static or incremental. Automatic reload of source and/or destination addresses can be
done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events
can trigger EDMA transfers.
The EDMA channels have individual configuration and control settings. This includes source or destination pointers,
transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when
a transaction is complete or when the EDMA controller detects an error on an EDMA channel.
To have flexibility in transfers, channels can be interlinked so that the second takes over the transfer when the first is
finished.
XMEGA E MANUAL 50
The EDMA controller supports extended features such as double buffering, data match for peripherals or data search for
SRAM or EEPROM.
The EDMA controller supports two types of channel. Each channel type can be selected individually.
5.2.1 Peripheral Channel

In peripheral channel configuration, a channel enables transfer from specific peripheral address to memory locations or
from memory locations to specific peripheral address. The specific peripheral address is provided by the selected trigger
source. In this configuration, up to four independent and parallel transfers are supported. The size of a block transfer is
limited to 256 bytes for each peripheral channel. The repeat feature enables transfers up to 512 bytes. Two channels can
be interlinked so that the second takes over the transfer when the first is finished.
In data match configuration, the EDMA compares the input data from the programmable source with a pattern contained
in an EDMA register. As example, this mode can be used with serial peripherals to enable the transfer only if specific
character/frame is received (ex. serial address field). Optionally, the transfer counter can be enabled to allow recognition
within a window.
Figure 5-1. EDMA – Full Peripheral Channel Mode Overview
EDMA Peripheral Channel 0

CTRLA EDMA trigger / Event
CTRLB
Enable TRIGSRC
Burst Arbitration R/W Master port
Control Logic
Arbiter
TRFCNT (PeriphAddr) Read
Repeat MEMADDR BUF
Write
EDMA Peripheral Channel 1 Bus
matrix
EDMA Peripheral Channel 2 CTRL
EDMA Peripheral Channel 3
Slave port
Read /
Write
5.2.2 Standard Channel

To create a standard channel, the EDMA controller uses resources of two peripheral channels. Register addresses are
re-arranged and the standard channel 0 is configured with resources found in the peripheral channels 0 and 1, the
standard channel 2 is configured with resources found in the peripheral channels 2 and 3.
In standard channel configuration, any transfer type can be enabled. The trigger source, source address and destination
address are independent and separately programmable. The size of a block transfer can be set up to 65536 bytes (64K)
for each standard channel. The repeat option enables transfers up to 131072 bytes (128K). Two channels can be
interlinked so that the second takes over the transfer when the first is finished, and vice versa.
In data search configuration, the EDMA searches for the data (8-bit or 16-bit) contained in an EDMA register within a
memory buffer. On a match, the source address register will provide to the user the intended data pointer.
XMEGA E MANUAL 51
Figure 5-2. EDMA – Full Standard Channel Mode Overview
EDMA Standard Channel 0

EDMA trigger / Event
CTRLA
CTRLB
TRIGSRC Arbitration R/W Master port
Enable
Burst Arbiter
Control Logic Read
TRFCNT SRCADDR BUF

Repeat DESTADDR Write
Bus
matrix
EDMA Standard Channel 2 CTRL
Slave port
Read /
Write
5.2.3 Channel Combinations

The EDMA can be configured in four different modes (CHMODE bits in “CTRL – Control Register ” on page 59) mixing
peripheral and standard channels.
Figure 5-3. EDMA – Channel Modes

1 standard channel 2 peripheral channels
4 peripheral channels 2 peripheral channels 1 standard channel 2 standard channels
PER 0123 Conf. STD0 Conf. STD2 Conf. STD02 Conf.
Per-Ch0 Per- Ch0

Std-Ch0 Std-Ch0
Per-Ch1 Per- Ch1
Per-Ch2 Per- Ch2
Std-Ch2 Std-Ch2
Per-Ch3 Per- Ch3
5.3 EDMA Transaction
Figure 5-4. EDMA Transaction
2-byte burst mode Repeat Block transfer Block size: 6 bytes
Trig. (Trig.) (Trig.) (Trig.) (Trig.) (Trig.) TRNIF
Burst transfer Burst transfer Burst transfer
Block transfer Block transfer
EDMA transaction
XMEGA E MANUAL 52
A complete EDMA read and write operation between memories and/or peripherals is called an EDMA transaction. A
transaction is done in data blocks, and the size of the transaction (number of bytes to transfer) is selectable from
software and controlled by the block size and repeat bit settings. Each block transfer is divided into bursts.
5.3.1 Block Transfer and Repeat Block Transfer

The size of the block transfer is set by the block transfer count register, and can be programmed from 1 byte to 64KB. If
the double buffering is not used, a repeat option can be enabled to repeat once a block transfer before a transaction is
complete.
5.3.2 Burst Transfer

Since the AVR CPU and EDMA controller use the same data buses, a block transfer is divided into smaller burst
transfers. The burst transfer is selectable to 1 or 2 bytes. This means that if a transfer request is pending and the EDMA
acquires the data bus, it will occupy the bus until all bytes in the burst are transferred.
A bus arbiter controls when the EDMA controller and the AVR CPU can use the bus. The CPU always has priority, and
so as long as the CPU requests access to the bus, any pending burst transfer must wait. The CPU requests bus access
when it executes an instruction that writes or reads data to SRAM, I/O memory or to the EEPROM. For more details on
memory access bus arbitration refer to.
5.4 Transfer Triggers

EDMA transfers can be started only when an EDMA transfer trigger is detected. A transfer trigger can be set-up by
software, from an external trigger source (peripheral), or from an event. There are dedicated source trigger selections for
each EDMA channel. The available trigger sources may vary from device to device, depending on the modules or
peripherals that exist in the device. Using a transfer trigger for a module or peripherals that does not exist will have no
effect. For a list of all transfer triggers of peripheral channels, refer to Table 5-8 on page 64 and for standard channels,
refer to Table 5-18 on page 71.
By default, a trigger starts a block transfer operation. When the block transfer is complete, the channel is automatically
disabled. When enabled again, the channel will wait for the next block transfer trigger.
It is possible to select the trigger to start a burst transfer instead of a block transfer. This is called a single-shot transfer,
and for each trigger only one burst is transferred. In this configuration, when block repeat transfer mode is enabled (and
if no double buffering mode), the next block transfer does not require a transfer trigger. It will start as soon as the
previous block is done.
If a source generates a transfer trigger during an ongoing transfer, this will be kept pending, and the transfer can start
when the ongoing one is done. Only one pending transfer can be kept, and so if the trigger source generates more
transfer triggers when one is already pending, these will be lost.
In peripheral channel configuration, setting the trigger source automatically determines the peripheral register address
and the data transfer direction.
5.5 Addressing and Transfer Count
5.5.1 Addressing in Peripheral Channel Configuration

In peripheral channel configuration, the memory address for an EDMA transfer can either be static or automatically
incremented and the 16-bit peripheral address is automatically incremented if 2-byte burst is set. When memory address
increment is used, the default behavior is to update the memory address after each access. The original memory
address is stored by the EDMA controller, and can be individually configured to be reloaded at the following points:
 End of each burst transfer
 End of each block transfer
 End of transaction
 Never reloaded
XMEGA E MANUAL 53
When 2-byte burst option is used to address 16-bit peripheral, the first byte access of the burst will be for the low byte of
the 16-bit register (ex: ACDA.CH0RESL) the second, for the high byte (ex: ACDA.CH0RESH). The 1-byte burst option is
reserved for 8-bit peripherals.
5.5.2 Addressing in Standard Channel Configuration

In standard channel configuration, the source and destination address for an EDMA transfer can either be static or
automatically incremented, with individual selections for source and destination. When address increment is used, the
default behavior is to update the address after each access. The original source and destination addresses are stored by
the EDMA controller, and so the source and destination addresses can be individually configured to be reloaded at the
following points:
 End of each burst transfer
 End of each block transfer
 End of transaction
 Never reloaded
5.5.3 Transfer Count Reload

When the channel transaction complete interrupt flag is set, the transfer counter is reloaded. The transfer counter is not
reloaded when the channel error interrupt flag is set.
5.6 Priority Between Channels

If several channels request a data transfer at the same time, a priority scheme is available to determine which channel is
allowed to transfer data. Application software can decide whether one or more channels should have a fixed priority or if
a round robin scheme should be used. A round robin scheme means that the channel that last transferred data will have
the lowest priority.
5.7 Double Buffering

Two channels can be interlinked so that two different EDMA transactions can be serialized, the second takes over the
transfer when the first is finished.
 This can leave time for the application to process the data transferred by the first channel, prepare fresh data
buffers, and set up the channel registers again while the second channel is working
 This can link two different processes as data match on serial peripheral and once matching (ex: address
recognition) a transfer of valid data is enabled
This is referred to as double buffering or chained transfers. The first channel is referred as the first software enabled
channel within the pair of linked channels.
DBUFMODE bits in CRTL register (CTRL.DBUFMODE) configure the double buffer modes. At channel level, the
REPEAT bit (CTRLA.REPEAT) of the second channel enables the link. The end of transfer (without error) on the first
channel enables the second channel (CTRLA.REPEAT).
Note that double buffering is incompatible with repeat block transfer.
XMEGA E MANUAL 54
Figure 5-5. EDMA - Double Buffer Modes Versus Channel Modes
CHMODE=00 CHMODE=01 CHMODE=10 CHMODE=11

(PER0123) (STD0) (STD2) (STD02)
Per-Ch0 Per-Ch0
Std-Ch0 Std-Ch0
m ble
m ble
e
e
Per-Ch1 Per-Ch1
od
od
DBUFMODE=01
er u
er u
ff d o
ff d o
Per-Ch2 Per-Ch2 (BUF01)
bu no
bu no
Std-Ch2 Std-Ch2
Per-Ch3 Per-Ch3
Per-Ch0 Per-Ch0
Std-Ch0 Std-Ch0
m ble
m ble
Per-Ch1
e
Per-Ch1 DBUFMODE=10
od
od
er u
er u
ff d o
ff do
bu no
bu no
Std-Ch2 Std-Ch2
Per-Ch3 Per-Ch3
Per-Ch0 Per-Ch0
Std-Ch0 Std-Ch0
Per-Ch1 Per-Ch1 DBUFMODE=11
Std-Ch2 Std-Ch2
Per-Ch3 Per-Ch3
5.8 Data Processing
5.8.1 Data Match

This feature is available only for peripheral channels doing transfer from peripheral to memory locations.
To avoid unnecessary data transfers between peripherals and data memory, the EDMA controller has a built-in data
match feature. In this mode, the memory address register is set to store the data used during match operation. The
operation stops on data match or if the transfer count reaches zero. If the block transfer counter is programmed with
zero, then the data match is in free running mode and stopped when a match occurs. In case of no match an abort could
be necessary.
If a data match occurs, the corresponding peripheral channel is disabled and optionally a transaction complete interrupt
is generated. To know the true matched data in Mask-match or OR-match setting, the matched data is updated in the
corresponding EDMA register. Note that the un-matched data are lost.
If the block transfer counter is used and no data match is detected, then the channel is disabled, the transfer counter is
reloaded and optionally an error interrupt is generated.
Repeat block transfer mode is unavailable in data match operation.
XMEGA E MANUAL 55
Figure 5-6. EDMA – Data Match
“Mask-Match” (DP1) serialized

t-1 t t+1
(1-byte burst length) 8-bit input

from peripheral
- - - -  time
st t
1 occurrence of ((peripheral _data & mask ) == (data & mask)) = Match
t
Update : data <= peripheral _data
“OR-Match” (DP2) serialized

t-1 t t+1

from peripheral
- - - -  time
st t t
1 occurrence of either (peripheral _data == data 1) or (peripheral _data == data 2) = Match
t
Update: data1 <= peripheral _data
“2-byte -Match” (DP3)

t-1 t t+1 t+2
serialized
from peripheral
- - -   time
t
st
1 occurrence of ((peripheral _data , peripheral _data t+1 == (data1 , data 2)) = Match
t
data1 = peripheral_data
t+1
data2 = peripheral_data
t-1 t t+1
serialized
(2-byte burst length) 16 -bit input
from peripheral
- -  time
st t
1 occurrence of ((peripheral _data == (data 1, data 2)) = Match
t
data1 = ( lsb ) peripheral _data
t
data2 = (msb) peripheral_data
5.8.2 Data Search

This feature is only available for standard channels.
To off-load the CPU, the EDMA controller has a built-in data search feature. In this mode, the destination address
register is set to store the bytes used for searching while the source address register is set to store the first address of
the memory buffer to scan. The data search operation stops on match or if the transfer count reaches zero. If the block
transfer counter is programmed with zero, then the data search is in free running mode and stopped when a match
occurs. In case on no match, an abort could be necessary.
If a data match occurs, the corresponding standard channel is disabled and optionally a transaction complete interrupt is
generated. To know the true matched data in Mask-match or OR-match setting, the matched data is updated in the
corresponding EDMA register. The source address register can be used to compute the data pointer.
If the block transfer counter is used and no data match is detected, then the channel is disabled, the transfer counter is
reloaded and optionally an error interrupt is generated.
Repeat block transfer mode is unavailable in data search operation.
In this mode, it is recommended to configure the increment mode and no reload mode for source address.
XMEGA E MANUAL 56
Figure 5-7. EDMA – Data Search
Search progression (INC mode)

“Mask-Search” (DP1)
[ 0] [1] [2] [3] [4] [5] [6] [7] [8]
(1-byte burst length) mem_buf [ ] - - - -  ptr
1 s t occurrence of ((mem_buf [n] & mask) == (data & mask)) = Match Pointer position on match
Update : data <= mem _buf [4 ]

“OR-Search” (DP2)
[ 0] [1] [2] [3] [4] [5] [6] [7] [8]
(1-byte burst length) mem_buf [ ] - - - -  ptr
1s t occurrence of either (mem_buf [n] == data 1) or (mem_buf [n] == data 2) = Match Pointer position on match
Update : data1 <= mem _buf [4 ]
“2-byte -Search” (DP3) Search progression (INC mode)

[ 0] [1] [2] [3] [4] [5] [6] [7] [8]
(1-byte burst length) mem_buf [ ] - - -   ptr
1s t occurrence of ((mem_buf [n], mem_buf [n+1]) == (data1 , data 2)) = Match Pointer position on match
data1 = mem _buf [3 ]

data2 = mem _buf [4 ]

[0] [1] [2] [3] [ 4]
(2-byte burst length) mem_buf [ ] -- --  Ptr ( *)
st
1 occurrence of (mem_buf [2]) == (data1 , data2)) = Match Pointer position on match
data1 = ( lsb ) mem _buf [2 ]

data2 = (msb) mem _buf [2 ]
*
( )
16-bit data pointer
5.9 Error Detection

The EDMA controller can detect erroneous operation. Error conditions are detected individually for each EDMA channel,
and the error conditions are:
 Write to EEPROM locations
 Reading EEPROM when the EEPROM is off (sleep entered)
 EDMA controller or a busy channel is disabled in software during a transfer
5.10 Software Reset

Both the EDMA controller and an EDMA channel can be reset from the user software. When the EDMA controller is
reset, all registers associated with the EDMA controller, including channels, are cleared. A software reset can be done
only when the EDMA controller is disabled.
When an EDMA channel is reset, all registers associated with the EDMA channel are cleared. A software reset can be
done only when the EDMA channel is disabled.
XMEGA E MANUAL 57
5.11 Protection
In order to enable a safe operation:
 The channel mode bits (CTRL.CHMODE) are protected against user modification when the EDMA controller is
enabled (ENABLE=1)
 Some channel bits and registers are protected against user modification during a transaction (CTRL.ENABLE=1):
 REPEAT and SINGLE bits in CTRLA register
 ADDCTRL (SRCADDCRTL) and DESTADDCTRL registers
 ADDR (SRCADDR) and DESTADDR 16-bit registers
 TRFCNTL (TRFCNT) and TRFCNTH registers.
Note that TRFREQ bit in CTRLA register and TRIGSRC register are not protected.
5.12 Interrupts
The EDMA controller can generate interrupts when an error is detected on an EDMA channel or when a transaction is
complete for an EDMA channel. Each EDMA channel has a separate interrupt vector, and there are different interrupt
flags for error and transaction complete.
XMEGA E MANUAL 58
5.13 Register Description – EDMA Controller
5.13.1 CTRL – Control Register
Bit 7 6 5 4 3 2 1 0
+0x00 ENABLE RESET CHMODE[1:0] DBUFMODE[1:0] PRIMODE[1:0]
 Bit 7 – ENABLE: Enable

Setting this bit enables the EDMA controller. If the EDMA controller is enabled and this bit is written to zero, the
ENABLE bit is not cleared before the internal transfer buffer is empty, and the EDMA data transfer is aborted.
 Bit 6 – RESET: Software Reset
Writing a one to RESET will be ignored as long as EDMA is enabled (ENABLE = 1). The software reset re-initial-
izes the controller and the channel registers. This bit can be set only when the EDMA controller is disabled
(ENABLE = 0).
 Bit 5:4 – CHMODE[1:0]: Channel Mode
These bits set the channel in standard or peripheral mode, according to Table 5-1 on page 59.
Table 5-1. Channel Configuration Settings
CMODE[1:0] Group configuration Description Channel number
00 PER0123 Four peripheral channels 0, 1, 2, 3
One standard channel 0

01 STD0
Two peripheral channels 2, 3
Two peripheral channels 0, 1

10 STD2
One standard channel 2
11 STD02 Two standard channels 0, 2
This field can be set only when the EDMA controller is disabled (ENABLE = 0).
 Bit 3:2 – DBUFMODE[1:0]: Double Buffer Mode
These bits enable the double buffer on the different channels according to Table 5-2 on page 59.
Table 5-2. EDMA Double Buffer Settings
DBUFMODE[1:0] Group configuration Description
00 DISABLED No double buffer enabled
01 BUF01 Double buffer enabled on peripheral channels 0 and 1 (if exist)
10 BUF23 Double buffer enabled on peripheral channels 2 and 3 (if exist)
- If CHMOD = 00:
Double buffer enabled on peripheral channels 0
and 1 and also on peripheral channels 2 and 3
11 BUF0123
- If CHMOD ! = 00:
Double buffer enabled on channels 0 and 2
(irrespective of the channel configuration)
XMEGA E MANUAL 59
In buffer modes, REPEAT bit of each channel controls the link (ex: to set-up a link from CHx to CHy, REPEAT bit of CHy
must be set).
There are no predefined channels order in the double buffer mode. The first channel that is enabled by software starts
first and, at the end of its transaction, it enables the second channel for a new transaction if the corresponding REPEAT
bit is set (hardware setting of CTRLA.ENABLE bit).
 Bit 1:0 – PRIMODE[1:0]: Priority Mode
These bits determine the internal channel priority according to Table 5-3 on page 60.
Table 5-3. EDMA Channel Priority Settings
PRIMODE[1:0] Group Configuration Description
00 RR0123 Round robin
01 RR123 Channel0 > Round robin (channel 1, 2, and 3)
10 RR23 Channel0 > Channel1 > Round robin (channel 2 and 3)
11 CH0123 Channel0 > Channel1 > Channel2 > Channel3
5.13.2 INTFLAGS – Interrupt Status Flags Register
Bit 7 6 5 4 3 2 1 0
+0x03 CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNIF CH2TRNIF CH1TRNIF CH0TRNIF
 Bit 7:4 – CHnERRIF: Channel n Error Interrupt Flag

If an error condition is detected on EDMA channel n, the CHnERRIF flag will be set. Writing a one to this bit loca-
tion will clear the flag.
These flags are duplicated in each CTRLB channel register.
 Bit 3:0 – CHnTRNIF: Channel n Transaction Complete Interrupt
When a transaction on channel n has been completed, the CHnTRFIF flag will be set. Writing a one to this bit loca-
tion will clear the flag.
These flags are duplicated in each CTRLB channel register.
5.13.3 STATUS –Status Register
Bit 7 6 5 4 3 2 1 0
+0x04 CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND
 Bit 7:4 – CHnBUSY: Channel n Busy

When channel n starts an EDMA transaction, the CHnBUSY flag will be read as one. This flag is automatically
cleared when the EDMA channel is disabled, when the channel n transaction complete interrupt flag is set, or if the
EDMA channel n error interrupt flag is set.
 Bit 3:0 – CHnPEND: Channel n Pending
If a block transfer is pending on EDMA peripheral channel n high, the CHnPEND flag will be read as one. This flag
is automatically cleared when the block transfer starts or if the transfer is aborted.
XMEGA E MANUAL 60
5.13.4 TEMP – Temporary Register
Bit 7 6 5 4 3 2 1 0
+0x06 TEMP[7:0]
 Bit 7:0 – TEMP[7:0]: Temporary Bits

This register is used when reading 16-bit registers in the EDMA controller. The high byte of the 16-bit register is
stored here when the low byte is read by the CPU. This register can also be read and written from the user soft-
ware. Reading and writing 16- bit registers requires special attention.
For details, refer to “Accessing 16-bit Registers” on page 13.
5.14 Register Description – Peripheral Channel
Bit 7 6 5 4 3 2 1 0
+0x00 ENABLE RESET REPEAT TRFREQ – SINGLE – BURSTLEN
Read/Write R/W R/W R/W R/W R R/W R R/W
 Bit 7 – ENABLE: Channel Enable

Setting this bit enables the peripheral channel. This bit is automatically cleared when the transaction is completed.
If the peripheral channel is enabled and this bit is written to zero, the channel is disabled between bursts and the
transfer is aborted.
Setting this bit will reset the peripheral channel. It can only be set when the peripheral channel is disabled
(CTRLA.ENABLE = 0). Writing a one to this bit will be ignored as long as the peripheral channel is enabled
(CHEN=1). This bit is automatically cleared when reset is completed.
 Bit 5 – REPEAT: Repeat Mode
Setting this bit enables the repeat mode. The repeat mode enables a “Repeat Block Transfer” if there is no double
buffering mode. Else this bit enables the link for the buffer mode and it is cleared by hardware at the end of the first
block transfer. A write to this bit will be ignored while the channel is enabled.
 Bit 4 – TRFREQ: Transfer Request
Setting this bit requests a data transfer on the peripheral channel and acts as a software trigger. This bit is auto-
matically cleared at the beginning of the data transfer. Writing this bit does not have any effect unless the
peripheral channel is enabled.
 Bit 2 – SINGLE: Single-Shot Data Transfer
Setting this bit enables the single-shot mode. The peripheral channel will then do a burst transfer of BURSTLEN
bytes on the transfer trigger. A write to this bit will be ignored while the channel is enabled.
 Bit 0 – BURSTLEN: Burst Length
This bit defines the peripheral channel burst length according to Table 5-4 on page 62.
This bit cannot be changed if the channel is busy.
XMEGA E MANUAL 61
Table 5-4. Peripheral Channel Burst Length
BURSTLEN Group configuration Description
00 1BYTE 1 byte burst
01 2BYTE 2 bytes burst
Bit 7 6 5 4 3 2 1 0
+0x01 CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0]
Read/Write R R R/W R/W R/W R/W R/W R/W
 Bit 7 – CHBUSY - Busy

When the peripheral channel starts an EDMA transaction, the BUSY flag will be read as one. This flag is automat-
ically cleared when the EDMA channel is disabled, when the channel transaction complete interrupt flag is set or
when the channel error interrupt flag is set.
 Bit 6 – CHPEND - Pending
If a block transfer is pending on the peripheral channel, the PEND flag will be read as one. This flag is automati-
cally cleared when the transfer starts or if the transfer is aborted.
 Bit 5 – ERRIF - Error Interrupt Flag
If an error condition is detected on the peripheral channel, the ERRIF flag will be set and the optional interrupt is
generated.
Since the peripheral channel error interrupt shares the interrupt address with the peripheral channel n transaction
complete interrupt, ERRIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing
a one to this location.
 Bit 4 – TRNIF - Transaction Complete Interrupt Flag
When a transaction on the peripheral channel has been completed, the TRNIF flag will be set and the optional
interrupt is generated. When repeat block transfer is not enabled, the transaction is completed and TRNIFR is set
after the block transfer. Else, TRNIF is also set after the last block transfer.
Since the peripheral channel transaction n complete interrupt shares the interrupt address with the peripheral
channel error interrupt, TRNIF will not be cleared when the interrupt vector is executed. This flag is cleared by writ-
ing a one to this location.
 Bit 3:2 – ERRINTLVL[1:0]: Channel Error Interrupt Level
These bits enable the interrupt for EDMA channel transfer errors and select the interrupt level, as described in
“PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will trig-
ger for the conditions when ERRIF is set.
 Bit 1:0 – TRNINTLVL[1:0]: Channel Transaction Complete Interrupt Level
These bits enable the interrupt for EDMA channel transaction completes and select the interrupt level, as
described in “PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled inter-
rupt will trigger for the conditions when TRNIF is set.
XMEGA E MANUAL 62
5.14.3 ADDCTRL – Address Control Register
Bit 7 6 5 4 3 2 1 0
+0x02 - - RELOAD[1:0] - DIR[2:0]
Read/Write R R R/W R/W R R/W R/W R/W

 Bit 5:4 – RELOAD[1:0]: Memory Address Reload
These bits decide the memory address reload according to Table 5-5 on page 63.
A write to these bits is ignored while the channel is busy.
Table 5-5. Memory Address Reload Settings
RELOAD[1:0] Group configuration Description
00 NONE No reload performed.
01 BLOCK Memory address register is reloaded with initial value at end of each block transfer.
10 BURST Memory address register is reloaded with initial value at end of each burst transfer.
11 TRANSACTION Memory address register is reloaded with initial value at end of each transaction.
 Bit 2:0 – DIR[2:0]: Memory Address Mode
These bits decide the memory address mode, according to Table 5-6 on page 63 and Table 5-7 on page 63.
These bits cannot be changed if the channel is busy.
Table 5-6. Memory Address Mode Settings – Transfer Memory to Peripheral
DIR[2:0] Group configuration Description
000 FIXED Fixed memory address
001 INC Increment
010 – Reserved
011 – Reserved
1xx – Reserved
Table 5-7. Memory Address Mode Settings – Transfer Peripheral to Memory
000 FIXED Fixed memory address
001 INC Increment
010 – Reserved
XMEGA E MANUAL 63
011 – Reserved
“Mask-Match” (1 byte)
- data: ADDRL register
100 DP1
- mask: ADDRH register (active bit-mask=1)
Note: Only available in 1-byte burst length mode
“OR-Match” (1 byte)
- data1: ADDRL register
101 DP2 OR
- data2: ADDRH register
“2-byte-Match” (two consecutive bytes)

- data1 (1st data or lsb) in DESTADDRL register
110 DP3
followed by
- data2 (2nd data or msb) in DESTADDRH register.
111 – Reserved
5.14.4 TRIGSRC – Trigger Source Register
Bit 7 6 5 4 3 2 1 0
+0x04 TRIGSRC[7:0]
 Bit 7:0 – TRIGSRC[7:0]: Peripheral Channel Trigger Source Select

These bits select which trigger source is used for triggering a transfer on the EDMA channel. Some modules or
peripherals are not available as trigger source for EDMA peripheral channels. Other codes than those of Table 5-8
on page 64 will have no effect.
If the interrupt flag related to the trigger source is cleared or the interrupt level enabled so that an interrupt is trig-
gered, the EDMA request will be lost. Since an EDMA request can clear the interrupt flag, interrupts can be lost.
Note: For most trigger sources, the request is cleared by accessing a register belonging to the peripheral with the request. Refer to the different peripheral
chapters for description on how requests are generated and cleared.
Table 5-8. Trigger Codes for EDMA Peripheral Channels
TRIGSRC[7:0] Group configuration Description
0x10 ADCA(1) ADCA EDMA triggers base value

(1)
0x15 DACA DACA EDMA triggers base value
0x4A SPIC SPI C EDMA triggers base value
0x4C USARTC0 USART C0 EDMA triggers base value
0x6C USARTD0 USART D0 EDMA triggers base value
Note: 1. It is recommended to set BURST2 configuration when reading or writing 16-bits registers.
XMEGA E MANUAL 64
Table 5-9. EDMA Trigger Source Offset Values for ADC Triggers
TRIGSRC offset value Group configuration Description
ADC channel 0
+0x00 CH0 - transfer direction: peripheral to memory
- EDMA reads CH0RES register
Table 5-10. EDMA Trigger Source Offset Values for DAC Triggers
DAC channel 0
+0x00 CH0 - transfer direction: memory to peripheral
- EDMA writes CH0DATA register
DAC channel 1
+0x01 CH1 - transfer direction: memory to peripheral
- EDMA writes CH1DATA register
Table 5-11. EDMA Trigger Source Offset Values for USART Triggers
Receive complete
+0x00 RXC - transfer direction: peripheral to memory
- EDMA reads DATA register
Data register empty

+0x01 DRE - transfer direction: memory to peripheral
- EDMA writes DATA register
Table 5-12. EDMA Trigger Source Offset Values for SPI Triggers
Transfer complete in standard mode or receive complete in

double buffer mode
+0x00 IFRXC
- transfer direction: peripheral to memory
- EDMA reads DATA register
Transfer complete in standard mode or data register empty in

double buffer mode
+0x01 IFDRE
- transfer direction: memory to peripheral
- EDMA writes DATA register
XMEGA E MANUAL 65
5.14.5 TRFCNT – Block Transfer Count Register
TRFCNT defines the number of bytes in a block transfer. The value of TRFCNT is decremented after each byte read by
the EDMA channel.
When TRFCNT reaches zero, the register is reloaded with the last value written to it.
Bit 7 6 5 4 3 2 1 0
+0x06 TRFCNT[7:0]
 Bit 7:0 – TRFCNT[7 :0]: Block Transfer Count

The default value of this register is 0x01. If in transfer mode the user writes 0x00 to this register and fires an EDMA
trigger, EDMA will perform 256 transfers. If this register is set to 0x00 in data match mode, the operation will have
no count limit and will run up to a match occurs.
5.14.6 ADDRL – Memory Address Register Low

ADDRL and ADDRH represent the 16-bit value ADDR, which is the memory address in a transaction executed by a
peripheral channel. ADDRH is the most significant byte in the register. ADDR may be automatically incremented based
on settings in the DIR bits in “ADDCTRL – Address Control Register” on page 63.
In data match mode, ADDR is used for data to recognize, according to the Table 5-7 on page 63.
Bit 7 6 5 4 3 2 1 0
+0x08 ADDR[7:0]
 Bit 7:0 – ADDR[7 :0]: Memory Address Low Byte

These bits hold the low-byte of the 16-bit memory address.
5.14.7 ADDRH – Memory Address Register High
Bit 7 6 5 4 3 2 1 0
+0x09 ADDR[15:8]
 Bit 7:0 – ADDR[15:8]: Memory Address High Byte

These bits hold the high-byte of the 16-bit memory address.
XMEGA E MANUAL 66
5.15 Register Description – Standard Channel
Bit 7 6 5 4 3 2 1 0
+0x00 ENABLE RESET REPEAT TRFREQ - SINGLE - BURSTLEN
Read/Write R/W R/W R/W R/W R R/W R R/W
 Bit 7 – ENABLE: Channel Enable

Setting this bit enables the standard channel. This bit is automatically cleared when the transaction is completed. If
the standard channel is enabled and this bit is written to zero, the channel is disabled between bursts, and the
transfer is aborted.
Setting this bit will reset the standard channel. It can only be set when the standard channel is disabled
(CTRLA.ENABLE=0). Writing a one to this bit will be ignored as long as the standard channel is enabled
(CTRLA.ENABLE=1). This bit is automatically cleared when reset is completed.
 Bit 5 – REPEAT: Repeat Mode
Setting this bit enables the repeat mode. The repeat mode enables a “Repeat Block Transfer” if there is no double
buffering mode. Else this bit enables the link for the buffer mode and it is cleared by hardware at the end of the first
block transfer. A write to this bit will be ignored while the channel is enabled.
 Bit 4 – TRFREQ: Transfer Request
Setting this bit requests a data transfer on the standard channel and acts as a software trigger. This bit is automat-
ically cleared at the beginning of the data transfer. Writing this bit does not have any effect unless the standard
channel is enabled.
 Bit 2 – SINGLE: Single-Shot Data transfer
Setting this bit enables the single-shot mode. The standard channel will then do a burst transfer of BURSTLEN
bytes on the transfer trigger. A write to this bit will be ignored while the channel is enabled.
 Bit 0 – BURSTLEN: Burst Length
This bit defines the standard channel burst length according to Table 5-13 on page 67.
This bit cannot be changed if the channel is busy.
Table 5-13. Standard Channel Burst Length
BURSTLEN Group configuration Description
00 1BYTE 1 byte burst
01 2BYTE 2 bytes burst
XMEGA E MANUAL 67
Bit 7 6 5 4 3 2 1 0
+0x01 CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0]
Read/Write R R R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0 0
 Bit 7 – CHBUSY - Channel Busy

When the standard channel starts an EDMA transaction, the CHBUSY flag will be read as one. This flag is auto-
matically cleared when the EDMA channel is disabled, when the channel transaction complete interrupt flag is set
or when the channel error interrupt flag is set.
 Bit 6 – CHPEND - Channel Pending
If a block transfer is pending on the standard channel, the CHPEND flag will be read as one. This flag is automati-
cally cleared when the transfer starts or if the transfer is aborted.
 Bit 5 – ERRIF - Error Interrupt Flag
If an error condition is detected on the standard channel, the ERRIF flag will be set and the optional interrupt is
generated.
Since the standard channel error interrupt shares the interrupt address with the peripheral channel n transaction
complete interrupt, ERRIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing
a one to this location.
 Bit 4 – TRNIF - Transaction Complete Interrupt Flag
When a transaction on the standard channel has been completed, the TRNIF flag will be set and the optional inter-
rupt is generated. When repeat block transfer is not enabled, the transaction is completed and TRNIFR is set after
the block transfer. Else, TRNIF is also set after the last block transfer.
Since the standard channel transaction n complete interrupt shares the interrupt address with the peripheral chan-
nel error interrupt, TRNIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing a
one to this location.
 Bit 3:2 – ERRINTLVL[1:0]: Channel Error Interrupt Level
These bits enable the interrupt for EDMA channel transfer errors and select the interrupt level, as described in
ger for the conditions when ERRIF is set.
 Bit 1:0 – TRNINTLVL[1:0]: Channel Transaction Complete Interrupt Level
These bits enable the interrupt for EDMA channel transaction completes and select the interrupt level, as
described in “PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled inter-
rupt will trigger for the conditions when TRNIF is set.
5.15.3 SRCADDCTRL – Source Address Control Register
Bit 7 6 5 4 3 2 1 0
+0x02 - - SRCRELOAD[1:0] - SRCDIR[2:0]

 Bit 5:4 – SRCRELOAD[1:0]: Source Address Reload
These bits decide the source address reload according to Table 5-14 on page 69. A write to these bits is ignored
while the channel is busy.
XMEGA E MANUAL 68
Table 5-14. Source Address Reload Settings
SRCRELOAD[1:0] Group configuration Description
Source address register is reloaded with initial value at end of each block
01 BLOCK
transfer.
Source address register is reloaded with initial value at end of each burst
10 BURST
transfer.
Source address register is reloaded with initial value at end of each

11 TRANSACTION
transaction.
 Bit 2:0 – SRCDIR[2:0]: Source Address Mode
These bits decide the source address mode, according to Table 5-15 on page 69.
Table 5-15. Source Address Mode Settings
SRCDIRD[2:0] Group configuration Description
000 FIXED Fixed address
001 INC Increment
010 - Reserved
011 - Reserved
1xx - Reserved
5.15.4 DESTADDCTRL – Destination Address Control Register
Bit 7 6 5 4 3 2 1 0
+0x03 - - DESTRELOAD[1:0] - DESTDIR[2:0

 Bit 5:4 – DESTRELOAD[1:0]: Destination Address Reload
These bits decide the destination address reload according to Table 5-16 on page 70.
A write to these bits is ignored while the channel is busy.
XMEGA E MANUAL 69
Table 5-16. EDMA Channel Source Address Reload Settings
DESTRELOAD[1:0] Group configuration Description
Destination address register is reloaded with initial value at end of each

01 BLOCK
block transfer.

10 BURST
burst transfer.

11 TRANSACTION
transaction.
 Bit 2:0 – DESTDIR[2:0]: Destination Address Mode
These bits decide the destination address mode, according to Table 5-17 on page 70.
Table 5-17. Destination Address Mode Settings
DESTDIR[1:0] Group configuration Description
000 FIXED Fixed address
001 INC Increment
010 - Reserved
011 - Reserved
“Mask-Search” (1 byte)
- data: DESTADDRL register
100 DP1
- mask: DESTADDRH register (active bit-mask=1)
“OR-Search” (1 byte)
- data1: DESTADDRL register
101 DP2 OR
- data2: DESTADDRH register
“2-byte-Search” (two consecutive bytes)

- data1 (1st data or lsb) in DESTADDRL register
110 DP3
followed by
- data2 (2nd data or msb) in DESTADDRH register.
111 - Reserved
XMEGA E MANUAL 70
5.15.5 TRIGSRC – Trigger Source Register
Bit 7 6 5 4 3 2 1 0
+0x04 TRIGSRC[7:0]
 Bit 7:0 – TRIGSRC[7:0]: Trigger Source Select

These bits select which trigger source is used for triggering a transfer on the EDMA standard channel. A zero
value means that the trigger source is disabled. Table 5-18 on page 71 shows the peripherals and triggers which
are supported by an EDMA standard channel. For modules or peripherals which do not exist for a device, the
transfer trigger does not exist. Refer to the device datasheet for the list of peripherals available.
If the interrupt flag related to the trigger source is cleared or the interrupt level enabled so that an interrupt is trig-
gered, the EDMA request will be lost. Since an EDMA request can clear the interrupt flag, interrupts can be lost.
Table 5-18. EDMA Trigger Source Base Values for all Modules and Peripherals
TRIGSRC base value Group configuration Description
Software triggers only (see TRFREQ bit in “CTRLA – Control

0x00 OFF
Register A” on page 61)
0x01 SYS Event system EDMA triggers base value
0x10 ADCA ADCA EDMA triggers base value
0x15 DACA DACA EDMA triggers base value
0x40 TCC4 Timer/counter C4 EDMA triggers base value
0x46 TCC5 Timer/counter C5 EDMA triggers base value
0x4A SPIC SPI C EDMA triggers base value
0x4C USARTC0 USART C0 EDMA triggers base value
0x66 TCD5 Timer/counter D5 EDMA triggers base value
0x6C USARTD0 USART D0 EDMA triggers base value
Table 5-19. EDMA Trigger Source Offset Values for ADC Triggers
+0x00 CH0 ADC channel 0
Table 5-20. EDMA Trigger Source Offset Values for DAC Triggers
+0x00 CH0 DAC channel 0
+0x01 CH1 DAC channel 1
XMEGA E MANUAL 71
Table 5-21. EDMA Trigger Source Offset Values for Event System Triggers
+0x00 CH0 Event channel 0
Table 5-22. EDMA Trigger Source Offset Values for Event System Triggers
+0x00 OVF Overflow/underflow
+0x01 ERR Error
+0x02 CCA Compare or capture channel A
+0x03 CCB Compare or capture channel B
+0x04 CCC(1) Compare or capture channel C

(1)
+0x05 CCD Compare or capture channel D
Note: 1. CC channel C and D triggers are available only for timer/counters 4.
Table 5-23. EDMA Trigger Source Offset Values for USART Triggers
+0x00 RXC Receive complete
+0x01 DRE Data register empty
Table 5-24. EDMA Trigger Source Offset Values for SPI Triggers
- Transfer complete in standard mode

+0x00 IFRXC
- Receive complete in double buffer mode
- Transfer complete in standard mode

+0x01 IFDRE
- Data register empty in double buffer mode
The group configuration is the “base_offset;” for example, TCC5_CCA for the timer/counter C5 CC channel A the transfer
trigger.
XMEGA E MANUAL 72
5.15.6 TRFCNTL – Block Transfer Count Register Low
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT defines the number of bytes
in a block transfer. The value of TRFCNT is decremented after each byte read by the EDMA standard channel.
The default value of this 16-bit register is 0x0101 (not 0x0001). If the user writes 0x0000 to this 16-bit register and fires
an EDMA trigger, EDMA will perform 65536 transfers or searches.
When TRFCNT reaches zero, the register is reloaded with the last value written to it.
Bit 7 6 5 4 3 2 1 0
+0x06 TRFCNT[7:0]
 Bit 7:0 – TRFCNT[7:0]: Block Transfer Count Low Byte

These bits hold the low-byte of the 16-bit block transfer count.
5.15.7 TRFCNTH – Block Transfer Count Register High
Bit 7 6 5 4 3 2 1 0
+0x07 TRFCNT [15:8]
 Bit 7:0 – TRFCNT[15:8]: Block Transfer Count High Byte

These bits hold the high-byte of the 16-bit block transfer count.
5.15.8 SRCADDRL – Source Address Register Low

SRCADDRL and SRCADDRH represent the16-bit value SRCADDR, which is the source address in a transaction
executed by a standard channel. SRCADDRH is the most significant byte in the register. SRCADDR may be
automatically incremented based on settings in the SRCDIR bits in “SRCADDCTRL – Source Address Control Register” .
Bit 7 6 5 4 3 2 1 0
+0x08 SRCADDR[7:0]
 Bit 7:0 – SRCADDR[7 :0]: Source Address Low Byte

These bits hold the low-byte of the 16-bit source address.
5.15.9 SRCADDRH – Source Address Register High
Bit 7 6 5 4 3 2 1 0
+0x09 SRCADDR[15:8]
 Bit 7:0 – SRCADDR[15:8]: Source Address High Byte

These bits hold the high-byte of the 16-bit source address.
XMEGA E MANUAL 73
5.15.10 DESTADDRL – Destination Address Register Low
DESTADDRL and DESTADDRH represent the16-bit value DESTADDR, which is the destination address in a transaction
executed by a standard channel. DESTADDRH is the most significant byte in the register. DESTADDR may be
automatically incremented based on settings in the DESTDIR bits in “DESTADDCTRL – Destination Address Control
Register” .
In data search mode, DESTADDR is used for data to recognize according to Table 5-17 on page 70.
Bit 7 6 5 4 3 2 1 0
+0x08 DESTADDR[7:0]
 Bit 7:0 – DESTADDR[7 :0]: Destination Address Low Byte

These bits hold the low-byte of the 16-bit destination address.
5.15.11 DESTADDRH – Destination Address Register High
Bit 7 6 5 4 3 2 1 0
+0x09 DESTADDR[15:8]
 Bit 7:0 – DESTADDR[15:8]: Destination Address High Byte

These bits hold the high-byte of the 16-bit destination address.
XMEGA E MANUAL 74
5.16 Register Summary – EDMA Controller in PER0123 Configuration
+0x00 CTRL ENABLE RESET CHMODE[1:0] DBUFMODE[1:0] PRIMODE[1:0] 59
+0x01 Reserved – – – – – – – –
+0x02 Reserved – – – – – – – –
CH3ERRI CH2ERRI CH2TRNFI

+0x03 INTFLAGS F F
CH1ERRIF CH0ERRIF CH3TRNFIF
F
CH1TRNFIF CH0TRNFIF 60
+0x04 STATUS CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND 60
+0x05 Reserved – – – – – – – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – – – – – – – –
+0x10/0x1F CH0 Register addresses for EDMA peripheral channel 0
5.17 Register Summary – EDMA Controller in STD0 Configuration

+0x01 Reserved – – – – – – – –
+0x02 Reserved – – – – – – – –
CH3ERRI CH2ERRI CH2TRNFI

+0x03 INTFLAGS F F
– CH0ERRIF CH3TRNFIF
F
– CH0TRNFIF 60
+0x04 STATUS CH3BUSY CH2BUSY – CH0BUSY CH3PEND CH2PEND – CH0PEND 60
+0x05 Reserved – – – – – – – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – – – – – – – –
+0x10/0x1F CH0 Register addresses for EDMA standard channel 0
+0x20/0x2F Reserved – – – – – – – –
XMEGA E MANUAL 75
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 bit 0 Page
+0x01 Reserved – – – – – – – –
+0x02 Reserved – – – – – – – –
CH1ERRI
+0x03 INTFLAGS – CH2ERRIF
F
CH0ERRIF – CH2TRNFIF CH1TRNFIF CH0TRNFIF 60
+0x04 STATUS – CH2BUSY CH1BUSY CH0BUSY – CH2PEND CH1PEND CH0PEND 60
+0x05 Reserved – – – – – – – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – – – – – – – –
+0x40/0x4F Reserved – – – – – – – –

+0x01 Reserved – – – – – – – –
+0x02 Reserved – – – – – – – –
+0x03 INTFLAGS – CH2ERRIF – CH0ERRIF – CH2TRNFIF – CH0TRNFIF 60
+0x04 STATUS – CH2BUSY – CH0BUSY – CH2PEND – CH0PEND 60
+0x05 Reserved – – – – – – – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – – – – – – – –
+0x20/0x2F Reserved – – – – – – – –
+0x40/0x4F Reserved – – – – – – – –
XMEGA E MANUAL 76
5.20 Register Summary – EDMA Peripheral Channel
+0x00 CTRLA ENABLE RESET REPEAT TRFREQ – SINGLE – BURSTLEN 61
+0x01 CTRLB CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0] 62
+0x02 ADDCTRL – – RELOAD[1:0] – DIR[2:0] 63
+0x03 Reserved – – – – – – – –
+0x04 TRIGSRC TRIGSRC[7:0] 64
+0x05 Reserved – – – – – – – –
+0x06 TRFCNTL TRFCNT[7:0] 66
+0x07 Reserved – – – – – – – –
+0x08 ADDRL ADDR[7:0] 66
+0x09 ADDRH ADDR[15:8] 66
+0x0A Reserved – – – – – – – –
+0x0B Reserved – – – – – – – –
+0x0C Reserved – – – – – – – –
+0x0D Reserved – – – – – – – –
+0x0E Reserved – – – – – – – –
+0x0F Reserved – – – – – – – –
5.21 Register Summary – EDMA Standard Channel

+0x00 CTRLA ENABLE RESET REPEAT TRFREQ – SINGLE – BURSTLEN 67
+0x01 CTRLB CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0] 68
+0x02 SRCADDCTRL – – SRCRELOAD[1:0] – SRCDIR[2:0] 68
+0x03 DESTADDCTRL – – DESTRELOAD[1:0] – DESTDIR[2:0] 69
+0x04 TRIGSRC TRIGSRC[7:0] 71
+0x05 Reserved – – – – – – – –
+0x06 TRFCNTL TRFCNT[7:0] 73
+0x07 TRFCNTH TRFCNT[15:8] 73
+0x08 SRCADDRL SRCADDR[7:0] 73
+0x09 SRCADDRH SRCADDR[15:8] 73
+0x0A Reserved – – – – – – – –
+0x0B Reserved – – – – – – – –
+0x0C DESTADDRL DESTADDR[7:0] 74
+0x0D DESTADDRH DESTADDR[15:8] 74
+0x0E Reserved – – – – – – – –
+0x0F Reserved – – – – – – – –
XMEGA E MANUAL 77
Table 5-25. EDMA Interrupt Vectors and their Word Offset Addresses from the EDMA Controller Interrupt Base
0x00 CH0_vect EDMA controller channel 0 interrupt vector
XMEGA E MANUAL 78
6. Event System
6.1 Features
 System for direct peripheral-to-peripheral communication and signalling
 Peripherals can directly send, receive, and react to peripheral events
 CPU and EDMA controller independent operation
 100% predictable signal timing
 Short and guaranteed response time
 Eight event channels for up to eight different and parallel signal routings and configurations
 Events can be sent and/or used by most peripherals, clock system, and software
 Additional functions include
 Quadrature decoders with rotary filtering
 Digital filtering of I/O pin state with flexible prescaler clock options
 Simultaneous synchronous and asynchronous events provided to peripheral
 Works in all sleep modes
6.2 Overview
The event system enables direct peripheral-to-peripheral communication and signalling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or EDMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It allows for synchronized timing of actions in several peripheral modules.
The event system enables also asynchronous event routing for instant actions in peripherals.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 6-1 on page 80 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog to digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM) and XMEGA Custom Logic (XCL). It can also be used to trigger EDMA transactions
(EDMA controller). Events can also be generated from software and peripheral clock.
XMEGA E MANUAL 79
Figure 6-1. Event System Overview and Connected Peripherals
CPU / EDMA
Software Controller
Event Routing Network

clkPER
ADC Prescaler
Real Time
Event Counter
AC System
Controller Timer /
Counters
DAC XMEGA
Custom Logic
IRCOM Port Pins
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow up to eight parallel event configurations and routings. The maximum
routing latency of an external synchronous event is two peripheral clock cycles due to re-synchronization, but several
peripherals can directly use the asynchronous event without any clock delay. The event system works in all sleep modes,
but only asynchronous events can be routed in sleep modes where the system clock is not available.
6.3 Events
In the context of the event system, an indication that a change of state within a peripheral has occurred is called an
event. There are three main types of events: signalling events, synchronous data events, and asynchronous data events.
Signalling events only indicate a change of state while data events contain additional information about the event.
The peripheral from which the event originates is called the event generator. Within each peripheral (for example, a
timer/counter), there can be several event sources, such as a timer compare match or timer overflow. The peripheral
using the event is called the event user, and the action that is triggered is called the event action.
Figure 6-2. Example of Event Source, Generator, User, and Action
Event Generator Event User
Timer/Counter ADC
Compare Match
Event Syncsweep
Over-/Underflow
| Routing
Network Single
Conversion
Error
Event Action Selection
Event Source Event Action
Events can also be generated manually in software.
XMEGA E MANUAL 80
6.4 Signalling Events
Signalling events are the most basic type of event. A signalling event does not contain any information apart from the
indication of a change in a peripheral. Most peripherals can only generate and use signalling events. Unless otherwise
stated, all occurrences of the word ”event” are to be understood as meaning signalling events, which is a strobe.
6.5 Data Events

Data events differ from signalling events in that they contain information that event users can decode to decide event
actions based on the receiver information. Data events can be synchronous or asynchronous.
Although the event routing network can route all events to all event users, those that are only meant to use signalling
events do not have decoding capabilities needed to utilize data events.
How event users decode data events is shown in Table 6-1 on page 81.
Event users that can utilize data events can also use signalling events. This is configurable, and is described in the
datasheet module for each peripheral.
6.6 Peripheral Clock Events

Each event channel includes a peripheral clock prescaler with a range from 1 (no prescaling) to 32768. This enables
configurable periodic event generation based on the peripheral clock. It is possible to periodically trigger events in a
peripheral or to periodically trigger synchronized events in several peripherals. Since each event channel include a
prescaler, different peripherals can receive triggers with different intervals.
6.7 Software Events

Events can be generated from software by writing the DATA and STROBE registers. The DATA register must be written
first, since writing the STROBE register triggers the operation. The DATA and STROBE registers contain one bit for each
event channel. Bit n corresponds to event channel n. It is possible to generate events on several channels at the same
time by writing to several bit locations at once.
Software-generated events last for one clock cycle and will overwrite events from other event generators on that event
channel during that clock cycle.
Table 6-1 on page 81 shows the different events, how they can be manually generated, and how they are decoded.
Table 6-1. Manually Generated Events and Decoding of Events
STROBE DATA Data event user Signalling event user
0 0 No Event No Event
0 1 Data Event 01 No Event
1 0 Data Event 02 Signalling Event
1 1 Data Event 03 Signalling Event
6.8 Event Routing Network

The event routing network routes the events between peripherals. It consists of eight multiplexers (CHnMUX), which can
each be configured to route any event source to any event users. The output from a multiplexer is referred to as an event
channel. For each peripheral, it is selectable if and how incoming events should trigger event actions. Details on
configurations can be found in the datasheet for each peripheral. The event routing network is shown in Figure 6-3 on
page 82.
XMEGA E MANUAL 81
Figure 6-3. Event Routing Network
Event Channel 7
Event Channel 6
Event Channel 5
Event Channel 4
Event Channel 3
Event Channel 2
Event Channel 1
Event Channel 0
(PORTC)
(8) TCC4 (6)
TCC5 (4)
CH0CTRL[7:0]
(PORTD) CH0MUX[7:0]
(8)
TCD5 (4)
CH1CTRL[7:0]
CH1MUX[7:0]
CH2CTRL[7:0]
(30) CH2MUX[7:0]
(8) ADCA (1)
(8)
(ACA)
(8) AC0 (3) CH3CTRL[7:0]
(8) AC1 CH3MUX[7:0]
(8) XCL (8)
RTC (2) CH4CTRL[7:0]
CH4MUX[7:0]
ClkPER (16)
CH5CTRL[7:0]
CH5MUX[7:0]
CH6CTRL[7:0]
CH6MUX[7:0]
(24)
PORTA (8)
PORTC (8)
PORTD (8)
CH7CTRL[7:0]
CH7MUX[7:0]
Eight multiplexers means that it is possible to route up to eight events at the same time. It is also possible to route one
event through several multiplexers.
Not all XMEGA devices contain all peripherals. This only means that a peripheral is not available for generating or using
events. The network configuration itself is compatible between all devices.
Event selection for each channel and event type is shown in Table 6-2 on page 83:
XMEGA E MANUAL 82
Table 6-2. Event Selection and Event Type
Event type
Peripheral Event source Strobe event Synchronous data Asynchronous data
RTC_OVF x x
RTC
RTC_CMP x x
AC_CH0 x x
AC AC_CH1 x x
AC_WIN x
ADC ADC_CH x
PRESCALER PRESC_M x
PORTn_PIN0 x x x
PORTn_PIN1 x x x
PORTn_PIN2 x x x
PORTn_PIN3 x x x
PORTn
PORTn_PIN4 x x x
PORTn_PIN5 x x x
PORTn_PIN6 x x x
PORTn_PIN7 x x x
TC4_OVF x
TC4_ERR x
TC4_CCA x
TC4
TC4_CCB x
TC4_CCC x
TC4_CCD x
TC5_OVF x
TC5_ERR x
TC5
TC5_CCA x
TC5_CCB x
XMEGA E MANUAL 83
Event type
Peripheral Event source Strobe event Synchronous data Asynchronous data
XCL_UNF0 x
XCL_UNF1 x
XCL_CC0 x
XCL_CC1 x
XCL
XCL_PEC0 x
XCL_PEC1 x
XCL_LUT0 x x x
XCL_LUT1 x x x
6.9 Event Timing

An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will
generate events continuously. Details on this are described in the datasheet for each peripheral, but unless otherwise
stated, an event lasts for one peripheral clock cycle.
It takes a maximum of two peripheral clock cycles from when an event is generated until the event actions in other
peripherals are triggered. This ensures short and 100% predictable response times, independent of CPU or EDMA
controller load or software revisions.
An asynchronous event is routed without any peripheral clock delay and it is present as long as the source is generating
this event.
6.10 Filtering
Each event channel includes a digital filter. When this is enabled, an event must be sampled with the same value for a
configurable number of system clock or prescaler clock cycles before it is accepted. This is primarily intended for pin
change events. The default clock for a digital filter is the system clock. Optionally, the clock can be divided by using the
prescaler with individual settings for each channel 0 to channel 3 or channel 4 to channel 7.
Event channels with quadrature decoder extension support rotary filter. Figure 6-4 on page 85 shows the output signals
of the rotary filter. The rotary filter output controls the QDEC up, down and index operation. The digital filter can be
enabled when using the rotary encoder.
XMEGA E MANUAL 84
Figure 6-4. Rotary Encoder Output Signals
FORWARD
PHASE0
DETECTA
PHASE90 DETECTC
PHASE0 DETECTD
DETECTB
unglitch
PHASE90
unglitch
PHASE Q0 Q2 Q3 Q1 Q0 Q2 Q3 Q1
PHASE EVENT
DIRECTION
DETECTA = Set PHASE0 unglitch when PHASE0 = 1 and PHASE90 = 0

DETECTB = Set PHASE90 unglitch when PHASE0 = 1 and PHASE90 = 1
DETECTC = Clear PHASE0 unglitch when PHASE0 = 0 and PHASE90 = 1
DETECTD = Clear PHASE90 unglitch when PHASE =0 and PHASE90 = 0
On phase event, update DIRECTION : 0=FORWARD/1=BACKWARD
PH0 rise : PH90
PH0 fall : not(PH90)
PH90 rise : not(PH0)
PH90 fall : PH0
BACKWARD
PHASE0
DETECTB
PHASE90 DETECTD
DETECTC
PHASE0
unglitch DETECTA
PHASE90
unglitch
PHASE Q0 Q1 Q3 Q2 Q0 Q1 Q3 Q2
DIRECTION
6.11 Quadrature Decoder

The event system includes three quadrature decoders (QDECs), which enable the device to decode quadrature input on
I/O pins and send data events that a timer/counter can decode to count up, count down, or index/reset. Table 6-3 on
page 86 summarizes which quadrature decoder data events are available, how they are decoded by timers, and how
they can be generated. The QDECs and related features and control and status registers are available for event
channels 0, 2, and 4.
XMEGA E MANUAL 85
Table 6-3. Quadrature Decoder Data Events
STROBE DATA Data event user Signalling event user
0 0 No Event No Event
0 1 Index/reset No Event
1 0 Count down Signalling Event
1 1 Count up Signalling Event
6.11.1 Quadrature Operation

A quadrature signal is characterized by having two square waves that are phase shifted 90 degrees relative to each
other. Rotational movement can be measured by counting the edges of the two waveforms. The phase relationship
between the two square waves determines the direction of rotation.
Figure 6-5. Quadrature Signals from a Rotary Encoder

1 cycle / 4 states
Forward Direction
QDPH0
QDPH90
QDINDX
00 10 11 01
Backward
Direction
QDPH0
QDPH90
QDINDX
01 11 10 00
Figure 6-5 on page 86 shows typical quadrature signals from a rotary encoder. The signals QDPH0 and QDPH90 are the
two quadrature signals. When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads
QDPH90, the rotation is defined as negative or reverse. The concatenation of the two phase signals is called the
quadrature state or the phase state.
In order to know the absolute rotary displacement, a third index signal (QDINDX) can be used. This gives an indication
once per revolution.
6.11.2 QDEC Setup

For a full QDEC setup, the following is required:
 Two or three I/O port pins for quadrature signal input
 Two event system channels for quadrature decoding
 One timer/counter for up, down, and optional index count
The following procedure should be used for QDEC setup:

1. Choose two successive pins on a port as QDEC phase inputs.
2. Set the pin direction for QDPH0 and QDPH90 as input.
XMEGA E MANUAL 86
3. Set the pin configuration for QDPH0 and QDPH90 to low level sense.
4. Select the QDPH0 pin as a multiplexer input for an event channel, n.
5. Enable quadrature decoding and digital filtering in the event channel.
6. Optional:
1. Set the digital filter control register (DFCTRL) options.
2. Set up a QDEC index (QINDX).
3. Select a third pin for QINDX input.
4. Set the pin direction for QINDX as input.
5. Set the pin configuration for QINDX to sense both edges.
6. Select QINDX as a multiplexer input for event channel n+1.
7. Set the quadrature index enable bit in event channel n+1.
8. Select the index recognition mode for event channel n+1.
9. Set quadrature decoding as the event action for a timer/counter.
10. Select event channel n as the event source for the timer/counter.
 Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the quadrature encoder
 Enable the timer/counter without clock prescaling
The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read directly from the
timer/counter count register. If the count register is different from BOTTOM when the index is recognized, the
timer/counter error flag is set. Similarly, the error flag is set if the position counter passes BOTTOM without the
recognition of the index.
XMEGA E MANUAL 87
6.12 Register Description
6.12.1 CHnMUX – Event Channel n Multiplexer Register
Bit 7 6 5 4 3 2 1 0
+n CHnMUX[7:0]
 Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer

These bits select the event source according to Table 6-4 on page 88. This table is valid for all XMEGA devices
regardless of whether the peripheral is present or not. Selecting event sources from peripherals that are not pres-
ent will give the same result as when this register is zero. When this register is zero, no events are routed through.
Manually generated events will override CHnMUX and be routed to the event channel even if this register is zero.
Table 6-4. CHnMUX Bit Settings
CHnMUX[7:4] CHnMUX[3:0] Group configuration Event source
0000 0 0 0 0 None (manually generated events only)
0000 0 0 0 1 (Reserved)
0000 0 0 1 x (Reserved)
0000 0 1 x x (Reserved)
0000 1 0 0 0 RTC_OVF RTC overflow
0000 1 0 0 1 RTC_CMP RTC compare match
0000 1 0 1 x (Reserved)
0000 1 1 x x (Reserved)
0001 0 0 0 0 ACA_CH0 ACA channel 0
0001 0 0 0 1 ACA_CH1 ACA channel 1
0001 0 0 1 0 ACA_WIN ACA window
0001 0 x x x (Reserved)
0010 0 0 0 0 ADCA_CH ADCA channel
0010 x x x x (Reserved)
0011 x x x X (Reserved)
0101 0 n PORTA_PINn(1) PORTA pin n (n = 0,1,2 … or 7)
0110 0 n PORTC_PINn(1) PORTC pin n (n = 0,1,2 … or 7)
0110 1 n PORTD_PINn(1) PORTD pin n (n = 0,1,2 … or 7)
1000 M PRESCALER_M ClkPER divide by 2M (M = 0 to 15)
XMEGA E MANUAL 88
CHnMUX[7:4] CHnMUX[3:0] Group configuration Event source
1011 0 E See Table 6-5 XCL event type E
1100 0 E See Table 6-6 Timer/counter C4 event type E
1100 1 E See Table 6-6 Timer/counter C5 event type E
1101 0 x X x (Reserved)
1101 1 E See Table 6-6 Timer/counter D5 event type E
Note: 1. The description of how the ports generate events is described in “Port Event” on page 146.
Table 6-5. XCL Events
T/C event E Group configuration Event type
0 0 0 XCL_UNF0 BTC0 underflow
0 0 1 XCL_UNF1 BTC1 underflow
0 1 0 XCL_CC0 BTC0 capture or compare
0 1 1 XCL_CC1 BTC1 capture or compare
1 0 0 XCL_PEC0 PEC0 restart
1 0 1 XCL_PEC1 PEC1 restart
1 1 0 XCL_LUT0 LUT0 output
1 1 1 XCL_LUT1 LUT1 output
Table 6-6. Timer/counter Events
T/C event E Group configuration Event type
0 0 0 TCxn_OVF Over/Underflow (x = C,D)(n = 4 or 5)
0 0 1 TCxn_ERR Error (x = C,D)(n = 4 or 5)
0 1 x (Reserved)
1 0 0 TCxn_CCA Capture or compare A (x = C,D)(n = 4 or 5)
1 0 1 TCxn_CCB Capture or compare B (x = C,D)(n = 4 or 5)
1 1 0 TCxn_CCC Capture or compare C (x = C)(n = 4)
1 1 1 TCxn_CCD Capture or compare D (x = C)(n = 4)
XMEGA E MANUAL 89
6.12.2 CHnCTRL – Event Channel n Control Register
Bit 7 6 5 4 3 2 1 0
+8x08 +n ROTARY QDIRM[1:0] QDIEN QDEN DIGFILT[2:0]
 Bit 7 – ROTARY: Rotary

Setting this bit enables rotary filter. This bit is available only for CH0CTRL.
 Bit 6:5 – QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals, where a valid index signal is rec-
ognized and the counter index data event is given according to Table 6-7 on page 90. These bits should only be
set when a quadrature encoder with a connected index signal is used. These bits are available only for CH0CTRL.
Table 6-7. QDIRM Bit Settings
QDIRM[1:0] Index recognition state
0 0 {QDPH0, QDPH90} = 0b00
0 1 {QDPH0, QDPH90} = 0b01
1 0 {QDPH0, QDPH90} = 0b10
1 1 {QDPH0, QDPH90} = 0b11
 Bit 4 – QDIEN: Quadrature Decode Index Enable

When this bit is set, the event channel will be used as a QDEC index source, and the index data event will be
enabled.
This bit is available only for CH0CTRL.
 Bit 3 – QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation. This bit is ignored if the rotary encoder is enabled.
This bit is available only for CH0CTRL.
 Bit 2:0 – DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event channel only when
the event source has been active and sampled with the same level for the number of prescaler peripheral clock
cycles defined by DIGFILT.
Table 6-8. Digital Filter Coefficient Values
DIGFILT[2:0] Group configuration Description
000 1SAMPLE One sample
001 2SAMPLES Two samples
010 3SAMPLES Three samples
011 4SAMPLES Four samples
100 5SAMPLES Five samples
101 6SAMPLES Six samples
110 7SAMPLES Seven samples
111 8SAMPLES Eight samples
XMEGA E MANUAL 90
6.12.3 STROBE – Event Strobe Register
If the STROBE register location is written, each event channel will be set according to the STROBE[n] and corresponding
DATA[n] bit settings, if any are unequal to zero.
A single event lasting for one peripheral clock cycle will be generated.
Bit 7 6 5 4 3 2 1 0
+0x10 STROBE[7:0]
6.12.4 DATA – Event DATA Register

This register contains the data value when manually generating a data event. This register must be written before the
STROBE register. For details, see “STROBE – Event Strobe Register” on page 91.
Bit 7 6 5 4 3 2 1 0
+0x11 DATA[7:0]
6.12.5 DFCTRL – Digital Filter Control Register
Bit 7 6 5 4 3 2 1 0
+0x12 PRESCFILT[3:0] FILTSEL PRESC[2:0]
 Bit 7:4 – PRESCFILT[3:0]: Prescaler Filter

These bits define the prescaler filter settings, according to Table 6-9 on page 91.
Table 6-9. Prescaler Filter Settings
PRESCFILT[3:0] Group configuration Description
xxx1 CH04 Enable prescaler filter for either channel 0 or 4
xx1x CH15 Enable prescaler filter for either channel 1 or 5
x1xx CH26 Enable prescaler filter for either channel 2 or 6
1xxx CH37 Enable prescaler filter for either channel 3 or 7
 Bit 3 – FILTSEL: Prescaler Filter Select

Setting this bit enables the prescaler clock option on event channels 4 to 7. Clearing this bit enables the prescaler
clock option on event channels 0 to 3. This bit is used with settings defined by PRESCFILT bits.
 Bit 2:0 – PRESC[2:0]: Prescaler
These bits select the digital filter clock prescaler settings, according to Table 6-10 on page 92.
XMEGA E MANUAL 91
Table 6-10. Prescaler Options
PRESC[2:0] Group configuration Description
000 CLKPER_8 ClkPER divide by 23
101 – (Reserved)
110 – (Reserved)
1111 – (Reserved)
XMEGA E MANUAL 92
+0x00 CH0MUX CH0MUX[7:0] 88

+0x08 CH0CTRL ROTARY QDIRM[1:0] QDIEN QDEN DIGFILT[2:0] 90
+0x09 CH1CTRL - - - - - DIGFILT[2:0] 90
+0x0A CH2CTRL - - - - - DIGFILT[2:0] 90
+0x0B CH3CTRL - - - - - DIGFILT[2:0] 90
+0x0C CH4CTRL - - - - - DIGFILT[2:0] 90
+0x0D CH5CTRL - - - - - DIGFILT[2:0] 90
+0x0E CH6CTRL - - - - - DIGFILT[2:0] 90
+0x0F CH7CTRL - - - - - DIGFILT[2:0] 90
+0x10 STROBE STROBE[7:0] 91
+0x11 DATA DATA[7:0] 91
+0x12 DFCTRL PRESCFILT[3:0] FILTSEL PRESC[2:0] 91
XMEGA E MANUAL 93
7. System Clock and Clock Options
7.1 Features
 Fast start-up time
 Safe run-time clock switching
 Internal oscillators:
 32MHz run-time calibrated oscillator
 8MHz calibrated oscillator with 2MHz output and fast start-up
 32.768kHz calibrated oscillator
 32kHz ultra low power (ULP) oscillator with 1kHz output
 External clock options
 0.4MHz - 16MHz crystal oscillator
 32.768kHz crystal oscillator
 External clock
 PLL with 20MHz - 128MHz output frequency
 Internal and external clock options and 1× to 31× multiplication
 Lock detector
 Clock prescalers with 1× to 2048× division
 Fast peripheral clocks running at 2 and 4 times the CPU clock
 Automatic run-time calibration of internal 32MHz oscillator
 External oscillator and PLL lock failure detection with optional non-maskable interrupt
7.2 Overview
XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate
internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and
clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available,
and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and
temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal
oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz output of 8MHz internal oscillator. During normal operation, the system clock
source and prescalers can be changed from software at any time.
Figure 7-1 on page 95 presents the principal clock system in the XMEGA family of devices. Not all of the clocks need to
be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 112.
XMEGA E MANUAL 94
Figure 7-1. The Clock System, Clock Sources, and Clock Distribution
Real Time Non-Volatile

Peripherals RAM AVR CPU
Counter Memory
clkPER
clkCPU
clkPER2
clkPER4
clk RTC
System Clock Prescalers

Brown-out Watchdog
Detector Timer
clkSYS
System Clock Multiplexer

RTCSRC
(SCLKSEL)
DIV32
DIV32
DIV32
PLL
PLLSRC
DIV4
DIV4
XOSCSEL
32 kHz 32.768 kHz 32.768 kHz 0.4 – 16 MHz 32 MHz 8 MHz

Int. ULP Int. OSC TOSC XTAL Int. Osc Int. Osc
PC[4]
TOSC1
TOSC2
XTAL1
XTAL2
7.3 Clock Distribution

Figure 7-1 presents the principal clock distribution system used in XMEGA devices.
7.3.1 System Clock - ClkSYS

The system clock is the output from the main system clock selection. This is fed into the prescalers that are used to
generate all internal clocks except the asynchronous clocks.
XMEGA E MANUAL 95
7.3.2 CPU Clock – ClkCPU
The CPU clock is routed to the CPU and nonvolatile memory. Halting the CPU clock inhibits the CPU from executing
instructions.
7.3.3 Peripheral Clock – ClkPER

The majority of peripherals and system modules use the peripheral clock. This includes the DMA controller, event
system, interrupt controller, external bus interface and RAM. This clock is always synchronous to the CPU clock, but may
run even when the CPU clock is turned off.
7.3.4 Peripheral 2x/4x Clocks – ClkPER2/ClkPER4

Modules that can run at two or four times the CPU clock frequency can use the peripheral 2× and peripheral 4× clocks.
7.3.5 Asynchronous Clock – ClkRTC

The asynchronous clock allows the real-time counter (RTC) to be clocked directly from an external 32.768kHz crystal
oscillator or the 32 times prescaled output from the internal 32.768kHz oscillator or ULP oscillator. The dedicated clock
domain allows operation of this peripheral even when the device is in sleep mode and the rest of the clocks are stopped.
7.4 Clock Sources

The clock sources are divided in two main groups; internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz output of 8MHz internal
oscillator. The other clock sources, DFLL and PLL, are turned off by default.
7.4.1 Internal Oscillators

The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
7.4.1.1 32kHz Ultra Low Power Oscillator

This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
7.4.1.2 32.768kHz Calibrated Oscillator

This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
7.4.1.3 32MHz Run-time Calibrated Oscillator

The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.
7.4.1.4 8MHz Calibrated Oscillator

The 8MHz calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to
provide a default frequency close to its nominal frequency.
XMEGA E MANUAL 96
7.4.2 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 or pin 4 from port C (PC4) can be used as input for an external clock signal. The TOSC1 and TOSC2 pins are
dedicated to driving a 32.768kHz crystal oscillator.
7.4.2.1 0.4MHz - 16MHz Crystal Oscillator

This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4MHz - 16MHz.
Figure 7-2 shows a typical connection of a crystal oscillator or resonator.
Figure 7-2. Crystal Oscillator Connection

C2
XTAL2
C1
XTAL1
GND
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal.
7.4.2.2 External Clock Input

To drive the device from an external clock source, XTAL1 pin must be driven as shown in Figure 7-3. In this mode,
XTAL2 can be used as a general I/O pin. Pin 4 from port C can be used as alternative position for external clock input.
Figure 7-3. External Clock Drive Configuration
General
Purpose XTAL2
I/O
External
Clock XTAL1 / PC4
Signal
XMEGA E MANUAL 97
7.4.2.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A typical connection is shown in Figure 7-4 on page 98. A low power mode with reduced
voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as
the DFLL reference clock.
Figure 7-4. 32.768kHz Crystal Oscillator Connection

C2
TOSC2
C1
TOSC1
GND
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal. For details
on recommended TOSC characteristics and capacitor load, refer to device datasheet.
7.5 System Clock Selection and Prescalers

All the calibrated internal oscillators, the external clock sources (XOSC), and the PLL output can be used as the system
clock source. The system clock source is selectable from software, and can be changed during normal operation. Built-in
hardware protection prevents unsafe clock switching. It is not possible to select a non-stable or disabled oscillator as the
clock source, or to disable the oscillator currently used as the system clock source. Each oscillator option has a status
flag that can be read from software to check that the oscillator is ready.
The system clock is fed into a prescaler block that can divide the clock signal by a factor from 1 to 2048 before it is routed
to the CPU and peripherals. The prescaler settings can be changed from software during normal operation. The first
stage, prescaler A, can divide by a factor of from 1 to 512. Then, prescalers B and C can be individually configured to
either pass the clock through or combine divide it by a factor from 1 to 4. The prescaler guarantees that derived clocks
are always in phase, and that no glitches or intermediate frequencies occur when changing the prescaler setting. The
prescaler settings are updated in accordance with the rising edge of the slowest clock.
Figure 7-5. System Clock Selection and Prescalers

Clock Selection
Internal 32.768 kHz Osc. ClkPER4 ClkPER2
Internal 8 MHz Osc. ClkCPU

ClkSYS Prescaler A Prescaler B Prescaler C
Internal 32 MHz Osc. 1, 2, 4, ... , 512 1, 2, 4 1, 2 ClkPER
External Clock .
Prescaler A divides the system clock, and the resulting clock is clkPER4. Prescalers B and C can be enabled to divide the
clock speed further to enable peripheral modules to run at twice or four times the CPU clock frequency. If Prescalers B
and C are not used, all the clocks will run at the same frequency as the output from Prescaler A.
The system clock selection and prescaler registers are protected by the configuration change protection mechanism,
employing a timed write procedure for changing the system clock and prescaler settings. For details, refer to
“Configuration Change Protection” on page 13.
XMEGA E MANUAL 98
7.6 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. The output frequency, fOUT, is given by the input frequency, fIN, multiplied
by the multiplication factor, PLL_FAC.
f OUT  f IN * PLL _ FAC
Four different clock sources can be chosen as input to the PLL:
 2MHz output from 8MHz internal oscillator
 8MHz internal oscillator
 32MHz internal oscillator divided by 4
 0.4MHz - 16MHz crystal oscillator
 External clock
To enable the PLL, the following procedure must be followed:
1. Enable reference clock source.
2. Set the multiplication factor and select the clock reference for the PLL.
3. Wait until the clock reference source is stable.
4. Enable the PLL.
Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The PLL must be disabled
before a new configuration can be written.
It is not possible to use the PLL before the selected clock source is stable and the PLL has locked.
The reference clock source cannot be disabled while the PLL is running.
7.7 DFLL 32MHz

Built-in digital frequency locked loop (DFLL) can be used to improve the accuracy of the 32MHz internal oscillators. The
DFLL compares the oscillator frequency with a more accurate reference clock to do automatic run-time calibration of the
oscillator and compensate for temperature and voltage drift. The choices for the reference clock sources are:
 32.768kHz calibrated internal oscillator
 32.768kHz crystal oscillator connected to the TOSC pins
 External clock
The DFLL divides the oscillator reference clock by 32 to use a 1.024kHz reference. The reference clock is individually
selected for each DFLL, as shown in Figure 7-6 on page 99.
Figure 7-6. DFLL Reference Clock Selection

XOSCSEL
TOSC1
32.768 kHz Crystal Osc
TOSC2
XTAL1
External Clock
PC4
32.768 kHz Int. Osc
DIV32
clkRC32MCREF
DFLL32M
32 MHz Int. OSC
XMEGA E MANUAL 99
The value that should be written to the COMP register is given by the following formula:
f OSC
COMP  hex( )
f RC 32MCREF
When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the
internal oscillator runs too fast or too slow, the DFLL will decrement or increment its calibration register value by one to
adjust the oscillator frequency. The oscillator is considered running too fast or too slow when the error is more than a half
calibration step size.
Figure 7-7. Automatic Run-time Calibration
clkRC32MCREF
DFLL CNT tRCnCREF
COMP
RCOSC slow,
Frequency CALA incremented
OK RCOSC fast,
CALA decremented
The DFLL will stop when entering a sleep mode where the oscillators are stopped. After wake up, the DFLL will continue
with the calibration value found before entering sleep. The reset value of the DFLL calibration register can be read from
the production signature row.
When the DFLL is disabled, the DFLL calibration register can be written from software for manual run-time calibration of
the oscillator.
7.8 PLL and External Clock Source Failure Monitor

A built-in failure monitor is available for the PLL and external clock source. If the failure monitor is enabled for the PLL
and/or the external clock source, and this clock source fails (the PLL looses lock or the external clock source stops) while
being used as the system clock, the device will:
 Switch to run the system clock from the 2MHz output from 8MHz internal oscillator
 Reset the oscillator control register and system clock selection register to their default values
 Set the failure detection interrupt flag for the failing clock source (PLL or external clock)
 Issue a non-maskable interrupt (NMI)
If the PLL or external clock source fails when not being used for the system clock, it is automatically disabled, and the
system clock will continue to operate normally. No NMI is issued. The failure monitor is meant for external clock sources
above 32kHz. It cannot be used for slower external clocks.
When the failure monitor is enabled, it will not be disabled until the next reset.
The failure monitor is stopped in all sleep modes where the PLL or external clock source, are stopped. During wake up
from sleep, it is automatically restarted.
The PLL and external clock source failure monitor settings are protected by the configuration change protection
mechanism, employing a timed write procedure for changing the settings. For details, refer to “Configuration Change
Protection” on page 13.
XMEGA E MANUAL 100

7.9 Register Description – Clock
Bit 7 6 5 4 3 2 1 0
+0x00 – – – – – SCLKSEL[2:0]
Read/Write R R R R R R/W R/W R/W
This register is write protected if the bit LOCK has been set in the LOCK register.
 Bit 2:0 – SCLKSEL[2:0]: System Clock Selection
These bits are used to select the source for the system clock. See Table 7-1 for the different selections. Changing
the system clock source will take two clock cycles on the old clock source and two more clock cycles on the new
clock source. These bits are protected by the configuration change protection mechanism. For details, refer to
“Configuration Change Protection” on page 13.
SCLKSEL cannot be changed if the new clock source is not stable. The old clock can not be disabled until the
clock switching is completed.
Table 7-1. System Clock Selection
SCLKSEL[2:0] Group configuration Description
000 RC2MHZ 2MHz from 8MHz internal oscillator
001 RC32MHZ 32MHz internal oscillator
010 RC32KHZ 32.768kHz internal oscillator
011 XOSC External oscillator or clock
100 PLL Phase locked loop
101 RC8MHZ 8MHz internal oscillator
110 – Reserved
111 – Reserved
7.9.2 PSCTRL – Prescaler Register
Bit 7 6 5 4 3 2 1 0
+0x01 – PSADIV[4:0] PSBCDIV[1:0]
This register is write protected if the bit LOCK has been set in the LOCK register.
 Bit 7 - Reserved
 Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor
These bits define the division ratio of the clock prescaler A according to Table 7-2. These bits can be written at
run-time to change the frequency of the ClkPER4 clock relative to the system clock, ClkSYS.
XMEGA E MANUAL 101

Table 7-2. Prescaler A Division Factor
PSADIV[4:0] Group configuration Description
00000 1 No division
00001 2 Divide by 2
00011 4 Divide by 4
00101 8 Divide by 8
00111 16 Divide by 16
01001 32 Divide by 32
01011 64 Divide by 64
01101 128 Divide by 128
01111 256 Divide by 256
10001 512 Divide by 512
10011 6 Divide by 6
10101 10 Divide by 10
10111 12 Divide by 12
11001 24 Divide by 24
11011 48 Divide by 48
11101 – Reserved
11111 – Reserved
 Bit 1:0 – PSBCDIV[1:0]: Prescaler B and C Division Factors

These bits define the division ratio of the clock prescalers B and C according to Table 7-3 on page 102. Prescaler
B will set the clock frequency for the ClkPER2 clock relative to the ClkPER4 clock. Prescaler C will set the clock fre-
quency for the ClkPER and ClkCPU clocks relative to the ClkPER2 clock. Refer to Figure 7-5 on page 98 for more
details.
Table 7-3. Prescaler B and C Division Factors
PSBCDIV[1:0] Group configuration Prescaler B division Prescaler C division
00 1_1 No division No division
01 1_2 No division Divide by 2
10 4_1 Divide by 4 No division
11 2_2 Divide by 2 Divide by 2
XMEGA E MANUAL 102

7.9.3 LOCK – Lock Register
Bit 7 6 5 4 3 2 1 0
+0x02 – – – – – – – LOCK

 Bit 0 – LOCK: Clock System Lock
When this bit is written to one, the CTRL and PSCTRL registers cannot be changed, and the system clock selec-
tion and prescaler settings are protected against all further updates until after the next reset. This bit is protected
by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page
13.
The LOCK bit can be cleared only by a reset.
7.9.4 RTCCTRL – RTC Control Register
Bit 7 6 5 4 3 2 1 0
+0x03 – – – – RTCSRC[2:0] RTCEN

 Bit 3:1 – RTCSRC[2:0]: RTC Clock Source
These bits select the clock source for the real-time counter according to Table 7-4 on page 103.
Table 7-4. RTC Clock Source Selection
RTCSRC[2:0] Group configuration Description
000 ULP 1kHz from 32kHz internal ULP oscillator
001 TOSC 1.024kHz from 32.768kHz crystal oscillator on TOSC
010 RCOSC 1.024kHz from 32.768kHz internal oscillator
011 - Reserved
100 - Reserved
101 TOSC32 32.768kHz from 32.768kHz crystal oscillator on TOSC
110 RCOSC32 32.768kHz from 32.768kHz internal oscillator
111 EXTCLK External clock from TOSC1
 Bit 0 – RTCEN: RTC Clock Source Enable

Setting the RTCEN bit enables the selected RTC clock source for the real-time counter.
XMEGA E MANUAL 103

7.10 Register Description – Oscillator
7.10.1 CTRL – Oscillator Control Register
Bit 7 6 5 4 3 2 1 0
+0x00 – RC8MLPM RC8MEN PLLEN XOSCEN RC32KEN RC32MEN RC2MEN
 Bit 6 – RC8MLPM: 8MHz Internal Oscillator Low Power Mode
Setting this bit enables the low power mode for the internal 8MHz oscillator. For details on characteristics and
accuracy of the internal oscillator in this mode, refer to the device datasheet.
 Bit 5 – RC8MEN: 8MHz Internal Oscillator Enable
Setting this bit will enable the 8MHz output of the internal oscillator. The oscillator must be stable before it is
selected as the source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
 Bit 4 – PLLEN: PLL Enable
Setting this bit enables the PLL. Before the PLL is enabled, it must be configured with the desired multiplication
factor and clock source. See “STATUS – Oscillator Status Register” on page 104.
 Bit 3 – XOSCEN: External Oscillator Enable
Setting this bit enables the selected external clock source. Refer to “XOSCCTRL – XOSC Control Register” on
page 105 for details on how to select the external clock source. The external clock source should be allowed time
to stabilize before it is selected as the source for the system clock. See “STATUS – Oscillator Status Register” on
page 104.
 Bit 2 – RC32KEN: 32.768kHz Internal Oscillator Enable
Setting this bit enables the 32.768kHz internal oscillator. The oscillator must be stable before it is selected as the
source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
Setting this bit will enable the 32MHz internal oscillator. The oscillator must be stable before it is selected as the
source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
Setting this bit will enable the 2MHz output of 8MHz internal oscillator. The oscillator must be stable before it is
selected as the source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
By default, the 2MHz output from RC8MHz internal oscillator is enabled and this bit is set.
7.10.2 STATUS – Oscillator Status Register
Bit 7 6 5 4 3 2 1 0
+0x01 – – RC8MRDY PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY

 Bit 5 – RC8MRDY: 8MHz Internal Oscillator Ready
This flag is set when the 8MHz output from RC8MHz internal oscillator is stable and is ready to be used as the sys-
tem clock source.
XMEGA E MANUAL 104

 Bit 4 – PLLRDY: PLL Ready
This flag is set when the PLL has locked on the selected frequency and is ready to be used as the system clock
source.
 Bit 3 – XOSCRDY: External Clock Source Ready
This flag is set when the external clock source is stable and is ready to be used as the system clock source.
 Bit 2 – RC32KRDY: 32.768kHz Internal Oscillator Ready
This flag is set when the 32.768kHz internal oscillator is stable and is ready to be used as the system clock source.
This flag is set when the 32MHz internal oscillator is stable and is ready to be used as the system clock source.
This flag is set when the 2MHz output from RC8MHz internal oscillator is stable and is ready to be used as the sys-
tem clock source.
7.10.3 XOSCCTRL – XOSC Control Register
Bit 7 6 5 4 3 2 1 0
XOSCPWR
+0x02 FRQRANGE[1:0] X32KLPM XOSCSEL[3:0]
XOSCSEL[4]
 Bit 7:6 – FRQRANGE[1:0]: 0.4 - 16MHz Crystal Oscillator Frequency Range Select
These bits select the frequency range for the connected crystal oscillator according to Table 7-5 on page 105.
Table 7-5. 16MHz Crystal Oscillator Frequency Range Selection(1)
Typical frequency range Recommended range for capacitors

FRQRANGE[1:0] Group configuration [MHz] C1 and C2 [pF]
00 04TO2 0.4 - 2 100-300
01 2TO9 2-9 10-40
10 9TO12 9 - 12 10-40
11 12TO16 12 - 16 10-30
Note: 1. Refer to Electrical Characteristics in device datasheet for finding the best setting for a given frequency.
 Bit 5 – X32KLPM: Crystal Oscillator 32.768kHz Low Power Mode

Setting this bit enables the low power mode for the 32.768kHz crystal oscillator. This will reduce the swing on the
TOSC2 pin.
 Bit 4 – XOSCPWR: Crystal Oscillator Drive
Setting this bit will increase the current in the 0.4MHz - 16MHz crystal oscillator and increase the swing on the
XTAL2 pin. This allows for driving crystals with higher load or higher frequency than specified by the FRQRANGE
bits.
 Bit 4 – XOSCSEL[4]: Crystal Oscillator Selection
This bit selects the pin position from which the external clock is used. When cleared, the external clock pin is
XTAL1 pin. When set, the external clock pin is port C, pin 4. The selection is ignored if XOSCSEL[3:0] settings do
not select the external clock option. For more details, refer to Table 7-6.
 Bit 3:0 – XOSCSEL[3:0]: Crystal Oscillator Selection
These bits select the type and start-up time for the crystal or resonator that is connected to the XTAL or TOSC
pins. See Table 7-6 for crystal selections. If an external clock or external oscillator is selected as the source for the
system clock, see “CTRL – Oscillator Control Register” on page 104”. This configuration cannot be changed.
XMEGA E MANUAL 105

Table 7-6. 16MHz Crystal Oscillator Frequency Range Selection
XOSCSEL[3:0] Group configuration Selected clock source Start-up time
0000 EXTCLK (3) External Clock from XTAL1 pin 6 CLK

(3)
0010 32KHZ 32.768kHz TOSC 16K CLK
0011 XTAL_256CLK (1) 0.4MHz - 16MHz XTAL 256 CLK
0111 XTAL_1KCLK (2) 0.4MHz - 16MHz XTAL 1K CLK
1011 XTAL_16KCLK 0.4MHz - 16MHz XTAL 16K CLK
Notes: 1. This option should be used only when frequency stability at startup is not important for the application. The option is not suitable for crystals.
2. This option is intended for use with ceramic resonators. It can also be used when the frequency stability at startup is not important for the
application.
3. When the external oscillator is used as the reference for a DFLL, only EXTCLK and 32KHZ can be selected.
7.10.4 XOSCFAIL – XOSC Failure Detection Register
Bit 7 6 5 4 3 2 1 0
+0x03 – – – – PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN

 Bit 3 – PLLFDIF: PLL Fault Detection Flag
If PLL failure detection is enabled, PLLFDIF is set when the PLL looses lock. Writing logic one to this location will
clear PLLFDIF.
 Bit 2 – PLLFDEN: PLL Fault Detection Enable
Setting this bit will enable PLL failure detection. A non-maskable interrupt will be issued when PLLFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protec-
tion” on page 13 for details.
 Bit 1 – XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, XOSCFDIF is set when a failure is detected. Writ-
ing logic one to this location will clear XOSCFDIF.
 Bit 0 – XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be issued when
XOSCFDIF is set.
tion” on page 13 for details. Once enabled, failure detection can only be disabled by a reset.
XMEGA E MANUAL 106

7.10.5 RC32KCAL – 32kHz Oscillator Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x04 RC32KCAL[7:0]
 Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator Calibration Bits

This register is used to calibrate the 32.768kHz internal oscillator. A factory-calibrated value is loaded from the sig-
nature row of the device and written to this register during reset, giving an oscillator frequency close to 32.768kHz.
The register can also be written from software to calibrate the oscillator frequency during normal operation.
7.10.6 PLLCTRL – PLL Control Register
Bit 7 6 5 4 3 2 1 0
+0x05 PLLSRC[1:0] PLLDIV PLLFAC[4:0]
 Bit 7:6 – PLLSRC[1:0]: Clock Source

The PLLSRC bits select the input source for the PLL according to Table 7-7.
Table 7-7. PLL Clock Source
PLLSRC[1:0] Group configuration Description
00 RC2M 2MHz output from 8MHz internal oscillator.
01 RC8M 8MHz output from 8MHz internal oscillator.
10 RC32M 32MHz internal oscillator.
11 XOSC External clock source (1)
Note: 1. The 32.768kHz TOSC cannot be selected as the source for the PLL. An external clock must be a minimum 0.4MHz to be used as the source clock.
 Bit 5 – PLLDIV: PLL Divided Output Enable

Setting this bit will divide the output from the PLL by 2.
 Bit 4:0 – PLLFAC[4:0]: Multiplication Factor
These bits select the multiplication factor for the PLL. The multiplication factor can be in the range of from 1x to
31x.
7.10.7 DFLLCTRL – DFLL Control Register
Bit 7 6 5 4 3 2 1 0
+0x06 – – – – – RC32MCREF[1:0] –
Read/Write R R R R R R/W R/W R

XMEGA E MANUAL 107

 Bit 2:1 – RC32MCREF[1:0]: 32MHz Oscillator Calibration Reference
These bits are used to select the calibration source for the 32MHz DFLL according to the Table 7-8 on page 108.
These bits will select only which calibration source to use for the DFLL. In addition, the actual clock source that is
selected must enabled and configured for the calibration to function.
Table 7-8. 32MHz Oscillator Reference Selection
RC32MCREF[1:0] Group configuration Description
00 RC32K 32.768kHz internal oscillator.
01 XOSC32 32.768kHz crystal oscillator on TOSC.
1x – Reserved
7.10.8 RC8MCAL – 8MHz Internal Oscillator Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x07 RC8MCAL[7:0]
 Bit 7:0 – RC8MCAL[7:0]: 8MHz Internal Oscillator Calibration Bits

This register is used to calibrate the 8MHz internal oscillator. A factory-calibrated value is loaded from the signa-
ture row of the device and written to this register during reset, giving an oscillator frequency close to 8MHz. The
register can also be written from software to calibrate the oscillator frequency during normal operation.
7.11 Register Description – DFLL32M
7.11.1 CTRL – DFLL Control Register
Bit 7 6 5 4 3 2 1 0
+0x00 – – – – – – – ENABLE

 Bit 0 – ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator. The reference clock must be
enabled and stable before the DFLL is enabled.
After disabling the DFLL, the reference clock can not be disabled before the ENABLE bit is read as zero.
XMEGA E MANUAL 108

7.11.2 CALA – DFLL Calibration Register A
The CALA and CALB registers hold the 13-bit DFLL calibration value that is used for automatic run-time calibration of the
internal oscillator. When the DFLL is disabled, the calibration registers can be written by software for manual run-time
calibration of the oscillator. The oscillators will also be calibrated according to the calibration value in these registers
when the DFLL is disabled.
Bit 7 6 5 4 3 2 1 0
+0x02 – CALA[6:0]
Initial value 0 x x x x x x x
 Bit 6:0 – CALA[6:0]: DFLL Calibration Bits
These bits hold the part of the oscillator calibration value that is used for automatic runtime calibration. A factory-
calibrated value is loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency approximate to the nominal frequency for the oscillator. The bits cannot be written when the
DFLL is enabled.
7.11.3 CALB – DFLL Calibration Register B
Bit 7 6 5 4 3 2 1 0
+0x03 – – CALB[5:0]
Initial value 0 0 x x x x x x

 Bit 5:0 – CALB[5:0]: DFLL Calibration Bits
These bits hold the part of the oscillator calibration value that is used to select the oscillator frequency. A factory-
calibrated value is loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency approximate to the nominal frequency for the oscillator. These bits are not changed during
automatic run-time calibration of the oscillator. The bits cannot be written when the DFLL is enabled. When cali-
brating to a frequency different from the default, the CALA bits should be set to a middle value to maximize the
range for the DFLL.
7.11.4 COMP1 – DFLL Compare Register 1

The COMP1 and COMP2 register pair represent the frequency ratio between the oscillator and the reference clock. The
initial value for these registers is the ratio between the internal oscillator frequency and a 1.024kHz reference.
Bit 7 6 5 4 3 2 1 0
+0x05 COMP[7:0]
 Bit 7:0 – COMP1[7:0]: Compare Value Byte 1

These bits hold byte 1 of the 16-bit compare register.
XMEGA E MANUAL 109

7.11.5 COMP2 – DFLL Compare Register 2
Bit 7 6 5 4 3 2 1 0
+0x06 COMP[15:8]
 Bit 7:0 – COMP2[15:8]: Compare Value Byte 2

These bits hold byte 2 of the 16-bit compare register.
Table 7-9. Nominal DFLL32M COMP Values for Different Output Frequencies
Oscillator frequency [MHz] COMP value (ClkRC32MCREF = 1.024kHz)
30.0 0x7270
32.0 0x7A12
34.0 0x81B3
36.0 0x8954
38.0 0x90F5
40.0 0x9896
42.0 0xA037
44.0 0xA7D8
46.0 0xAF79
48.0 0xB71B
50.0 0xBEBC
52.0 0xC65D
54.0 0xCDFE
XMEGA E MANUAL 110

7.12 Register Summary - Clock
+0x00 CTRL – – – – – SCLKSEL[2:0] 101
+0x01 PSCTRL – PSADIV[4:0] PSBCDIV[1:0] 101
+0x02 LOCK – – – – – – – LOCK 103
+0x03 RTCCTRL – – – – RTCSRC[2:0] RTCEN 103
+0x04 Reserved – – – – – – – –
+0x05 Reserved – – – – – – – –
+0x06 Reserved – – – – – – – –
+0x07 Reserved – – – – – – – –
7.13 Register Summary - Oscillator

+0x00 CTRL – RC8MLPM RC8MEN PLLEN XOSCEN RC32KEN RC32MEN RC2MEN 104
+0x01 STATUS – – RC8MRDY PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY 104
XOSCPWR
+0x02 XOSCCTRL FRQRANGE[1:0] X32KLPM XOSCSEL[3:0] 105
XOSCSEL[4]
+0x03 XOSCFAIL – – – – PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN 106
+0x04 RC32KCAL RC32KCAL[7:0] 107
+0x05 PLLCTRL PLLSRC[1:0] PLLDIV PLLFAC[4:0] 107
+0x06 DFLLCTRL – – – – – RC32MMCREF[1:0] – 107
+0x07 RC8MCAL RC8MCAL[7:0] 108
7.14 Register Summary – DFLL32M

+0x00 CTRL – – – – – – – ENABLE 108
+0x01 Reserved – – – – – – – –
+0x02 CALA – CALA[6:0] 109
+0x03 CALB – – CALB[5:0] 109
+0x04 Reserved – – – – – – – –
+0x05 COMP1 COMP[7:0] 109
+0x06 COMP2 COMP[15:8] 110
+0x07 Reserved – – – – – – – –
Table 7-10. Oscillator Failure Interrupt Vector and its Word Offset Address PLL and External Oscillator Failure Interrupt Base
0x00 OSCF_vect PLL and external oscillator failure interrupt vector (NMI)
XMEGA E MANUAL 111

8. Power Management and Sleep Modes
8.1 Features
 Power management for adjusting power consumption and functions
 Five sleep modes:
 Idle
 Power down
 Power save
 Standby
 Extended standby
 Power reduction register to disable clock and turn off unused peripherals in active and idle modes
8.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
8.3 Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
Table 8-1 on page 113 shows the different sleep modes and the active clock domains, oscillators, and wake-up sources.
XMEGA E MANUAL 112

Table 8-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active clock domain Oscillators Wake-up sources
Asynchronous port interrupts
TWI address match interrupts
Real time clock interrupts

System clock source
UART start of frame

RTC clock source
Peripheral clock
Sleep modes
All interrupts
CPU clock
RTC clock
Idle X X X X X X X X
Power down X X
Power save X X X(1) X X X
Standby X X X X
Extended standby X X X X X X X
Note: 1. Only from internal 8MHz oscillator in low power mode.
The wake-up time for the device is dependent on the sleep mode and the main clock source. The startup time for the
system clock source must be added to the wake-up time for sleep modes where the system clock source is not kept
running. For details on the startup time for the different oscillator options, refer to “System Clock and Clock Options” on
page 94.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
8.3.1 Idle Mode

In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
8.3.2 Power-down Mode

In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt, and asynchronous port interrupts.
8.3.3 Power-save Mode

Power-save mode is identical to power down, with two exceptions. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
If the UART start frame detector is enabled, the device can also wake-up from any UART interrupt, including start frame
interrupt. The internal 8MHz in low power mode must be used to wake-up the device from UART interrupts.
XMEGA E MANUAL 113

8.3.4 Standby Mode
Standby mode is identical to power down, with two exceptions.
To reduce the wake-up time, the enabled system clock sources are kept running while the CPU, peripheral, and RTC
clocks are stopped. If the UART start frame detector is enabled, the device can also wake-up from any UART interrupt,
including start frame interrupt.
8.3.5 Extended Standby Mode

Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
If the UART start frame detector is enabled, the device can also wake-up from any UART interrupt, including start frame
interrupt.
8.4 Power Reduction Registers

The power reduction (PR) registers provide a method to stop the clock to individual peripherals. When this is done, the
current state of the peripheral is frozen and the associated I/O registers cannot be read or written. Resources used by the
peripheral will remain occupied; hence, the peripheral should be disabled before stopping the clock. Enabling the clock to
a peripheral again puts the peripheral in the same state as before it was stopped. This can be used in idle mode and
active modes to reduce the overall power consumption. In all other sleep modes, the peripheral clock is already stopped.
Not all devices have all the peripherals associated with a bit in the power reduction registers. Setting a power reduction
bit for a peripheral that is not available will have no effect.
8.5 Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an AVR MCU controlled
system. In general, correct sleep modes should be selected and used to ensure that only the modules required for the
application are operating.
All unneeded functions should be disabled. In particular, the following modules may need special consideration when
trying to achieve the lowest possible power consumption.
8.5.1 Analog-to-Digital Converter - ADC

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any
sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to
“ADC – Analog to Digital Converter” on page 349 for details on ADC operation.
8.5.2 Analog Comparator - AC

When entering idle mode, the analog comparator should be disabled if not used. In other sleep modes, the analog
comparator is automatically disabled. However, if the analog comparator is set up to use the internal voltage reference as
input, the analog comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be
enabled, irrespective of sleep mode. Refer to “AC – Analog Comparator” on page 391 for details on how to configure the
analog comparator.
8.5.3 Brownout Detector

If the brownout detector is not needed by the application, this module should be turned off. If the brownout detector is
enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and always consume power. In the deeper sleep
modes, it can be turned off and set in sampled mode to reduce current consumption. Refer to “Brownout Detection” on
page 122 for details on how to configure the brownout detector.
XMEGA E MANUAL 114

8.5.4 Watchdog Timer
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled,
it will be enabled in all sleep modes and, hence, always consume power. Refer to “WDT – Watchdog Timer” on page 127
for details on how to configure the watchdog timer.
8.5.5 Internal 8MHz Oscillator

If the low power mode is not needed by the application, this feature should be turned off. If the lower mode is enabled, it
will be enabled in all sleep modes, and always consume power. Refer to “8MHz Calibrated Oscillator” on page 96 for
details on how to enable the low power mode.
8.5.6 UART Start Frame Detector

When entering the standby, extended standby or power save mode, the UART start frame detector should be disabled if
not used. When entering the power down sleep mode, the UART start frame detector must be disabled. In all other sleep
modes, the UART start frame detector is ignored. Refer to “USART” on page 279 for details on how to enable the start
frame detector.
8.5.7 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. Most important is to ensure that
no pins drive resistive loads. If the pin input sense is forced enabled, the corresponding pin input buffer will be enabled in
all sleep modes, and always consume power. If the input sense is not forced enabled, in sleep modes where the
Peripheral Clock (ClkPER) is stopped, the input buffers of the device will be disabled. This ensures that no power is
consumed by the input logic when not needed.
When the UART start frame detector is enabled, the input buffers of the corresponding UART pins are forced enabled
when entering sleep modes, and always consume power.
8.5.8 On-chip Debug System

If the On-chip debug system is enabled and the chip enters sleep mode, the main clock source is enabled and hence
always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
XMEGA E MANUAL 115

8.6 Register Description – Sleep
Bit 7 6 5 4 3 2 1 0
+0x00 – – – – SMODE[2:0] SEN

 Bit 3:1 – SMODE[2:0]: Sleep Mode Selection
These bits select sleep modes according to Table 8-2 on page 116.
Table 8-2. Sleep Mode
SMODE[2:0] Group configuration Description
000 IDLE Idle mode
001 – Reserved
010 PDOWN Power-down mode
011 PSAVE Power-save mode
100 – Reserved
101 – Reserved
110 STDBY Standby mode
111 ESTDBY Extended standby mode
 Bit 0 – SEN: Sleep Enable

This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruction is executed. To
avoid unintentional entering of sleep modes, it is recommended to write SEN just before executing the SLEEP
instruction and clear it immediately after waking up.
XMEGA E MANUAL 116

8.7 Register Description – Power Reduction
8.7.1 PRGEN – General Power Reduction Register
Bit 7 6 5 4 3 2 1 0
+0x00 XCL – – – – RTC EVSYS EDMA
Read/Write R/W R R R R R/W R/W R/W
 Bit 7 – XCL: XMEGA Custom Logic

Setting this bit stops the clock to the XMEGA Custom Logic. When this bit is cleared, the peripheral should be rein-
itialized to ensure proper operation.
 Bit 2 – RTC: Real-Time Counter
Setting this bit stops the clock to the real-time counter. When this bit is cleared, the peripheral should be reinitial-
ized to ensure proper operation.
 Bit 1 – EVSYS: Event System
Setting this stops the clock to the event system. When this bit is cleared, the module will continue as before it was
stopped.
 Bit 0 –EDMA: EDMA Controller
Setting this bit stops the clock to the EDMA controller. This bit can be set only if the EDMA controller is disabled.
8.7.2 PRPA – Power Reduction Port A Register
Bit 7 6 5 4 3 2 1 0
+0x01 – – – – – DAC ADC AC
Note: Disabling of analog modules stops the clock to the analog blocks themselves and not only the interfaces.

 Bit 2 – DAC: Power Reduction DAC
Setting this bit stops the clock to the DAC. The DAC should be disabled before stopped.
 Bit 1 – ADC: Power Reduction ADC
Setting this bit stops the clock to the ADC. The ADC should be disabled before stopped.
 Bit 0 – AC: Power Reduction Analog Comparator
Setting this bit stops the clock to the analog comparator. The AC should be disabled before shutdown.
XMEGA E MANUAL 117

8.7.3 PRPC/D – Power Reduction Port C/D Register
Bit 7 6 5 4 3 2 1 0
+0x03/+0x04 – TWI – USART0 SPI HIRES TC5 TC4
Read/Write R R/W R R/W R/W R/W R/W R/W
 Bit 6 – TWI: Two-Wire Interface
Setting this bit stops the clock to the two-wire interface. When this bit is cleared, the peripheral should be reinitial-
ized to ensure proper operation.
 Bit 4 – USART0
Setting this bit stops the clock to USART0. When this bit is cleared, the peripheral should be reinitialized to ensure
proper operation.
 Bit 3 – SPI: Serial Peripheral Interface
Setting this bit stops the clock to the SPI. When this bit is cleared, the peripheral should be reinitialized to ensure
proper operation.
 Bit 2 – HIRES: High-Resolution Extension
Setting this bit stops the clock to the high-resolution extension for the timer/counters. When this bit is cleared, the
peripheral should be reinitialized to ensure proper operation.
 Bit 1 – TC5: Timer/Counter 5
Setting this bit stops the clock to timer/counter 5. When this bit is cleared, the peripheral will continue like before
the shut down.
 Bit 0 – TC4: Timer/Counter 4
Setting this bit stops the clock to timer/counter 4. When this bit is cleared, the peripheral will continue like before
the shut down.
XMEGA E MANUAL 118

8.8 Register Summary – Sleep
+0x00 CTRL – – – – SMODE[2:0] SEN 116
8.9 Register Summary – Power Reduction

+0x00 PRGEN XCL – – – – RTC EVSYS EDMA 117
+0x01 PRPA – – – – – DAC ADC AC 117
+0x02 Reserved – – – – – – – –
+0x03 PRPC – TWI – USART0 SPI HIRES TC5 TC4 118
+0x04 PRPD – – – USART0 – – TC5 – 118
+0x05 Reserved – – – – – – – –
+0x06 Reserved – – – – – – – –
+0x07 Reserved – – – – – – – –
XMEGA E MANUAL 119

9. Reset System
9.1 Features
 Reset the microcontroller and set it to initial state when a reset source goes active
 Multiple reset sources that cover different situations
 Power-on reset
 External reset
 Watchdog reset
 Brownout reset
 PDI reset
 Software reset
 Asynchronous operation
 No running system clock in the device is required for reset
 Reset status register for reading the reset source from the application code
9.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontrollers operates below its power supply rating. If a
reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O
pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to
their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the
content of the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
An overview of the reset system is shown in Figure 9-1 on page 121.
XMEGA E MANUAL 120

Figure 9-1. Reset System Overview
MCU Status
Register (MCUSR)
PORF
BORF
EXTRF
WDRF
JTRF
Power-on Reset
Brown-out
BODLEVEL [2:0] Reset
Pull-up Resistor
SPIKE External
FILTER Reset
PDI
Reset
Software
Reset
Watchdog
Reset
ULP
Delay Counters
Oscillator TIMEOUT
SUT[1:0]
9.3 Reset Sequence

A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
 Reset counter delay
 Oscillator startup
 Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
9.3.1 Reset Counter

The reset counter can delay reset release with a programmable period from when all reset requests are released. The
reset delay is timed from the 1kHz output of the ultra low power (ULP) internal oscillator, and in addition 24 system clock
cycles (clkSYS) are counted before reset is released. The reset delay is set by the STARTUPTIME fuse bits. The
selectable delays are shown in Table 9-1 on page 121.
Table 9-1. Reset Delay
SUT[1:0] Number of 1kHz ULP oscillator clock cycles Recommended usage
00 64K ClkULP+ 24 ClkSYS Stable frequency at startup
01 4K ClkULP + 24 ClkSYS Slowly rising power
10 Reserved –
11 24 ClkSYS Fast rising power or BOD enabled
Whenever a reset occurs, the clock system is reset and the 2MHz output from the internal 8MHz oscillator is chosen as
the source for ClkSYS.
XMEGA E MANUAL 121

9.3.2 Oscillator Startup
After the reset delay, the 8MHz internal oscillator clock is started, and its calibration values are automatically loaded from
the production signature row to the calibration registers.
9.4 Reset Sources
9.4.1 Power-on Reset

A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
Figure 9-2. MCU Startup, RESET Tied to VCC

VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 9-3. MCU Startup, RESET Extended Externally

VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
9.4.2 Brownout Detection

The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
When the BOD is enabled and VCC decreases to a value below the trigger level (VBOT- in Figure 9-4 on page 123), the
brownout reset is immediately activated.
When VCC increases above the trigger level (VBOT+ in Figure 9-4 on page 123), the reset counter starts the MCU after the
timeout period, tTOUT has expired.
The trigger level has a hysteresis to ensure spike free brownout detection. The hysteresis on the detection level should
be interpreted as VBOT+= VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
The BOD circuit will detect a drop in VCC only if the voltage stays below the trigger level for longer than tBOD.
XMEGA E MANUAL 122

Figure 9-4. Brownout Detection Reset
tBOD
VCC VBOT+
VBOT-
TIME-OUT tTOUT
INTERNAL
RESET
For BOD characterization data consult the device datasheet. The programmable BODLEVEL setting is shown in Table 9-
2.
Table 9-2. Programmable BODLEVEL Setting
BOD level Fuse BODLEVEL[2:0](2) VBOT(1) Unit
BOD level 0 111 1.6
BOD level 1 110 1.8
BOD level 2 101 2.0
BOD level 3 100 2.2

V
BOD level 4 011 2.4
BOD level 5 010 2.6
BOD level 6 001 2.8
BOD level 7 000 3.0
Notes: 1. The values are nominal values only. For accurate, actual numbers, consult the device datasheet.
2. Changing these fuse bits will have no effect until leaving programming mode.
The BOD circuit has three modes of operation:

 Disabled: In this mode, there is no monitoring of the VCC level.
 Enabled: In this mode, the VCC level is continuously monitored, and a drop in VCC below VBOT for a period of tBOD
will give a brownout reset.
 Sampled: In this mode, the BOD circuit will sample the VCC level with a period identical to that of the 1kHz output
from the ultra low power (ULP) internal oscillator. Between each sample, the BOD is turned off. This mode will
reduce the power consumption compared to the enabled mode, but a fall in the VCC level between two positive
edges of the 1kHz ULP oscillator output will not be detected. If a brownout is detected in this mode, the BOD circuit
is set in enabled mode to ensure that the device is kept in reset until VCC is above VBOT again.
The BODACT fuse determines the BOD setting for active mode and idle mode, while the BODPD fuse determines the
brownout detection setting for all sleep modes, except idle mode.
XMEGA E MANUAL 123

Table 9-3. BOD Setting Fuse Decoding
BODACT[1:0]/ BODPD[1:0] Mode
00 Reserved
01 Sampled
10 Enabled
11 Disabled
9.4.3 External Reset

The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
Figure 9-5. External Reset Characteristics

CC
tEXT
For external reset characterization data consult the device datasheet.
9.4.4 Watchdog Reset

The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timout period, a watchdog reset will be given. The watchdog reset is active for one to
two 2MHz clock cycles from the 8MHz internal oscillator.
Figure 9-6. Watchdog Reset

CC
1-2 2MHz cycles
For information on configuration and use of the WDT, refer to the “WDT – Watchdog Timer” on page 127.
XMEGA E MANUAL 124

9.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
Figure 9-7. Software Reset

CC
1-2 2MHz cycles

SOFTWARE
9.4.6 Program and Debug Interface Reset

The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
XMEGA E MANUAL 125

Bit 7 6 5 4 3 2 1 0
+0x00 – – SRF PDIRF WDRF BORF EXTRF PORF
Initial Value – – – – – – – –

 Bit 5 – SRF: Software Reset Flag
This flag is set if a software reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
 Bit 4 – PDIRF: Program and Debug Interface Reset Flag
This flag is set if a programming interface reset occurs. The flag will be cleared by a power-on reset or by writing a
one to the bit location.
 Bit 3 – WDRF: Watchdog Reset Flag
This flag is set if a watchdog reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
 Bit 2 – BORF: Brownout Reset Flag
This flag is set if a brownout reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
 Bit 1 – EXTRF: External Reset Flag
This flag is set if an external reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
 Bit 0 – PORF: Power On Reset Flag
This flag is set if a power-on reset occurs. Writing a one to the flag will clear the bit location.
Bit 7 6 5 4 3 2 1 0
+0x01 – – – – – – – SWRST

 Bit 0 – SWRST: Software Reset
When this bit is set, a software reset will occur. The bit is cleared when a reset is issued. This bit is protected by
the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page
13.

+0x00 STATUS – – SRF PDIRF WDRF BORF EXTRF PORF 126
+0x01 CTRL – – – – – – – SWRST 126
XMEGA E MANUAL 126

10. WDT – Watchdog Timer
10.1 Features
 Issues a device reset if the timer is not reset before its timeout period
 Asynchronous operation from dedicated oscillator
 1kHz output of the 32kHz ultra low power oscillator
 11 selectable timeout periods, from 8ms to 8s
 Two operation modes:
 Normal mode
 Window mode
 Configuration lock to prevent unwanted changes
10.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
10.3 Normal Mode Operation

In normal mode operation, a single timeout period is set for the WDT. If the WDT is not reset from the application code
before the timeout occurs, then the WDT will issue a system reset. There are 11 possible WDT timeout (TOWDT) periods,
selectable from 8ms to 8s, and the WDT can be reset at any time during the timeout period. A new WDT timeout period
will be started each time the WDT is reset by the WDR instruction. The default timeout period is controlled by fuses.
Normal mode operation is illustrated in Figure 10-1 on page 127.
Figure 10-1. Normal Mode Operation
XMEGA E MANUAL 127

10.4 Window Mode Operation
In window mode operation, the WDT uses two different timeout periods, a "closed" window timeout period (TOWDTW) and
the normal timeout period (TOWDT). The closed window timeout period defines a duration of from 8ms to 8s where the
WDT cannot be reset. If the WDT is reset during this period, the WDT will issue a system reset. The normal WDT timeout
period, which is also 8ms to 8s, defines the duration of the "open" period during which the WDT can (and should) be
reset. The open period will always follow the closed period, and so the total duration of the timeout period is the sum of
the closed window and the open window timeout periods. The default closed window timeout period is controlled by fuses
(both open and closed periods are controlled by fuses). The window mode operation is illustrated in Figure 10-2.
Figure 10-2. Window Mode Operation
10.5 Watchdog Timer Clock

The WDT is clocked from the 1kHz output from the 32kHz ultra low power (ULP) internal oscillator. Due to the ultra low
power design, the oscillator is not very accurate, and so the exact timeout period may vary from device to device. When
designing software which uses the WDT, this device-to-device variation must be kept in mind to ensure that the timeout
periods used are valid for all devices. For more information on ULP oscillator accuracy, consult the device datasheet.
10.6 Configuration Protection and Lock

The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings.
The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing
the WDT control registers. In addition, for the new configuration to be written to the control registers, the register’s
change enable bit must be written at the same time.
The second mechanism locks the configuration by setting the WDT lock fuse. When this fuse is set, the watchdog time
control register cannot be changed; hence, the WDT cannot be disabled from software. After system reset, the WDT will
resume at the configured operation. When the WDT lock fuse is programmed, the window mode timeout period cannot
be changed, but the window mode itself can still be enabled or disabled.
XMEGA E MANUAL 128

Bit 7 6 5 4 3 2 1 0
+0x00 – – PER[3:0] ENABLE CEN
Read/Write (unlocked) R R R/W R/W R/W R/W R/W R/W
Read/Write (locked) R R R R R R R R
Initial value (x = fuse) 0 0 X X X X X 0
 Bits 7:6 – Reserved

 Bits 5:2 – PER[3:0]: Timeout Period
These bits determine the watchdog timeout period as a number of 1kHz ULP oscillator cycles. In window mode
operation, these bits define the open window period. The different typical timeout periods are found in Table 10-1.
The initial values of these bits are set by the watchdog timeout period (WDP) fuses, which are loaded at power-on.
In order to change these bits, the CEN bit must be written to 1 at the same time. These bits are protected by the
configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protection”
on page 13.
Table 10-1. Watchdog Timeout Periods
PER[3:0] Group configuration Typical timeout periods
0000 8CLK 8ms
0001 16CLK 16ms
0010 32CLK 32ms
0011 64CLK 64ms
0100 128CLK 0.128s
0101 256CLK 0.256s
0110 512CLK 0.512s
0111 1KCLK 1.0s
1000 2KCLK 2.0s
1001 4KCLK 4.0s
1010 8KCLK 8.0s
1011 – Reserved
1100 – Reserved
1101 – Reserved
1110 – Reserved
1111 – Reserved
Note: Reserved settings will not give any timeout.
XMEGA E MANUAL 129

This bit enables the WDT. Clearing this bit disables the watchdog timer.
In order to change this bit, the CEN bit in “CTRL – Control Register” on page 129 must be written to one at the
same time. This bit is protected by the configuration change protection mechanism. For a detailed description,
refer to “Configuration Change Protection” on page 13.
 Bit 0 – CEN: Change Enable
This bit enables the ability to change the configuration of the “CTRL – Control Register” on page 129. When writing
a new value to this register, this bit must be written to one at the same time for the changes to take effect. This bit
is protected by the configuration change protection mechanism. For a detailed description, refer to “Configuration
Change Protection” on page 13.
10.7.2 WINCTRL – Window Mode Control Register
Bit 7 6 5 4 3 2 1 0
+0x01 – – WPER[3:0] WEN WCEN
Read/Write (unlocked) R R R/W R/W R/W R/W R/W R/W
Read/Write (locked) R R R R R R R/W R/W
Initial value (x = fuse) 0 0 X X X X X 0

 Bit 5:2 – WPER[3:0]: Window Mode Timeout Period
These bits determine the closed window period as a number of 1kHz ULP oscillator cycles in window mode opera-
tion. The typical different closed window periods are found in Table 10-2. The initial values of these bits are set by
the watchdog window timeout period (WDWP) fuses, and are loaded at power-on. In normal mode these bits are
not in use.
In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by
the configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protec-
tion” on page 13.
Table 10-2. Watchdog Closed Window Periods
WPER[3:0] Group configuration Typical closed window periods
0000 8CLK 8ms
0001 16CLK 16ms
0010 32CLK 32ms
0011 64CLK 64ms
0100 128CLK 0.128s
0101 256CLK 0.256s
0110 512CLK 0.512s
0111 1KCLK 1.0s
1000 2KCLK 2.0s
1001 4KCLK 4.0s
1010 8KCLK 8.0s
1011 – Reserved
XMEGA E MANUAL 130

WPER[3:0] Group configuration Typical closed window periods
1100 – Reserved
1101 – Reserved
1110 – Reserved
1111 – Reserved
Note: Reserved settings will not give any timeout for the window.
 Bit 1 – WEN: Window Mode Enable

This bit enables the window mode. In order to change this bit, the WCEN bit in “WINCTRL – Window Mode Control
Register” on page 130 must be written to one at the same time. This bit is protected by the configuration change
protection mechanism. For a detailed description, refer to “Configuration Change Protection” on page 13.
 Bit 0 – WCEN: Window Mode Change Enable
This bit enables the ability to change the configuration of the “WINCTRL – Window Mode Control Register” on
page 130. When writing a new value to this register, this bit must be written to one at the same time for the
changes to take effect. This bit is protected by the configuration change protection mechanism, but not protected
by the WDT lock fuse.
Bit 7 6 5 4 3 2 1 0
+0x02 – – – – – – – SYNCBUSY

 Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set after writing to the CTRL or WINCTRL registers and the data are being synchronized from the sys-
tem clock to the WDT clock domain. This bit is automatically cleared after the synchronization is finished.
Synchronization will take place only when the ENABLE bit for the Watchdog Timer is set.

+0x00 CTRL – – PER[3:0] ENABLE CEN 129
+0x01 WINCTRL – – WPER[3:0] WEN WCEN 130
+0x02 STATUS – – – – – – – SYNCBUSY 131
XMEGA E MANUAL 131

11. PMIC – Interrupts and Programmable Multilevel Interrupt Controller
11.1 Features
 Short and predictable interrupt response time
 Separate interrupt configuration and vector address for each interrupt
 Programmable multilevel interrupt controller
 Interrupt prioritizing according to level and vector address
 Three selectable interrupt levels for all interrupts: low, medium and high
 Selectable, round-robin priority scheme within low-level interrupts
 Non-maskable interrupts for critical functions
 Interrupt vectors optionally placed in the application section or the boot loader section
11.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
11.3 Operation
Interrupts must be globally enabled for any interrupts to be generated. This is done by setting the global interrupt enable
( I ) bit in the CPU “SREG – Status Register” on page 17. The I bit will not be cleared when an interrupt is acknowledged.
Each interrupt level must also be enabled before interrupts with the corresponding level can be generated.
When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the interrupt request. Based on
the interrupt level and interrupt priority of any ongoing interrupts, the interrupt is either acknowledged or kept pending
until it has priority. When the interrupt request is acknowledged, the program counter is updated to point to the interrupt
vector. The interrupt vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.
After returning from the interrupt handler, program execution continues from where it was before the interrupt occurred.
One instruction is always executed before any pending interrupt is served.
The PMIC status register contains state information that ensures that the PMIC returns to the correct interrupt level when
the RETI (interrupt return) instruction is executed at the end of an interrupt handler. Returning from an interrupt will return
the PMIC to the state it had before entering the interrupt. The status register (SREG) is not saved automatically upon an
interrupt request. The RET (subroutine return) instruction cannot be used when returning from the interrupt handler
routine, as this will not return the PMIC to its correct state.
XMEGA E MANUAL 132

Figure 11-1. Interrupt Controller Overview
Interrupt Controller
Priority
INT LEVEL
decoder
Peripheral 1 INT REQ

INT ACK CPU ”RETI”
CPU INT ACK
INT LEVEL
INT LEVEL CPU
CPU INT REQ
Peripheral n
INT REQ
INT REQ
INT ACK
INT ACK Global
Interrupt
LEVEL Enable STATUS Enable Wake-up Sleep
CTRL INTPRI CPU.SREG Controller
11.4 Interrupts
All interrupts and the reset vector each have a separate program vector address in the program memory space. The
lowest address in the program memory space is the reset vector. All interrupts are assigned with individual control bits for
enabling and setting the interrupt level, and this is set in the control registers for each peripheral that can generate
interrupts. Details on each interrupt are described in the peripheral where the interrupt is available.
Each interrupt has an interrupt flag associated with it. When the interrupt condition is present, the interrupt flag will be set,
even if the corresponding interrupt is not enabled. For most interrupts, the interrupt flag is automatically cleared when
executing the interrupt vector. Writing a logical one to the interrupt flag will also clear the flag. Some interrupt flags are
not cleared when executing the interrupt vector, and some are cleared automatically when an associated register is
accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the interrupt flag will be set
and remembered until the interrupt has priority. If an interrupt condition occurs while the corresponding interrupt is not
enabled, the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software.
Similarly, if one or more interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then executed according to their
order of priority.
Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock bits are programmed.
This feature improves software security. Refer to “Memory Programming” on page 411 for details on lock bit settings.
Interrupts are automatically disabled for up to four CPU clock cycles when the configuration change protection register is
written with the correct signature. Refer to “Configuration Change Protection” on page 13 for more details.
11.4.1 NMI – Non-maskable Interrupts

Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non-maskable interrupts
must be enabled before they can be used. Refer to the device datasheet for NMI present on each device.
An NMI will be executed regardless of the setting of the I bit in the CPU status register, and it will never change the I bit.
No other interrupts can interrupt a NMI handler. If more than one NMI is requested at the same time, priority is static
according to the interrupt vector address, where the lowest address has highest priority.
11.4.2 Interrupt Response Time

The interrupt response time for all the enabled interrupts is three CPU clock cycles, minimum; one cycle to finish the
ongoing instruction and two cycles to store the program counter to the stack. After the program counter is pushed on the
stack, the program vector for the interrupt is executed. The jump to the interrupt handler takes three clock cycles.
If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is
served. See Figure 11-2 on page 134 for more details.
XMEGA E MANUAL 133

Figure 11-2. Interrupt Execution of a Multi-cycle Instruction
If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock
cycles. In addition, the response time is increased by the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the program counter.
During these clock cycles, the program counter is popped from the stack and the stack pointer is incremented.
11.5 Interrupt Level

The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives
the interrupt level for the interrupt. The interrupt levels and their corresponding bit values for the interrupt level
configuration of all interrupts are shown in Table 11-1 on page 135.
XMEGA E MANUAL 134

Table 11-1. Interrupt Levels
Interrupt level configuration Group configuration Description
00 OFF Interrupt disabled.
01 LO Low-level interrupt
10 MED Medium-level interrupt
11 HI High-level interrupt
The interrupt level of an interrupt request is compared against the current level and status of the interrupt controller. An
interrupt request of a higher level will interrupt any ongoing interrupt handler from a lower level interrupt. When returning
from the higher level interrupt handler, the execution of the lower level interrupt handler will continue.
11.6 Interrupt Priority

Within each interrupt level, all interrupts have a priority. When several interrupt requests are pending, the order in which
interrupts are acknowledged is decided both by the level and the priority of the interrupt request. Interrupts can be
organized in a static or dynamic (round-robin) priority scheme. High- and medium-level interrupts and the NMI will always
have static priority. For low-level interrupts, static or dynamic priority scheduling can be selected.
11.6.1 Static Priority

Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector address decides the priority
within one interrupt level, where the lowest interrupt vector address has the highest priority. Refer to the device datasheet
for the interrupt vector table with the base address for all modules and peripherals with interrupt capability. Refer to the
interrupt vector summary of each module and peripheral in this manual for a list of interrupts and their corresponding
offset address within the different modules and peripherals.
Figure 11-3. Static Priority

Lowes t Addres s IVEC 0 Highes t Priority
:
:
:
IVEC x
IVEC x+1
:
:
:
Highes t Addres s IVEC N Lowes t Priority
11.6.2 Round-robin Scheduling

To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be
served, the PMIC offers round-robin scheduling for low-level interrupts. When round-robin scheduling is enabled, the
interrupt vector address for the last acknowledged low-level interrupt will have the lowest priority the next time one or
more interrupts from the low level is requested.
XMEGA E MANUAL 135

Figure 11-4. Round-robin Scheduling
IV EC x las t ack now le dge d IV EC x+1 las t ack now le dge d

inte rrupt inte rrupt
IV EC 0 IV EC 0
: :
: :
: :
IV EC x Low est Priority IV EC x

IV EC x+1 Highest Priority IV EC x+1 Low est Priority
IV EC x+2 Highest Priority
:
:
:
:
:
:
IV EC N IV EC N
11.7 Interrupt Vector Locations

Table 11-2 shows reset and Interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings.
If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be
placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors
are in the Boot section or vice versa.
Table 11-2. Reset and Interrupt Vectors Placement
BOOTRST IVSEL Reset address Interrupt vectors start address
1 0 0x0000 0x0002
1 1 0x0000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x0002
0 1 Boot Reset Address Boot Reset Address + 0x0002
XMEGA E MANUAL 136

Bit 7 6 5 4 3 2 1 0
+0x00 NMIEX – – – – HILVLEX MEDLVLEX LOLVLEX
 Bit 7 – NMIEX: Non-Maskable Interrupt Executing

This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the
interrupt handler.
 Bit 2 – HILVLEX: High-level Interrupt Executing
This flag is set when a high-level interrupt is executing or when the interrupt handler has been interrupted by an
NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
 Bit 1 – MEDLVLEX: Medium-level Interrupt Executing
This flag is set when a medium-level interrupt is executing or when the interrupt handler has been interrupted by
an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
 Bit 0 – LOLVLEX: Low-level Interrupt Executing
This flag is set when a low-level interrupt is executing or when the interrupt handler has been interrupted by an
interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
11.8.2 INTPRI – Interrupt Priority Register
Bit 7 6 5 4 3 2 1 0
+0x01 INTPRI[7:0]
 Bit 7:0 – INTPRI: Interrupt Priority

When round-robin scheduling is enabled, this register stores the interrupt vector of the last acknowledged low-
level interrupt. The stored interrupt vector will have the lowest priority the next time one or more low-level interrupts
are pending. The register is accessible from software to change the priority queue. This register is not reinitialized
to its initial value if round-robing scheduling is disabled, and so if default static priority is needed, the register must
be written to zero.
Bit 7 6 5 4 3 2 1 0
+0x02 RREN IVSEL – – – HILVLEN MEDLVLEN LOLVLEN
Read/Write R/W R/W R R R R/W R/W R/W
 Bit 7 – RREN: Round-robin Scheduling Enable

When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts. When this bit is
cleared, the priority is static according to interrupt vector address, where the lowest address has the highest
priority.
XMEGA E MANUAL 137

 Bit 6 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the application section in flash.
When this bit is set (one), the interrupt vectors are placed in the beginning of the boot section of the flash. Refer to
the device datasheet for the absolute address.
tion” on page 13 for details.
 Bit 2 – HILVLEN: High-level Interrupt Enable(1)
When this bit is set, all high-level interrupts are enabled. If this bit is cleared, high-level interrupt requests will be
ignored.
 Bit 1 – MEDLVLEN: Medium-level Interrupt Enable(1)
When this bit is set, all medium-level interrupts are enabled. If this bit is cleared, medium-level interrupt requests
will be ignored.
 Bit 0 – LOLVLEN: Low-level Interrupt Enable(1)
When this bit is set, all low-level interrupts are enabled. If this bit is cleared, low-level interrupt requests will be
ignored.
Note: 1. Ignoring interrupts will be effective one cycle after the bit is cleared.

+0x00 STATUS NMIEX – – – – HILVLEX MEDLVLEX LOLVLEX 137
+0x01 INTPRI INTPRI[7:0] 137
+0x02 CTRL RREN IVSEL – – – HILVLEN MEDLVLEN LOLVLEN 137
XMEGA E MANUAL 138

12. I/O Ports
12.1 Features
 General purpose input and output pins with individual configuration
 Output driver with configurable driver and pull settings:
 Totem-pole
 Wired-AND
 Wired-OR
 Bus-keeper
 Inverted I/O
 Input with synchronous and/or asynchronous sensing with interrupts and events:
 Sense both edges
 Sense rising edges
 Sense falling edges
 Sense low level
 Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
 Optional slew rate control per I/O port
 Asynchronous pin change sensing that can wake the device from all sleep modes
 Port interrupt with pin masking
 Efficient and safe access to port pins
 Hardware read-modify-write through dedicated toggle/clear/set registers
 Configuration of multiple pins in a single operation
 Mapping of port registers into bit-accessible I/O memory space
 Peripheral clocks output on port pin
 Real-time counter clock output to port pin
 Event channels can be output on port pin
 Remapping of digital peripheral pin functions
 Selectable USART, and timer/counter input/output pin locations
 Selectable analog comparator outputs pins locations
12.2 Overview
AVR XMEGA microcontrollers have flexible general purpose I/O ports. One port consists of up to eight port pins: pin 0 to
7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement
synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions.
Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the
modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other peripherals, such as analog
comparator outputs, USART and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out
versus application needs.
Figure 12-1 on page 140 shows the I/O pin functionality and the registers that are available for controlling a pin.
XMEGA E MANUAL 139

Figure 12-1. General I/O Pin Functionality
Pull Enable
C
o Pull Keep
n
PINnCTRL
t Pull Direction
D Q r
o
l
R
L
o Input Disable
g
i Wired AND/OR
c Slew Rate Limit
Inverted I/O
OUTn
Pxn
D Q
DIRn
D Q
Synchronizer
INn
Q D Q D
R R
Digital Input Pin
Analog Input/Output
12.3 I/O Pin use and Configuration

Each port has one data direction (DIR) register and one data output value (OUT) register that are used for port pin
control. The data input value (IN) register is used for reading the port pins. In addition, each pin has a pin configuration
(PINnCTRL) register for additional pin configuration.
Direction of the pin is decided by the DIRn bit in the DIR register. If DIRn is written to one, pin n is configured as an output
pin. If DIRn is written to zero, pin n is configured as an input pin.
When direction is set as output, the OUTn bit in OUT is used to set the value of the pin. If OUTn is written to one, pin n is
driven high. If OUTn is written to zero, pin n is driven low.
The IN register is used for reading pin values. A pin value can always be read regardless of whether the pin is configured
as input or output, except if digital input is disabled.
The I/O pins are tri-stated when a reset condition becomes active, even if no clocks are running.
The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole,
wired-AND, or wired-OR configuration. It is also possible to enable inverted input and output for a pin.
A totem-pole output has four possible pull configurations: totem-pole (push-pull), pull-down, pull-up, and bus-keeper. The
bus-keeper is active in both directions. This is to avoid oscillation when disabling the output. The totem-pole
XMEGA E MANUAL 140

configurations with pull-up and pull-down have active resistors only when the pin is set as input. This feature eliminates
unnecessary power consumption. For wired-AND and wired-OR configuration, the optional pull-up and pull-down
resistors are active in both input and output directions.
Since pull configuration is configured through the pin configuration register, all intermediate port states during switching
of the pin direction and pin values are avoided.
The I/O pin configurations are summarized with simplified schematics in Figure 12-2 to Figure 12-7 on page 143.
12.3.1 Totem-pole
In the totem-pole (push-pull) configuration, the pin is driven low or high according to the corresponding bit setting in the
OUT register. In this configuration, there is no current limitation for sink or source other than what the pin is capable of. If
the pin is configured for input, the pin will float if no external pull resistor is connected.
Figure 12-2. I/O Pin Configuration - Totem-pole (Push-pull)

DIRxn
OUTxn Pxn
INxn
12.3.1.1 Totem-pole with Pull-down

In this mode, the configuration is the same as for totem-pole mode, expect the pin is configured with an internal pull-down
resistor when set as input.
Figure 12-3. I/O Pin Configuration - Totem-pole with Pull-down (on Input)
DIRxn
OUTxn Pxn
INxn
XMEGA E MANUAL 141

12.3.1.2 Totem-pole with Pull-up
In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pull-up when set as input.
Figure 12-4. I/O Pin Configuration - Totem-pole with Pull-up (on Input)
DIRxn
OUTxn Pxn
INxn
12.3.2 Bus-keeper
In the bus-keeper configuration, it provides a weak bus-keeper that will keep the pin at its logic level when the pin is no
longer driven to high or low. If the last level on the pin/bus was 1, the bus-keeper configuration will use the internal pull
resistor to keep the bus high. If the last logic level on the pin/bus was 0, the bus-keeper will use the internal pull resistor
to keep the bus low.
Figure 12-5. I/O Pin Configuration - Totem-pole with Bus-keeper
DIRxn
OUTxn Pxn
INxn
XMEGA E MANUAL 142

12.3.3 Wired-OR
In the wired-OR configuration, the pin will be driven high when the corresponding bits in the OUT and DIR registers are
written to one. When the OUT register is set to zero, the pin is released, allowing the pin to be pulled low with the internal
or an external pull-resistor. If internal pull-down is used, this is also active if the pin is set as input.
Figure 12-6. Output Configuration - Wired-OR with Optional Pull-down
OUTxn
Pxn
INxn
12.3.4 Wired-AND
In the wired-AND configuration, the pin will be driven low when the corresponding bits in the OUT and DIR registers are
written to zero. When the OUT register is set to one, the pin is released allowing the pin to be pulled high with the internal
or an external pull-resistor. If internal pull-up is used, this is also active if the pin is set as input.
Figure 12-7. Output Configuration - Wired-AND with Optional Pull-up
INxn
Pxn
OUTxn
XMEGA E MANUAL 143

12.4 Reading the Pin Value
Independent of the pin data direction, the pin value can be read from the IN register, as shown in Figure 12-1 on page
140. If the digital input is disabled, the pin value cannot be read. The IN register bit and the preceding flip-flop constitute
a synchronizer. The synchronizer introduces a delay on the internal signal line. Figure 12-8 on page 144 shows a timing
diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation
delays are denoted as tpd,max and tpd,min, respectively.
Figure 12-8. Synchronization when reading a Pin Value
PERIPHERAL CLK
INSTRUCTIONS xxx xxx lds r17, PORTx+IN
SYNCHRONIZER FLIPFLOP
INxn
r17 0x00 0xFF

tpd, max
tpd, min
12.5 Input Sense Configuration

Input sensing is used to detect an edge or level on the I/O pin input. The different sense configurations that are available
for each pin are detection of a rising edge, falling edge, or any edge or detection of a low level. High level can be
detected by using the inverted input configuration. Input sensing can be used to trigger interrupt requests (IREQ) or
events when there is a change on the pin.
The I/O pins support synchronous and asynchronous input sensing. Synchronous sensing requires the presence of the
peripheral clock, while asynchronous sensing does not require any clock.
Figure 12-9. Input Sensing

Asynchronous sensing
EDGE
DETECT Interrupt
IRQ
Control
Synchronous sensing
Pxn
Synchronizer
INn
EDGE Synchronous
D Q D Q
DETECT Events
R R
INVERTED I/O
Asynchronous
Events
XMEGA E MANUAL 144

12.6 Port Interrupt
Each port has one interrupt vector, and it is configurable which pins on the port will trigger it. Port interrupt must be
enabled before it can be used. Which sense configurations can be used to generate interrupt is dependent on whether
synchronous or asynchronous input sensing is available for the selected pin.
For synchronous sensing, all sense configurations can be used to generate interrupts. For edge detection, the changed
pin value must be sampled once by the peripheral clock for an interrupt request to be generated.
For asynchronous sensing, only port pin 2 on each port has full asynchronous sense support. This means that for edge
detection, pin 2 will detect and latch any edge and it will always trigger an interrupt request. The other port pins have
limited asynchronous sense support. This means that for edge detection, the changed value must be held until the device
wakes up and a clock is present. If the pin value returns to its initial value before the end of the device wake-up time, the
device will still wake up, but no interrupt request will be generated.
A low level can always be detected by all pins, regardless of a peripheral clock being present or not. If a pin is configured
for low-level sensing, the interrupt will trigger as long as the pin is held low. In active mode, the low level must be held
until the completion of the currently executing instruction for an interrupt to be generated. In all sleep modes, the low level
must be kept until the end of the device wake-up time for an interrupt to be generated. If the low level disappears before
the end of the wake-up time, the device will still wake up, but no interrupt will be generated.
Table 12-1, Table 12-2, and Table 12-3 summarize when interrupt can be triggered for the various input sense
configurations.
Table 12-1. Synchronous Sense Support
Sense settings Supported Interrupt description
Rising edge Yes Always triggered
Falling edge Yes Always triggered
Any edge Yes Always triggered
Low level Yes Pin level must be kept unchanged during wake up
Table 12-2. Full Asychronous Sense Support
Rising edge Yes Always triggered
Falling edge Yes Always triggered
Any edge Yes Always triggered
Table 12-3. Limited Asynchronous Sense Support
Rising edge No -
Falling edge No -
Any edge Yes Pin level must be kept unchanged during wake up
XMEGA E MANUAL 145

12.7 Port Event
Port pins can generate a synchronous event when there is a change on the pin, or an asynchronous event, where the pin
level is transferred internally without any delay. The sense configurations decide the conditions for each pin to generate
synchronous events. Synchronous event generation requires the presence of a peripheral clock, while asynchronous
event generation does not requires any clock. For edge sensing, the changed pin value must be sampled once by the
peripheral clock for a synchronous event to be generated.
For level sensing, a low-level pin value will not generate synchronous events, and a high-level pin value will continuously
generate synchronous events. For synchronous events to be generated on a low level, the pin configuration must be set
to inverted I/O.
For asynchronous event generation in all sleep modes where the clock is not present, the digital input buffer of the
selected pin must be forced enable. Table 12-6 on page 153 for details.
Table 12-4. Synchronous Event Sense Support
Sense settings Signal event Data event
Rising edge Rising edge Pin value
Falling edge Falling edge Pin value
Both edge Any edge Pin value
Low level Pin value Pin value
12.8 Alternate Port Functions

Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral.
The port override signals and related logic (grey) are shown in Figure 12-10 on page 147. These signals are not
accessible from software, but are internal signals between the overriding peripheral and the port pin.
XMEGA E MANUAL 146

Figure 12-10. Port Override Signals and Related Logic
Pull Enable
Pull Keep
C
o
Pull Direction
n
PINnCTRL t
r
D Q
o
l
R
L Digital Input Disable (DID)
o DID Override Value
g
i DID Override Enable
c
Wired AND/OR
Slew Rate Limit
Inverted I/O
OUTn
Pxn
D Q
OUT Override Value

R
OUT Override Enable
DIRn
D Q
DIR Override Value

R
DIR Override Enable
Synchronizer
INn
Q D Q D
R R
Digital Input Pin
Analog Input/Output
12.9 Slew Rate Control

Slew rate control can be enabled for each I/O port individually. Enabling the slew rate limiter will typically increase the
rise/fall time by 50% to 150%, depending on operating conditions and load. For information about the characteristics of
the slew rate limiter, refer to the device datasheet.
12.10 Clock and Event Output

It is possible to output the peripheral clock and event channel 0 events to a pin. This can be used to clock, control, and
synchronize external functions and hardware to internal device timing. The output port pin is selectable. If an event
occurs, it remains visible on the port pin as long as the event lasts, normally one peripheral clock cycle.
XMEGA E MANUAL 147

12.11 Multi-pin Configuration
The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the
port pin configuration registers. A mask register decides which port pin is configured when one port pin register is written,
while avoiding several pins being written the same way during identical write operations.
12.12 Virtual Ports

Virtual port registers allow the port registers to be mapped virtually in the bit-accessible I/O memory space. When this is
done, writing to the virtual port register will be the same as writing to the real port register. This enables the use of I/O
memory-specific instructions, such as bit-manipulation instructions, on a port register that normally resides in the
extended I/O memory space. There are four virtual ports, and so four ports can be mapped at the same time.
XMEGA E MANUAL 148

12.13 Register Descriptions – Ports
12.13.1 DIR – Data Direction Register
Bit 7 6 5 4 3 2 1 0
+0x00 DIR[7:0]
 Bit 7:0 – DIR[7:0]: Data Direction

This register sets the data direction for the individual pins of the port. If DIRn is written to one, pin n is configured
as an output pin. If DIRn is written to zero, pin n is configured as an input pin.
12.13.2 DIRSET – Data Direction Set Register
Bit 7 6 5 4 3 2 1 0
+0x01 DIRSET[7:0]
 Bit 7:0 – DIRSET[7:0]: Port Data Direction Set

This register can be used instead of a read-modify-write to set individual pins as output. Writing a one to a bit will
set the corresponding bit in the DIR register. Reading this register will return the value of the DIR register.
12.13.3 DIRCLR – Data Direction Clear Register
Bit 7 6 5 4 3 2 1 0
+0x02 DIRCLR[7:0]
 Bit 7:0 – DIRCLR[7:0]: Port Data Direction Clear

This register can be used instead of a read-modify-write to set individual pins as input. Writing a one to a bit will
clear the corresponding bit in the DIR register. Reading this register will return the value of the DIR register.
12.13.4 DIRTGL – Data Direction Toggle Register
Bit 7 6 5 4 3 2 1 0
+0x03 DIRTGL[7:0]
 Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle

This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a
bit will toggle the corresponding bit in the DIR register. Reading this register will return the value of the DIR
register.
XMEGA E MANUAL 149

12.13.5 OUT – Data Output Value Register
Bit 7 6 5 4 3 2 1 0
+0x04 OUT[7:0]
 Bit 7:0 – OUT[7:0]: Port Data Output Value

This register sets the data output value for the individual pins of the port. If OUTn is written to one, pin n is driven
high. If OUTn is written to zero, pin n is driven low. For this setting to have any effect, the pin direction must be set
as output.
12.13.6 OUTSET – Data Output Value Set Register
Bit 7 6 5 4 3 2 1 0
+0x05 OUTSET[7:0]
 Bit 7:0 – OUTSET[7:0]: Data Output Value Set

This register can be used instead of a read-modify-write to set the output value of individual pins to one. Writing a
one to a bit will set the corresponding bit in the OUT register. Reading this register will return the value in the OUT
register.
12.13.7 OUTCLR – Data Output Value Clear Register
Bit 7 6 5 4 3 2 1 0
+0x06 OUTCLR[7:0]
 Bit 7:0 – OUTCLR[7:0]: Data Output Value Clear

This register can be used instead of a read-modify-write to set the output value of individual pins to zero. Writing a
one to a bit will clear the corresponding bit in the OUT register. Reading this register will return the value in the
OUT register.
12.13.8 OUTTGL – Data Output Value Toggle Register
Bit 7 6 5 4 3 2 1 0
+0x07 OUTTGL[7:0]
 Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle

This register can be used instead of a read-modify-write to toggle the output value of individual pins. Writing a one
to a bit will toggle the corresponding bit in the OUT register. Reading this register will return the value in the OUT
register.
XMEGA E MANUAL 150

12.13.9 IN – Data Input Value Register
Bit 7 6 5 4 3 2 1 0
+0x08 IN[7:0]
 Bit 7:0 – IN[7:0]: Data Input Value

This register shows the value present on the pins if the digital input driver is enabled. INn shows the value of pin n
of the port. The input is not sampled and cannot be read if the digital input buffers are disabled.
Bit 7 6 5 4 3 2 1 0
+0x09 – – – – – – INTLVL[1:0]

 Bit 1:0 – INTLVL[1:0]: Interrupt Level
These bits enable port interrupt and select the interrupt level as described in “PMIC – Interrupts and Programma-
ble Multilevel Interrupt Controller” on page 132.
12.13.11 INTMASK – Interrupt Mask Register
Bit 7 6 5 4 3 2 1 0
+0x0A INTMASK[7:0]
 Bit 7:0 – INTMASK[7:0]: Interrupt Mask Bits

These bits are used to mask which pins can be used as sources for port interrupt. If INTMASKn is written to one,
pin n is used as source for port interrupt.The input sense configuration for each pin is decided by the PINnCTRL
registers.
12.13.12 INTFLAGS – Interrupt Flag Register
Bit 7 6 5 4 3 2 1 0
+0x0C INT7IF INT6IF INT5IF INT4IF INT3IF INT2IF INT1IF INT0IF
 Bit 7:0 – INTnIF: Interrupt Pin n Flag

The INTnIF flag is set when a pin change/state matches the pin's input sense configuration, and the pin is set as
source for port interrupt. Writing a one to this flag's bit location will clear the flag.
For enabling and executing the interrupt, refer to the interrupt level description.
XMEGA E MANUAL 151

12.13.13 REMAP – Pin Remap Register
The pin remap functionality is available for PORTC and PORTD only.
Bit 7 6 5 4 3 2 1 0
+0x0E – – – USART0 TC4D TC4C TC4B TC4A
Read/Write R R R R/W R/W R/W R/W R/W

 Bit 4 – USART0: USART0 Remap
Setting this bit to one will move the pin location of USART0 from Px[3:0] to Px[7:4].
 Bit 3 – TC4D: Timer/Counter 4 Output Compare D
Setting this bit will move the location of OC4D from Px3 to Px7.
 Bit 2 – TC4C: Timer/Counter 4 Output Compare C
Setting this bit will move the location of OC4C from Px2 to Px6.
 Bit 1 – TC4B: Timer/Counter 4 Output Compare B
Setting this bit will move the location of OC4B from Px1 to Px5. If this bit is set and PWM from both timer/counter 4
and timer/counter 5 is enabled, the resulting PWM will be an OR-modulation between the two PWM outputs.
 Bit 0 – TC4A: Timer/Counter 4 Output Compare A
Setting this bit will move the location of OC4A from Px0 to Px4. If this bit is set and PWM from both timer/counter 4
and timer/counter 5 is enabled, the resulting PWM will be an OR-modulation between the two PWM outputs. See
Figure 12-11.
Figure 12-11.I/O Timer/counter
OC4A
OC5A
OCA
12.13.14 PINnCTRL – Pin n Control Register
Bit 7 6 5 4 3 2 1 0
+0x10 +n – INVEN OPC[2:0] ISC[2:0]
 Bit 6 – INVEN: Inverted I/O Enable
Setting this bit will enable inverted output and input data on pin n.
 Bit 5:3 – OPC: Output and Pull Configuration
These bits set the output/pull configuration on pin n according to Table 12-5 on page 153.
XMEGA E MANUAL 152

Table 12-5. Output/pull Configuration
Description
OPC[2:0] Group configuration Output configuration Pull configuration
000 TOTEM Totem-pole (N/A)
001 BUSKEEPER Totem-pole Bus-keeper
010 PULLDOWN Totem-pole Pull-down (on input)
011 PULLUP Totem-pole Pull-up (on input)
100 WIREDOR Wired-OR (N/A)
101 WIREDAND Wired-AND (N/A)
110 WIREDORPULL Wired-OR Pull-down
111 WIREDANDPULL Wired-AND Pull-up
 Bit 2:0 – ISC[2:0]: Input/Sense Configuration

These bits set the input and sense configuration on pin n according to Table 12-6. The sense configuration
decides how the pin can trigger port interrupts and events. If the input buffer is not disabled, the input cannot be
read in the IN register.
Table 12-6. Input/sense Configuration
ISC[2:0] Group configuration Input/Sense configuration
000 BOTHEDGES Sense both edges
001 RISING Sense rising edge
010 FALLING Sense falling edge
011 LEVEL Sense low level(1)
100 – Reserved
101 – Reserved
110 FORCE_ENABLE Digital input buffer forced enable(2)
111 INTPUT_DISABLE Digital input buffer disabled(3)
Notes: 1. A low-level pin value will not generate events, and a high-level pin value will continuously generate events.
2. Only PORTA - PORTD support the input buffer force enable option. If the pin is not used for asynchronous event generation, it is recommended to
not use this configuration.
3. Only PORTA - PORTD support the input buffer disable option. If the pin is used for analog functionality, such as AC or ADC, it is recommended to
configure the pin to INPUT_DISABLE.
XMEGA E MANUAL 153

12.14 Register Descriptions – Port Configuration
12.14.1 MPCMASK – Multi-Pin Configuration Mask Register
Bit 7 6 5 4 3 2 1 0
+0x00 MPCMASK[7:0]
 Bit 7:0 – MPCMASK[7:0]: Multi-Pin Configuration Mask

The MPCMASK register enables configuration of several pins of a port at the same time. Writing a one to bit n
makes pin n part of the multi-pin configuration. When one or more bits in the MPCMASK register is set, writing any
of the PINnCTRL registers will update only the PINnCTRL registers matching the mask in the MPCMASK register
for that port. The MPCMASK register is automatically cleared after any PINnCTRL register is written.
12.14.2 CLKOUT – Clock Output Register
Bit 7 6 5 4 3 2 1 0
+0x04 CLKEVPIN RTCOUT[1:0] - CLKOUTSEL[1:0] CLKOUT[1:0]
Read/Write R/W R/W R/W R R/W R/W R/W R/W
 Bit 7 – CLKEVPIN: Clock and Event Output Pin Select

Setting this pin enables output of clock and event pins on port pin 4 instead of port pin 7.
 Bit 6:5 – RTCOUT[1:0]: RTC Clock Output Enable
Setting this bit enables output of the RTC clock source according to Table 12-7.
Table 12-7. Event output pin Selection
RTCOUT[1:0] Group configuration Description
00 OFF RTC clock output disabled
01 PC RTC clock output on PORTC, pin 6
10 PD RTC clock output on PORTD, pin 6
11 PR RTC clock output on PORTR, pin 0
 Bits 3:2 – CLKOUTSEL[1:0]: Clock Output Select
These bits are used to select which of the peripheral clocks will be output to the port pin if CLKOUT is configured.
XMEGA E MANUAL 154

Table 12-8. Event Output Clock selection
CLKOUTSEL[1:0] Group configuration Description
00 CLK1X CLKPER output to pin
01 CLK2X CLKPER2 output to pin
10 CLK4X CLKPER4 output to pin
11 – Reserved
 Bit 1:0 – CLKOUT[1:0]: Clock Output Port

These bits decide which port the peripheral clock will be output to. Pin 7 on the selected port is the default used.
The CLKOUT setting will override the EVOUT setting. Thus, if both are enabled on the same port pin, the periph-
eral clock will be visible. The port pin must be configured as output for the clock to be available on the pin.
Table 12-9 shows the possible configurations.
Table 12-9. Clock Output Port Configurations
CLKOUT[1:0] Group configuration Description
00 OFF Clock output disabled
01 PC Clock output on PORTC
10 PD Clock output on PORTD
11 PE Clock output on PORTR
12.14.3 ACEVOUT – Analog Comparator and Event Output Register
Bit 7 6 5 4 3 2 1 0
+0x06 ACOUT[1:0] EVOUT[1:0] EVASYEN EVOUTSEL[2:0]
 Bit 7:6 – ACOUT[1:0]: Analog Comparator Output Port

These bits decide which port analog comparator will be output to, according to Table 12-10.
The analog compare outputs are enabled in the module itself.
Table 12-10. Analog Comparator Output Port Selection
ACOUT[1:0] Group configuration Description
00 PA Analog Comparator outputs on PORTA
01 PC Analog Comparator outputs on PORTC
10 PD Analog Comparator outputs on PORTD
11 PR Analog Comparator outputs on PORTR
 Bit 5:4 – EVOUT[1:0]: Event Output Port

These bits decide which port event channel 0 from the event system will be output to, according to Table 12-11.
Pin 7 on the PORTC and PORTD, or pin 0 on the PORTR, is the default used, and the CLKOUT bits must be set
differently from those of EVOUT. The port pin must be configured as output for the event to be available on the pin.
XMEGA E MANUAL 155

Table 12-11. Event Output Pin Selection
EVOUT[1:0] Group configuration Description
00 OFF Event output disabled
01 PC Event channel 0 output on PORTC
10 PD Event channel 0 output on PORTD
11 PR Event channel 0 output on PORTR
 Bit 3 – EVASYEN: Asynchronous Event Enabled

Setting this bit enables the asynchronous event output. The event channel selected by EVOUTSEL bits must be
set accordingly.
 Bit 2:0 - EVOUTSEL[2:0]: Event Channel Output Selection
These bits define which channel from the event system is output to the port pin, according to Table 12-12.
Table 12-12. Event Channel Output Selection
EVOUTSEL[2:0] Group configuration Description
000 0 Event channel 0 output to pin
12.14.4 SRLCTRL – Slew Rate Limit Control Register
Bit 7 6 5 4 3 2 1 0
+0x07 SRLENR – – – SRLEND SRLENC – SRLENA
Read/Write R/W R R R R/W R/W R R/W
 Bit 7 – SRLENR: Slew Rate Limit Enable on PORTR

Setting this bit will enable slew rate limiting on port R.
 Bit 3 – SRLENRD: Slew Rate Limit Enable on PORTD
Setting this bit will enable slew rate limiting on port D.
 Bit 2 – SRLENRC: Slew Rate Limit Enable on PORTC
Setting this bit will enable slew rate limiting on port C.
XMEGA E MANUAL 156

 Bit 0 – SRLENRA: Slew Rate Limit Enable on PORTA
Setting this bit will enable slew rate limiting on port A.
12.15 Register Descriptions – Virtual Port
12.15.1 DIR – Data Direction register
Bit 7 6 5 4 3 2 1 0
+0x00 DIR[7:0]
 Bit 7:0 – DIR[7:0]: Data Direction

This register sets the data direction for the individual pins in the port. When a port is mapped as virtual, accessing
this register is identical to accessing the actual DIR register for the port.
12.15.2 OUT – Data Output Value Register
Bit 7 6 5 4 3 2 1 0
+0x01 OUT[7:0]
 Bit 7:0 – OUT[7:0]: Data Output Value

This register sets the data output value for the individual pins in the port. When a port is mapped as virtual, access-
ing this register is identical to accessing the actual OUT register for the port.
12.15.3 IN – Data Input Value Register
Bit 7 6 5 4 3 2 1 0
+0x02 IN[7:0]
 Bit 7:0 – IN[7:0]: Data Input Value

This register shows the value present on the pins if the digital input buffer is enabled. This register sets the data
direction for the individual pins in the port. When a port is mapped as virtual, accessing this register is identical to
accessing the actual IN register for the port.
Bit 7 6 5 4 3 2 1 0
+0x03 INT7IF INT6IF INT5IF INT4IF INT3IF INT2IF INT1IF INT0IF
 Bit 7:0 – INTnIF: Interrupt Pin n Flag

The INTnIF flag is set when a pin change/state matches the pin's input sense configuration, and the pin is set as
source for port interrupt. Writing a one to this flag's bit location will clear the flag. For enabling and executing the
interrupt, refer to the interrupt level description. When a port is mapped as virtual, accessing this register is identi-
cal to accessing the actual INTFLAGS register for the port.
XMEGA E MANUAL 157

12.16 Register Summary – Ports
+0x00 DIR DIR[7:0] 149
+0x01 DIRSET DIRSET[7:0] 149
+0x02 DIRCLR DIRCLR[7:0] 149
+0x03 DIRTGL DIRTGL[7:0] 149
+0x04 OUT OUT[7:0] 150
+0x05 OUTSET OUTSET[7:0] 150
+0x06 OUTCLR OUTCLR[7:0] 150
+0x07 OUTTGL OUTTGL[7:0] 150
+0x08 IN IN[7:0] 151
+0x09 INTCTRL - - - - - - INTLVL[1:0] 151
+0x0A INTMASK INTMASK[7:0] 151
+0x0B Reserved - - - - - - - -
+0x0C INTFLAGS INT7IF INT6IF INT5IF INT4IF INT3IF INT2IF INT1IF INT0IF 151
+0x0D Reserved - - - - - - - -
+0x0E REMAP - - - USART0 TC4D TC4C TC4B TC4A 152
+0x10 PIN0CTRL - INVEN OPC[2:0] ISC[2:0] 152
+0x18 Reserved - - - - - - - -
+0x19 Reserved - - - - - - - -
+0x1A Reserved - - - - - - - -
+0x1B Reserved - - - - - - - -
+0x1C Reserved - - - - - - - -
+0x1D Reserved - - - - - - - -
+0x1E Reserved - - - - - - - -
+0x1F Reserved - - - - - - - -
XMEGA E MANUAL 158

12.17 Register Summary – Port Configuration
+0x00 MPCMASK MPCMASK[7:0] 154
+0x01 Reserved - - - - - - - -
+0x02 Reserved - - - - - - - -
+0x03 Reserved - - - - - - - -
+0x04 CLKOUT CLKEVPIN RTCOUT[1:0] - CLKOUTSEL[1:0] CLKOUT[1:0] 154
+0x05 Reserved - - - - - - - -
+0x06 ACEVOUT ACOUT[1:0] EVOUT[1:0] EVASYEN EVCTRL[2:0] 155
+0x07 SRLCTRL SRLENR - - - SRLEND SRLENC - SRLENA 156
12.18 Register Summary – Virtual Ports

+0x00 DIR DIR[7:0] 157
+0x01 OUT OUT[7:0] 157
+0x02 IN IN[7:0] 157
+0x03 INTFLAGS INT7IF INT6IF INT5IF INT4IF INT3IF INT2IF INT1IF INT0IF 157
12.19 Interrupt Vector Summary – Ports
Table 12-13. USART Interrupt Vectors and their Word Offset Address
0x00 INT_vect Port Interrupt vector offset
XMEGA E MANUAL 159

13. TC4/5 – 16-bit Timer/Counter Type 4 and 5
13.1 Features
 16-bit timer/counter
 32-bit timer/counter support by cascading two timer/counters
 Up to four compare or capture (CC) channels:
 Four CC channels for timer/counters of type 4
 Two CC channels for timer/counters of type 5
 Double buffered timer period setting
 Double buffered capture or compare channels
 Waveform generation:
 Frequency generation
 Single-slope pulse width modulation
 Dual-slope pulse width modulation
 Input capture:
 Input capture with noise cancelling
 Frequency capture
 Pulse width capture
 32-bit input capture
 Timer overflow and error interrupts/events
 One compare match or input capture interrupt/event per CC channel
 Can be used with event system for:
 Quadrature decoding
 Count and direction control
 Capture
 Can be used with EDMA and to trigger EDMA transactions
 High-resolution extension:
 Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
 Waveform extension:
 Low- and high-side output with programmable dead-time insertion (DTI)
 Fault extension:
 Event controlled fault protection for safe disabling of drivers
13.2 Overview
Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include accurate program
execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital
signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation (PWM) generation, as well as various input capture operations. A timer/counter can be
configured for either capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 4 and type 5. Timer/counter 4 has four CC channels, and
timer/counter 5 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 4.
Both timer/counter 4 and 5 can be in 8-bit mode, allowing the application to double the number of compare and capture
channels that then get 8-bit resolution.
XMEGA E MANUAL 160

Some timer/counters have extensions to enable more specialized waveform and frequency generation. The waveform
extension (WeX) is intended for motor control, ballast, LED, H-bridge, power converters, and other types of power control
applications. It enables low- and high-side output with optional dead-time insertion. It can also generate a synchronized
bit pattern across the port pins. The high-resolution (Hi-Res) extension can increase the waveform resolution by four or
eight times by using an internal clock source running four times faster than the peripheral clock. The fault extension
(FAULT) enables fault protection for safe and deterministic handling, disabling and/or shut down of external drivers.
A block diagram of the 16-bit timer/counter with extensions and closely related peripheral modules (in grey) is shown in
Figure 13-1 on page 161.
Figure 13-1. 16-bit Timer/counter and Closely Related Peripherals

Timer/Counter
Base Counter Prescaler clkPER
Timer Period
Control Logic
Counter Event
System
clkPER4
Compare/Capture Channel D WeX

Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
Capture
Comparator
Control
Waveform
Buffer
Generation
13.2.1 Definitions
The following definitions are used throughout the documentation:
Table 13-1. Timer/counter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes zero (one in single slope counting-up mode).
MAX The counter reaches MAXimum when it becomes all ones.
The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value
TOP can be equal to the period (PER) or the compare channel A (CCA) register setting. This is selected by the
waveform generator mode.
UPDATE The timer/counter signals an update when it reaches BOTTOM or TOP, depending on the direction settings.
In general, the term “timer” is used when the timer/counter clock control is handled by an internal source, and the term
“counter” is used when the clock control is handled externally (e.g. counting external events). When used for compare
operations, the CC channels are referred to as “compare channels.” When used for capture operations, the CC channels
are referred to as “capture channels.”
XMEGA E MANUAL 161

13.3 Block Diagram
Figure 13-2 shows a detailed block diagram of the timer/counter without the extensions.
Figure 13-2. Timer/counter Block Diagram
Base Counter
Clock Select
BV PERBUF CTRLA
Event
Select
PER CTRLD
"count"
Counter
"clear"
OVF/UNF
(INT/EDMA Req.)
"load"
CNT Control Logic
"direction"
ERRIF
(INT Req.)
TOP
UPDATE
=
"ev"
BOTTOM
=0
Compare/Capture
(Unit x = {A,B,C,D})
BV CCBUFx Control Logic
CCx
Waveform
Generation
OCx Out
"match" CCxIF
= (INT/EDMA
Req.)
The counter register (CNT), period registers with buffer (PER and PERBUF), and compare and capture registers with
buffers (CCx and CCxBUF) are 16-bit registers. All buffer register have a buffer valid (BV) flag that indicates when the
buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value to determine
whether the counter has reached TOP or BOTTOM.
The counter value is also compared to the CCx registers. These comparisons can be used to generate interrupt
requests, request EDMA transactions or generate events for the event system. The waveform generator modes use
these comparisons to set the waveform period or pulse width.
A prescaled peripheral clock and events from the event system can be used to control the counter. The event system is
also used as a source to the input capture. Combined with the quadrature decoding functionality in the event system
(QDEC), the timer/counter can be used for quadrature decoding.
XMEGA E MANUAL 162

13.4 Clock and Event Sources
The timer/counter can be clocked from the peripheral clock (clkPER), or the event system, and Figure 13-3 shows the
clock and event selection.
Figure 13-3. Clock and Event Selection
Common clkPER /
clkPER
2{0,...,15}
Event system events
prescaler
clkPER /
{1,2,4,8,64,256,1024} event channels
CLKSEL
Control logic
EVSEL
CNT
EVACT (Encoding)
The peripheral clock is fed into a common prescaler (common for all timer/counters in a device). Prescaler outputs from 1
to 1/1024 are directly available for selection by the timer/counter. In addition, the whole range of prescaling from 1 to 215
times are available through the event system.
Clock selection (CLKSEL) selects one of the prescaler outputs directly or an event channel as the counter (CNT) input.
This is referred to as normal operation of the counter. For details, refer to “Normal Operation” on page 164. By using the
event system, any event source, such as an external clock signal on any I/O pin, may be used as the clock input.
In addition, the timer/counter can be controlled via the event system. The event selection (EVSEL) and event action
(EVACT) settings are used to trigger an event action from one or more events. This is referred to as event action
controlled operation of the counter. For details, refer to “Event Action Controlled Operation” on page 165. When event
action controlled operation is used, the clock selection must be set to use an event channel as the counter input.
13.5 Double Buffering

The period register and the CC registers are all double buffered, with circular buffer option on compare channel A. Each
buffer register has a buffer valid (BV) flag, which indicates that the buffer register contains a valid, i.e. new value that can
be copied into the corresponding period or CC register. When the period register and CC channels are used for a
compare operation, the buffer valid flag is set when data is written to the buffer register and cleared on an UPDATE
condition.
Circular buffer option can be enabled for both compare and waveform generation modes. On update condition, the
period and CCA registers can be optionally stored in their corresponding buffers. In the same way, the
corresponding buffers registers values are stored in period and CCA registers on the same update condition.
This is shown for a compare register in Figure 13-4 on page 164.
XMEGA E MANUAL 163

Figure 13-4. Period and Compare Double Buffering
"write enable" "data write"
UPDATE
BV EN CCxBUF
CIRCEN
EN CCx
UPDATE
CNT
"match"
=
When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case
the buffer valid flag is set on the capture event, as shown in Figure 13-5. For input capture, the buffer register and the
corresponding CCx register act like a FIFO. When the CC register is empty or read, any content in the buffer register is
passed to the CC register. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the optional
interrupt.
Figure 13-5. Capture Double Buffering

"capture" CNT
BV EN CCxBUF
IF EN CCx
"INT/DMA
request" data read
Both the CCx and CCxBUF registers are available as an I/O register. This allows initialization and bypassing of the buffer
register and the double buffering function.
13.6 Counter Operation

Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each
timer/counter clock input.
The timer/counter can be enabled in counting up or down in normal, single-slope or dual-slop operation.
13.6.1 Normal Operation

In normal operation, the counter will count in the direction set by the direction (DIR) bit for each clock until it reaches TOP
or BOTTOM. When up-counting and TOP is reached, the counter will be set to zero when the next clock is given. When
down-counting, the counter is reloaded with the period register value when BOTTOM is reached.
XMEGA E MANUAL 164

Figure 13-6. Normal Operation
CNT written
MAX
"update"
TOP
CNT
CCx
BOTTOM
DIR
WG output
As shown in Figure 13-6, it is possible to change the counter value when the counter is running. The write access has
higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed
during normal operation.
Normal operation must be used when using the counter as timer base for the input capture. When a waveform
generation (WG) mode is enabled, the waveform is output to a pin. For details, refer to “Waveform Generation” on page
169.
13.6.2 Event Action Controlled Operation

The event selection and event action settings can be used to control the counter from the event system. For the counter,
the following event actions can be selected:
 Event system controlled up/down counting
 Event n will be used as count enable
 Event n+1 will be used to select between up (1) and down (0). The pin configuration must be set to low level
sensing
 Event system controlled quadrature decode counting
13.6.3 32-bit Operation

Two timer/counters can be used together to enable 32-bit counter operation. By using two timer/counters, the overflow
event from one timer/counter (least-significant timer) can be routed via the event system and used as the clock input for
another timer/counter (most-significant timer).
13.6.4 Changing the Period

The counter period is changed by writing a new TOP value to the period register. If double buffering is not used, any
period update is immediate, as shown in Figure 13-7 on page 166.
XMEGA E MANUAL 165

Figure 13-7. Unbuffered Single-slope Operation
Counter Wraparound
MAX
"update"
"write"
CNT
BOTTOM
New TOP written to New TOP written to

PER that is higher PER that is lower
than current CNT than current CNT
A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in Figure 13-8.
This due to the fact that CNT and PER are continuously compared, and if a new TOP value that is lower than current
CNT is written to PER, it will wrap before a compare match happen.
Figure 13-8. Unbuffered Dual-slope Operation

Counter Wraparound
MAX
"update"
"write"
CNT
BOTTOM
New TOP written to New TOP written to

PER that is higher PER that is lower
When double buffering is used, the buffer can be written at any time and still maintain correct operation. The period
register is always updated on the UPDATE condition, as shown for dual-slope operation in Figure 13-9. This prevents
wraparound and the generation of odd waveforms.
Figure 13-9. Changing the Period using Buffering
MAX
"update"
"write"
CNT
BOTTOM
New Period written to New Period written to

New PER is updated
PERBUF that is higher PERBUF that is lower
with PERBUF value.
XMEGA E MANUAL 166

13.7 Capture Channel
The CC channels can be used as capture channels to capture external events and give them a timestamp. The capture
can be enabled in any timer/counter operation mode.
Events are used to trigger the input capture; i.e., any events from the event system, including pin change from any pin,
can trigger am input capture. The event source select setting selects which event channel will trigger CC channel A. The
subsequent event channels then trigger input capture on subsequent CC channels, if configured. For example, setting
the event source select to event channel 2 results in CC channel A capture being triggered by event channel 2, CC
channel B triggered by event channel 3, and so on.
For timer/counters with fault extension, an input channel capture can also be triggered by a fault condition. If the CAPTA
or CAPTB fault action is enabled in fault extension unit, a fault will trigger a CC channel capture.
Figure 13-10. Event Source Selection for Input Capture
Event System
CCA capture
CH0MUX Event channel 0
CH1MUX Event channel 1 CCB capture
CCC capture
CHnMUX Event channel n
CCD capture
Rotate
Event Source Selection
The event action setting in the timer/counter will determine the type of capture that is done.
The CC channels must be enabled individually before capture can be done. When the capture condition occur, the
timer/counter will time-stamp the event by copying the current CNT value in the count register into the enabled CC
channel register.
When an I/O pin is used as an event source for the capture, the pin must be configured for edge sensing. For details on
sense configuration on I/O pins, refer to “Input Sense Configuration” on page 144.
For details on event channels source selection, refer to Table 13-10 on page 177.
13.7.1 Input Capture

Selecting the input capture event action makes the enabled capture channel perform an input capture on an event. The
interrupt flags will be set and indicate that there is a valid capture result in the corresponding CC register. At the same
time, the buffer valid flags indicate valid data in the buffer registers.
A capture is enabled by enabling the corresponding CC channel in capture mode. The capture can be enabled in any
timer/counter operation mode. The Figure 13-11 shows four capture events for one capture channel when the
timer/counter is counting from BOTTOM to TOP.
A special case occurs when the timer/counter is set in dual slope mode. When DSBOTH operation is enabled, the DIR is
stored as most-significant bit of the captured value. In all other cases, the MSB bit of the timer/counter is stored as most-
significant bit of the captured value.
XMEGA E MANUAL 167

Figure 13-11. Input Capture Timing
events
TOP
CNT
BOTTOM
Capture 0 Capture 1 Capture 2 Capture 3
When selecting the pulse width and frequency capture event action, the enabled CCA or CCB channels perform input
captures on positive edge event on CCA channel and on negative edge event on CCB channel. Counter restart is
performed on positive edge event. This enables measurement of signal pulse width and frequency directly. The CCA
capture result will be the period (T) from the previous timer/counter restart until the event occurred. This can be used to
calculate the frequency (f) of the signal:
1
f = ---
T
The CCB capture result will be pulse width (tp) of the signal. The event source must be an I/O pin, and the sense
configuration for the pin must be set to generate an event on both edges.
Figure 13-12 on page 168 shows an example where the period and pulse width of an external signal is measured twice.
Figure 13-12. Frequency and Pulse Width Capture of an External Signal
13.7.2 32-bit Input Capture

Two timer/counters can be used together to enable true 32-bit input capture. In a typical 32-bit input capture setup, the
overflow event of the least-significant timer is connected via the event system and used as the clock input for the most-
significant timer.
XMEGA E MANUAL 168

The most-significant timer will be updated one peripheral clock period after an overflow occurs for the least-significant
timer. To compensate for this, the capture event for the most-significant timer must be equally delayed by setting the
event delay bit for this timer.
13.7.3 Capture Overflow

The timer/counter can detect buffer overflow of the input capture channels. When both the buffer valid flag and the
capture interrupt flag are set and a new capture event is detected, there is nowhere to store the new timestamp. If a
buffer overflow is detected, the new value is rejected, the error interrupt flag is set, and the optional interrupt is
generated.
13.8 Compare Channel

The CC channels can be used to compare the counter (CNT) value with the CC channels (CCx) register value. If CNT
equals CCx, the comparator signals a compare match. The compare match will set the CC channel's interrupt flag at the
next timer/counter clock cycle, and the event and the optional interrupt are generated.
The compare buffer register provides double buffer capability equivalent to that for the period buffer. The double
buffering synchronizes the update of the CCx register with the buffer value on the UPDATE condition. The
synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensure glitch-free output.
13.8.1 Waveform Generation

The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform
visible on the connected port pin, the following requirements must be fulfilled:
1. A waveform generation mode must be selected.
2. Event actions must be disabled.
3. The CC channels used must be enabled. This will override the corresponding port pin output register.
4. The direction for the associated port pin must be set to output.
Inverted waveform output is achieved by setting the invert output bit for the port pin.
For timer/counter with fault extension, edge aligned pulses (left or right) is achieved by setting the polarity bits. For more
details, refer to the fault extension unit description.
13.8.2 Frequency (FRQ) Waveform Generation

For frequency generation the period time (T) is controlled by the CCA register instead of PER. The waveform generation
(WG) output is toggled on each compare match between the CNT and CCA registers, as shown in Figure 13-13.
Figure 13-13. Frequency Waveform Generation
Period (T) Direction Change CNT written
MAX
"update"
TOP
CNT
BOTTOM
WG Output
The waveform frequency (fFRQ) is defined by the following equation:

fclk PER
f FRQ = ----------------------------------
2N  CCA + 1 
XMEGA E MANUAL 169

N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the
peripheral clock frequency (fclkPER) when CCA is set to zero (0x0000) and no prescaling is used. This also applies when
using the hi-res extension, since this increases the resolution and not the frequency.
13.8.3 Single-slope PWM Generation

For single-slope PWM generation, the period (T) is controlled by PER, while CCx registers control the duty cycle of the
WG output. Figure 13-14 shows how the counter counts from BOTTOM to TOP and then restarts from BOTTOM. The
waveform generator (WG) output is set on the compare match between the CNT and CCx registers and cleared at TOP.
Figure 13-14.Single-slope Pulse Width Modulation

"update"
Period (T) CCx=BOTTOM CCx=TOP
"match"
MAX
TOP
CNT
CCx
BOTTOM
WG Output
The PER register defines the PWM resolution. The minimum resolution is two bits (PER=0x0003), and the maximum
resolution is 16 bits (PER=MAX).
The following equation calculate the exact resolution for single-slope PWM (RPWM_SS):
log  PER + DIR 

R PWM_SS = -----------------------------------------
log  2 
The single-slope PWM frequency (fPWM_SS) depends on the period setting (PER) and the peripheral clock frequency
(fclkPER), and can be calculated by the following equation:
fclk PER
f PWM_SS = -------------------------------------
N  PER + DIR 
where N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the
peripheral clock frequency (fclkPER) when CCA is set to zero (0x0000) and no prescaling is used. This also applies when
The pulse width (PPWM_SS) depends on the compare channel settings (CCx), the direction (DIR) and the peripheral clock
frequency (fclkPER), and can be calculated by the following equation:
 N CCx 
P PWM_SS = -----------------------
fclk PER
where N represents the prescaler divider used. When counting up, the minimum pulse width is one peripheral clock.
XMEGA E MANUAL 170

13.8.4 Dual-slope PWM
For dual-slope PWM generation, the period (T) is controlled by PER, while CCx registers control the duty cycle of the WG
output. Figure 13-15 shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOP and then from
TOP to BOTTOM. The waveform generator output is set on BOTTOM, cleared on compare match when up-counting,
and set on compare match when down-counting.
Figure 13-15.Dual-slope Pulse Width Modulation
Using dual-slope PWM results in a lower maximum operation frequency compared to the single-slope PWM operation.
The period register (PER) defines the PWM resolution. The minimum resolution is two bits (PER=0x0003), and the
maximum resolution is 16 bits (PER=MAX).
The following equation calculate the exact resolution for dual-slope PWM (RPWM_DS):
log  PER + 1 
R PWM_DS = ---------------------------------
log  2 
The PWM frequency depends on the period setting (PER) and the peripheral clock frequency (fclkPER), and can be
calculated by the following equation:
fclk PER
f PWM_DS = ---------------------
2N PER
N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the
peripheral clock frequency (fclkPER) when PER is set to one (0x0001) and no prescaling is used. This also applies when
The pulse width (PPWM_DS) depends on the compare channel settings (CCx) and the peripheral clock frequency (fclkPER),
and can be calculated by the following equation:
2 N * ( PER  CCx )
PPWM _ DS 
fclk PER
where N represents the prescaler divider used. In this mode, the pulse can be inhibited.
13.8.5 Output Polarity

The polarity option is available in both single-slope and dual-slope PWM operation. In these modes, it is possible to
invert the pulse edge alignment on start or end of PWM cycle. The Table 13-2 on page 172 shows the waveform
output set/clear conditions, depending of timer/counter settings, direction and polarity setting.
XMEGA E MANUAL 171

Table 13-2. Waveform Generation Set/clear Conditions
WG output updates
WG Mode DIR Polarity Set Clear
0 Timer/counter update Timer/counter match

0
1 Timer/counter match Timer/counter update
Single-Slope PWM
0 Timer/counter match Timer/counter update
1
1 Timer/counter update Timer/counter match
0 Timer/counter match when counting up Timer/counter match when counting down

Dual-Slope PMW x
1 Timer/counter match when counting down Timer/counter match when counting up
13.8.6 Port Override for Waveform Generation

To make the waveform generation available on the port pins, the corresponding port pin direction must be set as output.
The timer/counter will override the port pin values when the CC channel is enabled (CCxMODE) and a waveform
generation mode is selected.
Figure 13-16 shows the port override for a timer/counter. The timer/counter CC channel will override the port pin output
value (OUT) on the corresponding port pin. Enabling inverted I/O on the port pin (INVEN) inverts the corresponding WG
output.
Figure 13-16. Port Override for Timer/counter 4 and 5
13.9 Interrupts and Events

The timer/counter can generate both interrupts and events. The counter can generate an interrupt on overflow/underflow,
and each CC channel has a separate interrupt that is used for compare or capture. In addition, an error interrupt can be
generated if any of the CC channels is used for capture and a buffer overflow condition occurs on a capture channel.
Events will be generated for all conditions that can generate interrupts. For details on event generation and available
events, refer to “Event System ” on page 79.
13.10 EDMA Support

The interrupt flags can be used to trigger EDMA transactions. Table 13-3 on page 173 lists the transfer triggers available
from the timer/counter and the EDMA action that will clear the transfer trigger. For more details on using EDMA, refer to
“EDMA – Enhanced Direct Memory Access” on page 50.
XMEGA E MANUAL 172

Table 13-3. EDMA Request Sources
Request Acknowledge Comment
EDMA controller writes to CNT

OVFIF/UNFIF EDMA controller writes to PER
EDMA controller writes to PERBUF
ERRIF N/A
EDMA controller access of CCx Input capture operation

CCxIF
EDMA controller access of CCxBUF Output compare operation
13.11 Timer/Counter Commands

A set of commands can be given to the timer/counter by software to immediately change the state of the module. These
commands give direct control of the UPDATE, RESTART, and RESET signals.
An update command has the same effect as when an update condition occurs. The update command is ignored if the
lock update bit is set.
The software can force a restart of the current waveform period by issuing a restart command. In this case the counter,
direction, and all compare outputs are set to zero.
A reset command will set all timer/counter registers to their initial values. A reset can be given only when the
timer/counter is not running (OFF).
XMEGA E MANUAL 173

13.12 Register Description – Standard Configuration
Bit 7 6 5 4 3 2 1 0
+0x00 – SYNCHEN EVSTART UPSTOP CLKSEL[3:0]
 Bit 6 – SYNCHEN: Synchronization Enabled
When this bit is set, the event actions and software commands are synchronized with the internal timer/counter
clock. When the bit is cleared, the event actions and software commands are synchronized with the peripheral
clock (CLKPER).
 Bit 5 – EVSTART: Start on Next Event
Setting this bit will enable the timer/counter on the next event from event line selected by EVSEL bits. If the bit is
cleared, the timer/counter can be enabled only by software, by clearing the STOP bit in CTRLGSET register.
 Bit 4 – UPSTOP: Stop on Next Update
Setting this bit will disable the timer/counter on next update condition (overflow/underflow or retrigger). The bit has
no effect if the timer/counter has been disabled by software.
 Bit 3:0 – CLKSEL[3:0]: Clock Select
These bits select the clock source for the timer/counter according to Table 13-4.
Setting CLKSEL to a no null value will start the timer, if EVSTART is written to 0 at the same time.
DIV1 configuration must be set to ensure a correct output from the waveform generator when the Hi-Res extension
is enabled.
Table 13-4. Clock Select Options
CLKSEL[3:0] Group configuration Command action
0000 OFF Prescaler: OFF
0001 DIV1 Prescaler: Clk
0010 DIV2 Prescaler: Clk/2
1nnn EVCHn Event channel n, n={0,…,7}
XMEGA E MANUAL 174

Bit 7 6 5 4 3 2 1 0
+0x01 BYTEM[1:0] CIRCEN[1:0] – WGMODE[2:0]
Read/Write R/W R/W R/W R/W R R/W R/W R/W
 Bit 7:6 – BYTEM[1:0]: Byte Mode

These bits select the timer/counter configuration mode according to Table 13-5.
Table 13-5. Byte Mode Selection
BYTEM[1:0] Group configuration Description
00 NORMAL Timer/counter is set to normal mode (timer/counter type 4/5)
One 8-bit timer/counter with doubled CC channels. Upper byte of the counter
01 BYTEMODE
(CNTH) will be set to zero after each counter clock cycle.
10 - Reserved
11 - Reserved
 Bit 5:3 – CIRCEN[1:0]: Circular Buffer Enable

Setting these bits enable the circular buffer options according to Table 13-6.
Table 13-6. Circular Buffer Selection
CIRCEN[1:0] Group configuration Description
00 DISABLE Circular buffer disabled
01 PER Circular buffer enabled on PER/PERBUF registers
10 CCA Circular buffer enabled on CCA/CCABUF registers
11 BOTH Circular buffer enabled on both PER/PERBUF and CCA/CCABUF registers
 Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode
These bits select the waveform generation mode, and control the counting sequence of the counter, TOP value,
UPDATE condition, interrupt/event condition, and type of waveform that is generated according to Table 13-7.
The result from the waveform generator can be directed to the port pins if the corresponding CCxMODE bits have
been set to enable this. The port pin direction must be set as output.
Table 13-7. Waveform Generation Mode
WGMODE[2:0] Group configuration Mode of operation Top Update OVFIF/Event
000 NORMAL Normal PER TOP/BOTTOM(1) TOP/BOTTOM(1)
001 FRQ Frequency CCA TOP/BOTTOM(1) TOP/BOTTOM(1)
010 – Reserved N/A N/A N/A
011 SINGLESLOPE Single-slope PWM PER TOP/BOTTOM(1) TOP/BOTTOM(1)
XMEGA E MANUAL 175

101 DSTOP Dual-slope PWM PER BOTTOM TOP
110 DSBOTH Dual-slope PWM PER BOTTOM TOP and BOTTOM
111 DSBOTTOM Dual-slope PWM PER BOTTOM BOTTOM
Note: 1. Depends on DIR settings.
13.12.3 CTRLC – Control Register C
Bit 7 6 5 4 3 2 1 0
+0x02 POLD POLC POLB POLA CMPD CMPC CMPB CMPA
 Bit 7:4 – POLx: Output Polarity x

Setting these bits enable the output polarity. For more details, refer to “Output Polarity” on page 171.
 Bit 3:0 – CMPx: Compare Output Value x
These bits allow direct access to the waveform generator's output compare value when the timer/counter is set in
the OFF state. This is used to set or clear the WG output value when the timer/counter is not running.
13.12.4 CTRLD – Control Register D
Bit 7 6 5 4 3 2 1 0
+0x03 EVACT[2:0] EVDLY EVSEL[3:0]
 Bit 7:5 – EVACT[2:0]: Event Action

These bits define the event action the timer will perform on an event according to Table 13-8. The EVSEL setting
will decide which event source or sources have control in this case.
Table 13-8. Event Action Selection
EVACT[2:0] Group configuration Command action
000 OFF None
001 FMODE1(1) Fault Mode 1 capture

(1)
010 FMODE2 Fault mode 2 capture
011 UPDOWN Externally controlled up/down count
100 QDEC Quadrature decode
101 RESTART Restart waveform period
110 PWF Pulse width and frequency capture
111 – Reserved
Note: 1. Set the EVACT[2:0] to 000 (Off condition) and select the event channel with the EVSEL[3:0] bits. Also, the CTRLE.CCxMODE has to be set to
CAPT.
XMEGA E MANUAL 176

 Bit 4 – EVDLY: Timer Delay Event
When this bit is set, the selected event source is delayed by one peripheral clock cycle. This is intended for 32-bit
input capture operation. Adding the event delay is necessary to compensate for the carry propagation delay when
cascading two counters via the event system.
 Bit 3:0 – EVSEL[3:0]:Timer Event Source Select
These bits select the event channel source for the timer/counter. For the selected event channel to have any
effect, the event action bits (EVACT) must be set according to Table 13-9.
Table 13-9. Event Source Selection
EVSEL[3:0] Group configuration Command action
0000 OFF None
0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1nnn CHn Event channel n, n={0,…,7}
By default, the selected event channel n will be the event channel source for CC channel A, and event channel
(n+1)%8, (n+2)%8, and (n+3)%8 will be the event channel source for CC channel B, C, and D.
Table 13-10 shows the event channel source for each CC channel, depending of EVACT settings.
Table 13-10. Event Channel Source Selection
Event channel selection
EVACT[2:0] OCD CCC CCB CCA Restart condition
000 (n+3)%8 (n+2)%8 (n+1)%8 n Software
001 (n+3)%8 (n+2)%8 FAULTA/B FAULTA/B Software or fault
010 FAULTB FAULTA FAULTB FAULTA Software or fault
011 (n+3)%8 (n+2)%8 (n+1)%8 n Software
100 (n+3)%8 (n+2)%8 (n+1)%8 n Quadrature decoder
101 (n+3)%8 (n+2)%8 (n+1)%8 n Event channel n
110 (n+3)%8 (n+2)%8 n n Event channel n
111 N/A N/A N/A N/A Reserved
XMEGA E MANUAL 177

13.12.5 CTRLE – Control Register E
Bit 7 6 5 4 3 2 1 0
+0x04 CCDMODE[1:0] CCCMODE[1:0] CCBMODE[1:0] CCAMODE[1:0]
 Bit 7:0 – CCxMODE[2:0] - Compare or Capture x Mode

These bits enable the compare and capture operation on corresponding CCx channel, according to Table 13-11.
Table 13-11. CC Mode Selection
CCMODE[1:0] Group configuration Command action
00(1) INTERNAL COMP(2) Output compare and capture are disabled
01 OUTPUT COMP Output compare enabled
10 CAPT Input capture enabled
11 BOTHCC(2) Both compare and capture enabled
Note: 1. If CCxMODE=00 then the Internal Compare mode is enabled.

2. This mode should be used only if the Fault Unit extension is set in conditional capture fault mode. For more details, refer to “Fault Extension” on
page 209 description.
13.12.6 INTCTRLA – Interrupt Control Register A
Bit 7 6 5 4 3 2 1 0
+0x06 – – TRGINTLVL[1:0] ERRINTLVL[1:0] OVFINTLVL[1:0]

 Bit 5:4 – TRGINTLVL[1:0]:Timer Trigger Restart Interrupt Level
These bits enable the interrupt for the timer trigger restart and select the interrupt level as described in “PMIC –
Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will trigger for the
conditions when TRGIF flag is set.
 Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level
These bits enable the timer error interrupt and select the interrupt level as described in “PMIC – Interrupts and Pro-
grammable Multilevel Interrupt Controller” on page 132.
 Bit 1:0 – OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level
These bits enable interrupt for the timer overflow/underflow and select the interrupt level as described in “PMIC –
conditions when OVFIF flag is set.
XMEGA E MANUAL 178

13.12.7 INTCTRLB – Interrupt Control Register B
Bit 7 6 5 4 3 2 1 0
+0x07 CCDINTLVL[1:0] CCCINTLVL[1:0] CCBINTLVL[1:0] CCAINTLVL[1:0]
 Bit 7:0 – CCxINTLVL[2:0] - Compare or Capture x Interrupt Level

These bits enable the timer compare or capture interrupt for channel x and select the interrupt level as described in
“PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132.
13.12.8 CTRLGCLR/CTRLGSET – Control Register G Clear/Set

This register is mapped into two I/O memory locations, one for clearing (CTRLxCLR) and one for setting the
register bits (CTRLxSET) when written. Both memory locations will give the same result when read.
The individual status bit can be set by writing a one to its bit location in CTRLxSET, and cleared by writing a one to
its bit location in CTRLxCLR. This allows each bit to be set or cleared without use of a read-modify-write operation
on a single register.
Bit 7 6 5 4 3 2 1 0
– – STOP – CMD[1:0] LUPD DIR
Read/Write R R R/W R R/W R/W R/W R/W

 Bit 5 – STOP: Timer/Counter Stop
When this bit is set, the timer/counter is automatically stopped and all events and waveform outputs will be dis-
abled. When this bit is cleared, the timer/counter is automatically restarted if CLKSEL setting is not in OFF state.
These bits can be used for software control of update, restart, and reset of the timer/counter. The command bits
are always read as zero.
Table 13-12. Command Selection
CMD[1:0] Group configuration Command action
00 NONE None
01 UPDATE Force update
10 RESTART Force restart
11 RESET Force hard reset (ignored if T/C is not in OFF state)
 Bit 1 – LUPD: Lock Update

When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has
occurred. Locking the update ensures that all buffers, including DTI buffers, are valid before an update is
performed.
This bit has no effect when input capture operation is enabled.
XMEGA E MANUAL 179

 Bit 0 – DIR: Counter Direction
When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that the counter is in
the down-counting (decrementing) state.
Normally this bit is controlled in hardware by the waveform generation mode or by event actions, but this bit can
also be changed from software.
13.12.9 CTRLHCLR/CTRLHSET – Control Register H Clear/Set

Refer to “CTRLGCLR/CTRLGSET – Control Register G Clear/Set” on page 179 for information on how to access
this type of status register.
Bit 7 6 5 4 3 2 1 0
– – – CCDBV CCCBV CCBBV CCABV PERBV

 Bit 4:1 – CCxBV: Compare or Capture x Buffer Valid
These bits are set when a new value is written to the corresponding CCxBUF register. These bits are automatically
cleared on an UPDATE condition.
Note that when input capture operation is used, this bit is set on a capture event and cleared if the corresponding
CCxIF is cleared.
 Bit 0 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically cleared on an UPDATE
condition.
13.12.10 INTFLAGS – Interrupt Flags Register
Bit 7 6 5 4 3 2 1 0
+0x0C CCDIF CCCIF CCBIF CCAIF – TRGIF ERRIF OVFIF
 Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag

The compare or capture interrupt flag (CCxIF) is set on a compare match or on an input capture event on the cor-
responding CC channel.
For all modes of operation except for capture, the CCxIF will be set when a compare match occurs between the
count register (CNT) and the corresponding compare register (CCx). The CCxIF is automatically cleared when the
corresponding interrupt vector is executed.
For input capture operation, the CCxIF will be set if the corresponding compare buffer contains valid data (i.e.,
when CCxBV is set). The flag will be cleared when the CCx register is read. Executing the interrupt vector in this
mode of operation will not clear the flag.
The flag can also be cleared by writing a one to its bit location.
The CCxIF can be used for requesting an EDMA transfer. An EDMA read or write access of the corresponding
CCx or CCxBUF will then clear the CCxIF and release the request.
 Bit 2 – TRGIF: Trigger Restart Interrupt Flag
This flag is set when hardware restart condition is detected. Optionally an interrupt can be generated. The flag is
cleared by writing a one to its bit location.
XMEGA E MANUAL 180

 Bit 1 – ERRIF: Error Interrupt Flag
This flag is set on multiple occasions, depending on the mode of operation.
In the FAULT1 or FAULT2 mode of operation, ERRIF is set on a fault condition from the fault extension unit that
requests for software action to resume. For timer/counters which do not have the FAULT extension available, this
flag is never set in FAULT1 or FAULT2 mode of operation.
For capture operation, ERRIF is set if a buffer overflow occurs on any of the CC channels.
For event controlled QDEC operation, ERRIF is set when an incorrect index signal is given.
This flag is automatically cleared when the corresponding interrupt vector is executed. The flag can also be
cleared by writing a one to this location.
 Bit 0 – OVFIF: Overflow/Underflow Interrupt Flag
This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting.
The flag is cleared by writing a one to its bit location.
OVFIF can also be used for requesting an EDMA transfer. An EDMA write access of CNT, PER, or PERBUF will
then clear the OVFIF bit.
13.12.11 TEMP – Temporary Register for 16-bit Access
Bit 7 6 5 4 3 2 1 0
+0x0F TEMP[7:0]
 Bit 7:0 – TEMP[7:0]: Temporary Bits

The TEMP register is used for single-cycle, 16-bit access to the 16-bit timer/counter registers by the CPU. The
EDMA controller has a separate temporary storage register. There is one common TEMP register for all the 16-bit
Timer/counter registers.
For more details on reading and writing 16-bit registers, refer to “Accessing 16-bit Registers” on page 13.
13.12.12CNTL – Counter Register Low

The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the
timer/counter. CPU and EDMA write access has priority over count, clear, or reload of the counter.
Bit 7 6 5 4 3 2 1 0
+0x20 CNT[7:0]
 Bit 7:0 – CNT[7:0]: Counter Low Byte

These bits hold the LSB of the 16-bit counter register.
13.12.13 CNTH – Counter Register High
Bit 7 6 5 4 3 2 1 0
+0x21 CNT[15:8]
 Bit 7:0 – CNT[15:8]: Counter High Byte

These bits hold the MSB of the 16-bit counter register.
XMEGA E MANUAL 181

13.12.14 PERL – Period Register Low
The PERH and PERL register pair represents the 16-bit value, PER. PER contains the 16-bit TOP value in the
timer/counter.
Bit 7 6 5 4 3 2 1 0
+0x26 PER[7:0]
 Bit 7:0 – PER[7:0]: Period Low Byte

These bits hold the MSB of the 16-bit period register.
13.12.15 PERH – Period Register High
Bit 7 6 5 4 3 2 1 0
+0x27 PER[15:8]
 Bit 7:0 – PER[15:8]: Period High Byte

These bits hold the MSB of the 16-bit period register.
13.12.16 CCxL – Compare or Capture x Register Low

The CCxH and CCxL register pair represents the 16-bit value, CCx. These 16-bit register pairs have two functions,
depending of the mode of operation.
For capture operation, these registers constitute the second buffer level and access point for the CPU and EDMA.
For compare operation, these registers are continuously compared to the counter value. Normally, the outputs
form the comparators are then used for generating waveforms. CCx registers are updated with the buffer value
from their corresponding CCxBUF register when an UPDATE condition occurs.
Bit 7 6 5 4 3 2 1 0
CCx[7:0]
 Bit 7:0 – CCx[7:0]: Compare or Capture x Low Byte

These bits hold the MSB of the 16-bit compare or capture register.
13.12.17 CCxH – Compare or Capture x Register High
Bit 7 6 5 4 3 2 1 0
CCx[15:8]
 Bit 7:0 – CCx[15:8]: Compare or Capture x High Byte

These bits hold the MSB of the 16-bit compare or capture register.
XMEGA E MANUAL 182

13.12.18 PERBUFL – Period Buffer Register Low
The PERBUFH and PERBUFL register pair represents the 16-bit value, PERBUF. This 16-bit register serves as
the buffer for the period register (PER). Accessing this register using the CPU or EDMA will affect the PERBUFV
flag.
Bit 7 6 5 4 3 2 1 0
+0x37 PERBUF[7:0]
 Bit 7:0 – PERBUF[7:0]: Period Buffer Low Byte

These bits hold the LSB of the 16-bit period buffer register.
13.12.19 PERBUFH – Period Buffer High
Bit 7 6 5 4 3 2 1 0
+0x38 PERBUF[15:8]
 Bit 7:0 – PERBUF[15:8]: Period Buffer High Byte

These bits hold the MSB of the 16-bit period buffer register.
13.12.20 CCxBUFL – Compare or Capture x Buffer Register Low

The CCxBUFH and CCxBUFL register pair represents the 16-bit value, CCxBUF. These 16-bit registers serve as
the buffer for the associated compare or capture registers (CCx). Accessing any of these registers using the CPU
or EDMA will affect the corresponding CCxBV status bit.
Bit 7 6 5 4 3 2 1 0
CCxBUF[7:0]
 Bit 7:0 – CCxBUF[7:0]: Compare or Capture x Buffer Low Byte

These bits hold the LSB of the 16-bit compare or capture buffer register.
13.12.21 CCxBUFH – Compare or Capture x Buffer Register H
Bit 7 6 5 4 3 2 1 0
CCxBUF[15:8]
 Bit 7:0 – CCxBUF[15:8]: Compare or Capture x Buffer High Byte

These bits hold the MSB of the 16-bit compare or capture buffer register.
XMEGA E MANUAL 183

13.13 Register Description – Byte Mode Configuration
Bit 7 6 5 4 3 2 1 0
+0x00 – SYNCHEN EVSTART UPSTOP CLKSEL[3:0]
 Bit 6 – SYNCHEN: Synchronization Enabled
When this bit is set, the event actions and software commands are synchronized with the internal timer/counter
clock. When the bit is cleared, the event actions and software commands are synchronized with the peripheral
clock (CLKPER).
 Bit 5 – EVSTART: Start on Next Event
Setting this bit will enable the timer/counter on the next event from event line selected by EVSEL bits. If the bit is
cleared, the timer/counter can be enabled only by software, by clearing the LSTOP bit in CTRLGSET register.
 Bit 4 – UPSTOP: Stop on next update
Setting this bit will disable the timer/counter on next update condition (overflow/underflow or retrigger). The bit has
no effect is the timer/counter has been disabled by software.
These bits select the clock source for the timer/counter according to Table 13-13.
DIV1 configuration must be set to ensure a correct output from the waveform generator when the hires extension
is enabled.
CLKSEL[3:0] Group configuration Command action
0001 DIV1 Prescaler: Clk
1nnn EVCHn Event channel n, n={0,…,7}
XMEGA E MANUAL 184

Bit 7 6 5 4 3 2 1 0
+0x01 BYTEM[1:0] CIRCEN[1:0] – WGMODE[2:0]
 Bit 7:6 – BYTEM[1:0]: Byte Mode

These bits select the timer/counter operation mode according to Table 13-14.
Table 13-14. Timer/Counter Byte Mode Selection
BYTEM[1:0] Group configuration Description
00 NORMAL Timer/counter is set to normal mode (timer/counter type 4/5)
One 8-bit timer/counter with doubled CC channels. Upper byte of the counter
01 BYTEMODE
(CNTH) will be set to zero after each counter clock cycle.
10 – Reserved
11 – Reserved
 Bit 5:4 – CIRCEN[1:0]: Circular Buffer Enable

Setting these bits enable the circular buffer option according to Table 13-15.
Table 13-15. Circular Buffer Selection
CIRCEN[1:0] Group configuration Description
00 DISABLE Circular buffer disabled
01 PER Circular buffer enabled on PER/PERBUF registers
10 CCA Circular buffer enabled on LCCA/LCCABUF registers
11 BOTH Circular buffer enabled on both PER/PERBUF and LCCA/LCCABUF registers
 Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode
These bits select the waveform generation mode, and control the counting sequence of the counter, TOP value,
UPDATE condition, interrupt/event condition, and type of waveform that is generated according to Table 13-16.
The result from the waveform generator can be directed to the port pins if the corresponding CCxMODE bits have
been set to enable this. The port pin direction must be set as output.
Table 13-16. Timer Waveform Generation Mode
000 NORMAL Normal PER TOP/BOTTOM(1) TOP/BOTTOM(1)
001 FRQ Frequency CCA TOP/BOTTOM(1) TOP/BOTTOM(1)
011 SINGLESLOPE Single-slope PWM PER TOP/BOTTOM(1) TOP/BOTTOM(1)
XMEGA E MANUAL 185

101 DSTOP Dual-slope PWM PER BOTTOM TOP
110 DSBOTH Dual-slope PWM PER BOTTOM TOP and BOTTOM
111 DSBOTTOM Dual-slope PWM PER BOTTOM BOTTOM

Note: 1. Depends on DIR settings.
Bit 7 6 5 4 3 2 1 0
+0x02 HCMPD HCMPC HCMPB HCMPA LCMPD LCMPC LCMPB LCMPA
 Bit 7:0 – HCMPx/LCMPx: High/Low Compare x Output Value

These bits allow direct access to the waveform generator's output compare value when the timer/counter is OFF.
This is used to set or clear the WG output value when the timer/counter is not running.
Bit 7 6 5 4 3 2 1 0
+0x03 EVACT[2:0] EVDLY EVSEL[3:0]
 Bit 7:5 – EVACT[2:0]: Event Action

These bits define the event action the timer will perform on an event according to Table 13-17. The EVSEL setting
will decide which event source or sources have control in this case.
Table 13-17. Timer Event Action Selection
EVACT[2:0] Group configuration Command action
000 OFF None
001 FMODE1(1) Fault Mode 1 capture
010 FMODE2(1) Fault mode 2 capture
011 UPDOWN Externally controlled up/down count
100 QDEC Quadrature decode
101 RESTART Restart waveform period
110 PWF Pulse width and frequency capture
111 - Reserved
Note: 1. This mode is available only for timer/counter with FAULT extension. For timer/counter without FAULT extension, an input capture will be done.
 Bit 4 – EVDLY: Timer Delay Event

When this bit is set, the selected event source is delayed by one peripheral clock cycle. This is intended for 32-bit
input capture operation. Adding the event delay is necessary to compensate for the carry propagation delay when
cascading two counters via the event system.
XMEGA E MANUAL 186

 Bit 3:0 – EVSEL[3:0]:Timer Event Source Select
These bits select the event channel source for the timer/counter. For the selected event channel to have any
effect, the event action bits (EVACT) must be set according to Table 13-18.
Table 13-18. Timer Event Source Selection
EVSEL[3:0] Group configuration Command action
0000 OFF None
0001 – Reserved
0010 – Reserved
0011 – Reserved
0100 – Reserved
0101 – Reserved
0110 – Reserved
0111 – Reserved
1nnn CHn Event channel n, n={0,…,7}
By default, the selected event channel n will be the event channel source for CC channel A, and event channel
(n+1)%8, (n+2)%8, and (n+3)%8 will be the event channel source for CC channel B, C, and D.
Table 13-19 and Table 13-20 show the event channel source for each CC channel, depending of EVACT settings:
Table 13-19. Event Low Channel Source Selection
EVACT[2:0] LCCD LCCC LCCB LCCA Restart condition
000 (n+3)%8 (n+2)%8 (n+1)%8 n Software
001 (n+3)%8 (n+2)%8 FAULTB FAULTA Software or fault
010 FAULTB FAULTA FAULTB FAULTA Software or fault
011 (n+3)%8 (n+2)%8 (n+1)%8 n Software
100 (n+3)%8 (n+2)%8 (n+1)%8 n Quadrature decoder
101 (n+3)%8 (n+2)%8 (n+1)%8 n Event channel n
110 (n+3)%8 (n+2)%8 n n Event channel n
XMEGA E MANUAL 187

Table 13-20. Event High Channel Source Selection
EVACT[2:0] HCCD HCCC HCCB HCCA Restart condition
000 (n+7)%8 (n+6)%8 (n+5)%8 (n+4)%8 Software
001 (n+7)%8 (n+6)%8 (n+5)%8 (n+4)%8 Software
010 (n+7)%8 (n+6)%8 (n+5)%8 (n+4)%8 Software
011 (n+7)%8 (n+6)%8 (n+5)%8 (n+4)%8 Software
100 (n+7)%8 (n+6)%8 (n+5)%8 (n+4)%8 Quadrature decoder
101 (n+7)%8 (n+6)%8 (n+5)%8 (n+4)%8 Event channel n
110 (n+7)%8 (n+6)%8 (n+5)%8 (n+4)%8 Event channel n
Bit 7 6 5 4 3 2 1 0
+0x04 LCCDMODE[1:0] LCCCMODE[1:0] LCCBMODE[1:0] LCCAMODE[1:0]
 Bit 7:0 – LCCxMODE[2:0] – Low Channel Compare or Capture x Mode

These bits enable the compare and capture operation on corresponding CCx low channel, according to Table 13-
21.
13.13.6 CTRLF – Control Register F
Bit 7 6 5 4 3 2 1 0
+0x05 HCCDMODE[1:0] HCCCMODE[1:0] HCCBMODE[1:0] HCCAMODE[1:0]
 Bit 7:0 – HCCxMODE[2:0] – High Channel Compare or Capture x Mode

These bits enable the compare and capture operation on corresponding CCx high channel, according to Table 13-
21.
Table 13-21. CC Mode Selection
CCMODE[1:0] Group configuration Command action
00 DISABLE Compare or capture disabled
01 COMP Output compare enabled
10 CAPT Input capture enabled
11 BOTHCC(1) Both compare and capture enabled
Note: 1. This mode should be used only if the Fault Unit extension is set in conditional capture fault mode. For more details, refer to“Fault Extension” on
page 209 for description.
XMEGA E MANUAL 188

13.13.7 INTCTRLA – Interrupt Control Register A
Bit 7 6 5 4 3 2 1 0
+0x06 – – TRGINTLVL[1:0] ERRINTLVL[1:0] OVFINTLVL[1:0]

 Bit 5:4 – TRGINTLVL[1:0]:Timer Trigger Restart Interrupt Level
These bits enable the interrupt for the timer trigger restart and select the interrupt level as described in “PMIC –
conditions when TRGIF flag is set.
 Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level
These bits enable the timer error interrupt and select the interrupt level as described in “PMIC – Interrupts and Pro-
grammable Multilevel Interrupt Controller” on page 132.
 Bit 1:0 – OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level
These bits enable interrupt for the timer overflow/underflow and select the interrupt level as described in “PMIC –
conditions when OVFIF flag is set.
13.13.8 INTCTRLB – Interrupt Control Register B
Bit 7 6 5 4 3 2 1 0
+0x07 LCCDINTLVL[1:0] LCCCINTLVL[1:0] LCCBINTLVL[1:0] LCCAINTLVL[1:0]
 Bit 7:0 – LCCxINTLVL[2:0] – Low-channel Compare or Capture x Interrupt Level

These bits enable the timer compare or capture interrupt for low channel x and select the interrupt level as
described in “PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132.
13.13.9 CTRLGCLR/CTRLGSET – Control Register G Clear/Set

This register is mapped into two I/O memory locations, one for clearing (CTRLxCLR) and one for setting the
register bits (CTRLxSET) when written. Both memory locations will give the same result when read.
The individual status bit can be set by writing a one to its bit location in CTRLxSET, and cleared by writing a one to
its bit location in CTRLxCLR. This allows each bit to be set or cleared without use of a read-modify-write operation
on a single register.
Bit 7 6 5 4 3 2 1 0
– – STOP – CMD[1:0] LUPD DIR
Read/Write R R R/W R R/W R/W R/W R/W

 Bit 5 – STOP: Timer/Counter Stop
When this bit is set, the timer/counter is automatically stopped and all events and waveform outputs will be dis-
abled. When this bit is cleared, the timer/counter is automatically restarted if CLKSEL setting is not OFF state.
XMEGA E MANUAL 189

These bits can be used for software control of update, restart, and reset of the low-byte timer/counter, according to
Table 13-22 on page 190. The command bits are always read as zero.
Table 13-22. Command Selections
CMD[1:0] Group configuration Command action
00 NONE None
01 UPDATE Force update
10 RESTART Force restart
11 RESET Force hard reset (ignored if T/C is not in OFF state)
 Bit 1 – LUPD: Lock Update

When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has
occurred. Locking the update ensures that all buffers, including DTI buffers, are valid before an update is
performed.
This bit has no effect when input capture operation is enabled.
 Bit 0 – DIR: Counter Direction
When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that the counter is in
the down-counting (decrementing) state.
Normally this bit is controlled in hardware by the waveform generation mode or by event actions, but this bit can
also be changed from software.
13.13.10 CTRLHCLR/CTRLHSET – Control Register H Clear/Set

Refer to “CTRLGCLR/CTRLGSET – Control Register G Clear/Set” on page 179 for information on how to access
this type of status register.
Bit 7 6 5 4 3 2 1 0
– – – LCCDBV LCCCBV LCCBBV LCCABV LPERBV

 Bit 4:1 – LCCxBV: Low Channel Compare or Capture x Buffer Valid
These bits are set when a new value is written to the corresponding LCCxBUF register. These bits are automati-
cally cleared on an UPDATE condition.
Note that when input capture operation is used, this bit is set on a capture event and cleared if the corresponding
LCCxIF is cleared.
The feature is not present on high channels.
 Bit 0 – LPERBV: Low Period Buffer Valid
This bit is set when a new value is written to the LPERBUF register. This bit is automatically cleared on an
UPDATE condition.
XMEGA E MANUAL 190

Bit 7 6 5 4 3 2 1 0
+0x0C LCCDIF LCCCIF LCCBIF LCCAIF – TRGIF ERRIF OVFIF
 Bit 7:4 – LCCxIF: Low Channel Compare or Capture x Interrupt Flag

The compare or capture interrupt flag (LCCxIF) is set on a compare match or on an input capture event on the cor-
responding LCC channel.
For all modes of operation except for capture, the LCCxIF will be set when a compare match occurs between the
count register (LCNT) and the corresponding compare register (LCCx). The LCCxIF is automatically cleared when
the corresponding interrupt vector is executed.
For input capture operation, the LCCxIF will be set if the corresponding compare buffer contains valid data (i.e.,
when LCCxBV is set). The flag will be cleared when the LCCx register is read. Executing the interrupt vector in this
mode of operation will not clear the flag.
The LCCxIF can be used for requesting an EDMA transfer. An EDMA read or write access of the corresponding
LCCx or LCCxBUF will then clear the LCCxIF and release the request.
 Bit 2 – TRGIF: Timer/Counter Trigger Restart Interrupt Flag
This flag is set when hardware restart condition is detected. Optionally an interrupt can be generated. Since the
trigger restart interrupt shares the interrupt address with the overflow/underflow interrupt, TRGIF will not be
cleared when the interrupt vector is executed. The flag is cleared by writing a one to its bit location.
 Bit 1 – ERRIF: Error Interrupt Flag
This flag is set on multiple occasions, depending on the mode of operation.
In the FAULT1 or FAULT2 mode of operation, ERRIF is set on a fault detect condition from the FAULT unit exten-
sion that requests for software action to resume. For timer/counters which do not have the FAULT extension
available, this flag is never set in FAULT1 or FAULT2 mode of operation.
For capture operation, ERRIF is set if a buffer overflow occurs on any of the low CC channels.
For event controlled QDEC operation, ERRIF is set when an incorrect index signal is given.
This flag is automatically cleared when the corresponding interrupt vector is executed. The flag can also be
cleared by writing a one to this location.
 Bit 0 – OVFIF: Timer Overflow/Underflow Interrupt Flag
This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting.
Since the overflow/underflow interrupt shares the interrupt address with the trigger restart interrupt, OVFIF will not
be cleared when the interrupt vector is executed. The flag is cleared by writing a one to its bit location.
OVFIF can also be used for requesting an EDMA transfer. An EDMA write access of LCNT, LPER, or LPERBUF
will then clear the OVFIF bit.
13.13.12 LCNT – Low Counter Register
Bit 7 6 5 4 3 2 1 0
+0x20 LCNT[7:0]
 Bit 7:0 – LCNT[7:0]: Low Counter Byte

These bits hold the 8-bit counter register.
XMEGA E MANUAL 191

13.13.13 LPER – Low Period Register
Bit 7 6 5 4 3 2 1 0
+0x26 LPER[7:0]
 Bit 7:0 – LPER[7:0]: Low Period Byte

These bits hold the 8-bit period register.
13.13.14 LCCx – Low Channel Compare or Capture x Register
Bit 7 6 5 4 3 2 1 0
LCCx[7:0]
 Bit 7:0 – LCCx[7:0]: Low Channel Compare or Capture x Byte

These bits hold the 8-bit low channels compare or capture register.
13.13.15 HCCx – High-Channel Compare or Capture x Register
Bit 7 6 5 4 3 2 1 0
HCCx[7:0]
 Bit 7:0 – HCCx[7:0]: High Channel Compare or Capture x Byte

These bits hold the 8-bit high-channel compare or capture register.
13.13.16 LPERBUF – Low Period Buffer Register
Bit 7 6 5 4 3 2 1 0
+0x37 LPERBUF[7:0]
 Bit 7:0 – LPERBUF[7:0]: Low Period Buffer Byte

These bits hold the 8-bit period buffer register.
13.13.17 LCCxBUF – Low Channel Compare or Capture x Buffer Register
Bit 7 6 5 4 3 2 1 0
LCCxBUF[7:0]
 Bit 7:0 – LCCxBUF[7:0]: Low Channel Compare or Capture x Buffer Byte

These bits hold the 8-bit low-channel compare or capture buffer register.
XMEGA E MANUAL 192

13.13.18 HCCxBUF – High Channel Compare or Capture x Buffer Register
Bit 7 6 5 4 3 2 1 0
HCCxBUF[7:0]
 Bit 7:0 – HCCxBUF[7:0]: High Channel Compare or Capture x Buffer Byte

These bits hold the 8-bit high-channel compare or capture buffer register.
XMEGA E MANUAL 193

13.14 Register Summary – Standard Configuration
+0x00 CTRLA - SYNCHEN EVSTART UPSTOP CLKSEL[3:0] 174
+0x01 CTRLB BYTEM[1:0] CIRCEN[1:0] - WGMODE[2:0] 175
+0x02 CTRLC POLD POLC POLB POLA CMPD CMPC CMPB CMPA 176
+0x03 CTRLD EVACT[2:0] EVDLY EVSEL[3:0] 176
+0x04 CTRLE CCDMODE[1:0] CCCMODE[1:0] CCBMODE[1:0] CCAMODE[1:0] 178
+0x05 Reserved - - - - - - - -
+0x06 INTCTRLA - - TRGINTLVL[1:0] ERRINTLVL [1:0] OVFINTLVL[1:0] 178
+0x07 INTCTRLB CCDINTLVL[1:0] CCCINTLVL[1:0] CCBINTLVL[1:0] CCAINTLVL[1:0] 179
+0x08 CTRLGCLR - - STOP - CMD[1:0] LUPD DIR 179
+0x09 CTRLGSET - - STOP - CMD[1:0] LUPD DIR 179
+0x0A CTRLHCLR - - - CCDBV CCCBV CCBBV CCABV PERBV 180
+0x0B CTRLHSET - - - CCDBV CCCBV CCBBV CCABV PERBV 180
+0x0C INTFLAGS CCDIF CCCIF CCBIF CCAIF - TRGIF ERRIF OVFIF 180
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F TEMP TEMP[7:0] 181
+0x10 - +0x1F Reserved - - - - - - - -
+0x20 CNTL CNT[7:0] 181
+0x21 CNTH CNT[15:8] 181
+0x22 - +0x25 Reserved - - - - - - - -
+0x26 PERL PER[7:0] 182
+0x27 PERH PER[15:8] 182
+0x28 CCAL CCA[7:0] 182
+0x29 CCAH CCA[15:8] 182
+0x2A CCBL CCB[7:0] 182
+0x2B CCBH CCB[15:8] 182
+0x2C CCCL CCC[7:0] 182
+0x2D CCCH CCC[15:8] 182
+0x2E CCDL CCD[7:0] 182
+0x2F CCDH CCD[15:8] 182
+0x30 - +0x35 Reserved - - - - - - - -
+0x36 PERBUFL PERBUF[7:0] 183
+0x37 PERBUFH PERBUF[15:8] 183
+0x38 CCABUFL CCABUF[7:0] 183
+0x39 CCABUFH CCABUF[15:8] 183
+0x3A CCBBUFL CCBBUF[7:0] 183
+0x3B CCBBUFH CCBBUF[15:8] 183
+0x3C CCCBUFL CCCBUF[7:0] 183
+0x3D CCCBUFH CCCBUF[15:8] 183
+0x3E CCDBUFL CCDBUF[7:0] 183
+0x3F CCDBUFH CCDBUF[15:8] 183
XMEGA E MANUAL 194

13.15 Interrupt Vector Summary – Standard Configuration
Table 13-23. Timer/counter interrupt vectors and their word offset address
0x00 OVF_vect Timer/counter overflow/underflow interrupt vector offset
0x02 ERR_vect Timer/counter error interrupt vector offset
0x04 CCA_vect Timer/counter compare or capture channel A interrupt vector offset
0x06 CCB_vect Timer/counter compare or capture channel B interrupt vector offset

(1)
0x08 CCC_vect Timer/counter compare or capture channel C interrupt vector offset
0x0A CCD_vect(1) Timer/counter compare or capture channel D interrupt vector offset
Note: 1. Available only on timer/counters with four compare or capture channels.
XMEGA E MANUAL 195

13.16 Register Summary – Byte Configuration
+0x00 CTRLA - SYNCHEN EVSTART UPSTOP CLKSEL[3:0] 184
+0x01 CTRLB BYTEM[1:0] CIRCEN[1:0] - WGMODE[2:0] 185
+0x02 CTRLC HCMPD HCMPC HCMPB HCMPA LCMPD LCMPC LCMPB LCMPA 186
+0x03 CTRLD EVACT[2:0] EVDLY EVSEL[3:0] 186
+0x04 CTRLE LCCDMODE[1:0] LCCCMODE[1:0] LCCBMODE[1:0] LCCAMODE[1:0] 188
+0x05 CTRLF HCCDMODE[1:0] HCCCMODE[1:0] HCCBMODE[1:0] HCCAMODE[1:0] 188
+0x06 INTCTRLA - - TRGINTLVL [1:0] ERRINTLVL[1:0] OVFINTLVL[1:0] 189
+0x07 INTCTRLB LCCDINTLVL[1:0] LCCCINTLVL[1:0] LCCBINTLVL[1:0] LCCAINTLVL[1:0] 189
+0x08 CTRLGCLR - - STOP - CMD[1:0] LUPD DIR 189
+0x09 CTRLGSET - - STOP - CMD[1:0] LUPD DIR 189
+0x0A CTRLHCLR - - - LCCDBV LCCCBV LCCBBV LCCABV LPERBV 190
+0x0B CTRLHSET - - - LCCDBV LCCCBV LCCBBV LCCABV LPERBV 190
+0x0C INTFLAGS LCCDIF LCCCIF LCCBIF LCCAIF - TRGIF ERRIF OVFIF 191
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
+0x10 - +0x1F Reserved - - - - - - - -
+0x20 LCNT Low-byte Timer/Counter Count Register 191
+0x21 Reserved - - - - - - - -
+0x22 - +0x25 Reserved - - - - - - - -
+0x26 LPER Low-byte Timer/Counter Period Register 192
+0x27 Reserved - - - - - - - -
+0x28 LCCA Low Channel Compare or Capture Register A 192
+0x29 HCCA High Channel Compare or Capture Register A 192
+0x2A LCCB Low Channel Compare or Capture Register B 192
+0x2B HCCB High Channel Compare or Capture Register B 192
+0x2C LCCC Low Channel Compare or Capture Register C 192
+0x2D HCCC High Channel Compare or Capture Register C 192
+0x2E LCCD Low Channel Compare or Capture Register D 192
+0x2F HCCD High Channel Compare or Capture Register D 192
+0x30 - +0x35 Reserved - - - - - - - -
+0x36 LPERBUF Low- byte Timer/Counter Period Buffer Register 192
+0x37 Reserved - - - - - - - -
+0x38 LCCABUF Low Channel Compare or Capture Buffer Register A 192
+0x39 HCCABUF High Channel Compare or Capture Buffer Register A 193
+0x3A LCCBBUF Low Channel Compare or Capture Buffer Register B 192
+0x3B HCCBBUF High Channel Compare or Capture Buffer Register B 193
+0x3C LCCCBUF Low Channel Compare or Capture Buffer Register C 192
+0x3D HCCCBUF High Channel Compare or Capture Buffer Register C 193
+0x3E LCCDBUF Low Channel Compare or Capture Buffer Register D 192
+0x3F HCCDBUF High Channel Compare or Capture Buffer Register D 193
XMEGA E MANUAL 196

13.17 Interrupt Vector Summary – Byte Configuration
Table 13-24. Timer/counter interrupt vectors and their word offset address
0x00 OVF_vect Timer/Counter overflow/underflow interrupt vector offset
0x02 ERR_vect Timer/Counter error interrupt vector offset
0x04 CCA_vect Timer/Counter compare or capture channel A interrupt vector offset
0x06 CCB_vect Timer/Counter compare or capture channel B interrupt vector offset
0x08 CCC_vect(1) Timer/Counter compare or capture channel C interrupt vector offset
0x0A CCD_ vect(1) Timer/Counter compare or capture channel D interrupt vector offset
Note: 1. Available only on timer/counters with four compare or capture channels.
XMEGA E MANUAL 197

14. WeX – Waveform Extension
14.1 Features
 Module for more customized and advanced PWM and waveform output
 Optimized for various types of motor, ballast and power stage control
 Output matrix for timer/counter compare channel distribution:
 Configurable distribution of compare channel outputs across port pins
 Redistribution of dead-time insertion resources between TC4 and TC5.
 Four dead-time insertion (DTI) units, each with:
 Complementary high and low channel with non overlapping outputs
 Separate dead-time setting for high and low side
 8-bit resolution
 Four swap (SWAP) units:
 Separate port pair or low/high side drivers swap
 Double buffered swap feature
 Pattern generation creating synchronized bit pattern across the port pins
 Double buffered pattern generation
14.2 Overview
The waveform extension (WEX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is
primarily intended for use in different types of motor control, ballast, LED, H-bridge, power converter and other types of
power control applications. The WEX consists of five independent and successive units, as shown in Figure 14-1.
Figure 14-1. Waveform Extention and Closely Related Peripherals (grey)

WEX
Px7
DTI3 SWAP3
Px6
Pattern Generator
Px5
Fault
Output Matrix
T/C5 DTI2 SWAP2

Unit 5 OUTOVDIS Px4
HIRES
Px3
DTI1 SWAP1
Px2
T/C4
Fault Px1
Unit 4 DTI0 SWAP0
Px0
The output matrix (OTMX) can distribute and route out the waveform outputs from timer/counter 4 and 5 across the port
pins in different configurations, each optimized for different application types.
The dead time insertion (DTI) unit splits the four lower OTMX outputs into a two non-overlapping signals, the non-
inverted low side (LS) and inverted high side (HS) of the waveform output with optional dead-time insertion between LS
and HS switching.
The swap (SWAP) unit can swap the LS and HS pin position. This can be used for fast decay motor control.
The pattern generation unit generates synchronized output waveform with constant logic level. This can be used for easy
stepper motor and full bridge control.
The output override disable unit can disable the waveform output on selectable port pins to optimize the pins usage. This
is to free the pins for other functional use, when the application does not need the waveform output spread across all the
port pins as they can be selected by the OTMX configurations.
XMEGA E MANUAL 198

Figure 14-2 shows a schematic diagram of action of each WEX unit on a port pin pair. The WEX DTI and SWAP units
can be seen as a four port pair slices:
 Slice 0, DTI0/ SWAP0 acting on port pins (Px[0],Px[1])
 Slice 1, DTI1/ SWAP1 acting on port pins (Px[2],Px[3])
And more generally:
 Slice n, DTIn/ SWAPn acting on port pins (Px[2n],Px[2n+1])
Figure 14-2. Waveform Extention Stage Details

WeX PORTS
OTMX DTI SWAP PATTERN
OTMX[2x+1] PGV[2x+1]
P[2x+1]
LS
PGO[2x+1] INV[2x+1]
OTMX OTMX[x] DTIx DTIxEN SWAPx
PGO[2x] INV[2x]
HS
P[2x]
OTMX[2x] PGV[2x]
14.3 Port Override

The port override logic is common for all the timer/counter extensions. By default, when the dead-time enable (DTIENx)
bit is set, the timer/counter extension takes control over the pin pair for the corresponding channel. The default behavior
can be changed in one of the following conditions:
 PORTCTRL bit in “CTRLA – Control Register A” on page 218 is set. For details on fault port control mode, refer to
“Fault Extension” on page 209.
 The output is disabled by setting the corresponding bit in the output override disable register. When set, the
corresponding I/O pin can be used by any other alternative pin function. For details, refer to “OUTOVDIS – Output
Override Disable Register” on page 206.
14.4 Output Matrix

The output matrix (OTMX) unit distributes and routes waveform output across the port pins, according to the selectable
configurations, as shown in Table 14-1 on page 200.
XMEGA E MANUAL 199

Table 14-1. Timer/counter 4 and 5 Compare Channel Pin Routing Configuration
OTMX[2:0] PIN7 PIN 6 PIN 5 PIN 4 PIN 3 PIN 2 PIN 1 PIN 0
000 TC5CCB TC5CCA TC4CCD TC4CCC TC4CCB TC4CCA
001 TC5CCB TC5CCA TC5CCB TC5CCA TC4CCD TC4CCC TC4CCB TC4CCA
010 TC5CCB TC5CCA TC4CCB TC4CCA TC5CCB TC5CCA TC4CCB TC4CCA
011 TC4CCA TC4CCA TC4CCA TC4CCA TC4CCA TC4CCA TC4CCA TC4CCA
100 TC4CCB TC4CCA TC4CCA TC4CCA TC4CCA TC4CCA TC4CCA TC4CCA
101 – – – – – – – –
110 – – – – – – – –
111 – – – – – – – –
1. Configuration 000 is default configuration. The pin location is the default one, and corresponds to the default
timer/counter configuration.
2. Configuration 001 distributes the waveform outputs from timer/counter 5 compare channel A and B (TC5 CCA and
TC5 CCB) on four pin locations. This provides for example, the enable control of the four transistors of a full bridge
with only the use of two compare channels. Using pattern generation, some of these four outputs can be overwrit-
ten by a constant level, enabling flexible drive of a full bridge in all quadrant configurations.
3. Configuration 010 distributes the waveform outputs from compare channels A and B (CCA and CCB) from both
timer/counter 4 and 5 on two other pin locations.
4. Configuration 011 distributes the waveform outputs from timer/counter 4 compare channel A (TC4CCA) to all port
pins. Enabling pattern generation in this mode will control a stepper motor.
5. Configuration 100 distributes the waveform output from timer/counter 5 compare channel A (TC5 CCA) to pin 7
and the waveform output from timer/counter 4 compare channel A (TC4 CCA) to all other pins (Px0 to Px6). This,
together with pattern generation and the fault extension, enable control of one to seven LED strings.
14.5 Dead-time Generator

The dead-time insertion (DTI) unit generates OFF time on which the non-inverted low side (LS) and inverted high side
(HS) of the WG outputs are both low. This OFF time is called dead time. Dead-time insertion ensures that the LS and HS
never switch simultaneously.
The DTI stage consists of four equal dead-time insertion generators, one for each timer/counter 4 compare channels.
They can be also redistributed to timer/counter 5 channels through output matrix (configuration 010).
Figure 14-3 on page 201 shows the block diagram of one DTI generator. The four channels have a common register that
controls independently the high side and low side dead times.
XMEGA E MANUAL 200

Figure 14-3. Dead-time Generator Block Diagram
As shown in Figure 14-4, the 8-bit dead-time counter is decremented by one at each peripheral clock cycle, until it
reaches zero. A nonzero counter value will force both the low side and high side outputs into their OFF state. When the
output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input. When the
output changes from low to high (positive edge) it initiates counter reload of the DTLS register, and when the output
changes from high to low (negative edge) a reload of the DTHS register.
Figure 14-4. Dead-time Generator Timing Diagram
14.6 Pattern Generator

The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern
generation features are primarily intended for handling the commutation sequence in brushless DC motor (BLDC),
stepper motor and full bridge control. A block diagram of the pattern generator is shown in Figure 14-5 on page 202.
XMEGA E MANUAL 201

Figure 14-5. Pattern Generator Block Diagram
4 5
As with other double buffered timer/counter registers, the register update is synchronized to the UPDATE condition, set
by the timer/counter waveform generation mode. If the synchronization provided is not required by the application, the
application code can simply access the PGO, PGV, or PORTx registers directly.
In addition to port override condition, the timer/counter channel CCxMode associated to output port must be set to COMP
or BOTHCC to make corresponding pattern generator be visible on the port.
14.7 Change Protection

To avoid unintentional configuration changes, five control registers in the WEX can be protected by writing the
corresponding lock bit in the waveform extension lock register. For more details, refer to “I/O Memory Protection” on
page 25 and “WEXLOCK – Waveform Extension Lock Register” on page 44.
When the lock bit is set, the CTRL, DTBOTH, DTLS, DTHS, and OUTOVDIS registers cannot be changed.
XMEGA E MANUAL 202

Bit 7 6 5 4 3 2 1 0
+0x00 UPSEL OTMX[2:0] DTI3EN DTI2EN DTI1EN DTI0EN
 Bit 7 – UPSEL: Update Source Selection

By default the timer/counter 4 update condition is used by the swap and pattern generation units to update their
register content. Setting this bit, makes the timer/counter 5 update condition as source of register update.
 Bit 6:4 – OTMX[2:0]: Output Matrix
These bits define the matrix routing of the timer/counters waveform generation outputs to the port pins, according
to Table 14-1 on page 200.
 Bit 3:0 – DTIxEN: Dead-Time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will
override the output matrix [2x] and [2x+1], with the low side and high side waveform respectively. The bits are read
zero if the fault blanking is enabled. For details on fault blanking, refer to “Fault Blanking” on page 211.
14.8.2 DTBOTH – Dead-Time Concurrent Write to Both Sides Register
Bit 7 6 5 4 3 2 1 0
+0x01 DTBOTH[7:0]
Read/Write W W W W W W W W
 Bit 7:0 – DTBOTH[7:0]: Dead-Time Both Side Bits

Writing to this register will update the DTHS and DTLS registers at the same time (i.e., at the same I/O write
access). Reading it, give 0x00 Value.
14.8.3 DTLS – Dead-Time Low Side Register
Bit 7 6 5 4 3 2 1 0
+0x02 DTLS[7:0]
 Bit 7:0 – DTLS[7:0]: Dead-time Low Side Bits

This register holds the number of peripheral clock cycles for the dead-time low side.
14.8.4 DTHS – Dead-Time High Side Register
Bit 7 6 5 4 3 2 1 0
+0x03 DTHS[7:0]
 Bit 7:0 – DTHS[7:0]: Dead-Time High Side Bits

This register holds the number of peripheral clock cycles for the dead-time high side.
XMEGA E MANUAL 203

14.8.5 STATUSCLR/STATUSSET – Status Clear/Set Register
Bit 7 6 5 4 3 2 1 0
+0x04/0x05 – – – – – SWAPBUFV PGVBUFV PGOBUFV

 Bit 2 – SWAPBUFV: SWAP Buffer Valid
If this bit is set, the swap buffer is written and contains valid data that will be copied into the SWAP register on the
next UPDATE condition. If this bit is zero, no action will be taken. The connected timer/counter lock update (LUPD)
flag also affects the update for the swap registers.
 Bit 1 – PGVBUFV: Pattern Generator Value Buffer Valid
If this bit is set, the pattern generation value (PGV) buffer is written and contains valid data that will be copied into
the PGV register on the next UPDATE condition. If this bit is zero, no action will be taken. The connected
timer/counter lock update (LUPD) flag also affects the update of the PGV buffer.
 Bit 0 – PGOBUFV: Pattern Generator Overwrite Buffer Valid
If this bit is set, the pattern generation overwrite (PGO) buffer is written and contains valid data that will be copied
into the PGO register on the next UPDATE condition. If this bit is zero, no action will be taken. The connected
timer/counter lock update (LUPD) flag also affects the update for the PGO buffers.
14.8.6 SWAP – Swap Register
Bit 7 6 5 4 3 2 1 0
+0x06 – – – – SWAP3 SWAP2 SWAP1 SWAP0

 Bit 3:0 – SWAPx: Swap DTI Output Pair
Setting these bits enables output swap of DTI outputs [2x] and [2x+1]. Note the DTIxEN settings will not affect the
swap operation.
14.8.7 PGO – Pattern Generation Override Register
Bit 7 6 5 4 3 2 1 0
+0x07 PGO[7:0]
 Bit 7:0 – PGO[7:0]: Pattern Generation Override

This register holds the enables of pattern generation for each output. A bit position at one, overrides the corre-
sponding SWAP output with the respective PGV bit value.
XMEGA E MANUAL 204

14.8.8 PGV – Pattern Generation Value Register
Bit 7 6 5 4 3 2 1 0
+0x08 PGV[7:0]
 Bit 7:0 – PGV[7:0]: Pattern Generation Value

This register holds the values of pattern for each output.
14.8.9 SWAPBUF – Swap Buffer Register
Bit 7 6 5 4 3 2 1 0
+0x0A – – – – SWAP3BUF SWAP2BUF SWAP1BUF SWAP0BUF

 Bit 3:0 – SWAPxBUF: Swap DTI Output Pair
These register bits are the buffer for the SWAP register bits. If double buffering is used, valid content in these bits
are copied to the corresponding SWAPx bits on an UPDATE condition.
14.8.10 PGOBUF – Pattern Generation Overwrite Buffer Register
Bit 7 6 5 4 3 2 1 0
+0x0B PGOBUF[7:0]
 Bit 7:0 – PGOBUF[7:0]: Pattern Generation Override Buffer

This register is the buffer for the PGO register. If double buffering is used, valid content in this register is copied to
the PGO register on an UPDATE condition.
14.8.11 PGVBUF – Pattern Generation Value Buffer Register
Bit 7 6 5 4 3 2 1 0
+0x0C PGVBUF[7:0]
 Bit 7:0 – PGVBUF[7:0]: Pattern Generation Value Buffer

This register is the buffer for the PGV register. If double buffering is used, valid content in this register is copied to
the PGV register on an UPDATE condition.
XMEGA E MANUAL 205

14.8.12 OUTOVDIS – Output Override Disable Register
Bit 7 6 5 4 3 2 1 0
+0x0F OUTOVDIS[7:0]
 Bit 7:0 – OUTOVDIS[7:0]: Output Override Disable

These bits disable the automatic override of the corresponding output port register (i.e., one-to-one bit relation to
pin position).

+0x00 CTRL UPSEL OTMX[2:0] DTI3EN DTI2EN DTI1EN DTI0EN 203
+0x01 DTBOTH DTBOTH[7:0] 203
+0x02 DTLS DTLS[7:0] 203
+0x03 DTHS DTHS[7:0] 203
+0x04 STATUSCLR – – – – – SWAPBUFV PGVBUFV PGOBUFV 204
+0x05 STATUSSET – – – – – SWAPBUGV PGVBUFV PGOBUFV 204
+0x06 SWAP – – – – SWAP3 SWAP2 SWAP1 SWAP0 204
+0x07 PGO PGO[7:0] 204
+0x08 PGV PGV[7:0] 205
+0x09 Reserved – – – – – – – –
+0x0A SWAPBUF – – – – SWAP3BUF SWAP2BUF SWAP1BUF SWAP0BUF 205
+0x0B PGOBUF PGOBUF[7:0] 205
+0x0C PGVBUF PGVBUF[7:0] 205
+0x0D Reserved – – – – – – – –
+0x0E Reserved – – – – – – – –
+0x0F OUTOVDIS OUTOVDIS[7:0] 206
XMEGA E MANUAL 206

15. Hi-Res – High-Resolution Extension
15.1 Features
 Increases waveform generator resolution up to 8x (3 bits)
 Supports frequency, single-slope PWM, and dual-slope PWM generation
 Supports the waveform extension when this is used for the same timer/counter
15.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the waveform extension (WeX) if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled. Refer to “System Clock Selection and Prescalers” on page 98 for more details.
Figure 15-1. Timer/counter Operation with Hi-res Extension Enabled
Override Disable
extension
Generation
Dead-Time
Insertion
Fault
Pattern
Output
Output
SWAP
Matrix
When the hi-res extension is enabled, the timer/counter must run from a non-prescaled peripheral clock. The
timer/counter will ignore its two least-significant bits (lsb) in the counter, and counts by four for each peripheral clock
cycle. Overflow/underflow and compare match of the 14 most-significant bits (msb) is done in the timer/counter. Count
and compare of the two lsb is handled and compared in the hi-res extension running from the peripheral 4x clock.
The two lsb of the timer/counter period register must be set to zero to ensure correct operation. If the count register is
read from the application code, the two lsb will always be read as zero, since the timer/counter run from the peripheral
clock. The two lsb are also ignored when generating events.
When the hi-res plus feature is enabled, the function is the same as with the hi-res extension, but the resolution will
increase by eight instead of four. This also means that the three lsb are handled by the hi-res extension instead of two
lsb, as when only hi-res is enabled. The extra resolution is achieved by counting on both edges of the peripheral 4x clock.
The hi-res extension will not output any pulse shorter than one peripheral clock cycle; i.e., a compare value lower than
four will have no visible output.
XMEGA E MANUAL 207

Bit 7 6 5 4 3 2 1 0
+0x00 – – – – HRPLUS[1:0] HREN[1:0]

 Bit 3:2 – HRPLUS[1:0]: High Resolution Plus
These bits enable the high-resolution plus mode for a timer/counter according to Table 15-1.
Hi-res plus is the same as hi-res, but will increase the resolution by eight (three bits) instead of four. The extra res-
olution is achieved by operating at both edges of the peripheral 4x clock.
Table 15-1. High Resolution Plus
HRPLUS[1:0] Group configuration Description
00 NONE None
01 HRP4 Hi-res plus enabled on timer/counter 4
10 HRP5 Hi-res plus enabled on timer/counter 5
11 BOTH Hi-res plus enabled on both timer/counters 4 and 5
 Bit 1:0 – HREN[1:0]: High Resolution Enable

These bits enables the high-resolution mode for a timer/counter according to Table 15-2.
Setting one or both HREN bits will enable high-resolution waveform generation output for the entire general pur-
pose I/O port. This means that both timer/counters connected to the same port must enable hi-res if both are used
for generating PWM or FRQ output on pins.
Table 15-2. High Resolution Enable
HREN[1:0] Group configuration Description
00 NONE None
01 HR4 Hi-res enabled on timer/counter 4
10 HR5 Hi-res enabled on timer/counter 5
11 BOTH Hi-res enabled on both timer/counters 4 and 5

+0x00 CTRLA – – – – HRPLUS[1:0] HREN[1:0] 208
XMEGA E MANUAL 208

16. Fault Extension
16.1 Features
 Connected to timer/counter output and waveform extension input
 Event controlled fault protection for instant and predictable fault triggering
 Fast, synchronous and asynchronous fault triggering
 Flexible configuration with multiple fault sources
 Recoverable fault modes:
 Restart or halt the timer/counter on fault condition
 Timer/counter input capture on fault condition
 Waveform output active time reduction on fault condition
 Non-recoverable faults:
 Waveform output is forced to a pre-configured safe state on fault condition
 Optional fuse output value configuration defining the output state during system reset
 Flexible fault filter selections:
 Digital filter to prevent false triggers from I/O pin glitches
 Fault blanking to prevent false triggers during commutation
 Fault input qualification to filter the fault input during the inactive output compare states
16.2 Overview
The fault extension enables event controlled fault protection by acting directly on the generated waveforms from
timer/counter compare outputs. It can be used to trigger two types of faults with the following actions:
 Recoverable faults: the timer/counter can be restarted or halted as long as the fault condition is preset. The compare
output pulse active time can be reduced as long as the fault condition is preset. This is typically used for current
sensing regulation, zero crossing re-triggering, demagnetization re-triggering, and so on.
 Non-recoverable faults: the compare outputs are forced to a safe and pre-configured values that are safe for the
application. This is typically used for instant and predictable shut down and to disable the high current or voltage
drivers.
Events are used to trigger a fault condition. One or several simultaneous events are supported, both synchronously or
asynchronously. By default, the fault extension supports asynchronous event operation, ensuring predictable and instant
fault reaction, including system power modes where the system clock is stopped.
By using the input blanking, the fault input qualification or digital filter option in event system, the fault sources can be
filtered to avoid false faults detection.
16.3 Timer/counter Considerations

Each timer/counter supports the fault extension, but the fault extension may not be enabled for all timer/counters. For
details on available fault extension units and corresponding timer/counters, refer to the device datasheet.
16.3.1 Polarity Configuration

For details on output polarity description and settings, refer to “Output Polarity” on page 171 and “CTRLC – Control
Register C” on page 176.
16.3.2 Waveform Generation

The recoverable faults can be enabled in any waveform generation mode, except dual slope PWM. Non-recoverable
faults can be enabled in any timer/counter operation mode.
XMEGA E MANUAL 209

16.4 Faults
A fault input is an event from the event system. When an event occurs, the fault triggers the configured fault actions.
All events from the event system can be used as fault input. For details on event system and available events, refer to
“Event System ” on page 79.
16.4.1 Fault Types

The fault extension defines two fault types:
 Recoverable faults can restart or halt the timer/counter. Two fault inputs, called fault A and fault B, can trigger
recoverable fault actions on compare channels A and B from the corresponding timer/counter. The compare channels
outputs can be clamped to inactive state as long as the fault condition is present, or from the first valid fault condition
detection and until the end of the timer/counter cycle.
 Non-recoverable fault forces the compare channels outputs to a safe and pre-configured value. The fault input, called
fault E, performs non-recoverable fault actions on all compare channels from the corresponding timer/counter.
16.4.2 Input Selection

The fault extension uses up to three event channels. The lowest channel is selected by the EVSEL bits in the
corresponding timer/counter, as described in “CTRLD – Control Register D” on page 176. The next two subsequent
event channels are automatically selected for the fault extension.
The first two event channels can be used as fault A or fault B inputs. In two ramp mode of operation, it is also possible to
link the fault source for the current cycle, to the fault state from the previous cycle. This is typically used for various
applications, such LED control.
The non-recoverable fault can use any of the three available even lines.
16.4.3 Ramp Modes

Two ramp modes are supported and both require the timer/counter running in single slope PWM mode. By default, the
timer/counter is enabled in RAMP1 mode, which is the standard timer/counter operation described in “Compare Channel”
on page 169. In RAMP2 mode, two consecutive timer/counter cycles are interleaved, as shown in Figure 16-1. In cycle A,
the waveform output B is disabled, and in cycle B, the waveform output A is disabled. The cycle index (cycle A or cycle B)
can be controlled using the cycle index commands bits. For details refer to “CTRLGSET – Control Register G Set” on
page 223.
Figure 16-1. Timer/counter Cycle in RAMP2 Mode
Cycle A B A B
"update"
"match"
Period (T) CCx=BOT CCx=TOP
MAX
TOP
CNT
CCA/CCB
BOTTOM
WG Output A
WG Output B
XMEGA E MANUAL 210

16.4.4 Fault Filtering
Three filtering types are available. The recoverable faults can use all three filters independently or various filters
combination. The non-recoverable fault can use the input filtering method only.
The filter type or filter combination must be decided by the application.
16.4.4.1 Input Filtering

By default, the event detection is asynchronous. When the event occurs, the fault system will immediately and
asynchronously performs the selected fault action on the compare channel output, including system power modes where
the clock is not available. To avoid false fault detection on external events (e.g. a glitch on I/O port) the digital filter can be
enabled in the corresponding event channel. In this case, the event detection and routing will be synchronous, and the
event action will be delayed between two and three peripheral clock cycles, plus the selected digital filter coefficient.
For details on digital filter coefficient, refer to DIGFILT description in “CHnCTRL – Event Channel n Control Register” on
page 90.
16.4.4.2 Fault Blanking

Fault blanking (BLANK) provides a way to suppress fault inputs during the beginning of the active time of the waveform
output. Using this method, faults can be triggered only after a configured time, and will prevent false fault triggering
during commutation. The fault blanking time is set in DTLS and DTHS registers in waveform extension unit (WeX). The
registers values define the number of peripheral clock cycles where the fault input is inhibited. The blanking always starts
from the beginning of the cycle. As shown in Figure 16-2, the compare output value can be kept inactive until the end of
the cycle, or resume the standard operation when the fault condition is no longer present.
DTLS register configures the blanking time of compare channel A from each TC4 and TC5. Both compare channels A will
have the same blanking time. For details on DTLS register, refer to “DTLS – Dead-Time Low Side Register” on page 203.
DTHS register configures the blanking time of compare channel B from each TC4 and TC5. Both compare channels B
will have the same blanking time. For details on DTHS register, refer to “DTHS – Dead-Time High Side Register” on page
203.
Figure 16-2. Waveform Generation with Blanking Enabled
0$;
XSGDWH
723
PDWFK
&17 &&$
%27720
)DXOW,QSXW$
'7/6 '7/6!
:*2XWSXW$
.HHS .HHS 1R.HHS
As example, the maximum blanking time is:

 256 / (32 ×106s) = 8µs when 32MHz peripheral clock frequency
 256 / (106s) = 256µs when 1MHz peripheral clock frequency
16.4.4.3 Fault Input Qualification

If the fault input qualification (QUAL) is enabled, the fault A and B will trigger fault actions if the corresponding compare
channel output has an active level, as shown in Figure 16-3 on page 212 and Figure 16-4 on page 212.
XMEGA E MANUAL 211

Figure 16-3. Fault Input Qualification in RAMP1 Mode
MAX
"update"
TOP
"match"
CNT CCA
CCB
BOTTOM
Fault A Input Qual - -  - -  - 

x x x x x x x x x
Fault Input A
Fault B Input Qual -  - - -  - -

x x x x x x x x x x x x x x x x x x x
Fault Input B
Figure 16-4. Fault Input Qualification in RAMP2 Mode with Inverted Polarity
Cycle A B A B
MAX
"update"
TOP
"match"
CNT CCA
CCB
BOTTOM
Fault A Input Qual -  -  - 

x x x x x x x x x x x x
Fault Input A
Fault B Input Qual -  -  -

x x x x x x x x x x x x x x x
Fault Input B
16.4.5 Fault Actions

Different fault actions can be configured individually for fault A and fault B. Most fault actions are not mutually exclusive;
hence two or more actions can be enabled at the same time to achieve a result that is a combination of fault actions.
16.4.5.1 Keep Action

When the keep action (KEEP) is enabled, the output will be clamped to its inactive value when the fault condition is
present. The clamp will be released on the start of the first cycle after the fault condition is no longer present.
Figure 16-5 on page 213 shows compare channel A output when keep action and fault input qualification are enabled for
fault A.
XMEGA E MANUAL 212

Figure 16-5. Waveform Generation with Fault Input Qualification and Keep Action
MAX
"update"
TOP
"match"
CNT CCA
BOTTOM
Fault A Input Qual - -  - -  - 

x x x x x x x
Fault Input A
NO
WG Output A KEEP
KEEP
16.4.5.2 Restart Action

When restart action (RESTART) is enabled, the timer/counter will be restarted when a fault condition is present. The on-
going cycle is stopped and the timer/counter starts a new cycle, as shown in Figure 16-6. When the new cycle starts, the
compare outputs will be clamped to inactive level as long as the fault condition is present.
Figure 16-6. Waveform Generation with Restart Action in RAMP1 Mode
MAX
"update"
TOP
"match"
CCA
CNT
CCB
BOTTOM
Restart Restart
Fault Input A
WG Output A
WG Output B
Note that in RAMP2 mode of operation, when a new timer/counter cycle starts, the cycle index will change automatically,
as shown in Figure 16-7 on page 214. Fault A and fault B are qualified only during the cycle A and cycle B respectively,
i.e. the compare channel outputs are not forced to inactive level as long as the fault condition is present in cycle B or
cycle A respectively.
XMEGA E MANUAL 213

Figure 16-7. Waveform Generation with Restart Action in RAMP2 Mode
Cycle A B A B
"update"
Period (T) CCx=BOT CCx=TOP "match"
MAX
TOP
CNT
CCA/CCB
BOTTOM
No fault A action
in cycle B Restart
Fault Input A
WG Output A
WG Output B
The Control logic of the restart command is shown in Figure 16-8 below.
Figure 16-8. Control Logic of Restart Command
16.4.5.3 Capture Action

When capture action (CAPT) is enabled, the fault can be time stamped assuming a timer/counter capture channel is
enabled and the event action selection is set to fault capture (FAULTx). For details on event actions, refer to “CTRLD –
Control Register D” on page 176.
Figure 16-8 and Figure 16-9 on page 215 show the control logic of the Capture command.
XMEGA E MANUAL 214

Figure 16-9. Control Logic of the Capture Command IN FMODE1
Figure 16-10.Control Logic of the Capture Command in FMODE2
16.4.5.4 Hardware Halt Action

When hardware halt action (HWHALT) is enabled, the timer/counter is halted and the cycle is extended as long as the
fault is present. Figure 16-11 shows an example where keep and hardware halt actions are enabled for fault A. The
compare channel output A is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes
the counting operation as soon as the fault condition is no longer present.
XMEGA E MANUAL 215

Figure 16-11.Waveform Generation with Hardware Halt, Fault Input Qualification, and Keep Action
MAX
"update"
TOP
"match"
CNT CCA
HALT
BOTTOM
Resume
Fault A Input Qual - -  - - -

x x x
Fault Input A
WG Output A KEEP
If the restart action is enabled, the timer/counter is halted as long as the fault condition is present and restarted when the
fault condition is no longer present, as shown in Figure 16-12 on page 216. The compare channel output A is clamped to
inactive level as long as the timer/counter is halted. Note that in RAMP2 mode of operation, when a new timer/counter
cycle starts, the cycle index will change automatically.
Figure 16-12.Waveform Generation with Hardware Halt and Restart Action
MAX
"update"
TOP
"match"
CCA
CNT
HALT
BOTTOM
Restart Restart
Fault Input A
WG Output A
16.4.5.5 Software Halt Action

The software halt action (SWHALT) is similar to hardware halt action with one exception. To restart the timer/counter, the
fault condition is no longer present and the corresponding HALTxCLR bit in “CTRLGCLR – Control Register G Clear” on
page 222 must be set, as shown in Figure 16-13.
XMEGA E MANUAL 216

Figure 16-13.Waveform Generation with Software Halt, Fault Input Qualification, and Restart and Keep Actions
MAX
"update"
TOP
"match"
CNT CCA
HALT
BOTTOM
Restart Restart
Fault A Input Qual - -   - -

x x
Fault Input A
Software Clear
NO
WG Output A KEEP
KEEP
16.4.5.6 Non-recoverable Fault Action

The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed in FUSEBYTE6, as
described in section “FUSEBYTE6 – Fuse Byte 6” on page 33.
If the FUSE configuration is set, the enabled compare channel output will be forced as long as the non-recoverable fault
is present. When the fault condition is no longer present, timer/counter restarts when the STATEECLR bit in
“CTRLGCLR – Control Register G Clear” on page 222 is set. To restart the timer/counter from the beginning of a new
cycle, the restart command in “CTRLGCLR/CTRLGSET – Control Register G Clear/Set” on page 179 must be written
before writing the STATEECLR bit.
16.4.6 Interrupts and Events

If SOFTA bit in “CTRLB – Control Register B” on page 219 is set, a fault A detection will set the FAULTA flag in
“CTRLGCLR – Control Register G Clear” on page 222 and the error interrupt flag in “ INTFLAGS – Interrupt Flags
Register” on page 180. If enabled, the optional timer/counter error interrupt is generated.
If SOFTB bit in “CTRLD – Control Register D” on page 220 is set, a fault B detection will set the FAULTB flag in
“CTRLGCLR – Control Register G Clear” on page 222 and the error interrupt flag in “ INTFLAGS – Interrupt Flags
Register” on page 180. If enabled, the optional timer/counter error interrupt is generated.
A fault E detection will set the FAULTE flag in “CTRLGCLR – Control Register G Clear” on page 222 and the error
interrupt flag in “ INTFLAGS – Interrupt Flags Register” on page 180. If enabled, the optional timer/counter error interrupt
is generated.
The fault extension is not source of events to the event system. The fault extension uses events as described in section
“Input Selection” on page 210.
16.4.7 Change Protection

To avoid unintentional configuration changes, the CTRLA register in the FAULT can be protected by writing the
corresponding lock bit in the fault extension lock register. For more details, refer to“I/O Memory Protection” on page 25
and “FAULTLOCK – Fault Extension Lock Register” on page 45.
When the lock bit is set, CTRLA register cannot be changed.
XMEGA E MANUAL 217

Bit 7 6 5 4 3 2 1 0
+0x00 RAMP[1:0] FDDBD PORTCTRL FUSE FILTERE SRCE[1:0]
 Bit 7:6 – RAMP[1:0]: Ramp Mode Selection

These bits select the ramp mode (RAMP) according to Table 16-1, and define in which cycle fault A and B will trig-
ger fault actions.
Table 16-1. RAMP Mode Selection
RAMP[1:0] Group configuration Description

Default mode:
00 RAMP1 - Fault A triggers fault action in any cycle
- Fault B triggers fault action in any cycle
01 Reserved
Cycle A and cycle B are interleaved:

10 RAMP2 - Fault A triggers fault action in cycle A
- Fault B triggers fault action in cycle B
11 Reserved
 Bit 5 – FDDBD: Fault Detection on Debug Break Detection

By default, the on-chip debug interface fault protection is enabled and a request from the debug interface will trig-
ger an non-recoverable fault. When this bit is set, the on-chip debug interface fault protection is disabled and a
break request will not trigger any fault.
 Bit 4 – PORTCTRL: Port Control Mode
When this bit is set, an enabled compare channel will force the output configuration on the corresponding I/O pin.
This bit has no effect if the channel is disabled or configured in capture mode of operation.
 Bit 3 – FUSE: Fuse State
When this bit is set, the fuse value programmed in FUSEBYTE6 is forced on enabled compare channels outputs
when a non-recoverable fault condition is present. Note that when FDACTx fuses are programmed, the same fuse
value is applied during the system reset sequence. For details on fuse settings, refer to “FUSEBYTE6 – Fuse Byte
6” on page 33.
 Bit 2 – FILTERE: Fault E Digital Filter Selection
Setting this bit enables the selected event channel digital filter output as event source for fault E. For details refer
to “Input Filtering” on page 211.
 Bit 1:0 – SRCE[1:0]: Fault E Input Selection
These bits select the event channel input for fault E input, as shown in Table 16-2 on page 219. For details on
event channel selection, refer to EVSEL description in “CTRLD – Control Register D” on page 176.
XMEGA E MANUAL 218

Table 16-2. Fault E Input Selection
SRCE[1:0] Group configuration Description
00 DISABLE Fault protection disabled
01 CHn Event channel n
10 CHn1 Event channel n+1
11 CHn2 Event channel n+2
Bit 7 6 5 4 3 2 1 0
+0x01 SOFTA HALTA[1:0] RESTARTA KEEPA – SRCA[1:0]
Read/Write R/W R/W R/W R/W R/W R R/W R/W
 Bit 7 – SOFTA: Fault A Software Mode

When this bit is set, a fault A detection will set the timer/counter error interrupt flag, as described in section “Inter-
rupts and Events” on page 217.
 Bit 6:5 – HALTA[1:0]: Fault A Halt Action
These bits select the halt action for fault A, as defined in Table 16-3.
Table 16-3. Fault A Halt Action Selection
HALTA[1:0] Group configuration Description
00 DISABLE Halt action disabled
01 HW Hardware halt action
10 SW Software halt action
11 – Reserved
 Bit 4 – RESTARTA: Fault A Restart Action

Setting this bit enables the restart action for the fault A.
 Bit 3 – KEEPA: Fault A Keep Action
Setting this bit enables keep action for the fault A.
This bit is unused and reserved for future use. For compatibility with future devices, always write these bits to zero
 Bit 1:0 – SRCA[1:0]: Fault A Source Selection
These bits select the event channel source for the fault A, as defined in Table 16-4 on page 220. For details on
event channel selection, refer to EVSEL description in “CTRLD – Control Register D” on page 176.
XMEGA E MANUAL 219

Table 16-4. Fault A Source Selection
SRCA[1:0] Group configuration Description
00 DISABLE Fault disabled
10 CHn1 Event channel (n+1)
Fault A input source is linked to the fault B state from the end of the
previous cycle. If keep action is disabled, the fault A duration is one
11 LINK
peripheral clock cycle. Alternatively, if the keep action is enabled, the fault
A duration is one complete timer/counter cycle.
Bit 7 6 5 4 3 2 1 0
+0x02 – – CAPTA – – FILTERA BLANKA QUALA
Read/Write R R R/W R R R/W R/W R/W

 Bit 5 – CAPTA: Fault A Capture
When this bit is set, the fault A detection triggers a timer/counter input capture operation. For details on event acti-
ons and event selection, refer to “CTRLD – Control Register D” on page 176.
 Bit 2 – FILTERA: Fault A Digital Filter Selection
Setting this bit enables the selected event channel digital filter output as event source for fault A. For details refer
 Bit 1 – BLANKA: Fault A Blanking
Setting this bit enables input blanking for fault A. For details, refer to “Fault Blanking” on page 211.
 Bit 0 – QUALA: Fault A Qualification
Setting this bit enables the fault A input qualification. For details, refer to“Fault Input Qualification” on page 211.
Bit 7 6 5 4 3 2 1 0
+0x03 SOFTB HALTB[1:0] RESTARTB KEEPB – SRCB[1:0]
Read/Write R/W R/W R/W R/W R/W R R/W R/W
 Bit 7 – SOFTB: Fault B Software Mode

When this bit is set, a fault B detection will set the timer/counter error interrupt flag, as described in section “Inter-
rupts and Events” on page 217.
 Bit 6:5 – HALTB [1:0]: Fault B Halt Action
These bits select the halt action for fault B as defined in Table 16-5 on page 221.
XMEGA E MANUAL 220

Table 16-5. Fault B Halt Action Selection
HALTB[1:0] Group configuration Description
00 DISABLE Halt action disabled
01 HW Hardware halt action
10 SW Software halt action
11 – Reserved
 Bit 4 – RESTARTB: Fault B Restart Action

Setting this bit enables the restart action for fault B.
 Bit 3 – KEEPB: Fault B Keep Action
Setting this bit enables the keep action for fault B.
This bit is unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written
 Bit 1:0 – SRCB[1:0]: Fault B Source Selection
These bits select the event channel source for fault B, as defined in Table 16-6. For details on event channel
selection, refer to EVSEL description in“CTRLD – Control Register D” on page 176.
Table 16-6. Fault B Source Selection
SRCB[1:0] Group configuration Description
00 DISABLE Fault disabled
10 CHn1 Event channel (n+1)
Fault B input source is linked to the fault A state from the end of the previous
cycle. If keep action is disabled, the fault B duration is one peripheral clock
11 LINK
cycle. Alternatively, if the keep action is enabled, the fault B duration is one
complete timer/counter cycle.
Bit 7 6 5 4 3 2 1 0
+0x04 – – CAPTB – – FILTERB BLANKB QUALB
Read/Write R R R/W R R R/W R/W R/W

 Bit 5 – CAPTB: Fault B Capture
When this bit is set, the fault B detection triggers a timer/counter input capture operation. For details on event acti-
ons and event selection, refer to “CTRLD – Control Register D” on page 176.
XMEGA E MANUAL 221

 Bit 2 – FILTERB: Fault B Digital Filter Selection
Setting this bit enables the selected event channel digital filter output as event source for fault B. For details, refer
 Bit 1 – BLANKB: Fault B Blanking
Setting this bit enables input blanking for fault B. For details, refer to “Fault Blanking” on page 211.
 Bit 0 – QUALB: Fault B Qualification
Setting this bit enables the fault B input qualification. For details, refer to“Fault Input Qualification” on page 211.
Bit 7 6 5 4 3 2 1 0
+0x05 STATEB STATEA STATEE – IDX FAULTBIN FAULTAIN FAULTEIN
 Bit 7 – STATEB: Fault B State

This bit is set by hardware when fault B condition is present. The bit is cleared by hardware when the fault A action
is completed.
 Bit 6 – STATEA: Fault A State
This bit is set by hardware when fault A condition is present. The bit is cleared by hardware when the fault B action
is completed.
 Bit 5 – STATEE: Fault E State
This bit is set by hardware when fault E condition is present. The bit is cleared by hardware when the fault E action
is completed.
 Bit 3 – IDX: Channel Index Flag
In RAMP2 mode of operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1 mode of
operation, the bit is always read zero. For details on ramp modes, refer to section “Ramp Modes” on page 210.
 Bit 2 – FAULTBIN: Fault B Flag
This flag is set by hardware as long as the fault B condition is present. The flag is cleared by hardware when the
fault B condition is no longer present.
 Bit 1 – FAULTAIN: Fault A Flag
This flag is set by hardware as long as the fault A condition is present. The flag is cleared by hardware when the
fault A condition is no longer present.
 Bit 0 – FAULTEIN: Fault E Flag
This flag is set by hardware when fault E condition is present. The flag is cleared by hardware when the fault E
condition is no longer present.
16.5.7 CTRLGCLR – Control Register G Clear
Bit 7 6 5 4 3 2 1 0
+0x06 HALTBCLR HALTACLR STATEECLR – – FAULTB FAULTA FAULTE
Read/Write R/W R/W R/W R R R/W R/W R/W
 Bit 7 – HALTBCLR: State B Clear

Setting this bit will clear the STATEB bit in STATUS register when FAULTBIN is cleared. If software halt command
is enabled, the timer/counter internal halt command is released.
XMEGA E MANUAL 222

 Bit 6 – HALTACLR: State A Clear
Setting this bit will clear the STATEA bit in STATUS register when FAULTAIN is cleared. If software halt command
is enabled, the timer/counter internal halt command is released.
 Bit 5 – STATEECLR: State E Clear
Setting this bit will clear the STATEE bit in STATUS register when FAULTEIN is cleared. The timer/counter will
restart from the last CNT value. To restart the timer/counter from BOTTOM, the timer/counter restart command
must be executed before setting the STATEECLR bit. For details on timer/counter commands, refer to command
description in“CTRLGCLR/CTRLGSET – Control Register G Clear/Set” on page 189.
 Bit 2 – FAULTB: Fault B Flag
This bit is set by hardware when fault B input occurs and if SOFTB bit is set. The flag is cleared by writing a one to
its bit location.
 Bit 1 – FAULTA: Fault A Flag
This bit is set by hardware when fault A input occurs and if SOFTA bit is set. The flag is cleared by writing a one to
its bit location.
 Bit 0 – FAULTE: Fault E Flag
This bit is set by hardware when fault E input occurs. The flag is cleared by writing a one to its bit location.
16.5.8 CTRLGSET – Control Register G Set
Bit 7 6 5 4 3 2 1 0
+0x07 FAULTBSW FAULTASW FAULTESW IDXCMD[1:0] – – –
Read/Write R/W R/W R/W R/W R/W R R R
 Bit 7 – FAULTBSW: Software Fault B

Setting this bit will trigger and force the fault B action by software. The bit and corresponding fault input are auto-
matically cleared by hardware in the next peripheral clock cycle (clkPER).
 Bit 6 – FAULTASW: Software Fault A
Setting this bit will trigger and force the fault A action by software. The bit and corresponding fault input are auto-
 Bit 5 – FAULTESW: Software Fault E
Setting this bit will trigger and force the fault E action by software. The bit and corresponding fault input are auto-
 Bit 4:3 – IDXCMD[1:0]: Cycle Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 mode according to Table 16-7. On
timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated and the
IDXCMD command is cleared.
Table 16-7. Index Command Selection
IDXCMD[1:0] Group configuration Description
00 DISABLE Command disabled: IDX toggles between cycles A and B
01 SET Set IDX: cycle B will be forced in the next cycle
10 CLEAR Clear IDX: cycle A will be forced in next cycle
11 HOLD Hold IDX: the next cycle will be the same as the current cycle.
XMEGA E MANUAL 223


+0x00 CTRLA RAMP[1:0] FDDBD PORTCTRL FUSE FILTERE SRCE[1:0] 218
+0x01 CTRLB SOFTA HALTA[1:0] RESTARTA KEEPA - SRCA[1:0] 219
+0x02 CTRLC - - CAPTA - - FILTERA BLANKA QUALA 220
+0x03 CTRLD SOFTB HALTB[1:0] RESTARTB KEEPB - SRCB[1:0] 220
+0x04 CTRLE - - CAPTB - - FILTERB BLANKB QUALB 221
+0x05 STATUS STATEB STATEA STATEE - IDX FAULTBIN FAULTAIN FAULTEIN 222
+0x06 CTRLGCLR HALTBCLR HALTACLR STATEECLR - - FAULTB FAULTA FAULTE 222
+0x07 CTRLGSET FAULTBSW FAULTASW FAULTESW IDXCMD[1:0] - - - 223
XMEGA E MANUAL 224

17. RTC – Real Time Counter
17.1 Features
 Selectable clock source
 32.768kHz external crystal
 External clock
 32.768kHz internal oscillator
 32kHz internal ULP oscillator
 Programmable 10-bit clock prescaling
 One Compare register
 One Period register
 Clear counter on period overflow
 Optional interrupt/event on overflow and compare match
 Correction for external crystal selection
17.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The RTC clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration
most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution
higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the
32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5μs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum time-out period is more than 18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
The RTC also supports correction when operated using external crystal selection. An externally calibrated value will be
used for correction. The RTC can be calibrated by software to an accuracy of ±0.5PPM relative to a minimum reference
clock of 2MHz. The RTC correction operation will either speed up (by skipping count) or slow down (adding extra cycles)
the prescaler to account for the clock error.
XMEGA E MANUAL 225

Figure 17-1. Real-time Counter Overview
External Clock
TOSC1
32.768 kHz Crystal
TOSC2 Osc
32.768 kHz Int. Osc
32 kHz int ULP
DIV32
DIV32
(DIV32)
RTCSRC
CALIB PER
clkRTC
TOP/
=
Overflow
Correction Hold Count 10-bit
Counter
CNT
prescaler
”match”/
=
Compare
COMP
17.3 Clock Domains

The RTC is asynchronous, operating from a different clock source independently of the main system clock and its
derivative clocks, such as the peripheral clock. For control and count register updates, it will take a number of RTC clock
and/or peripheral clock cycles before an updated register value is available in a register or until a configuration change
has effect on the RTC. This synchronization time is described for each register.

The RTC can generate both interrupts and events. The RTC will give a compare interrupt and/or event at the first count
after the counter value equals the Compare register value. The RTC will give an overflow interrupt request and/or event
at the first count after the counter value equals the Period register value. The overflow will also reset the counter value to
zero.
Due to the asynchronous clock domain, events will be generated only for every third overflow or compare match if the
period register is zero. If the period register is one, events will be generated only for every second overflow or compare
match. When the period register is equal to or above two, events will trigger at every overflow or compare match, just as
the interrupt request.
17.5 Correction
The RTC can do internal correction on the RTC crystal clock by taking the PPM error value from the CALIB Register. The
CALIB register will be written by software after external calibration or temperature corrections. Correction is done within
an interval of approximately 1 million cycles. The correction operation is performed as a single cycle operation – adding
or removing one cycle, depending on the nature of error. These single cycle operations will be performed repeatedly the
error number of times (ERROR[6:0] - CALIB Register) spread through out the 1 million cycle correction interval. The
correction spread over this correction interval is based on the error value. The final correction of the clock will be reflected
in the RTC count value available through the CNTL and CNTH registers. When the required correction is speeding up the
XMEGA E MANUAL 226

clock by skipping cycles, it is required to run the prescaler at a minimum setting of DIV2 (RTC clock/2). When the system
correction is disabled by software, the correction is disabled internally when the ongoing one million correction cycle is
completed.
Figure 17-2. Real-time Counter Clock/count Correction
PRESCALER=DIV8
CORRECT=0
Count enable
PRESCALER=DIV8
CORRECT=4
Count enable
Adjusting 4 times within

1 Million clkRTC cycle
PRESCALER=DIV8
CORRECT=-4
Count enable
XMEGA E MANUAL 227

Bit 7 6 5 4 3 2 1 0
+0x00 – – – – CORREN PRESCALER[2:0]

 Bit 3 – CORREN: Correction Enable
Setting this bit enables the correction process. When this bit is written low, the correction is disabled when the
ongoing correction cycle is completed. Refer to CALIB Register for the correction value and type.
 Bits 2:0 – PRESCALER[2:0]: RTC Clock Prescaling Factor
These bits define the prescaling factor for the RTC clock according to Table 17-1 on page 228.
Table 17-1. Real Time Counter Clock Prescaling Factor
PRESCALER[2:0] Group configuration RTC clock prescaling
000 OFF No clock source, RTC stopped
001 DIV1 RTC clock / 1 (No prescaling)
010 DIV2 RTC clock / 2
111 DIV1024 RTC clock / 1024
17.6.2 STATUS - Status Register
Bit 7 6 5 4 3 2 1 0
+0x01 – – – – – – – SYNCBUSY

 Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set when the CNT, CTRL, PER, or COMP register is busy synchronizing between the RTC clock and
system clock domains. This flag is automatically cleared when the synchronization is complete.
XMEGA E MANUAL 228

17.6.3 INTCTRL - Interrupt Control Register
Bit 7 6 5 4 3 2 1 0
+0x02 – – – – COMPINTLVL[1:0] OVFINTLVL[1:0]

 Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Enable
These bits enable the RTC compare match interrupt and select the interrupt level, as described in “PMIC – Inter-
rupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will trigger when
COMPIF in the INTFLAGS register is set.
 Bits 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Enable
These bits enable the RTC overflow interrupt and select the interrupt level, as described in “PMIC – Interrupts and
Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will trigger when OVFIF in the
INTFLAGS register is set.
Bit 7 6 5 4 3 2 1 0
+0x03 – – – – – – COMPIF OVFIF

zero when this register is written
 Bit 1 – COMPIF: RTC Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. It is cleared automatically when the RTC
compare match interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
 Bit 0 – OVFIF: RTC Overflow Match Interrupt Flag
This flag is set on the next count after an overflow condition occurs. It is cleared automatically when the RTC over-
flow interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
17.6.5 TEMP - Temporary Register
Bit 7 6 5 4 3 2 1 0
+0x04 TEMP[7:0]
 Bits 7:0 – TEMP[7:0]: Temporary Bits

This register is used for 16-bit access to the counter value, compare value, and TOP value registers. The low byte
of the 16-bit register is stored here when it is written by the CPU. The high byte of the 16-bit register is stored when
the low byte is read by the CPU.
XMEGA E MANUAL 229

17.6.6 CALIB – Calibration Register
This register stores the error value and the type of correction to be done. This register is written by software with any
error value based on external calibration and/or temperature correction/s.
Bit 7 6 5 4 3 2 1 0
+0x06 SIGN ERROR[6:0]
 Bit 7 – SIGN: Correction Sign

This bit indicates the direction of correction.
If this bit is LOW then the RTC counter will be slowed down by adding clocks.
If this bit is HIGH, then the RTC counter will be speeded up by removing clocks. For this setting it is required to set
the prescaler to minimum setting of DIV2 (RTC clock/2).
 Bit 6:0 – ERROR[6:0]: Error Value
These bits hold the error value for correction operation.
17.6.7 CNTL – Count Register Low

The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT counts positive clock edges on the prescaled
RTC clock. Reading and writing 16-bit values requires special attention.
Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles
from updating the register until this has an effect. Application software needs to check that the SYNCBUSY flag in the
“STATUS - Status Register” on page 228 is cleared before writing to this register.
Bit 7 6 5 4 3 2 1 0
+0x08 CNT[7:0]
 Bits 7:0 – CNT[7:0]: Counter Value Low Byte

These bits hold the LSB of the 16-bit Real Time Counter value.
17.6.8 CNTH – Count Register High
Bit 7 6 5 4 3 2 1 0
+0x09 CNT[15:8]
 Bits 7:0 – CNT[15:8]: Counter Value High Byte

These bits hold the MSB of the 16-bit Real Time Counter value.
XMEGA E MANUAL 230

17.6.9 PERL – Period Register Low
The PERH and PERL register pair represents the 16-bit value, PER. PER is constantly compared with the counter value
(CNT). A match will set OVFIF in the INTFLAGS register and clear CNT. Reading and writing 16-bit values requires
special attention.
Bit 7 6 5 4 3 2 1 0
+0x0A PER[7:0]
 Bits 7:0 – PER[7:0]: Period Low Byte

These bits hold the LSB of the 16-bit RTC TOP value.
17.6.10 PERH - Period Register High
Bit 7 6 5 4 3 2 1 0
+0x0B PER[15:8]
 Bits 7:0 – PER[15:8]: Period High Byte

These bits hold the MSB of the 16-bit RTC TOP value.
17.6.11 COMPL – Compare Register Low

The COMPH and COMPL register pair represent the 16-bit value, COMP. COMP is constantly compared with the
counter value (CNT). A compare match will set COMPIF in the INTFLAGS register. Reading and writing 16-bit values
requires special attention.
If the COMP value is higher than the PER value, no RTC compare match interrupt requests or events will ever be
generated.
Bit 7 6 5 4 3 2 1 0
+0x0C COMP[7:0]
 Bits 7:0 – COMP[7:0]: Compare Value Low Byte

These bits hold the LSB of the 16-bit RTC compare value.
XMEGA E MANUAL 231

17.6.12 COMPH – Compare Register High
Bit 7 6 5 4 3 2 1 0
+0x0D COMP[15:8]
 Bits 7:0 – COMP[15:8]: Compare Value High Byte

These bits hold the MSB of the 16-bit RTC compare value.
XMEGA E MANUAL 232

0x00 CTRL – – – – CORREN PRESCALER[2:0] 228

0x01 STATUS – – – – – – – SYNCBUSY 228
0x02 INTCTRL – – – – COMPINTLVL[1:0] OVFINTLVL[1:0] 229
0x03 INTFLAGS – – – – – – COMP OVFIF 229
0X04 TEMP TEMP[7:0] 229
0X05 Reserved – – – – – – – –
0X06 CALIB SIGN ERROR[6:0] 230
0X07 Reserved – – – – – – – –
0x08 CNTL CNT[7:0] 230
0x09 CNTH CNT[15:8] 230
0x0A PERL PER[7:0] 231
0x0B PERH PER[15:8] 231
0x0C COMPL COMP[7:0] 231
0x0D COMPH COMP[15:8] 232
Table 17-2. RTC Interrupt Vectors and their Word Offset
0x00 OVF_vect Real-time counter overflow interrupt vector
0x02 COMP_vect Real-time counter compare match interrupt vector
XMEGA E MANUAL 233

18. TWI – Two-Wire Interface
18.1 Features
 Bidirectional, two-wire communication interface
 Phillips I2C compatible
 System Management Bus (SMBus) compatible
 Bus master and slave operation supported
 Slave operation
 Single bus master operation
 Bus master in multi-master bus environment
 Multi-master arbitration
 Bridge mode with independent and simultaneous master and slave operation
 Flexible slave address match functions
 7-bit and general call address recognition in hardware
 10-bit addressing supported
 Address mask register for dual address match or address range masking
 Optional software address recognition for unlimited number of addresses
 Slave can operate in all sleep modes, including power-down
 Slave address match can wake device from all sleep modes
 Up to 1MHz bus frequency support
 Slew-rate limited output drivers
 Input filter for bus noise and spike suppression
 Support arbitration between start/repeated start and data bit (SMBus)
 Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
 Supports SMBUS Layer 1 timeouts
 Configurable timeout values
 Independent timeout counters in master and slave (Bridge mode support)
18.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. All 100kHz, 400kHz, and 1MHz bus frequencies are supported. Quick
command and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
XMEGA E MANUAL 234

It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
It is also possible to enable the bridge mode. In this case, the slave I/O pins are selected from an alternative port,
enabling independent and simultaneous master and slave operation.
18.3 General TWI Bus Concepts

The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial clock line (SCL) and a serial
data line (SDA). The two lines are open-collector lines (wired-AND), and pull-up resistors (Rp) are the only external
components needed to drive the bus. The pull-up resistors provide a high level on the lines when none of the connected
devices are driving the bus.
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus. A device connected to
the bus can be a master or slave, where the master controls the bus and all communication.
Figure 18-1 on page 235 illustrates the TWI bus topology.
Figure 18-1. TWI Bus Topology
VCC
RP RP TWI TWI TWI

DEVICE #1 DEVICE #2 DEVICE #N
RS RS RS RS RS RS
SDA
SCL
Note: RS is optional
An unique address is assigned to all slave devices connected to the bus, and the master will use this to address a slave
and initiate a data transaction.
Several masters can be connected to the same bus, called a multi-master environment. An arbitration mechanism is
provided for resolving bus ownership among masters, since only one master device may own the bus at any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by responding to more than
one address.
A master indicates the start of a transaction by issuing a START condition (S) on the bus. An address packet with a slave
address (ADDRESS) and an indication whether the master wishes to read or write data (R/W) are then sent. After all
data packets (DATA) are transferred, the master issues a STOP condition (P) on the bus to end the transaction. The
receiver must acknowledge (A) or not-acknowledge (A) each byte received.
Figure 18-2 on page 236 shows a TWI transaction.
XMEGA E MANUAL 235

Figure 18-2. Basic TWI Transaction Diagram Topology for a 7-bit Address Bus
SDA
SCL 6 ... 0 7 ... 0 7 ... 0
S ADDRESS R/W ACK DATA ACK DATA ACK/NACK P
S ADDRESS R/W A DATA A DATA A/A P
Direction
Address Packet Data Packet #0 Data Packet #1
Transaction
The master provides data on the bus

The master or slave can provide data on the bus
The slave provides data on the bus
The master provides the clock signal for the transaction, but a device connected to the bus is allowed to stretch the low-
level period of the clock to decrease the clock speed.
18.3.1 Electrical Characteristics

The TWI module in XMEGA devices follows the electrical specifications and timing of I2C bus and SMBus. These
specifications are not 100% compliant, and so to ensure correct behavior, the inactive bus timeout period should be set
in TWI master mode. Refer to “TWI Master Operation” on page 241 for more details.
18.3.2 START and STOP Conditions

Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a transaction. The master
issues a START condition (S) by indicating a high-to-low transition on the SDA line while the SCL line is kept high. The
master completes the transaction by issuing a STOP condition (P), indicated by a low-to-high transition on the SDA line
while SCL line is kept high.
Figure 18-3. START and STOP Conditions
SDA
SCL
S P
START STOP
Condition Condition
Multiple START conditions can be issued during a single transaction. A START condition that is not directly following a
STOP condition is called a repeated START condition (Sr).
18.3.3 Bit Transfer

As illustrated by Figure 18-4, a bit transferred on the SDA line must be stable for the entire high period of the SCL line.
Consequently the SDA value can only be changed during the low period of the clock. This is ensured in hardware by the
TWI module.
XMEGA E MANUAL 236

Figure 18-4. Data Validity
SDA
SCL
DATA Change
Valid Allowed
Combining bit transfers results in the formation of address and data packets. These packets consist of eight data bits
(one byte) with the most-significant bit transferred first, plus a single-bit not-acknowledge (NACK) or acknowledge (ACK)
response. The addressed device signals ACK by pulling the SCL line low during the ninth clock cycle, and signals NACK
by leaving the line SCL high.
18.3.4 Address Packet

After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is always transmitted by the
master. A slave recognizing its address will ACK the address by pulling the data line low for the next SCL cycle, while all
other slaves should keep the TWI lines released and wait for the next START and address. The address, R/W bit, and
acknowledge bit combined is the address packet. Only one address packet for each START condition is allowed, also
when 10-bit addressing is used.
The R/W bit specifies the direction of the transaction. If the R/W bit is low, it indicates a master write transaction, and the
master will transmit its data after the slave has acknowledged its address. If the R/W bit is high, it indicates a master read
transaction, and the slave will transmit its data after acknowledging its address.
18.3.5 Data Packet

An address packet is followed by one or more data packets. All data packets are nine bits long, consisting of one data
byte and an acknowledge bit. The direction bit in the previous address packet determines the direction in which the data
are transferred.
18.3.6 Transaction
A transaction is the complete transfer from a START to a STOP condition, including any repeated START conditions in
between. The TWI standard defines three fundamental transaction modes: Master write, master read, and a combined
transaction.
Figure 18-5 on page 237 illustrates the master write transaction. The master initiates the transaction by issuing a START
condition (S) followed by an address packet with the direction bit set to zero (ADDRESS+W).
Figure 18-5. Master Write Transaction
Transaction
Address Packet Data Packet
S ADDRESS W A DATA A DATA A/A P
N data packets
Assuming the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK or
NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a STOP
condition (P) directly after the address packet. There are no limitations to the number of data packets that can be
XMEGA E MANUAL 237

transferred. If the slave signals a NACK to the data, the master must assume that the slave cannot receive any more
data and terminate the transaction.
Figure 18-6 on page 238 illustrates the master read transaction. The master initiates the transaction by issuing a START
condition followed by an address packet with the direction bit set to one (ADDRESS+R). The addressed slave must
acknowledge the address for the master to be allowed to continue the transaction.
Figure 18-6. Master Read Transaction
Transaction
Address Packet Data Packet
S ADDRESS R A DATA A DATA A P
N data packets
Assuming the slave acknowledges the address, the master can start receiving data from the slave. There are no
limitations to the number of data packets that can be transferred. The slave transmits the data while the master signals
ACK or NACK after each data byte. The master terminates the transfer with a NACK before issuing a STOP condition.
Figure 18-7 illustrates a combined transaction. A combined transaction consists of several read and write transactions
separated by repeated START conditions (Sr).
Figure 18-7. Combined Transaction
Transaction
Address Packet #1 N Data Packets Address Packet #2 M Data Packets
S ADDRESS R/W A DATA A/A Sr ADDRESS R/W A DATA A/A P
Direction Direction
18.3.7 Clock and Clock Stretching

All devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock
frequency or to insert wait states while processing data. A device that needs to stretch the clock can do this by
holding/forcing the SCL line low after it detects a low level on the line.
Three types of clock stretching can be defined, as shown in Figure 18-8.
Figure 18-8. Clock Stretching (1)
SDA bit 7 bit 6 bit 0 ACK/NACK
SCL
S
Wakeup clock Periodic clock Random clock

stretching stretching stretching
Note: 1. Clock stretching is not supported by all I2C slaves and masters.
If a slave device is in sleep mode and a START condition is detected, the clock stretching normally works during the
wake-up period. For AVR XMEGA devices, the clock stretching will be either directly before or after the ACK/NACK bit,
as AVR XMEGA devices do not need to wake up for transactions that are not addressed to it.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This allows the slave
to run at a lower system clock frequency. However, the overall performance of the bus will be reduced accordingly. Both
XMEGA E MANUAL 238

the master and slave device can randomly stretch the clock on a byte level basis before and after the ACK/NACK bit.
This provides time to process incoming or prepare outgoing data, or perform other time-critical tasks.
In the case where the slave is stretching the clock, the master will be forced into a wait state until the slave is ready, and
vice versa.
18.3.8 Arbitration
A master can start a bus transaction only if it has detected that the bus is idle. As the TWI bus is a multi-master bus, it is
possible that two devices may initiate a transaction at the same time. This results in multiple masters owning the bus
simultaneously. This is solved using an arbitration scheme where the master loses control of the bus if it is not able to
transmit a high level on the SDA line. The masters who lose arbitration must then wait until the bus becomes idle (i.e.,
wait for a STOP condition) before attempting to reacquire bus ownership. Slave devices are not involved in the arbitration
procedure.
Figure 18-9. TWI Arbitration

DEVICE1 Loses arbitration
DEVICE1_SDA
DEVICE2_SDA
SDA
bit 7 bit 6 bit 5 bit 4
(wired-AND)
SCL
S
Figure 18-9 shows an example where two TWI masters are contending for bus ownership. Both devices are able to issue
a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is
transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data bit, or a repeated START
condition and a STOP condition are not allowed and will require special handling by software.
18.3.9 Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one master is trying to control the
SCL line at the same time. The algorithm is based on the same principles used for the clock stretching previously
described. Figure 18-10 shows an example where two masters are competing for control over the bus clock. The SCL
line is the wired-AND result of the two masters clock outputs.
XMEGA E MANUAL 239

Figure 18-10.Clock Synchronization
Low Period Wait High Period
Count State Count
DEVICE1_SCL
DEVICE2_SCL
SCL
(wired-AND)
A high-to-low transition on the SCL line will force the line low for all masters on the bus, and they will start timing their low
clock period. The timing length of the low clock period can vary among the masters. When a master (DEVICE1 in this
case) has completed its low period, it releases the SCL line. However, the SCL line will not go high until all masters have
released it. Consequently, the SCL line will be held low by the device with the longest low period (DEVICE2). Devices
with shorter low periods must insert a wait state until the clock is released. All masters start their high period when the
SCL line is released by all devices and has gone high. The device which first completes its high period (DEVICE1) forces
the clock line low, and the procedure is then repeated. The result is that the device with the shortest clock period
determines the high period, while the low period of the clock is determined by the device with the longest clock period.
18.4 TWI Bus State Logic

The bus state logic continuously monitors the activity on the TWI bus lines when the master is enabled. It continues to
operate in all sleep modes, including power-down.
The bus state logic includes START and STOP condition detectors, collision detection, inactive bus timeout detection,
and a bit counter. These are used to determine the bus state. Software can get the current bus state by reading the bus
state bits in the master status register. The bus state can be unknown, idle, busy, or owner, and is determined according
to the state diagram shown in Figure 18-11. The values of the bus state bits according to state are shown in binary in the
figure.
Figure 18-11.Bus State, State Diagram
RESET
UNKNOWN
(0b00)
P + Timeout
S
Sr
IDLE BUSY
(0b01) P + Timeout (0b11)
Command P
Arbitration
Write ADDRESS Lost
(S) OWNER
(0b10)
Write
ADDRESS(Sr)
XMEGA E MANUAL 240

After a system reset and/or TWI master enable, the bus state is unknown. The bus state machine can be forced to enter
idle by writing to the bus state bits accordingly. If no state is set by application software, the bus state will become idle
when the first STOP condition is detected. If the master inactive bus timeout is enabled, the bus state will change to idle
on the occurrence of a timeout. After a known bus state is established, only a system reset or disabling of the TWI master
will set the state to unknown.
When the bus is idle, it is ready for a new transaction. If a START condition generated externally is detected, the bus
becomes busy until a STOP condition is detected. The STOP condition will change the bus state to idle. If the master
inactive bus timeout is enabled, the bus state will change from busy to idle on the occurrence of a timeout.
If a START condition is generated internally while in idle state, the owner state is entered. If the complete transaction was
performed without interference, i.e., no collisions are detected, the master will issue a STOP condition and the bus state
will change back to idle. If a collision is detected, the arbitration is assumed lost and the bus state becomes busy until a
STOP condition is detected. A repeated START condition will only change the bus state if arbitration is lost during the
issuing of the repeated START. Arbitration during repeated START can be lost only if the arbitration has been ongoing
since the first START condition. This happens if two masters send the exact same ADDRESS+DATA before one of the
masters issues a repeated START (Sr).
18.5 TWI Master Operation

The TWI master is byte-oriented, with an optional interrupt after each byte. There are separate interrupts for master write
and master read. Interrupt flags can also be used for polled operation. There are dedicated status flags for indicating
ACK/NACK received, bus error, arbitration lost, clock hold, and bus state.
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data, and
will in most cases require software interaction. Figure 18-12 shows the TWI master operation. The diamond shaped
symbols (SW) indicate where software interaction is required. Clearing the interrupt flags releases the SCL line.
Figure 18-12.TWI Master Operation

APPLICATION MASTER WRITE INTERRUPT + HOLD
M1 M2 M3 M4
BUSY P IDLE S ADDRESS R/W BUSY SW BUSY M1
Wait for
SW
IDLE
R/W A SW P IDLE M2
W A SW Sr M3 BUSY M4
SW DATA A/A
SW Driver software
MASTER READ INTERRUPT + HOLD
The master provides data
on the bus
Slave provides data on

SW A BUSY M4
the bus
A/A P IDLE M2
Bus state
A/A Sr M3
Mn Diagram connections
A/A
R A DATA
The number of interrupts generated is kept to a minimum by automatic handling of most conditions. Quick command and
smart mode can be enabled to auto-trigger operations and reduce software complexity.
XMEGA E MANUAL 241

18.5.1 Transmitting Address Packets
After issuing a START condition, the master starts performing a bus transaction when the master address register is
written with the 7-bit slave address and direction bit. If the bus is busy, the TWI master will wait until the bus becomes idle
before issuing the START condition.
Depending on arbitration and the R/W direction bit, one of four distinct cases (M1 to M4) arises following the address
packet. The different cases must be handled in software.
18.5.1.1 Case M1: Arbitration Lost or Bus Error during Address Packet
If arbitration is lost during the sending of the address packet, the master write interrupt flag and arbitration lost flag are
both set. Serial data output to the SDA line is disabled, and the SCL line is released. The master is no longer allowed to
perform any operation on the bus until the bus state has changed back to idle.
A bus error will behave in the same way as an arbitration lost condition, but the error flag is set in addition to the write
interrupt and arbitration lost flags.
18.5.1.2 Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave
If no slave device responds to the address, the master write interrupt flag and the master received acknowledge flag are
set. The clock hold is active at this point, preventing further activity on the bus.
18.5.1.3 Case M3: Address Packet Transmit Complete - Direction Bit Cleared
If the master receives an ACK from the slave, the master write interrupt flag is set and the master received acknowledge
flag is cleared. The clock hold is active at this point, preventing further activity on the bus.
18.5.1.4 Case M4: Address Packet Transmit Complete - Direction Bit Set
If the master receives an ACK from the slave, the master proceeds to receive the next byte of data from the slave. When
the first data byte is received, the master read interrupt flag is set and the master received acknowledge flag is cleared.
The clock hold is active at this point, preventing further activity on the bus.
18.5.2 Transmitting Data Packets

Assuming case M3 above, the master can start transmitting data by writing to the master data register. If the transfer was
successful, the slave will signal with ACK. The master write interrupt flag is set, the master received acknowledge flag is
cleared, and the master can prepare new data to send. During data transfer, the master is continuously monitoring the
bus for collisions.
The received acknowledge flag must be checked by software for each data packet transmitted before the next data
packet can be transferred. The master is not allowed to continue transmitting data if the slave signals a NACK.
If a collision is detected and the master loses arbitration during transfer, the arbitration lost flag is set.
18.5.3 Receiving Data Packets

Assuming case M4 above, the master has already received one byte from the slave. The master read interrupt flag is set,
and the master must prepare to receive new data. The master must respond to each byte with ACK or NACK. Indicating
a NACK might not be successfully executed, as arbitration can be lost during the transmission. If a collision is detected,
the master loses arbitration and the arbitration lost flag is set.
18.6 TWI Slave Operation

The TWI slave is byte-oriented with optional interrupts after each byte. There are separate slave data and address/stop
interrupts. Interrupt flags can also be used for polled operation. There are dedicated status flags for indicating
ACK/NACK received, clock hold, collision, bus error, and read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond or handle data, and will in
most cases require software interaction. Figure 18-13. shows the TWI slave operation. The diamond shapes symbols
(SW) indicate where software interaction is required.
XMEGA E MANUAL 242

Figure 18-13.TWI Slave Operation
SLAVE ADDRESS INTERRUPT SLAVE DATA INTERRUPT
P S2
S1 S3 A S1 Sr S3
S2 S ADDRESS R SW A SW DATA A/A
P S2
A S1 Sr S3
SW Driver software
W SW A/A DATA SW A/A
The master provides data
on the bus
Interrupt on STOP
SW
Condition Enabled
Slave provides data on
the bus Collision Release
(SMBus)
SW
Hold S1
Sn Diagram connections
The number of interrupts generated is kept to a minimum by automatic handling of most conditions. Quick command can
be enabled to auto-trigger operations and reduce software complexity.
Promiscuous mode can be enabled to allow the slave to respond to all received addresses.
18.6.1 Receiving Address Packets

When the TWI slave is properly configured, it will wait for a START condition to be detected. When this happens, the
successive address byte will be received and checked by the address match logic, and the slave will ACK a correct
address and store the address in the DATA register. If the received address is not a match, the slave will not
acknowledge and store address, and will wait for a new START condition.
The slave address/stop interrupt flag is set when a START condition succeeded by a valid address byte is detected. A
general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition is an illegal operation, and the bus error flag is set.
The R/W direction flag reflects the direction bit received with the address. This can be read by software to determine the
type of operation currently in progress.
Depending on the R/W direction bit and bus condition, one of four distinct cases (S1 to S4) arises following the address
packet. The different cases must be handled in software.
18.6.1.1 Case S1: Address Packet Accepted - Direction Bit Set

If the R/W direction flag is set, this indicates a master read operation. The SCL line is forced low by the slave, stretching
the bus clock. If ACK is sent by the slave, the slave hardware will set the data interrupt flag indicating data is needed for
transmit. Data, repeated START, or STOP can be received after this. If NACK is sent by the slave, the slave will wait for
a new START condition and address match.
18.6.1.2 Case S2: Address Packet Accepted - Direction Bit Cleared

If the R/W direction flag is cleared, this indicates a master write operation. The SCL line is forced low, stretching the bus
clock. If ACK is sent by the slave, the slave will wait for data to be received. Data, repeated START, or STOP can be
received after this. If NACK is sent, the slave will wait for a new START condition and address match.
18.6.1.3 Case S3: Collision

If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the data and acknowledge
output from the slave logic. The clock hold is released. A START or repeated START condition will be accepted.
XMEGA E MANUAL 243

18.6.1.4 Case S4: STOP Condition Received
When the STOP condition is received, the slave address/stop flag will be set, indicating that a STOP condition, and not
an address match, occurred.
18.6.2 Receiving Data Packets

The slave will know when an address packet with R/W direction bit cleared has been successfully received. After
acknowledging this, the slave must be ready to receive data. When a data packet is received, the data interrupt flag is set
and the slave must indicate ACK or NACK. After indicating a NACK, the slave must expect a STOP or repeated START
condition.
18.6.3 Transmitting Data Packets

The slave will know when an address packet with R/W direction bit set has been successfully received. It can then start
sending data by writing to the slave data register. When a data packet transmission is completed, the data interrupt flag
is set. If the master indicates NACK, the slave must stop transmitting data and expect a STOP or repeated START
condition.
18.7 Enabling External Driver Interface

An external driver interface can be enabled. When this is done, the internal TWI drivers with input filtering and slew rate
control are bypassed. The normal I/O pin function is used, and the direction must be configured by the user software.
When this mode is enabled, an external TWI compliant tri-state driver is needed for connecting to a TWI bus.
By default, port pins 0 (Pn0) and 1 (Pn1) are used for SDA and SCL. The external driver interface uses port pins 0 to 3 for
the SDA_IN, SCL_IN, SDA_OUT, and SCL_OUT signals.
18.8 Bridge Mode

When enabling the bridge mode, both master and slave can be active at the same time, each with its specific IO pins.
Refer to the device datasheet to see which actual I/O port is used as alternative port selection for the slave in bridge
mode
Figure 18-14.TWI Bus Topology Example when one Device is Enabled in Bridge Mode
SCL
SDA
RP RP RS RS RS RS
VCC
Slave Master
RP RP
TWI DEVICE #1 TWI DEVICE #2 TWI DEVICE #3 TWI DEVICE #N
Master Slave Slave
RS RS RS RS RS RS
SDA
SCL
XMEGA E MANUAL 244

18.9 SMBUS L1 Compliance
The Industry Standard SMBus-2.0 specifies three time-outs for Layer 1 Compliance.
 Ttimeout – Continuous SCL low for 25ms
 Tlowsext – Cumulative slave SCL extend from START to STOP for 25ms
 Tlowmext – Cumulative master SCL extend from START- ACK or ACK-ACK or ACK – STOP for 10ms
All these time-outs are supported in the TWI module.
18.9.1 Overview
18.9.1.1 Ttimeout Specification

The TTIMEOUT,MIN (25ms) parameter allows a master or slave to conclude that a defective device is holding the clock
low indefinitely or a master is intentionally trying to drive devices off the bus. It is highly recommended that a slave device
release the bus (stop driving the bus and let SCL and SDA float high) when it detects any single clock held low longer
than TTIMEOUT,MIN. Devices that have detected this condition must reset their communication and be able to receive a
new START condition in no later than TIMEOUT,MAX (35ms).
Figure 18-15.Timeout Condition
Ttimeout
25ms
SCL
STOP
SDA
TTIMEOUT
18.9.1.2 Tlowsext Specification

This is the cumulative time the slave device is allowed to extend the SCL from START to STOP. The value for this
timeout is 25ms.
18.9.1.3 Tlowmext Specification

This is the cumulative time a master device is allowed to extend its clock cycles within one byte in a message as
measured from
START to ACK
ACK to ACK
ACK to STOP
The value for this timeout is 10ms.
XMEGA E MANUAL 245

Figure 18-16.Tlowsext/Tlowmext Condition
Tlowsext
25ms
Tlowmext Tlowmext Tlowmext

10ms 10ms 10ms
SCL
START ACK ACK STOP
SDA
18.9.2 Operation
For the operation of SMBUS timeout counters, the 2MHz internal oscillator should be in the oscillator control register,
“CTRL – Oscillator Control Register” on page 104.
18.9.2.1 Ttimeout Implementation

When this Timeout occurs in slave mode, slave resets the communication and lines are released by hardware. The Slave
is ready to receive a new start pulse. When this Timeout occurs in master mode, stop condition is sent by hardware. The
master is ready to start a new transaction on the bus. If TWI is configured as master, but lost arbitration on the bus then
TTIMEOUT counter is disabled.
18.9.2.2 Tlowsext Implementation

When this timeout occurs the master sends a STOP pulse immediately or at the end of current byte in progress,
depending on whether the master is in control of SDA. The slave resets its communication on receiving a STOP pulse
from master on timeout. If TWI is configured as master, but lost arbitration on the bus, the TLOWSEXT counter is
disabled.
18.9.2.3 Tlowmext Implementation

from master on timeout. If TWI is configured as master but lost arbitration on the bus, the TLOWMEXT counter is
disabled.
XMEGA E MANUAL 246

18.9.2.4 Timeouts Summary
Table 18-1. Summary of SMBUS Timeout Implementation
SMBUS L1 Timeouts Master Slave
Stop condition sent by hardware. The Slave resets the communication and releases the
Ttimeout master is ready to start a new transaction bus. Ready to receive a START condition in no
on the bus. later than TIMEOUT,MAX
Stop condition sent by hardware. The Slave resets the communication after detecting a
Tlowsext master is ready to start a new transaction stop pulse after timeout. Ready to receive a
on the bus. START condition.
Tlowmext master is ready to start a new transaction stop pulse after timeout. Ready to receive a
Arbitration lost All timeouts disabled -
18.9.2.5 Timeout Enable and Status Indication

 Separate Timeout enable for three timeouts (Ttimeout, Tlowsext, Tlowmext) in CTRLB register
 Common interrupt enable for all timeouts in CTRLB register
 Separate Status bit for three timeouts (Ttimeout, Tlowsext, Tlowmext) in “TOS – Timeout Status Register” on page
258
 Timeout configuration registers (“TOCONF – Timeout Configuration Register” on page 259) to program positive
and negative offsets in timeout value
 All status registers are reset on timeout except bus error flag (indicates incomplete transaction on bus) and
configuration registers are left unchanged
XMEGA E MANUAL 247

18.10 Register Description – TWI
Bit 7 6 5 4 3 2 1 0
+0x00 BRIDGEEN SFMPEN SSDAHOLD[1:0] FMPEN SDAHOLD[1:0] EDIEN
 Bit 7 – BRIDGEEN: Bridge Enable

Setting this bit to one enables the TWI Bridge Mode.
 Bit 6 – SFMPEN: Slave Fast Mode Plus Enable
Setting this bit to one enables the slave 1MHz bus speed operation. This bit setting is ignored if bridge mode is
disabled.
 Bit 5:4 – SSDAHOLD[1:0]: Slave SDA Hold Time Enable
Setting these bits to one enables an internal hold time on slave SDA with respect to the negative edge of SCL, as
defined by Table 18-2 on page 248. These bits settings are ignored if bridge mode is disabled.
 Bit 3 – FMPEN: FM Plus Enable
Setting this bit to one enables the 1MHz bus speed operation. By default, the setting applies to the master/slave
node. If the bridge mode is enabled, the setting applies to the master node only.
 Bit 2:1 – SDAHOLD[1:0]: SDA Hold Time Enable
Setting these bits to one enables an internal hold time on SDA with respect to the negative edge of SCL. By
default, the setting applies to the master/slave node. If the bridge mode is enabled, the setting applies to the mas-
ter node only.
Table 18-2. SDA Hold Time
SDAHOLD[1:0] Group configuration Description
00 OFF SDA hold time off
01 50NS Typical 50ns hold time
 Bit 0 – EDIEN: External Driver Interface Enable

Setting this bit enables the use of the external driver interface, and clearing this bit enables normal two-wire mode.
See Table 18-3 on page 248 for details. If bridge mode is enabled, this bit setting applies to both master and slave
nodes.
Table 18-3. External Driver Interface Enable
EDIEN Mode Comment
0 Normal TWI Two-pin interface, slew rate control, and input filter
1 External driver interface Four-pin interface, standard I/O, no slew rate control, and no input filter
XMEGA E MANUAL 248

18.11 Register Description – TWI master
Bit 7 6 5 4 3 2 1 0
+0x00 INTLVL[1:0] RIEN WIEN ENABLE – – –
Read/Write R/W R/W R/W R/W R/W R R R

These bits select the interrupt level for the TWI master interrupt, as described in “PMIC – Interrupts and Program-
mable Multilevel Interrupt Controller” on page 132.
 Bit 5 – RIEN: Read Interrupt Enable
Setting the read interrupt enable (RIEN) bit enables the read interrupt when the read interrupt flag (RIF) in the
STATUS register is set. In addition the INTLVL bits must be nonzero for TWI master interrupts to be generated.
 Bit 4 – WIEN: Write Interrupt Enable
Setting the write interrupt enable (WIEN) bit enables the write interrupt when the write interrupt flag (WIF) in the
STATUS register is set. In addition the INTLVL bits must be nonzero for TWI master interrupts to be generated.
 Bit 3 – ENABLE: Enable TWI Master
Setting the enable TWI master (ENABLE) bit enables the TWI master.
Bit 7 6 5 4 3 2 1 0
+0x01 TOIE TMEXTEN TSEXTEN TTOUTEN TIMEOUT[1:0] QCEN SMEN
 Bit 7 – TOIE: Timeout Interrupt Enable

Setting this bit to one enables interrupt on all master timeout interrupt flags (TTOUTMIF, TSEXTIF, TMEXTIF). A
TWI master timeout interrupt would be generated only if any one of the master timeout interrupt flags (TTOUT-
MIF/TSEXTIF/TMEXTIF), TOIE and Global Interrupt Enable are all set to one, and master interrupt level
(INTLVL[1:0]) is not equal to zero.
 Bit 6 – TMEXTEN: Tlowmext Enable
When tlowmext (TMEXTEN) is enabled, the master monitors the bus for tlowmext condition and the corresponding
interrupt flag (TMEXTIF) is set immediately after the tlowmext condition occurs.
 Bit 5 –TSEXTEN: Tlowsext Enable
When tlowsext (TSEXTEN) is enabled, the master monitors the bus for tlowsext condition and the corresponding
interrupt flag (TSEXTIF) is set immediately after the tlowsext condition occurs.
 Bit 4 – TTOUTEN: Ttimeout Enable
When ttimeout (TTOUTEN) is enabled, the master monitors the bus for ttimeout condition and the corresponding
interrupt flag (TTOUTMIF) is set immediately after the ttimeout condition occurs.
 Bit 3:2 – TIMEOUT[1:0]: Inactive Bus Timeout
Setting the inactive bus timeout (TIMEOUT) bits to a nonzero value will enable the inactive bus timeout supervisor.
If the bus is inactive for longer than the TIMEOUT setting, the bus state logic will enter the idle state.
Table 18-4 on page 250 lists the timeout settings.
XMEGA E MANUAL 249

Table 18-4. TWI Master Inactive Bus Timeout Settings
TIMEOUT[1:0] Group configuration Description
00 DISABLED Disabled, normally used for I2C
01 50US 50µs, normally used for SMBus at 100kHz
10 100US 100µs
11 200US 200µs
 Bit 1 – QCEN: Quick Command Enable

When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges
the address (read or write interrupt). At this point, software can issue either a STOP or a repeated START
condition.
 Bit 0 – SMEN: Smart Mode Enable
Setting this bit enables smart mode. When smart mode is enabled, the acknowledge action, as set by the ACKACT
bit in the CTRLC register, is sent immediately after reading the DATA register.
Bit 7 6 5 4 3 2 1 0
+0x02 – – – – – ACKACT CMD[1:0]

 Bit 2 – ACKACT: Acknowledge Action
This bit defines the master's acknowledge behavior in master read mode. The acknowledge action is executed
when a command is written to the CMD bits. If SMEN in the CTRLB register is set, the acknowledge action is per-
formed when the DATA register is read.
Table 18-5 lists the acknowledge actions.
Table 18-5. ACKACT Bit Description
ACKACT Action
0 Send ACK
1 Send NACK

Writing the command (CMD) bits triggers a master operation as defined by Table 18-6 on page 251. The CMD bits
are strobe bits, and always read as zero. The acknowledge action is only valid in master read mode (R). In master
write mode (W), a command will only result in a repeated START or STOP condition. The ACKACT bit and the
CMD bits can be written at the same time, and then the acknowledge action will be updated before the command
is triggered.
XMEGA E MANUAL 250

Table 18-6. CMD Bits Description
CMD[1:0] Group configuration MODE Operation
00 NOACT X Reserved
01 START X Execute acknowledge action succeeded by repeated START condition
W No operation
10 BYTEREC
R Execute acknowledge action succeeded by a byte receive
11 STOP X Execute acknowledge action succeeded by issuing a STOP condition
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
Bit 7 6 5 4 3 2 1 0
+0x03 RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[1:0]
Read/Write R/W R/W R R R/W R/W R/W R/W
 Bit 7 – RIF: Read Interrupt Flag

This flag is set when a byte is successfully received in master read mode; i.e., no arbitration was lost or bus error
occurred during the operation. Writing a one to this bit location will clear RIF. When this flag is set, the master
forces the SCL line low, stretching the TWI clock period. Clearing the interrupt flags will release the SCL line.
This flag is also cleared automatically when:
 Writing to the ADDR register
 Writing to the DATA register
 Reading the DATA register
 Writing a valid command to the CMD bits in the CTRLC register
 Bit 6 – WIF: Write Interrupt Flag
This flag is set when a byte is transmitted in master write mode. The flag is set regardless of the occurrence of a
bus error or an arbitration lost condition. WIF is also set if arbitration is lost during sending of a NACK in master
read mode, and if issuing a START condition when the bus state is unknown. Writing a one to this bit location will
clear WIF. When this flag is set, the master forces the SCL line low, stretching the TWI clock period. Clearing the
interrupt flags will release the SCL line.
The flag is also cleared automatically for the same conditions as RIF.
 Bit 5 – CLKHOLD: Clock Hold
This flag is set when the master is holding the SCL line low. This is a status flag and a read-only flag that is set
when RIF or WIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag.
The flag is also cleared automatically for the same conditions as RIF.
 Bit 4 – RXACK: Received Acknowledge
This flag contains the most recently received acknowledge bit from the slave. This is a read-only flag. When read
as zero, the most recent acknowledge bit from the slave was ACK, and when read as one the most recent
acknowledge bit was NACK.
 Bit 3 – ARBLOST: Arbitration Lost
This flag is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a START or
repeated START condition on the bus. Writing a one to this bit location will clear ARBLOST.
Writing the ADDR register will automatically clear ARBLOST.
 Bit 2 – BUSERR: Bus Error
This flag is set if an illegal bus condition has occurred. An illegal bus condition occurs if a repeated START or a
STOP condition is detected, and the number of received or transmitted bits from the previous START condition is
not a multiple of nine. Writing a one to this bit location will clear BUSERR.
XMEGA E MANUAL 251

Writing the ADDR register will automatically clear BUSERR.
 Bit 1:0 – BUSSTATE[1:0]: Bus State
These bits indicate the current TWI bus state as defined in Table 18-7. The change of bus state is dependent on
bus activity. Refer to the “TWI Bus State Logic” on page 240.
Table 18-7. TWI Master Bus State
BUSSTATE[1:0] Group configuration Description
00 UNKNOWN Unknown bus state
01 IDLE Idle bus state
10 OWNER Owner bus state
11 BUSY Busy bus state
Writing 01 to the BUSSTATE bits forces the bus state logic into the idle state. The bus state logic cannot be forced into
any other state. When the master is disabled, and after reset, the bus state logic is disabled and the bus state is
unknown.
18.11.5 BAUD – Baud Rate Register
Bit 7 6 5 4 3 2 1 0
+0x04 BAUD[7:0]
The baud rate (BAUD) register defines the relation between the system clock and the TWI bus clock (SCL) frequency.
The frequency relation can be expressed by using the following equation:
f sys
f TWI = --------------------------------------- [Hz] [1]
2(5 +  BAUD )
The BAUD register must be set to a value that results in a TWI bus clock frequency (fTWI) equal or less than 100kHz or
400kHz, depending on which standard the application should comply with. The following equation [2] expresses equation
[1] solved for the BAUD value:
f sys
BAUD = -------------- – 5 [2]
2f TWI
The BAUD register should be written only while the master is disabled.
18.11.6 ADDR – Address Register
Bit 7 6 5 4 3 2 1 0
+0x05 ADDR[7:0]
When the address (ADDR) register is written with a slave address and the R/W bit while the bus is idle, a START
condition is issued and the 7-bit slave address and the R/W bit are transmitted on the bus. If the bus is already owned
XMEGA E MANUAL 252

when ADDR is written, a repeated START is issued. If the previous transaction was a master read and no acknowledge
is sent yet, the acknowledge action is sent before the repeated START condition.
After completing the operation and the acknowledge bit from the slave is received, the SCL line is forced low if arbitration
was not lost. WIF is set.
If the bus state is unknown when ADDR is written, WIF is set and BUSERR is set.
All TWI master flags are automatically cleared when ADDR is written. This includes BUSERR, ARBLOST, RIF, and WIF.
The master ADDR can be read at any time without interfering with ongoing bus activity.
18.11.7 DATA – Data Register
Bit 7 6 5 4 3 2 1 0
+0x06 DATA[7:0]
The data (DATA) register is used when transmitting and receiving data. During data transfer, data are shifted from/to the
DATA register and to/from the bus. This implies that the DATA register cannot be accessed during byte transfers, and
this is prevented by hardware. The DATA register can only be accessed when the SCL line is held low by the master; i.e.,
when CLKHOLD is set.
In master write mode, writing the DATA register will trigger a data byte transfer followed by the master receiving the
acknowledge bit from the slave. WIF and CLKHOLD are set.
In master read mode, RIF and CLKHOLD are set when one byte is received in the DATA register. If smart mode is
enabled, reading the DATA register will trigger the bus operation as set by the ACKACT bit. If a bus error occurs during
reception, WIF and BUSERR are set instead of RIF.
Accessing the DATA register will clear the master interrupt flags and CLKHOLD.
XMEGA E MANUAL 253

18.12 Register Description – TWI Slave
Bit 7 6 5 4 3 2 1 0
+0x00 INTLVL[1:0] DIEN APIEN ENABLE PIEN PMEN SMEN

These bits select the interrupt level for the TWI master interrupt, as described in “PMIC – Interrupts and Program-
 Bit 5 – DIEN: Data Interrupt Enable
Setting the data interrupt enable (DIEN) bit enables the data interrupt when the data interrupt flag (DIF) in the STA-
TUS register is set. The INTLVL bits must be nonzero for the interrupt to be generated.
 Bit 4 – APIEN: Address/Stop Interrupt Enable
Setting the address/stop interrupt enable (APIEN) bit enables the address/stop interrupt when the address/stop
interrupt flag (APIF) in the STATUS register is set. The INTLVL bits must be nonzero for interrupt to be generated.
 Bit 3 – ENABLE: Enable TWI Slave
Setting this bit enables the TWI slave.
 Bit 2 – PIEN: Stop Interrupt Enable
Setting the this bit will cause APIF in the STATUS register to be set when a STOP condition is detected.
 Bit 1 – PMEN: Promiscuous Mode Enable
By setting the this bit, the slave address match logic responds to all received addresses. If this bit is cleared, the
address match logic uses the ADDR register to determine which address to recognize as its own address.
 Bit 0 – SMEN: Smart Mode Enable
This bit enables smart mode. When Smart mode is enabled, the acknowledge action, as set by the ACKACT bit in
the CTRLB register, is sent immediately after reading the DATA register.
Bit 7 6 5 4 3 2 1 0
+0x01 TOIE – – TTOUTEN – ACKACT CMD[1:0]
Read/Write R/W R R R/W R R/W R/W R/W

Setting this bit to one enables interrupt on slave timeout interrupt flag (TTOUTSIF). A TWI slave timeout interrupt
would be generated if TTOUTSIF, TOIE, and Global Interrupt Enable are all set to one, and slave interrupt level
(INTLVL[1:0]) is not equal to zero.
When ttimeout (TTOUTEN) is enabled, the slave monitors the bus for ttimeout condition and the corresponding
interrupt flag (TTOUTSIF) is set immediately after the ttimeout condition occurs.
XMEGA E MANUAL 254

 Bit 2 – ACKACT: Acknowledge Action
This bit defines the slave's acknowledge behavior after an address or data byte is received from the master. The
acknowledge action is executed when a command is written to the CMD bits. If the SMEN bit in the CTRLA regis-
ter is set, the acknowledge action is performed when the DATA register is read.
Table 18-8 on page 255 lists the acknowledge actions.
Table 18-8. TWI Slave Acknowledge Actions
ACKACT Action
0 Send ACK
1 Send NACK

Writing these bits trigger the slave operation as defined by Table 18-9. The CMD bits are strobe bits and always
read as zero. The operation is dependent on the slave interrupt flags, DIF, and APIF. The acknowledge action is
only executed when the slave receives data bytes or address byte from the master.
Table 18-9. TWI Slave Command
CMD[1:0] Group configuration DIR Operation
00 NOACT X No action
01 X Reserved
Used to complete transaction
Execute acknowledge action succeeded by waiting for any START (S/Sr)

10 COMPLETE 0
condition
1 Wait for any START (S/Sr) condition
Used in response to an address byte (APIF is set)
0 Execute acknowledge action succeeded by reception of next byte
1 Execute acknowledge action succeeded by DIF being set

11 RESPONSE
Used in response to a data byte (DIF is set)
0 Execute acknowledge action succeeded by waiting for the next byte
1 No operation
Writing the CMD bits will automatically clear the slave interrupt flags and CLKHOLD, and release the SCL line. The
ACKACT bit and CMD bits can be written at the same time, and then the acknowledge action will be updated before the
command is triggered.
XMEGA E MANUAL 255

Bit 7 6 5 4 3 2 1 0
+0x02 DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP
Read/Write R/W R/W R R R/W R/W R/W R/W
 Bit 7 – DIF: Data Interrupt Flag

This flag is set when a data byte is successfully received; i.e., no bus error or collision occurred during the opera-
tion. Writing a one to this bit location will clear DIF. When this flag is set, the slave forces the SCL line low,
stretching the TWI clock period. Clearing the interrupt flags will release the SCL line.
This flag is also cleared automatically when writing a valid command to the CMD bits in the CTRLB register.
 Bit 6 – APIF: Address/Stop Interrupt Flag
This flag is set when the slave detects that a valid address has been received, or when a transmit collision is
detected. If the PIEN bit in the CTRLA register is set, a STOP condition on the bus will also set APIF. Writing a one
to this bit location will clear APIF. When set for an address interrupt, the slave forces the SCL line low, stretching
the TWI clock period. Clearing the interrupt flags will release the SCL line.
The flag is also cleared automatically for the same condition as DIF.
 Bit 5 – CLKHOLD: Clock Hold
This flag is set when the slave is holding the SCL line low.This is a status flag and a read-only bit that is set when
DIF or APIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag.
 Bit 4 – RXACK: Received Acknowledge
This flag contains the most recently received acknowledge bit from the master. This is a read-only flag. When read
as zero, the most recent acknowledge bit from the maser was ACK, and when read as one, the most recent
acknowledge bit was NACK.
 Bit 3 – COLL: Collision
This flag is set when a slave has not been able to transfer a high data bit or a NACK bit. If a collision is detected,
the slave will commence its normal operation, disable data, and acknowledge output, and no low values will be
shifted out onto the SDA line. Writing a one to this bit location will clear COLL.
The flag is also cleared automatically when a START or repeated START condition is detected.
 Bit 2 – BUSERR: TWI Slave Bus Error
This flag is set when an illegal bus condition occurs during a transfer. An illegal bus condition occurs if a repeated
START or a STOP condition is detected, and the number of bits from the previous START condition is not a multi-
ple of nine. Writing a one to this bit location will clear BUSERR.
For bus errors to be detected, the bus state logic must be enabled. This is done by enabling the TWI master.
 Bit 1 – DIR: Read/Write Direction
The R/W direction (DIR) flag reflects the direction bit from the last address packet received from a master. When
this bit is read as one, a master read operation is in progress. When read as zero, a master write operation is in
progress.
 Bit 0 – AP: Slave Address or Stop
This flag indicates whether a valid address or a STOP condition caused the last setting of APIF in the STATUS
register.
Table 18-10. TWI Slave Address or Stop
AP Description
0 A STOP condition generated the interrupt on APIF
1 Address detection generated the interrupt on APIF
XMEGA E MANUAL 256

18.12.4 ADDR – Address Register
The TWI slave address register should be loaded with the 7-bit slave address (in the seven most significant bits of
ADDR) to which the TWI will respond. The lsb of ADDR is used to enable recognition of the general call address (0x00).
Bit 7 6 5 4 3 2 1 0
+0x03 ADDR[7:1] ADDR[0]
 Bit 7:1 – ADDR[7:1]: TWI Slave Address

This register contains the TWI slave address used by the slave address match logic to determine if a master has
addressed the slave. The seven most-significant bits (ADDR[7:1]) represent the slave address.
When using 10-bit addressing, the address match logic only supports hardware address recognition of the first
byte of a 10-bit address. By setting ADDR[7:1] = 0b11110nn, ”nn” represents bits 9 and 8 of the slave address.
The next byte received is bits 7 to 0 in the 10-bit address, and this must be handled by software.
When the address match logic detects that a valid address byte is received, APIF is set and the DIR flag is
updated.
If the PMEN bit in CTRLA is set, the address match logic responds to all addresses transmitted on the TWI bus.
The ADDR register is not used in this mode.
 Bit 0 – ADDR: General Call Recognition Enable
When ADDR[0] is set, this enables general call address recognition logic so the device can respond to a general
address call that addresses all devices on the bus.
Bit 7 6 5 4 3 2 1 0
+0x04 DATA[7:0]
The data (DATA) register is used when transmitting and received data. During data transfer, data are shifted from/to the
DATA register and to/from the bus. This implies that the DATA register cannot be accessed during byte transfers, and
this is prevented by hardware. The DATA register can be accessed only when the SCL line is held low by the slave; i.e.,
when CLKHOLD is set.
When a master is reading data from the slave, data to send must be written to the DATA register. The byte transfer is
started when the master starts to clock the data byte from the slave, followed by the slave receiving the acknowledge bit
from the master. DIF and CLKHOLD are set.
When a master writes data to the slave, DIF and CLKHOLD are set when one byte has been received in the DATA
register. If smart mode is enabled, reading the DATA register will trigger the bus operation as set by the ACKACT bit.
Accessing the DATA register will clear the slave interrupt flags and CLKHOLD. When an address match occurs, the
received address will be stored in the DATA register.
18.12.6 ADDRMASK – Address Mask Register
Bit 7 6 5 4 3 2 1 0
+0x05 ADDRMASK[7:1] ADDREN
 Bit 7:1 – ADDRMASK[7:1]: Address Mask

These bits can act as a second address match register or as an address mask register, depending on the
ADDREN setting.
XMEGA E MANUAL 257

If ADDREN is set to zero, ADDRMASK can be loaded with a 7-bit slave address mask. Each bit in ADDRMASK
can mask (disable) the corresponding address bit in the ADDR register. If the mask bit is one, the address match
between the incoming address bit and the corresponding bit in ADDR is ignored; i.e., masked bits will always
match.
If ADDREN is set to one, ADDRMASK can be loaded with a second slave address in addition to the ADDR regis-
ter. In this mode, the slave will match on two unique addresses, one in ADDR and the other in ADDRMASK.
 Bit 0 – ADDREN: Address Enable
By default, this bit is zero, and the ADDRMASK bits acts as an address mask to the ADDR register. If this bit is set
to one, the slave address match logic responds to the two unique addresses in ADDR and ADDRMASK.
18.13 Register Description – TWI Timeout
18.13.1 TOS – Timeout Status Register
Bit 7 6 5 4 3 2 1 0
+0x00 – – – TTOUTSIF – TMEXTIF TSEXTIF TTOUTMIF
Read/Write R R R R/W R R/W R/W R/W
 Bit 4 – TTOUTSIF: Slave Ttimeout Interrupt Flag

The slave ttimeout interrupt flag in set when ttimeout enable (TTOUTEN) is set and ttimeout condition occurs in
slave. The slave releases the bus after this condition and ready to receive a new START pulse. Writing a one to its
bit location will clear the TTOUTSIF flag.
 Bit 2 – TMEXTIF: Tlowmext Interrupt Flag
The tlowmext interrupt flag in set when tlowmext enable (TMEXTEN) is set and tlowmext condition occurs in mas-
ter. Writing a one to its bit location will clear the TMEXTIF flag. This flag is also automatically cleared by writing into
master address register (ADDR[7:0]).
 Bit 1 – TSEXTIF: Tlowsext Interrupt Flag
The tlowsext interrupt flag in set when tlowsext enable (TSEXTEN) is set and tlowsext condition occurs in master.
Writing a one to its bit location will clear the TSEXTIF flag. This flag is also automatically cleared by writing into
 Bit 0 – TTOUTMIF: Master Ttimeout Interrupt Flag
The master ttimeout interrupt flag in set when ttimeout enable (TTOUTEN) is set and ttimeout condition occurs in
master. The master should wait for BUS IDLE condition before starting the next transaction. This ensures that all
slave devices have released the bus following the ttimeout condition and ready to receive a new START pulse.
Writing a one to its bit location will clear the TTOUTMIF flag. This flag is also automatically cleared by writing into
XMEGA E MANUAL 258

18.13.2 TOCONF – Timeout Configuration Register
Bit 7 6 5 4 3 2 1 0
+0x01 TTOUTSSEL[2:0] TMSEXTSEL[1:0] TTOUTMSEL[2:0]
 Bit 7:5 – TTOUTSSEL[2:0]: Slave Ttimeout select

These bits select slave ttimeout value according to Table 18-11 on page 259.
 Bit 4:3 – TMSEXTSEL[1:0]: Master Tlowsext/Tlowmext select
These bits select master tlowsext/tlowmext value according Table 18-12 on page 259.
 Bit 2:0 – TTOUTMSEL[2:0]: Master Ttimeout select
These bits select master ttimeout value according to Table 18-11 on page 259.
Table 18-11. Ttimeout Configuration
TTOUTMSEL[2:0] TOUTSSEL[2:0] Ttimeout Value
3’b000 3’b000 25ms
3’b001 3’b001 24ms
3’b010 3’b010 23ms
3’b011 3’b011 22ms
3’b100 3’b100 26ms
3’b101 3’b101 27ms
3’b110 3’b110 28ms
3’b111 3’b111 29ms
Table 18-12. Tlowsext/Tlowmext Configuration
TMSEXTSEL[1:0] Tlowsext Value Tlowmext Value
2’b00 25ms 10ms
2’b01 24ms 9ms
2’b10 26ms 11ms
2’b11 27ms 12ms
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18.14 Register Summary - TWI
+0x00 CTRL BRIDGEEN SFMPEN SSDAHOLD[1:0] FMPEN SDAHOLD[1:0] EDIEN 248
+0x01 MASTER Offset address for TWI Master
+0x08 SLAVE Offset address for TWI Slave
18.15 Register Summary - TWI Master

+0x00 CTRLA INTLVL[1:0] RIEN WIEN ENABLE – – – 249
+0x01 CTRLB TOIE TMEXTEN TSEXTEN TTOUTEN TIMEOUT[1:0] QCEN SMEN 249
+0x02 CTRLC – – – – – ACKACT CMD[1:0] 250
ARBLOS
+0x03 STATUS RIF WIF CLKHOLD RXACK BUSERR BUSSTATE[1:0] 251
T
+0x04 BAUD BAUD[7:0] 252
+0x05 ADDR ADDR[7:0] 252
+0x06 DATA DATA[7:0] 253
18.16 Register Summary - TWI Slave

+0x00 CTRLA INTLVL[1:0] DIEN APIEN ENABLE PIEN PMEN SMEN 254
+0x01 CTRLB TOIE – – TTOUTEN – ACKACT CMD[1:0] 254
+0x02 STATUS DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP 256
+0x03 ADDR ADDR[7:0] 257
+0x04 DATA DATA[7:0] 257
+0x05 ADDRMASK ADDRMASK[7:1] ADDREN 257
18.17 Register Summary – TWI Timeout

Address Name 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 TOS – – – TTOUTSI – TMEXTI TSEXTIF 258
+0x01 TOCONF TTOUTSSEL[2:0] TMSEXTSEL[1:0] TTOUTMSEL[2:0] 259
Table 18-13. TWI Interrupt Vectors and their Word Offset Addresses
0x00 SLAVE_vect TWI slave interrupt vector
0x02 MASTER_vect TWI master interrupt vector
XMEGA E MANUAL 260

19. TWI SMBUS L1 Compliance
19.1 Features
 Supports SMBUS Layer 1 timeouts
 Configurable timeout values
 Independent timeout counters in master and slave (Bridge mode support)
19.2 TWI SMBUS L1 Compliance

The Industry Standard SMBus-2.0 specifies three timeouts for Layer 1 Compliance.
 Ttimeout – Continuous SCL low for 25ms
 Tlowsext – Cumulative slave SCL extend from START to STOP for 25ms
 Tlowmext – Cumulative master SCL extend from START- ACK or ACK-ACK or ACK – STOP for 10ms
All these timeouts are supported in the TWI module.
19.3 Overview
19.3.1 TTIMEOUT Specification

The TTIMEOUT,MIN (25ms) parameter allows a master or slave to conclude that a defective device is holding the clock
low indefinitely or a master is intentionally trying to drive devices off the bus. It is highly recommended that a slave device
release the bus (stop driving the bus and let SMBCLK and SMBDAT float high) when it detects any single clock held low
longer than TTIMEOUT,MIN. Devices that have detected this condition must reset their communication and be able to
receive a new START condition in no later than TIMEOUT,MAX (35ms).
Figure 19-1. Ttimeout Condition
Ttimeout
25ms
SCL
STOP
SDA
TTIMEOUT
19.3.2 Tlowsext Specification

This is the cumulative time the slave device is allowed to extend the SCL from START to STOP. The value for this
timeout is 25ms.
XMEGA E MANUAL 261

19.3.3 Tlowmext Specification
This is the cumulative time a master device is allowed to extend its clock cycles within one byte in a message as
measured from
START to ACK
ACK to ACK
ACK to STOP
The value for this timeout is 10ms.
Table 19-1. Tlowsext/Tlowmext Condition
Tlowsext
25ms
Tlowmext Tlowmext Tlowmext

10ms 10ms 10ms
SCL
START ACK ACK STOP
SDA
19.4 Operation
For the operation of SMBUS timeout counters, the 2MHz internal oscillator should be enabled in the OSC_CTRL register.
19.4.1 Ttimeout Implementation

When this Timeout occurs in slave mode, slave resets the communication and lines are released by hardware. The Slave
is ready to receive a new start pulse. When this Timeout occurs in master mode, stop condition is sent by hardware. The
master is ready to start a new transaction on the bus. If TWI is configured as master, but lost arbitration on the bus then
TTIMEOUT counter is disabled.
19.4.2 Tlowsext Implementation

from master on timeout. If TWI is configured as master, but lost arbitration on the bus, the TLOWSEXT counter is
disabled.
19.4.3 Tlowmext Implementation

from master on timeout. If TWI is configured as master but lost arbitration on the bus, the TLOWMEXT counter is
disabled.
XMEGA E MANUAL 262

19.4.4 Timeouts Summary
Table 19-2. Summary of SMBUS Timeout Implementation
SMBUS L1 Timeouts Master Slave
Stop condition sent by hardware. The Slave resets the communication and releases the
Ttimeout master is ready to start a new transaction bus. Ready to receive a START condition in no
on the bus. later than TIMEOUT,MAX
Tlowsext master is ready to start a new transaction stop pulse after timeout. Ready to receive a
Tlowmext master is ready to start a new transaction stop pulse after timeout. Ready to receive a
Arbitration lost All timeouts disabled -
19.4.5 Timeout Enable and Status Indication

 Separate Timeout enable for three timeouts (Ttimeout, Tlowsext, Tlowmext) in CTRLB register
 Common interrupt enable for all timeouts in CTRLB register
 Separate Status bit for three timeouts (Ttimeout, Tlowsext, Tlowmext) in TWITOS register
 An interrupt will be generated only if the interrupt enable bit, any one status bit indicating timeout, global interrupt
enable are all set to one and interrupt level is not zero in the twi control register
 Timeout configuration registers (TWITOCONF) to program positive and negative offsets in timeout value
 All status registers are reset on timeout except bus error flag (indicates incomplete transaction on bus) and
configuration registers are left unchanged
XMEGA E MANUAL 263

19.5 Register Description – TWI Master
Bit 7 6 5 4 3 2 1 0
+0x01 TOIE TMEXTEN TSEXTEN TTOUTEN TIMEOUT[1:0] QCEN SMEN

Setting this bit to one enables interrupt on all master timeout interrupt flags (TTOUTMIF, TSEXTIF, TMEXTIF). A
TWI master timeout interrupt would be generated only if any one of the master timeout interrupt flags (TTOUT-
MIF/TSEXTIF/TMEXTIF), TOIE and Global Interrupt Flag (I) are all set to one, and TWMLVL is not equal to zero.
 Bit 6 – TMEXTEN: Tlowmext Enable
When tlowmext (TMEXTEN) is enabled, the master monitors the bus for tlowmext condition and the corresponding
interrupt flag (TMEXTIF) is set immediately after the tlowmext condition occurs.
 Bit 5 –TSEXTEN: Tlowsext Enable
When tlowsext (TSEXTEN) is enabled, the master monitors the bus for tlowsext condition and the corresponding
interrupt flag (TSEXTIF) is set immediately after the tlowsext condition occurs.
When ttimeout (TTOUTEN) is enabled, the master monitors the bus for ttimeout condition and the corresponding
interrupt flag (TTOUTMIF) is set immediately after the ttimeout condition occurs.
 Bit 3:0 – <Existing register bits. Refer TWI specification>
19.6 Register Description – TWI Slave
Bit 7 6 5 4 3 2 1 0
+0x01 TOIE – – TTOUTEN – ACKACT CMD[1:0]
Read/Write R/W R R R/W R R/W R/W R/W

Setting this bit to one enables interrupt on slave timeout interrupt flag (TTOUTSIF). A TWI slave timeout interrupt
would be generated if TTOUTSIF, TOIE and Global Interrupt Flag (I) are all set to one, and TWSLVL is not equal
to zero.
When ttimeout (TTOUTEN) is enabled, the slave monitors the bus for ttimeout condition and the corresponding
interrupt flag (TTOUTSIF) is set immediately after the ttimeout condition occurs.
 Bit 2:0 – <Existing register bits. Refer TWI specification>
XMEGA E MANUAL 264

19.7 Register Description – TWI Timeout
19.7.1 TOS – Timeout Status Register
Bit 7 6 5 4 3 2 1 0
+0x00 – – – TTOUTSIF – TMEXTIF TSEXTIF TTOUTMIF
Read/Write R R R R/W R R/W R/W R/W
 Bit 4 – TTOUTSIF: Slave Ttimeout Interrupt Flag

The slave ttimeout interrupt flag in set when ttimeout enable (TTOUTEN) is set and ttimeout condition occurs in
slave. The slave releases the bus after this condition and ready to receive a new START pulse. Writing a one to its
bit location will clear the TTOUTSIF flag.
 Bit 2 – TMEXTIF: Tlowmext Interrupt Flag
The tlowmext interrupt flag in set when tlowmext enable (TMEXTEN) is set and tlowmext condition occurs in mas-
ter. Writing a one to its bit location will clear the TMEXTIF flag. However, normal use of the TWI does not require
the TMEXTIF flag to be cleared by using this method since the flag is automatically cleared when writing into mas-
ter address register (ADDR[7:0]).
 Bit 1 – TSEXTIF: Tlowsext Interrupt Flag
The tlowsext interrupt flag in set when tlowsext enable (TSEXTEN) is set and tlowsext condition occurs in master.
Writing a one to its bit location will clear the TSEXTIF flag. However, normal use of the TWI does not require the
TSEXTIF flag to be cleared by using this method since the flag is automatically cleared when writing into master
address register (ADDR[7:0]).
 Bit 0 – TTOUTMIF: Master Ttimeout Interrupt Flag
The master ttimeout interrupt flag in set when ttimeout enable (TTOUTEN) is set and ttimeout condition occurs in
master. The master should wait for BUS IDLE condition before starting the next transaction. This ensures that all
slave devices have released the bus following the ttimeout condition and ready to receive a new START pulse.
Writing a one to its bit location will clear the TTOUTMIF flag. However, normal use of the TWI does not require the
TTOUTMIF flag to be cleared by using this method since the flag is automatically cleared when writing into master
address register (ADDR[7:0]).
19.7.2 TOCONF – Timeout Configuration Register
Bit 7 6 5 4 3 2 1 0
+0x01 TTOUTSSEL[2:0] TMSEXTSEL[1:0] TTOUTMSEL[2:0]
 Bit 7:5 – TTOUTSSEL[2:0]: Slave Ttimeout select

These bits select slave ttimeout value according to Table 19-3 on page 266.
 Bit 4:3 – TMSEXTSEL[1:0]: Master Tlowsext/Tlowmext select
These bits select master tlowsext/tlowmext value according Table 19-4 on page 266.
 Bit 2:0 – TTOUTMSEL[2:0]: Master Ttimeout select
These bits select master ttimeout value according to Table 19-3 on page 266.
XMEGA E MANUAL 265

Table 19-3. Ttimeout Configuration
TTOUTMSEL[2:0] TOUTSSEL[2:0] Ttimeout Value
3’b000 3’b000 25ms
3’b001 3’b001 24ms
3’b010 3’b010 23ms
3’b011 3’b011 22ms
3’b100 3’b100 26ms
3’b101 3’b101 27ms
3’b110 3’b110 28ms
3’b111 3’b111 29ms
Table 19-4. Tlowsext/Tlowmext Configuration
TMSEXTSEL[1:0] Tlowsext Value Tlowmext Value
2’b00 25ms 10ms
2’b01 24ms 9ms
2’b10 26ms 11ms
2’b11 27ms 12ms
XMEGA E MANUAL 266

19.8 Register Summary – TWI
+0x01 MASTER Offset address for TWI master 264
+0x08 SLAVE Offset address for TWI slave 264
+0x0E TIMEOUT Offset address for TWI timeout 265
19.9 Register Summary – TWI Master

+0x01 CTRLB TOIE TMEXTEN TSEXTEN TTOUTEN TIMEOUT[1:0] QCEN SMEN 264
19.10 Register Summary – TWI Slave

+0x01 CTRLB TOIE – – TTOUTEN – ACKACT CMD[1:0] 264
19.11 Register Summary – TWI Timeout

+0x00 TOS – – – TTOUTSIF – TMEXTIF TSEXTIF TTOUTMIF 265
+0x01 TOCONF TTOUTSSEL[2:0] TMSEXTSEL[1:0] TTOUTMSEL[2:0] 265
XMEGA E MANUAL 267

20. SPI – Serial Peripheral Interface
20.1 Features
 Full-duplex, three-wire synchronous data transfer
 Master or slave operation
 Lsb first or msb first data transfer
 Eight programmable bit rates
 Optional double buffered receive
 Optional buffered transmit
 Optional separate interrupts for:
 Receive complete
 Transmit complete
 Transmit data register empty
 Slave Select line pulled low
 Data overrun detection
 Wake up from idle sleep mode
 Double speed master mode
20.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an XMEGA device and peripheral devices or between several microcontrollers. The
SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave.The master initiates and controls all data transactions. The
interconnection between master and slave devices with SPI is shown in Figure 20-1 on page 268. The system consists of
two shift registers and a master clock generator. The SPI master initiates the communication cycle by pulling the slave
select (SS) signal low for the desired slave. Master and slave prepare the data to be sent in their respective shift
registers, and the master generates the required clock pulses on the SCK line to interchange data. Data are always
shifted from master to slave on the master output, slave input (MOSI) line, and from slave to master on the master input,
slave output (MISO) line. After each data packet, the master can synchronize the slave by pulling the SS line high.
Figure 20-1. SPI Master-slave Interconnection
MASTER
SLAVE
Transmit Data Register
Transmit Data Register
(DATA)
(DATA)
msb lsb MISO MISO
8-bit Shift Register
MOSI MOSI lsb msb
8-bit Shift Register
SPI CLOCK SCK SCK
GENERATOR
SS SS
Receive Buffer Register
Receive Buffer Register
Receive Data Register

Receive Data Register
(DATA)
(DATA)
In SPI slave mode, the control logic will sample the incoming signal on the SCK pin. To ensure correct sampling of this
clock signal, the minimum low and high periods must each be longer than two CPU clock cycles.
XMEGA E MANUAL 268

When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 20-1 on page 269. The pins with user-defined direction must be configured from software to have the correct
direction according to the application.
Table 20-1. SPI Pin Override and Directions
Pin Master mode Slave mode
MOSI User defined Input
MISO Input User defined
SCK User defined Input
SS User defined Input
20.3 Master Mode

In master mode, the SPI interface has no automatic control of the SS line. If the SS pin is used, it must be configured as
output and controlled by user software. If the bus consists of several SPI slaves and/or masters, a SPI master can use
general purpose I/O pins to control the SS line to each of the slaves on the bus.
Writing a byte to the DATA register starts the SPI clock generator and the hardware shifts the eight bits into the selected
slave. After shifting one byte and there are no pending data, Data Register Empty Interrupt flag (DREIF) is set, the SPI
clock generator stops and the Transfer Complete interrupt flag (TXCIF) is set.
If there are pending data, DREIF is cleared; the master will continue to shift the next bytes and after each byte is shifted
out, the new data is copied to the shift register and the DREIF is set. Only when a shift is completed and there are no
more pending data, will the TXCIF be set. An end of transfer can also be signaled by pulling the SS line high. The last
incoming byte will be kept in the shift register.
If the SS pin is not used it can be disabled by writing the Slave Select Disable (SSD) bit in the CTRLB register. If not
disabled and is configured as input, it must be held high to ensure master operation. If the SS pin is set as input and is
being driven low, the SPI module will interpret this as another master trying to take control of the bus. To avoid bus
contention, the master will take the following action:
1. The master enters slave mode.
2. The slave select interrupt flag (SSIF) is set.
20.4 Slave Mode

In slave mode, the SPI module will remain sleeping with the MISO line tri-stated as long as the SS pin is driven high. In
this state, software may update the contents of the DATA register, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. If SS is driven low, the slave will start to shift out data on the first
SCK clock pulse. When one byte has been completely shifted, the SPI interrupt flag is set. The slave may continue
placing new data to be sent into the DATA register before reading the incoming data. The last incoming byte will be kept
in the buffer register.
When SS is driven high, the SPI logic is halted, and the SPI slave will not receive any new data. Any partially received
packet in the shift register will be dropped.
As the SS pin is used to signal the start and end of a transfer, it is also useful for doing packet/byte synchronization,
keeping the slave bit counter synchronous with the master clock generator.
To ensure that write collision never can happen, SPI module can be configured in buffered mode. Data is copied from the
Transmit Register to the Shift Register only at receive complete. This means that, after data is written to the Transmit
Buffer, one SPI transfer must be completed before the data is copied into the shift register.
XMEGA E MANUAL 269

20.5 Buffer Modes
There are three buffer modes:
 Unbuffered mode:
The default SPI module is unbuffered in the transmit direction and single buffered in the receive direction. This
means that bytes to be transmitted cannot be written to the SPI DATA register before the entire shift cycle is com-
pleted. When receiving data, a received character must be read from the DATA register before the next character
has been completely shifted in. Otherwise, the first byte will be lost.
 Buffered mode 1:
The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when a full character has been received. When
receiving data, a received character must be read from the DATA register before the third character has been
completely shifted in to avoid loosing data.
 Buffered mode 2:
The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when the SPI is enabled. Then, one SPI transfer must
be completed before the data is copied to the shift register.
20.6 Data Modes

There are four combinations of SCK phase and polarity with respect to serial data. The SPI data transfer formats are
shown in Figure 20-2. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient
time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
XMEGA E MANUAL 270

Figure 20-2. SPI Transfer Modes
Cycle # 1 2 3 4 5 6 7 8
SPI - Mode 0
/SS
SCK
sampling
MISO HZ 1 2 3 4 5 6 7 8 HZ
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI - Mode 1
/SS
SCK
sampling
MISO HZ 1 2 3 4 5 6 7 8 HZ
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI - Mode 2
/SS
SCK
sampling
MISO HZ 1 2 3 4 5 6 7 8 HZ
MOSI 1 2 3 4 5 6 7 8
Cycle # 1 2 3 4 5 6 7 8
SPI - Mode 3
/SS SPI Mode 3
SCK
sampling
MISO HZ 1 2 3 4 5 6 7 8 HZ
MOSI 1 2 3 4 5 6 7 8
XMEGA E MANUAL 271

20.7 Interrupts
The SPI module has four interrupt sources. These are combined into one interrupt vector, the SPI interrupt. The interrupt
is enabled by setting the interrupt level (INTLVL), while different interrupt sources are enabled individually.
Figure 20-3 summarizes the interrupts sources for the SPI module, and shows how they are enabled.
Figure 20-3. SPI Interrupt Summary
Unbuffered SPI Mode

"SPI Interrupt Request"
Status IF WRCOL - - - - - -
Register RXCI F TXCI F DREI F SSI F - - - BUFOVF
"SPI Interrupt Request"

Buffered SPI Modes
Interrupt RXCI E TXCI E DREI E SSI E - - I NTLVL[ 1: 0]

Control
Register - - - - - - I NTLVL[ 1: 0]
20.8 EDMA Support

The SPI slave can trigger an EDMA transfer either as one byte has been moved into the DATA register or as data has
been shifted out and new transmit data can be written. The EDMA can be used for half duplex SPI operation using the
data register empty or receive complete EDMA triggers.
Figure 20-4 summarizes the interrupts sources for the SPI module, and shows how they are enabled.
Figure 20-4. SPI EDMA Request Summary
"SPI Trigger Source (offset 0)"

IFRXC (SPI to MEM.) Unbuffered SPI Mode
IFDRE (MEM. to SPI)
Status IF WRCOL - - - - - -
Register RXCI F TXCI F DREI F TXCI F - - - BUFOVF
IFRXC (SPI to MEM.)
IFDRE (MEM. to SPI)
Buffered SPI Modes
It is possible to use the XMEGA USART in SPI mode and then have EDMA support in master mode. For details, refer to
“USART in Master SPI mode” on page 293.
XMEGA E MANUAL 272

Bit 7 6 5 4 3 2 1 0
+0x00 CLK2X ENABLE DORD MASTER MODE[1:0] PRESCALER[1:0]
 Bit 7 – CLK2X: Clock Double

When this bit is set, the SPI speed (SCK frequency) will be doubled in master mode.
Setting this bit enables the SPI module. This bit must be set to enable any SPI operations.
 Bit 5 – DORD: Data Order
DORD decides the data order when a byte is shifted out from the DATA register. When DORD is written to one,
the least-significant bit (lsb) of the data byte is transmitted first, and when DORD is written to zero, the most-signif-
icant bit (msb) of the data byte is transmitted first.
 Bit 4 – MASTER: Master Select
This bit selects master mode when written to one, and slave mode when written to zero. If SS is configured as an
input and driven low while master mode is set, master mode will be cleared.
 Bit 3:2 – MODE[1:0]: Transfer Mode
These bits select the transfer mode. The four combinations of SCK phase and polarity with respect to the serial
data are shown in Table 20-2. These bits decide whether the first edge of a clock cycle (leading edge) is rising or
falling, and whether data setup and sample occur on the leading or trailing edge.
When the leading edge is rising, the SCK signal is low when idle, and when the leading edge is falling, the SCK
signal is high when idle.
Table 20-2. SPI Transfer Modes
MODE[1:0] Group configuration Leading edge Trailing edge
00 0 Rising, sample Falling, setup
01 1 Rising, setup Falling, sample
10 2 Falling, sample Rising, setup
11 3 Falling, setup Rising, sample
 Bits 1:0 – PRESCALER[1:0]: Clock Prescaler

These two bits control the SPI clock rate configured in master mode. These bits have no effect in slave mode. The
relationship between SCK and the peripheral clock frequency (clkPER) is shown in Table 20-4 on page 274.
Setting the CLK2X will double the frequency as shown in Table 20-4 on page 274.
XMEGA E MANUAL 273

Table 20-3. Prescaler Clock Configuration
PRESCALER[1:0] Group configuration Comment
00 DIV4 Divide clock by 4
Table 20-4. Relationship between SCK and the Peripheral Clock (ClkPER) Frequency
CLK2X PRESCALER[1:0] SCK frequency
0 00 ClkPER/4
0 01 ClkPER/16
0 10 ClkPER/64
0 11 ClkPER/128
1 00 ClkPER/2
1 01 ClkPER/8
1 10 ClkPER/32
1 11 ClkPER/64
Bit 7 6 5 4 3 2 1 0
Unbuffered mode – – – – – –
+0x01 INTLVL[1:0]
Buffer modes RXCIE TXCIE DREIE SSIE – –
Unbuffered mode Read/Write R R R R R R R/W R/W
Buffer modes Read/Write R/W R/W R/W R/W R R R/W R/W
Note: For details on buffer modes, refer to Table 20-5 on page 277.
20.9.2.1 Unbuffered Mode

These bits enable the SPI interrupt and select the interrupt level, as described in “PMIC – Interrupts and Program-
mable Multilevel Interrupt Controller” on page 132. The enabled interrupt will be triggered when IF is set in the
STATUS register.
20.9.2.2 Buffered Modes

 Bit 7 – RXCIE – Receive Complete Interrupt Enable
This bit enables the receive complete interrupt. The interrupt level is defined by INTLVL[1:0]. The enabled interrupt
will be triggered when the RXCIF flag in the STATUS register is set.
XMEGA E MANUAL 274

 Bit 6 – TXCIE – Transfer Complete Interrupt Enable
This bit enables the transfer complete interrupt. The interrupt level is defined by INTLVL[1:0]. The enabled inter-
rupt will be triggered when the TXCIF flag in the STATUS register is set.
 Bit 5 – DREIE – Data Register Empty Interrupt Enable
This bit enables the data register empty interrupt. The interrupt level is defined by INTLVL[1:0]. The enabled inter-
rupt will be triggered when the DREIF flag in the STATUS register is set.
 Bit 4 – SSIE – Slave Select trigger Interrupt Enable
This bit enables the Slave Select interrupt. The interrupt level is defined by INTLVL[1:0]. The enabled interrupt will
be triggered when the SSIF flag in the STATUS register is set.
These bits enable the SPI interrupt and select the interrupt level, as described in “PMIC – Interrupts and Program-
mable Multilevel Interrupt Controller” on page 132. The enabled interrupt will be triggered when corresponding
flags are set in the STATUS register.
Bit 7 6 5 4 3 2 1 0
Unbuffered mode IF WRCOL – – – – – –
+0x02
Buffer modes RXCIF TXCIF DREIF SSIF – – – BUFOVF
Unbuffered mode Read/Write R R R R R R R R
Buffer modes Read/Write R/W R/W R/W R/W R R R R/W
Note: For details on buffer modes, refer to Table 20-5 on page 277.
20.9.3.1 Unbuffered Mode

 Bit 7 – IF: Interrupt Flag
This flag is set when a serial transfer is complete and one byte is completely shifted in/out of the DATA register. If
SS is configured as input and is driven low when the SPI is in master mode, this will also set this flag. IF is cleared
by hardware when executing the corresponding interrupt vector. Alternatively, the IF flag can be cleared by first
reading the STATUS register when IF is set, and then accessing the DATA register.
 Bit 6 – WRCOL: Write Collision Flag
The WRCOL flag is set if the DATA register is written during a data transfer. This flag is cleared by first reading the
STATUS register when WRCOL is set, and then accessing the DATA register.
20.9.3.2 Buffered Modes

 Bit 7 – RXCIF: Receive Complete Interrupt Flag
This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty (i.e.,
does not contain any unread data).
When interrupt-driven data reception is used, the receive complete interrupt routine must read the received data
from DATA in order to clear RXCIF. If not, a new interrupt will occur directly after the return from the current inter-
rupt. This flag can also be cleared by writing a one to its bit location.
 Bit 6 – TXCIF: Transfer Complete Interrupt Flag
This flag is set when all the data in the transmit shift register has been shifted out and there are no new data in the
transmit buffer (DATA). The flag is cleared by writing a one to its bit location.
XMEGA E MANUAL 275

 Bit 5 – DREIF: Data Register Empty Interrupt Flag
This flag indicates whether the transmit buffer (DATA) is ready to receive new data. The flag is one when the trans-
mit buffer is empty and zero when the transmit buffer contains data to be transmitted that has not yet been moved
into the shift register. DREIF is set after a reset to indicate that the transmitter is ready.
DREIF is cleared by writing DATA. When interrupt-driven data transmission is used, the data register empty inter-
rupt routine must either write new data to DATA in order to clear DREIF or disable the data register empty
interrupt. If not, a new interrupt will occur directly after the return from the current interrupt.
 Bit 4 – SSIF: Slave Select Interrupt Flag
This flag indicates that the SPI has been in master mode and the SS line has been pulled low externally so the SPI
is now working in slave mode. The flag will only be set if the Slave Select Disable (SSD) is not enabled. The flag is
 Bit 0 – BUFOVF: Buffer Overflow
This flag indicates data loss due to a receiver buffer full condition. This flag is set if a buffer overflow condition is
detected. A buffer overflow occurs when the receive buffer is full (two characters) and the third byte has been
received. If there is no transmit data the buffer overflow will not be set before the start of a new serial transfer. This
flag is valid until the receive buffer (DATA) is read. Always write this bit location to zero when writing the STATUS
register.
Bit 7 6 5 4 3 2 1 0
+0x03 DATA[7:0]
 Bit 7:0 DATA[7:0] – SPI Data

The DATA register is used for sending and receiving data. Writing to the register initiates the data transmission,
and the byte written to the register will be shifted out on the SPI output line.
Reading the register causes the first byte in the buffer FIFO to be read. Additionally received bytes will then be
shifted in the FIFO.
Bit 7 6 5 4 3 2 1 0
+0x04 BUFMODE[1:0] – – – SSD – –
Read/Write R/W R/W R R R R/W R R
 Bit 7:6 – BUFMODE[1:0]: Buffer Modes

Setting these bits will enable the buffer modes for SPI. Buffers for both receive and transmit are added to the SPI.
XMEGA E MANUAL 276

Table 20-5. SPI Buffer Modes
BUFMODE[1:0] Group configuration Description
Unbuffered mode:
00 OFF - 1 buffer in reception, no buffer in transmission
- 1 interrupt flag for both transmission and reception
01 - Reserved
Buffer Mode 1:
- 2 buffers in reception, 1 buffer in transmission
10 BUFMODE1 - Separated interrupt flags for transmission and reception
- 1 SPI transfer must be completed before the data is copied into the shift
register, even after SPI enable (1st data transmitted = dummy byte)
Buffer Mode 2:
- 2 buffers in reception, 1 buffer in transmission
11 BUFMODE2 - Separated interrupt flags for transmission and reception
- Immediate write data into shift register after SPI enable. Then, 1 SPI
transfer must be completed before the data is copied into the shift register.

 Bit 2 – SSD: Slave Select Disable
Setting this bit will disable the Slave Select line when operating as SPI Master.
XMEGA E MANUAL 277

+0x00 CTRL CLK2X ENABLE DORD MASTER MODE[1:0] PRESCALER[1:0] 273

– – – – – –
+0x01 INTCTRL INTLVL[1:0] 274
RXCIE TXCIE DREIE SSIE – –
IF WRCOL – – – – – –
+0x02 STATUS 275
RXCIF TXCIF DREIF SSIF – – – BUFOVF
+0x03 DATA DATA[7:0] 276
+0x04 CTRLB BUFMODE[1:0] – – – SSD – – 276
+0x05 Reserved – – – – – – – –
+0x06 Reserved – – – – – – – –
+0x07 Reserved – – – – – – – –
Table 20-6. SPI Interrupt vectors and their word offset address
0x00 SPI_vect SPI interrupt vector
XMEGA E MANUAL 278

21. USART
21.1 Features
 Full-duplex or one-wire half-duplex operation
 Asynchronous or synchronous operation
 Synchronous clock rates up to 1/2 of the device clock frequency
 Asynchronous clock rates up to 1/8 of the device clock frequency
 Supports serial frames with:
 5, 6, 7, 8, or 9 data bits
 Optionally even and odd parity bits
 1 or 2 stop bits
 Fractional baud rate generator
 Can generate desired baud rate from any system clock frequency
 No need for external oscillator with certain frequencies
 Built-in error detection and correction schemes
 Odd or even parity generation and parity check
 Data overrun and framing error detection
 Noise filtering includes false start bit detection and digital low-pass filter
 Separate interrupts for
 Transmit complete
 Transmit Data Register empty
 Receive complete
 Multiprocessor communication mode
 Addressing scheme to address a specific devices on a multi-device bus
 Enable unaddressed devices to automatically ignore all frames
 Start Frame detection in UART mode
 Master SPI mode
 Double buffered operation
 Configurable data order
 Operation up to 1/2 of the peripheral clock frequency
 IRCOM module for IrDA compliant pulse modulation/demodulation
 Can be linked with XMEGA Custom Logic (XCL):
 Send and receive events from peripheral counter (PEC) to extend frame length
 Modulate/demodulate data within the frame by using the glue logic outputs
21.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication, asynchronous and synchronous operation and
one-wire configurations. The USART can be set in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
A block diagram of the USART and closely related peripheral modules (in grey) is shown in Figure 21-1 on page 280.The
main functional blocks are the clock generator, the transmitter, and the receiver, which are indicated in dashed boxes.
XMEGA E MANUAL 279

Figure 21-1. USART Block Diagram
Clock Generator
BSEL[H:L]
OSC
BAUD RATE GENERATOR

FRACTIONAL DIVIDE
SYNT LOGIC
PIN
XCK
CONTROL
Transmitter
XCL
TX PEC 1
DATA (Transmit)
CONTROL
DATA BUS
PARITY
TxD
GENERATOR PIN
CONTROL
TRANSMIT SHIFT REGISTER
XCL
LUT
OUT1
Receiver
CLOCK RX XCL
RECOVERY CONTROL PEC 0
DATA PIN RxD

RECEIVE SHIFT REGISTER
RECOVERY CONTROL RxD/TxD
XCL
LUT
PARITY
DATA (Receive) OUT 0
CHECKER
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
The transmitter consists of a single write buffer (DATA), a Shift Register and a parity generator. The write buffer allows
continuous data transmission without any delay between frames.
The receiver consists of a two-level receive buffer (DATA) and a Shift Register. Data and clock recovery units ensure
robust synchronization and noise filtering during asynchronous data reception. It includes frame error, buffer overflow,
and parity error detection.
When the USART is set in one-wire mode, the transmitter and the receiver share the same RxD I/O pin.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, Shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2kbps. For details, refer to “IRCOM – IR Communication Module” on page 304.
XMEGA E MANUAL 280

One USART can be linked to the XMEGA Custom Logic unit (XCL). When used with the XCL, the data length within an
USART/SPI frame can be controlled by the peripheral counter (PEC) within the XCL. In addition, the TxD/RxD data can
be encoded/decoded before the signal is fed into the USART receiver or after the signal is output from transmitter when
the USART is connected to XCL LUT outputs. For more details on how using and setting the LUT’s and PEC’s, refer to
“XCL – XMEGA Custom Logic” on page 308 module.
21.3 Clock Generation

The clock used for baud rate generation and for shifting and sampling data bits is generated internally by the fractional
baud rate generator or externally from the transfer clock (XCK) pin. Five modes of clock generation are supported:
normal and double-speed asynchronous mode, master and slave synchronous mode, and master SPI mode.
Figure 21-2. Clock Generation Logic Block Diagram

BSEL CLK2X
Baud Rate f BAUD /2 /4 /2 0

Generator
f OSC
0
DDR_XCK
txclk
PORT_INV
1
Synch Edge 0
Register Detector
XCK
UMSEL[1]
Pin
1
rxclk
0
21.3.1 Internal Clock Generation - The Fractional Baud Rate Generator

The fractional baud rate generator is used for internal clock generation for asynchronous modes, synchronous master
mode, and master SPI mode operation. The output frequency generated (fBAUD) is determined by the period setting
(BSEL), an optional scale setting (BSCALE), and the peripheral clock frequency (fPER). Table 21-1 on page 282 contains
equations for calculating the baud rate (in bits per second) and for calculating the BSEL value for each mode of
operation. It also shows the maximum baud rate versus peripheral clock frequency. BSEL can be set to any value
between 0 and 4095. BSCALE can be set to any value between -7 and +7, and increases or decreases the baud rate
slightly to provide the fractional baud rate scaling of the baud rate generator.
When BSEL is 0, BSCALE must also be 0. Also, the value 2ABS(BSCALE) must at most be one half of the minimum number
of clock cycles a frame requires. For more details, see “Internal Clock Generation - The Fractional Baud Rate Generator”
on page 281”.
XMEGA E MANUAL 281

Table 21-1. Equations for Calculating Baud Rate Register Setting
Operating mode Conditions Baud rate calculation (1) BSEL value calculation
BSCALE ≥ 0
f PER f PER
f PER f BAUD  BSEL  1
f BAUD  2 BSCALE
 16( BSEL  1) 2 BSCALE
 16 f BAUD
Asynchronous Normal
16
Speed mode (CLK2X = 0) BSCALE < 0
f PER 1  f PER 
f PER f BAUD  BSEL    1
f BAUD  BSCALE
 BSEL)  1) BSCALE
16
16((2 2  16 f BAUD 
BSCALE ≥ 0
f PER f PER
f PER f BAUD  BSEL  1
f BAUD  2 BSCALE
 8( BSEL  1) 2 BSCALE
 8 f BAUD
Asynchronous Double
8
Speed mode (CLK2X = 1) BSCALE < 0
f PER 1  f PER 
f PER f BAUD  BSEL    1
f BAUD  BSCALE
 BSEL)  1) BSCALE
8
8((2 2  8 f BAUD 
Synchronous and master f PER f PER f PER

f BAUD  f BAUD  BSEL  1
SPI mode
2 2( BSEL  1) 2 f BAUD
Notes: 1. The baud rate is defined to be the transfer rate bit per second (bps).
For BSEL = 0, all baud rates be achieved by changing BSEL instead of setting BSCALE: BSEL = (2 BSCALE-1).
BSCALE BSEL BSCALE BSEL
1 0  0 1
2 0  0 3
3 0  0 7
4 0  0 15
5 0  0 31
6 0  0 63
7 0  0 127
21.3.2 External Clock

External clock (XCK) is used in synchronous slave mode operation. The XCK clock input is sampled on the peripheral
clock frequency (fPER), and the maximum XCK clock frequency (fXCK) is limited by the following:
For each high and low period, XCK clock cycles must be sampled twice by the peripheral clock. If the XCK clock has
jitter, or if the high/low period duty cycle is not 50/50, the maximum XCK clock speed must be reduced accordingly.
21.3.3 Double Speed Operation

Double speed operation allows for higher baud rates under asynchronous operation with lower peripheral clock
frequencies. When this is enabled, the baud rate for a given asynchronous baud rate setting shown in Table 21-1 on
page 282 will be doubled. In this mode, the receiver will use half the number of samples (reduced from 16 to 8) for data
sampling and clock recovery. Due to the reduced sampling, a more accurate baud rate setting and peripheral clock are
required. See “Asynchronous Data Reception” on page 287 for more details.
XMEGA E MANUAL 282

21.3.4 Synchronous Clock Operation
When synchronous mode is used, the XCK pin controls whether the transmission clock is input (slave mode) or output
(master mode). The corresponding port pin must be set to output for master mode or to input for slave mode. The normal
port operation of the XCK pin will be overridden. The dependency between the clock edges and data sampling or data
change is the same. Data input (on RxD) is sampled at the XCK clock edge which is opposite the edge where data output
(TxD) is changed.
Figure 21-3. Synchronous Mode XCK Timing
INVEN = 1 XCK
RxD / TxD
Sample
INVEN = 0 XCK
RxD / TxD
Sample
Using the inverted I/O (INVEN) setting for the corresponding XCK port pin, the XCK clock edges used for data sampling
and data change can be selected. If inverted I/O is disabled (INVEN=0), data will be changed at the rising XCK clock
edge and sampled at the falling XCK clock edge. If inverted I/O is enabled (INVEN=1), data will be changed at the falling
XCK clock edge and sampled at the rising XCK clock edge. For more details, see “I/O Ports” on page 139.
21.3.5 Master SPI Mode Clock Generation

For master SPI mode operation, only internal clock generation is supported. This is identical to the USART synchronous
master mode, and the baud rate or BSEL setting is calculated using the same equations (see Table 21-1 on page 282).
There are four combinations of the SPI clock (SCK) phase and polarity with respect to the serial data, and these are
determined by the clock phase (UCPHA) control bit and the inverted I/O pin (INVEN) settings. The data transfer timing
diagrams are shown in Figure 21-4 on page 284.
Data bits are shifted out and latched in on opposite edges of the XCK signal, ensuring sufficient time for data signals to
stabilize. The UCPHA and INVEN (bit of POTRTx.PINnCTRL Register) settings are summarized in Table 21-2 on page
283. Changing the setting of any of these bits during transmission will corrupt both the receiver and transmitter.
Table 21-2. INVEN and UCPHA Functionality
SPI mode INVEN UCPHA Leading edge Trailing edge
0 0 0 Rising, sample Falling, setup
1 0 1 Rising, setup Falling, sample
2 1 0 Falling, sample Rising, setup
3 1 1 Falling, setup Rising, sample
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
XMEGA E MANUAL 283

Figure 21-4. UCPHA and INVEN Data Transfer Timing Diagrams
INVEN=0 INVEN=1
SPI Mode 1 SPI Mode 3
UCPHA=1
XCK XCK
Data setup (TXD) Data setup (TXD)
Data sample (RXD) Data sample (RXD)
SPI Mode 0 SPI Mode 2

UCPHA=0
XCK XCK
Data setup (TXD) Data setup (TXD)
Data sample (RXD) Data sample (RXD)
21.4 Frame Formats

Data transfer is frame based, where a serial frame consists of one character of data bits with synchronization bits (start
and stop bits) and an optional parity bit for error checking. Note that this does not apply to master SPI operation (See
“SPI Frame Formats” on page 285). The USART accepts all combinations of the following as valid frame formats:
 1 start bit
 5, 6, 7, 8 or 9 data bits
 variable data bits, controlled by the peripheral counter from XCL (PEC)
 no, even, or odd parity bit
 1 or 2 stop bits
A frame starts with the start bit, followed by all the data bits (least-significant bit first and most significant bit last). If
enabled, the parity bit is inserted after the data bits, before the first stop bit. One frame can be directly followed by a start
bit and a new frame, or the communication line can return to the idle (high) state. Figure 21-5 illustrates the possible
combinations of frame formats. Bits inside brackets are optional.
Figure 21-5. Frame Formats
FRAME
(IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE)
St Start bit, always low.

(n) Data bits (0 to 8 in standard mode, variable when controlled by PEC).
P Parity bit, may be odd or even.
Sp Stop bit, always high.
IDLE No transfer on the communication line (RxD or TxD). The IDLE state is always high.
21.4.1 Parity Bit Calculation

Even or odd parity can be selected for error checking. If even parity is selected, the parity bit is set to one if the number of
logical one data bits is odd (making the total number of ones even). If odd parity is selected, the parity bit is set to one if
the number of logical one data bits is even (making the total number of ones odd).
When variable data length mode is enabled, the parity bit calculation is not supported.
XMEGA E MANUAL 284

21.4.2 SPI Frame Formats
The serial frame in SPI mode is defined to be one character of eight data bits. The USART in master SPI mode has three
valid frame formats:
 8-bit data, msb first
 8-bit data, lsb first
 variable data bits (lsb first), controlled by the peripheral counter from XCL (PEC)
After a complete frame is transmitted, a new frame can directly follow it, or the communication line can return to the idle
(high) state.
21.5 USART Full-duplex Initialization

For setting the USART in full-duplex mode, the following initialization sequence is recommended:
1. Set the TxD pin value high, and optionally set the XCK pin low.
2. Set the TxD and optionally the XCK pin as output.
3. Set the baud rate and frame format.
4. Set the mode of operation (enables XCK pin output in synchronous mode).
5. Optionally configure the XCL for variable data length and encoding/decoding truth table.
6. Enable the transmitter or the receiver, depending on the usage.
For interrupt-driven USART operation, global interrupts should be disabled during the initialization.
Before doing a re-initialization with a changed baud rate or frame format, be sure that there are no ongoing transmissions
while the registers are changed.
21.6 USART One-wire Initialization

For setting the USART in one-wire mode, the following initialization sequence is recommended:
1. Set the TxD/RxD pin value high, and optionally set the XCK pin low.
2. Optionally, set the TxD/RxD input pin as Wired-AND or Wired-OR.
3. Set the TxD/RxD and optionally the XCK pin as output.
4. Set the baud rate and frame format.
5. Set the mode of operation (enables XCK pin output in synchronous mode).
6. Optionally configure the XCL for variable data length and encoding/decoding truth table.
7. Enable the transmitter or the receiver, depending on the usage.
For interrupt-driven USART operation, global interrupts should be disabled during the initialization.
Before doing a re-initialization with a changed baud rate or frame format, be sure that there are no ongoing transmissions
while the registers are changed.
21.7 Data Transmission - The USART Transmitter

When the transmitter has been enabled, the normal port operation of the TxD pin is overridden by the USART and given
the function as the transmitter's serial output. The direction of the pin must be set as output using the direction register for
the corresponding port. For details on port pin control and output configuration, refer to “I/O Ports” on page 139. If the
USART is configured for one-wire operation, the USART will automatically override the RxD/TxD pin to output, when the
transmitter is enabled.
21.7.1 Sending Frames

A data transmission is initiated by loading the transmit buffer (DATA) with the data to be sent. The data in the transmit
buffer are moved to the Shift Register when the Shift Register is empty and ready to send a new frame. The Shift
Register is loaded if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame
is transmitted. When the Shift Register is loaded with data, it will transfer one complete frame.
XMEGA E MANUAL 285

When the data frame length is controlled by the peripheral counter in the XCL unit, the XCL and event controlled mode in
USART have to be initiated before enabling the transmitter. In variable data length mode, the minimum frame length is
one bit, the maximum is 256 bits. The maximum size must be chosen according to the oscillator accuracy.
A transmission is initiated by loading the transmit buffer (DATA) with the data to be sent. When the first data is loaded in
the Shift Register, the USART provides the restart command to the peripheral counter. Each bit shift will decrement the
peripheral counter. A compare match is provided by the XCL when the internal counter value reaches BOTTOM (zero).
While the compare match is not received, the USART continues to shift out the data bits. If the compare match occurs
before completing an 8-bit data shift, the USART changes its state to stop bits. If the Shift Register is empty before the
compare match is received, then new data is automatically loaded in the Shift Register and transmission continues. If
there is no more data to transmit and the compare match is not received, the transmission is aborted and Data Register
empty flag (DREIF) is generated. The USART returns to IDLE state and stops any event generation for peripheral
counter. The user can then calculate the number of bits already sent over the line.
When not used with the EDMA, the system has to spend the minimum of time in the interrupt routine to load new data in
the DATA Register.
The transmit complete interrupt flag (TXCIF) is set and the optional interrupt is generated when the entire frame in the
Shift Register has been shifted out and there are no new data present in the transmit buffer.
The Transmit Data Register (DATA) can only be written when the Data Register Empty Flag (DREIF) is set, indicating
that the register is empty and ready for new data.
When using frames with fewer than eight bits, the most-significant bits written to DATA are ignored. If 9-bit characters are
used, the ninth bit must be written to the TXB8 bit before the low byte of the character is written to DATA.
21.7.2 Disabling the Transmitter

A disabling of the transmitter will not become effective until ongoing and pending transmissions are completed; i.e., when
the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted and optionally while the
compare match is not received from peripheral counter. In this case, it is possible to write 0x00 to the peripheral Counter
Register to generate the compare match. When the transmitter is disabled, it will no longer override the TxDn pin, and the
pin direction is set as input automatically by hardware, even if it was configured as output by the user.
21.8 Data Reception - The USART Receiver

When the receiver is enabled, the RxD pin functions as the receiver's serial input. The direction of the pin must be set as
input, which is the default pin setting.
21.8.1 Receiving Frames

The receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the
baud rate or XCK clock and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second
stop bit will be ignored by the receiver. When the first stop bit is received and a complete serial frame is present in the
Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive complete
interrupt flag (RXCIF) is set, and the optional interrupt is generated.
When the data frame length is controlled by the peripheral counter in the XCL unit, the XCL and event controlled mode in
USART have to be initiated before enabling the receiver. When a start bit is detected, the USART sends the restart
command to the peripheral counter.
Each bit shift will decrement the peripheral counter. A compare match is provided by the XCL when the internal counter
value reaches BOTTOM (zero). While the compare match is not received, the USART continues to shift in the data bits.
If the compare match occurs before completing an 8-bit data shifts, the USART changes its state to stop bits. After each
8-bit data reception, data receive flag (DRIF) and optionally an interrupt, is generated. If the data buffer overflow
condition is generated, the reception is aborted and buffer overflow flag is set. No more counter commands are
generated for the peripheral counter while a new start bit condition is not detected. In such error condition, it is highly
recommended to disable the receiver part, unless any falling edge will be considered as a valid start bit and the
peripheral counter can automatically restart its operation. Data receive interrupt flag and receive complete interrupt flag
XMEGA E MANUAL 286

share the same interrupt line and interrupt settings. When not used with the EDMA, the system has to spend the
minimum of time in the interrupt routine to read data from Data Register (DATA).
The receiver buffer can be read by reading the Data Register (DATA) location. DATA should not be read unless the
receive complete interrupt flag is set. When using frames with fewer than eight bits, the unused most-significant bits are
read as zero. If 9-bit characters are used, the ninth bit must be read from the RXB8 bit before the low byte of the
character is read from DATA.
If data frame length is controlled by the peripheral timer, the RXB8 bit is unused during reception. This bit location will be
used to store the data reception flag.
21.8.2 Receiver Error Flags

The USART receiver has three error flags. The frame error (FERR), buffer overflow (BUFOVF) and parity error (PERR)
flags are accessible from the Status Register. The error flags are located in the receive FIFO buffer together with their
corresponding frame. Due to the buffering of the error flags, the Status Register must be read before the receive buffer
(DATA), since reading the DATA location changes the FIFO buffer.
21.8.3 Parity Checker

When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit of the corresponding frame. If a parity error is detected, the parity error flag is set.
When variable data length mode is enabled, the parity checker is not supported.
21.8.4 Disabling the Receiver

A disabling of the receiver will be immediate. The receiver buffer will be flushed, and data from ongoing receptions will be
lost.
21.8.5 Flushing the Receive Buffer

If the receive buffer has to be flushed during normal operation, read the DATA location until the receive complete
interrupt flag is cleared.
21.9 Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock
recovery unit is used for synchronizing the incoming asynchronous serial frames at the RxD pin to the internally
generated baud rate clock. It samples and low-pass filters each incoming bit, thereby improving the noise immunity of the
receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the
rate of the incoming frames, and the frame size in number of bits.
21.9.1 Asynchronous Clock Recovery

The clock recovery unit synchronizes the internal clock to the incoming serial frames. Figure 21-6 on page 288 illustrates
the sampling process for the start bit of an incoming frame. The sample rate is 16 times the baud rate for normal mode,
and eight times the baud rate for double speed mode. The horizontal arrows illustrate the synchronization variation due
to the sampling process. Note the larger time variation when using the double speed mode of operation. Samples
denoted as zero are samples done when the RxD line is idle; i.e., when there is no communication activity.
XMEGA E MANUAL 287

Figure 21-6. Start Bit Sampling
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection
sequence is initiated. Sample 1 denotes the first zero-sample, as shown in the figure. The clock recovery logic then uses
samples 8, 9, and 10 for normal mode and samples 4, 5, and 6 for double speed mode to decide if a valid start bit is
received. If two or three samples have a low level, the start bit is accepted. The clock recovery unit is synchronized, and
the data recovery can begin. If two or three samples have a high level, the start bit is rejected as a noise spike, and the
receiver looks for the next high-to-low transition. The process is repeated for each start bit.
21.9.2 Asynchronous Data Recovery

The data recovery unit uses sixteen samples in normal mode and eight samples in double speed mode for each bit.
Figure 21-7 shows the sampling process of data and parity bits.
Figure 21-7. Sampling of Data and Parity Bits
RxD BIT n
Sample
(CLK2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(CLK2X = 1) 1 2 3 4 5 6 7 8 1
As for start bit detection, an identical majority voting technique is used on the three center samples for deciding of the
logic level of the received bit. The process is repeated for each bit until a complete frame is received. It includes the first
stop bit, but excludes additional ones. If the sampled stop bit is a 0 value, the frame error (FERR) flag will be set. Figure
21-8 shows the sampling of the stop bit in relation to the earliest possible beginning of the next frame's start bit.
Figure 21-8. Stop Bit and Next Start Bit Sampling
RxD STOP 1 (A) (B) (C)
Sample
(CLK2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(CLK2X = 1) 1 2 3 4 5 6 0/1
A new high-to-low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. For normal speed mode, the first low level sample can be at the point marked (A) in Stop Bit Sampling
and Next Start Bit Sampling. For double speed mode, the first low level must be delayed to point (B). Point (C) marks a
stop bit of full length at nominal baud rate. The early start bit detection influences the operational range of the receiver.
XMEGA E MANUAL 288

21.9.3 Asynchronous Operational Range
The operational range of the receiver is dependent on the mismatch between the received bit rate and the internally
generated baud rate. If an external transmitter is sending using bit rates that are too fast or too slow, or if the internally
generated baud rate of the receiver does not match the external source’s base frequency, the receiver will not be able to
synchronize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate.
( D  1) S ( D  2) S
Rslow  R fast 
S 1 D  S  SF ( D  1)  S  S M
D Sum of character size and parity size (D = 5 to 10 bit).
S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.
SF First sample number used for majority voting. SF = 8 for normal speed and SF = 4 for Double Speed mode.
SM Middle sample number used for majority voting. SM = 9 for normal speed and SM = 5 for Double Speed
mode.
Rslow Is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate.
Rfast Is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate.
Table 21-3 and Table 21-4 list the maximum receiver baud rate error that can be tolerated. Normal Speed mode has
higher toleration of baud rate variations.
Table 21-3. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (CLK2X = 0)
D #(Data + Parity bit) Rslow [%] Rfast [%] Maximum total error [%] Receiver max. receiver error [%]
5 93.20 106.67 +6.67/-6.80 ±3.0
6 94.12 105.79 +5.79/-5.88 ±2.5
7 94.81 105.11 +5.11/-5.19 ±2.0
8 95.36 104.58 +4.58/-4.54 ±2.0
9 95.81 104.14 +4.14/-4.19 ±1.5
10 96.17 103.78 +3.78/-3.83 ±1.5
Table 21-4. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (CLK2X = 1)
D #(Data + Parity bit) Rslow [%] Rfast [%] Maximum total error [%] Receiver max. receiver error [%]
5 94.12 105.66 +5.66/-5.88 ±2.5
6 94.92 104.92 +4.92/-5.08 ±2.0
7 95.52 104.35 +4.35/-4.48 ±1.5
8 96.00 103.90 +3.90/-4.00 ±1.5
9 96.39 103.53 +3.53/-3.61 ±1.5
10 96.70 103.23 +3.23/-3.30 ±1.0
The recommendations of the maximum receiver baud rate error were made under the assumption that the Receiver and
Transmitter equally divide the maximum total error.
XMEGA E MANUAL 289

21.9.4 Start Frame Detection
The start frame detection is supported in UART mode only and takes place only if the system is in deeper sleep modes.
The UART start frame detector can wake up the system from power save, standby or extended standby sleep modes
when a start bit is detected. In power save mode, the internal 8MHz oscillator in low power mode must be used as clock
source, but in standby or extended standby modes it can operate with any clock source.
When a high-to-low transition is detected on RxDn, the oscillator is powered up and the UART clock is enabled. After
start-up, the rest of the data frame can be received, provided that the baud rate is slow enough in relation to the oscillator
start-up time. Start-up time of the oscillators varies with supply voltage and temperature. For details on oscillator start-up
time characteristics, refer to device datasheet.
If a false start bit is detected and if the system has not been waken-up by another source, the oscillator will be
automatically powered-off and the UART waits for the next transition.
The UART start frame detection works in asynchronous mode only. It is enabled by writing the Start Frame Detection bit
(SFDEN) in “CTRLB – Control Register B” on page 298”. If the start bit is detected, the UART Start Interrupt Flag (RXSIF)
bit is set.
In active and idle sleep modes, the asynchronous detection is automatically disabled. In power down sleep mode, the
asynchronous detector is enabled, but the internal oscillator is never powered. In such case, it is highly recommended to
disable the start detector before going in power down sleep mode.
The UART receive complete flag and UART start interrupt flag share the same interrupt line, but each has its dedicated
interrupt settings. The Table 21-5 shows the USART start frame detection modes, depending of interrupt setting.
Table 21-5. USART Start Frame Detection Modes
SFDEN RXSIF interrupt RXCIF interrupt Comment
0 x x Standard mode
Only the oscillator is powered during the frame reception.

1 Disabled Disabled If the interrupts are disabled and buffer overflow is
ignored, all incoming frames will be lost
System/all clocks waked-up on Receive Complete

1 (1) Disabled Enabled
interrupt
1 (1) Enabled x System/all clocks waked-up on UART Start Detection
Note: 1. The SLEEP instruction will not shut down the oscillator if on going communication.
21.10 Fractional Baud Rate Generation

Fractional baud rate generation is possible for asynchronous operation due to the relatively high number of clock cycles
for each frame. Each bit is sampled sixteen times, but only the three middle samples are of importance. The total number
of samples for one frame is also relatively high. Given a 1-start, 8-data, no-parity, and 1-stop-bit frame format, and
assuming that normal speed mode is used, the total number of samples for a frame is (1+8+1) × 16 or 160. As stated
earlier, the UART can tolerate some variation in clock cycles for each sample. The critical factor is the time from the
falling edge of the start bit (i.e., the clock synchronization) until the last bit's (i.e., the first stop bit’s) value is recovered.
Standard baud rate generators have the unwanted property of having large frequency steps between high baud rate
settings. The worst case is found between the BSEL values 0x000 and 0x001. Going from a BSEL value of 0x000, which
has a 10-bit frame of 160 clock cycles, to a BSEL value of 0x001, with 320 clock cycles, gives a 50% change in
frequency. Ideally, the step size should be small even between the fastest baud rates. This is where the advantage of the
fractional baud rate generator emerges.
XMEGA E MANUAL 290

In principle, the fractional baud rate generator works by doing uneven counting and then distributing the error evenly over
the entire frame. A typical count sequence for an ordinary baud rate generator is:
2, 1, 0, 2, 1, 0, 2, 1, 0, 2, …
which has an even period time. A baud rate clock ticks each time the counter reaches zero, and a sample of the signal
received on RxD is taken for every 16th baud rate clock tick.
For the fractional baud rate generator, the count sequence can have an uneven period:
2, 1, 0, 2, 1-1, 0, 2, 1, 0, 2, 1-1, 0,...
In this example, an extra cycle is added to every second baud clock. This gives a baud rate clock tick jitter, but the
average period has been increased by a fraction of 0.5 clock cycles.
Figure 21-9 shows an example of how BSEL and BSCALE can be used to achieve baud rates in between what is
possible by just changing BSEL.
The impact of fractional baud rate generation is that the step size between baud rate settings has been reduced. Given a
scale factor of -1, the worst-case step then becomes from 160 to 240 clock cycles per 10-bit frame, compared to the
previous step of from 160 to 320. A higher negative scale factor gives even finer granularity. There is a limit, however, to
how high the scale factor can be. The value 2|BSCALE| must be at most half the minimum number of clock cycles of a
frame. For instance, for 10-bit frames, the minimum number of clock cycles is 160. This means that the highest
applicable scale factor is -6 (2-6 = 64 < 160/2 = 80). For higher BSEL settings, the scale factor can be increased.
Figure 21-9. Fractional Baud Rate Example
BSEL=0
BSCALE=0
fBAUD=f PER/8
clkBAUD8
BSEL=3
BSCALE=-6
fBAUD=f PER/8.375
clkBAUD8
Extra clock cycle added
BSEL=3
BSCALE=-4
fBAUD=f PER/9.5
clkBAUD8
XMEGA E MANUAL 291

Table 21-6. USART Baud Rate
Baud fOSC = 32.0000MHz
CLK2X = 0 CLK2X = 1
rate (bps)
BSEL BSCALE Error [%] BSEL BSCALE Error [%]
2400 12 6 0.2 12 7 0.2
4800 12 5 0.2 12 6 0.2
9600 12 4 0.2 12 5 0.2
34 2 0.8 34 3 0.8
14.4k
138 0 -0.1 138 1 -0.1
19.2k 12 3 0.2 12 4 0.2
34 1 -0.8 34 2 -0.8
28.8k
137 -1 -0.1 138 0 -0.1
38.4k 12 2 0.2 12 3 0.2
34 0 -0.8 34 1 -0.8
57.6k
135 -2 -0.1 137 -1 -0.1
76.8k 12 1 0.2 12 2 0.2
33 -1 -0.8 34 0 -0.8
115.2k
131 -3 -0.1 135 -2 -0.1
31 -2 -0.8 33 -1 -0.8
230.4k
123 -4 -0.1 131 -3 -0.1
27 -3 -0.8 31 -2 -0.8
460.8k
107 -5 -0.1 123 -4 -0.1
19 -4 -0.8 27 -3 -0.8
921.6k
75 -6 -0.1 107 -5 -0.1
7 -4 0.6 15 -3 0.6
1.382M
57 -7 0.1 121 -6 0.1
3 -5 -0.8 19 -4 -0.8
1.843M
11 -7 -0.1 75 -6 -0.1
2.00M 0 0 0.0 1 0 0.0
3 -2 -0.8
2.304M – – –
47 -6 -0.1
19 -4 0.4
2.5M – – –
77 -7 -0.1
XMEGA E MANUAL 292

Baud fOSC = 32.0000MHz
11 -5 -0.8
3.0M – – –
43 -7 -0.2
4.0M – – – 0 0 0.0
Max. 2.0Mbps 4.0Mbps
21.11 USART in Master SPI mode

Using the USART in master SPI mode requires the transmitter to be enabled. The receiver can optionally be enabled to
serve as the serial input. The XCK pin will be used as the transfer clock.
As for the USART, a data transfer is initiated by writing to the DATA Register. This is the case for both sending and
receiving data, since the transmitter controls the transfer clock. The data written to DATA are moved from the transmit
buffer to the Shift Register when the Shift Register is ready to send a new frame.
The transmitter and receiver interrupt flags and corresponding USART interrupts used in master SPI mode are identical
in function to their use in normal USART operation. The receiver error status flags are not in use and are always read as
zero.
Disabling of the USART transmitter or receiver in master SPI mode is identical to their disabling in normal USART
operation.
21.12 USART SPI vs. SPI

The USART in master SPI mode is fully compatible with the standalone SPI module in that:
 Timing diagrams are the same
 UCPHA bit functionality is identical to that of the SPI CPHA bit
 UDORD bit functionality is identical to that of the SPI DORD bit
When the USART is set in master SPI mode, configuration and use are in some cases different from those of the
standalone SPI module. In addition, the following difference exists:
 The USART in master SPI mode does not include the SPI (Write Collision) feature
The USART in master SPI mode does not include the SPI double speed mode feature, but this can be achieved by
configuring the baud rate generator accordingly:
 Interrupt timing is not compatible
 Pin control differs due to the master-only operation of the USART in SPI master mode
A comparison of the USART in master SPI mode and the SPI pins is shown in Table 21-7.
Table 21-7. Prescaler Options
USART SPI Comment
TxD MOSI Master out only
RxD MISO Master in only
XCK SCK Functionally identical
N/A SS Not supported by USART in master SPI mode
XMEGA E MANUAL 293

21.13 Multiprocessor Communication Mode
The multiprocessor communication mode effectively reduces the number of incoming frames that have to be handled by
the receiver in a system with multiple microcontrollers communicating via the same serial bus. In this mode, a dedicated
bit in the frames is used to indicate whether the frame is an address or data frame type.
If the receiver is set up to receive frames that contain five to eight data bits, the first stop bit is used to indicate the frame
type. If the receiver is set up for frames with nine data bits, the ninth bit is used. When the frame type bit is one, the frame
contains an address. When the frame type bit is zero, the frame is a data frame. If 5-bit to 8-bit character frames are
used, the transmitter must be set to use two stop bits, since the first stop bit is used for indicating the frame type.
If a particular slave MCU has been addressed, it will receive the following data frames as usual, while the other slave
MCUs will ignore the frames until another address frame is received.
21.13.1 Using Multiprocessor Communication Mode

The following procedure should be used to exchange data in multiprocessor communication mode (MPCM):
1. All slave MCUs are in multiprocessor communication mode.
2. The master MCU sends an address frame, and all slaves receive and read this frame.
3. Each slave MCU determines if it has been selected.
4. The addressed MCU will disable MPCM and receive all data frames. The other slave MCUs will ignore the data
frames.
5. When the addressed MCU has received the last data frame, it must enable MPCM again and wait for a new
address frame from the master.
The process then repeats from step 2.
Using any of the 5- to 8-bit character frame formats is impractical, as the receiver must change between using n and n+1
character frame formats. This makes full-duplex operation difficult, since the transmitter and receiver must use the same
character size setting.
21.14 One-wire Mode

In this mode the TxD pin is connected to the RxD pin internally. If the receiver is enabled when transmitting it will receive
what the transmitter is sending. This can be used to check that no one else is trying to transmit since received data will
not be the same as the transmitted data.
21.15 Data Encoding/Decoding

When this mode is used, the USART frame can be encoded or decoded using the LUT units in the XCL module, as
shown in Figure 21-1 on page 280. For more details on how using and setting the LUT’s, refer to “XCL – XMEGA Custom
Logic” on page 308 module.
The USART can support independent encoding or decoding operation, each with dedicated lookup table. The USART
implements different encoding and decoding types, but these options apply to both transmitter and receiver internal
engines.
In transmission, and depending on encoding type settings, data sent to the pin is taken from the USART output or from
XCL LUT1 output directly. In reception and depending on the decoding type settings, the data sent to the USART is taken
directly from pin or from XCL LUT0 output.
For mode details on decoding/encoding types, refer to “CTRLD – Control Register D” on page 301 description.
XMEGA E MANUAL 294

Figure 21-10.USART Encoding/Decoding Scheme
DIRx
XCK
Clock
Control Digital Input Pin
DIRy
Base
OUTy RxD
USART
(*)
LUT0 IN0 Digital Input Pin
Receive OUT0 Δ
Truth
Δ
Shift Table IN1
Register
FSM
IN2 LUT1(*)
Transmit Δ OUT1
Truth
Δ
DIRz
Shift IN3 Table
Register TxD
Input Pin
(*) Belongs to XCL module
21.16 IRCOM Mode of Operation

IRCOM mode can be enabled to use the IRCOM module with the USART. This enables IrDA 1.4 compliant modulation
and demodulation for baud rates up to 115.2kbps. When IRCOM mode is enabled, double speed mode cannot be used
for the USART. For devices with more than one USART, IRCOM mode can be enabled for only one USART at a time,
which is not linked with the XCL module. For details, refer to “IRCOM – IR Communication Module” on page 304.
21.17 EDMA Support

EDMA support is available on UART, USART, and master SPI mode peripherals. For details on different USART EDMA
transfer triggers, refer to “Transfer Triggers” on page 53.
In variable data length receive mode, the data reception flag is used to trigger an EDMA transfer.
XMEGA E MANUAL 295

Bit 7 6 5 4 3 2 1 0
RXB[7:0]
+0x00
TXB[7:0]
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address
referred to as USART Data Register (DATA). The Transmit Data Buffer Register (TXB) will be the destination for data
written to the DATA Register location. Reading the DATA Register location will return the contents of the Receive Data
Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver.
The transmit buffer can only be written when the DREIF Flag in the STATUS Register is set. Data written to DATA when
the DREIF Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the
Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is
empty. The data is then transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO and the corresponding flags in the Status Register (STATUS)
will change state whenever the receive buffer is accessed (read). Always read STATUS before DATA in order to get the
correct flags.
Bit 7 6 5 4 3 2 1 0
+0x01 RXCIF TXCIF DREIF FERR BUFOVF PERR RXSIF RXB8/DRIF
Read/Write R/W R/W R/W R/W R/W R/W R R/W
 Bit 7 – RXCIF: Receive Complete Interrupt Flag

In standard mode, this flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). When the Receiver is disabled, the receive buffer will be
flushed and consequently the RXCIF will become zero.
from DATA in order to clear the RXCIF. If not, a new interrupt will occur directly after the return from the current
interrupt. This flag can also be cleared by writing a one to its bit location.
In variable data length mode, this flag is generated when the valid STOP bit is detected. The DRIF status bit indi-
cates if unread data in receive buffer is present or not. Since the RXCIF interrupt shares the interrupt address with
the DRIF interrupt, RXCIF will not be cleared when the interrupt vector is executed. The flag is cleared by writing a
one to its bit location.
 Bit 6 – TXCIF: Transmit Complete Interrupt Flag
This flag is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data
in the transmit buffer (DATA). The TXCIF is automatically cleared when the transmit complete interrupt vector is
executed. The flag can also be cleared by writing a one to its bit location.
XMEGA E MANUAL 296

 Bit 5 – DREIF: Data Register Empty Flag
The DREIF indicates if the transmit buffer (DATA) is ready to receive new data. The flag is one when the transmit
buffer is empty, and zero when the transmit buffer contains data to be transmitted that has not yet been moved into
the Shift Register. DREIF is set after a reset to indicate that the Transmitter is ready. Always write this bit to zero
when writing the STATUS Register.
DREIF is cleared by writing DATA. When interrupt-driven data transmission is used, the Data Register Empty
interrupt routine must either write new data to DATA in order to clear DREIF or disable the Data Register Empty
interrupt. If not, a new interrupt will occur directly after the return from the current interrupt.
 Bit 4 – FERR: Frame Error
The FERR flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The bit
is set if the received character had a Frame Error, i.e. when the first stop bit was zero, and cleared when the stop
bit of the received data is one. This bit is valid until the receive buffer (DATA) is read. The FERR is not affected by
setting the SBMODE bit in CTRLC since the Receiver ignores all, except for the first stop bit. Always write this bit
location to zero when writing the STATUS Register.
This flag is not used in master SPI mode operation.
 Bit 3 – BUFOVF: Buffer Overflow
The BUFOVF flag indicates data loss due to a receiver buffer full condition. This flag is set if a Buffer Overflow con-
dition is detected. A Buffer Overflow occurs when the receive buffer is full (two characters), it is a new character
waiting in the Receive Shift Register, a new start bit is detected in standard mode, or a new bit is received in vari-
able data length mode. This flag is valid until the receive buffer (DATA) is read. Always write this bit location to
zero when writing the STATUS Register.
 Bit 2 – PERR: Parity Error
If parity checking is enabled and the next character in the receive buffer has a Parity Error this flag is set. If Parity
Check is not enabled the PERR will always be read as zero. This bit is valid until the receive buffer (DATA) is read.
Always write this bit location to zero when writing the STATUS Register. For details on parity calculation refer to
“Parity Bit Calculation” on page 284.
 Bit 1 – RXSIF: RX Start Flag
The RXSIF flag indicates a valid start condition on RxD line. The flag is set when the system is in power save,
standby or extended standby modes and a high (IDLE) to low (START) valid transition is detected on the RxD line.
If the start detection is not enabled, the RXSIF will always be read as zero.
When interrupt-driven data reception is used, the receive complete interrupt routine must read the STATUS Regis-
ter first. This flag can only be cleared by writing a one to its bit location.
 Bit 0 – RXB8: Receive Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. When
used, this bit must be read before reading the low bits from DATA. This bit is unused when peripheral counter con-
trols the frame data length.
 Bit 0 – DRIF: Data Reception Flag
This flag is set in variable data length mode only when there are unread data in the receive buffer. The flag is
cleared when the receive buffer is empty (i.e., does not contain any unread data). When the Receiver is disabled,
the receive buffer will be flushed and consequently the DRIF will become zero.
Optionally an interrupt can be generated. The DRIF interrupt shares the interrupt address with the RXCIF interrupt.
from DATA in order to clear the DRIF. If not, a new interrupt will occur directly after the return from the current
interrupt. This flag can also be cleared by writing a one to its bit location.
XMEGA E MANUAL 297

Bit 7 6 5 4 3 2 1 0
+0x02 RXSIE DRIE RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0]
 Bit 7 – RXSIE: Receive Start of Frame Interrupt Enable

Setting this bit enables the start of frame interrupt. The interrupt level is controlled by receive complete interrupt
level bits settings.
The enabled interrupt will trigger for the conditions when RXSIF flag is set.
 Bit 6 – DRIE: Data Reception Interrupt Enable
Setting this bit enables the data reception interrupt. The interrupt level is controlled by receive complete interrupt
level bits settings.
The enabled interrupt will trigger for the conditions when DRIF flag is set.
 Bit 5:4 – RXCINTLVL[1:0]: Receive Complete Interrupt Level
These bits enable the Receive Complete Interrupt and select the interrupt level as described in“PMIC – Interrupts
and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will be triggered when the
RXCIF in the STATUS Register is set.
 Bit 3:2 – TXCINTLVL[1:0]: Transmit Complete Interrupt Level
These bits enable the Transmit Complete Interrupt and select the interrupt level as described in “PMIC – Interrupts
and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will be triggered when the
TXCIF in the STATUS Register is set.
 Bit 1:0 – DREINTLVL[1:0]: Data Register Empty Interrupt Level
These bits enable the Data Register Empty Interrupt and select the interrupt level as described in “PMIC – Inter-
rupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will be triggered when
the DREIF in the STATUS Register is set.
Bit 7 6 5 4 3 2 1 0
+0x03 ONEWIRE SFDEN – RXEN TXEN CLK2X MPCM TXB8
Read/Write R/W R/W R R/W R/W R/W R R/W
 Bit 7 – ONEWIRE: One-Wire Configuration Enabled

Setting this bit enables the USART TxD and RxD pins multiplexing, as described in “One-wire Mode” on page 294.
 Bit 6 – SFDEN: Start Frame Detection Enable
Writing this bit to one enables the USART Start Frame Detection mode. The start frame detector is able to wake up
the system from power-save or standby sleep modes when a high (IDLE) to low (START) transition is detected on
the RxDn line, as described in “Start Frame Detection” on page 290. The bit setting is ignored if the system is in
the IDLE or ACTIVE modes. If the bit is set, the corresponding RXD pin has to be driven to avoid power consump-
tion is deep sleep modes.
This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit zero
 Bit 4 – RXEN: Receiver Enable
Setting this bit enables the USART Receiver. The receiver will override normal port operation for the RxD pin when
enabled. Disabling the receiver will flush the receive buffer invalidating the FERR, BUFOVF, and PERR flags.
 Bit 3 – TXEN: Transmitter Enable
Setting this bit enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin
when enabled. Disabling the Transmitter (writing TXEN to zero) will not become effective until ongoing and pend-
XMEGA E MANUAL 298

ing transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not
contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD port.
 Bit 2 – CLK2X: Double Transmission Speed
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for
asynchronous communication modes.
 Bit 1 – MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, the USART
Receiver ignores all the incoming frames that do not contain address information. The Transmitter is unaffected by
the MPCM setting. For more detailed information see “Multiprocessor Communication Mode” on page 294.
 Bit 0 – TXB8: Transmit Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits.
When used, this bit must be written before writing the low bits to DATA. This bit is ignored when peripheral counter
controls the frame data length.
Bit 7 6 5 4 3 2 1 0
+0x04 CMODE[1:0] PMODE[1:0] SBMODE CHSIZE[2:0]
+0x04 (1) CMODE[1:0] – – – UDORD UCPHA –
Note: 1. Master SPI mode.
 Bit 7:6 – CMODE[1:0]: Communication Mode

These bits select the mode of operation of the USART as shown in Table 21-8.
Table 21-8. CMODE Bit Settings
CMODE[1:0] Group configuration Mode
00 ASYNCHRONOUS Asynchronous USART
01 SYNCHRONOUS Synchronous USART
10 IRCOM IRCOM (1)
11 MSPI Master SPI (2)
Note: 1. See “IRCOM – IR Communication Module” on page 304 for full description on using IRCOM mode.
2. See “USART in Master SPI mode” on page 293 for full description of master SPI operation.
 Bit 5:4 – PMODE[1:0]: Parity Mode

These bits enable and set the type of parity generation according to Table 21-9 on page 300. When enabled, the
transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The
receiver will generate a parity value for the incoming data and compare it to the PMODE setting and if a mismatch
is detected, the PERR flag in STATUS will be set.
XMEGA E MANUAL 299

Table 21-9. PMODE Bit Settings
PMODE[1:0] Group configuration Mode
00 DISABLED Disabled
01 – Reserved
10 EVEN Enabled, Even Parity
11 ODD Enabled, Odd Parity
 Bit 3 – SBMODE: Stop Bit Mode

This bit selects the number of stop bits to be inserted by the transmitter according to Table 21-10. The receiver
ignores this setting.
Table 21-10. SBMODE Bit Settings
SBMODE Stop bit(s)
0 1-bit
1 2-bit
 Bit 2:0 – CHSIZE[2:0]: Character Size

The CHSIZE[2:0] bits sets the number of data bits in a frame according to Table 21-11. The receiver and transmit-
ter use the same setting. The CHSIZE bits settings are ignored when peripheral counter controls the frame data
length.
Table 21-11. CHSIZE Bits Settings
CHSIZE[2:0] Group configuration Character size
000 5BIT 5-bit
001 6BIT 6-bit
010 7BIT 7-bit
011 8BIT 8-bit
100 – Reserved
101 – Reserved
110 – Reserved
111 9BIT 9-bit
 Bit 2 – UDORD: Data Order

This bit sets the frame format. When written to one, the lsb of the data word is transmitted first. When written to
zero, the msb of the data word is transmitted first. The receiver and transmitter use the same setting. Changing the
setting of UDORD will corrupt all ongoing communication for both receiver and transmitter. This bit is valid only for
master SPI mode.
In variable data length mode, this bit must be set to one.
 Bit 1 – UCPHA: Clock Phase
The UCPHA bit setting determine whether data are sampled on the leading (first) edge or tailing (last) edge of
XCKn. Refer to the “Master SPI Mode Clock Generation” on page 283 for details.
XMEGA E MANUAL 300

Bit 7 6 5 4 3 2 1 0
+0x05 – – DECTYPE[1:0] LUTACT[1:0] PECACT[1:0]

These bits are reserved and will always be read as zero. For compatibility with future devices, always write these
bits zero when this register is written.
 Bit 5:4 – DECTYPE[1:0]: Decoding and encoding type
These bits decide the decoding and encoding type that is applied to both receiver and transmitter engines, as
shown in Table 21-12. The settings are applied according to LUTACT settings.
Table 21-12. USART Decoding and Encoding Types
DECTYPE[1:0] Group configuration Description
00 DATA LUT OUT applies during data field only
01 – Reserved
10 SDATA LUT OUT applies during start and data field
- Inverted LUT OUT applies during start field

11 NOTSDATA
- LUT OUT applies during data field
 Bit 3:2 – LUTACT[1:0]: LUT Action

These bits decide the action the USART performs when linked to LUT units from XCL module, according to Table
21-13.
Table 21-13. USART LUT Action Selection
LUTACT[1:0] Group configuration Event action
00 OFF Standard Configuration
01 RX Enable decoding for on receiver engine
10 TX Enable encoding on transmitter engine
11 BOTH Enable both encoding/decoding
 Bit 1:0 – PECACT[1:0]: Peripheral Counter Action

This bit decides the event action the USART performs on XCL PEC event, according to Table 21-14.
Table 21-14. USART Peripheral Counter Action Selection
PECACT[1:0] Group configuration Event action
00 OFF Standard Configuration
01 PEC0 Receiver data length controlled by peripheral counter 0
10 PEC1 Transmitter data length controlled by peripheral counter 1
- Receiver data length controlled by peripheral counter 0

11 PEC01
- Transmitter data length controlled by peripheral counter 1
XMEGA E MANUAL 301

21.18.7 BAUDCTRLA – Baud Rate Control Register A
Bit 7 6 5 4 3 2 1 0
+0x06 BSEL[7:0]
 Bit 7:0 – BSEL[7:0]: Baud Rate Bits

This is a 12-bit value which contains the USART baud rate setting. The BAUDCTRLB contains the four most signif-
icant bits, and the BAUDCTRLA contains the eight least significant bits of the USART baud rate. Ongoing
transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing BAUDCTRLA
will trigger an immediate update of the baud rate prescaler.
21.18.8 BAUDCTRLB – Baud Rate Control Register B
Bit 7 6 5 4 3 2 1 0
+0x07 BSCALE[3:0] BSEL[11:8]
 Bit 7:4 – BSCALE[3:0]: Baud Rate Scale Factor

These bits select the Baud Rate Generator scale factor. The scale factor is given in two's complement form from -
7 (0b1001) to 7 (0b0111). The -8 (0b1000) setting is reserved. For positive scale values the Baud Rate Generator
is prescaled by 2BSCALE. For negative values the Baud Rate Generator will use fractional counting, which increases
the resolution. See equations in Table 21-1 on page 282.
 Bit 3:0 – BSEL[11:8]: Baud Rate Bits
This is a 12-bit value which contains the USART baud rate setting. The BAUDCTRLB contains the four most signif-
icant bits, and the BAUDCTRLA contains the eight least significant bits of the USART baud rate. Ongoing
transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing BAUDCTRLA
will trigger an immediate update of the baud rate prescaler.
XMEGA E MANUAL 302

21.19.1 Register Summary – USART

+0x00 DATA DATA[7:0] 296

+0x01 STATUS RXCIF TXCIF DREIF FERR BUFOVF PERR RXSIF RXB8/DRIF 296
+0x02 CTRLA RXSIE DRIE RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] 298
+0x03 CTRLB ONEWIRE SFDEN – RXEN TXEN CLK2X MPCM TXB8 298
+0x04 CTRLC CMODE[1:0] PMODE[1:0] SBMODE CHSIZE[2:0] 299
+0x05 CTRLD – – DECTYPE[1:0] LUTACT[1:0] PECACT[1:0] 301
+0x06 BAUDCTRLA BSEL[7:0] 302
+0x07 BAUDCTRLB BSCALE[3:0] BSEL[11:8] 302
21.19.2 Register Summary – USART in Master SPI Mode

+0x00 DATA DATA[7:0] 296
+0x01 STATUS RXCIF TXCIF DREIF – – – – – 296

+0x02 CTRLA – – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] 298
+0x03 CTRLB – – – RXEN TXEN – – – 298
+0x04 CTRLC CMODE[1:0] – – – UDORD UCPHA – 299
+0x05 CTRLD – – DECTYPE[1:0] LUTACT[1:0] PECACT[1:0] 301
+0x06 BAUDCTRLA BSEL[7:0] 302
+0x07 BAUDCTRLB BSCALE[3:0] BSEL[11:8] 302
21.20 Interrupt Vector Summary – USART
Table 21-15. USART Interrupt Vectors and their Word Offset Address
0x00 RXC_vect USART Receive Complete Interrupt vector
0x02 DRE_vect USART Data Register Empty Interrupt vector
0x04 TXC_vect USART Transmit Complete Interrupt vector
XMEGA E MANUAL 303

22. IRCOM – IR Communication Module
22.1 Features
 Pulse modulation/demodulation for infrared communication
 IrDA compatible for baud rates up to 115.2kbps
 Selectable pulse modulation scheme
 3/16 of the baud rate period
 Fixed pulse period, 8-bit programmable
 Pulse modulation disabled
 Built-in filtering
 Can be connected to and used by any USART
22.2 Overview
XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to
115.2kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
Figure 22-1. IRCOM Connection to USARTs and Associated Port Pins
Event System events

DIF
RXDxn
USARTxn
TXDxn
IRCOM
.... RXD...
TXD...
encoded RXD USARTD0 RXDD0
Pulse
TXDD0
Decoding
USARTC0 RXDC0
decoded RXD TXDC0
decoded TXD
Pulse
Encoding encoded TXD
The IRCOM is automatically enabled when a USART is set in IRCOM mode. The signals between the USART and the
RX/TX pins are then routed through the module as shown in Figure 22-1. The data on the TX/RX pins are the inverted
value of the transmitted/received infrared pulse. It is also possible to select an event channel from the event system as
input for the IRCOM receiver. This will disable the RX input from the USART pin.
For transmission, three pulse modulation schemes are available:
 3/16 of the baud rate period
 Fixed programmable pulse time based on the peripheral clock frequency
 Pulse modulation disabled
XMEGA E MANUAL 304

For reception, a fixed programmable minimum high-level pulse width for the pulse to be decoded as a logical 0 is used.
Shorter pulses will then be discarded, and the bit will be decoded to logical 1 as if no pulse was received.
The module can only be used in combination with one USART at a time. Thus, IRCOM mode must not be set for more
than one USART at a time. This must be ensured in the user software.
22.2.1 Event System Filtering

The event system can be used as the receiver input. This enables IRCOM or USART input from I/O pins or sources other
than the corresponding RX pin. If event system input is enabled, input from the USART's RX pin is automatically
disabled. The event system has a digital input filter (DIF) on the event channels that can be used for filtering.
Refer to “Event System ” on page 79 for details on using the event system.
XMEGA E MANUAL 305

22.3 Registers Description
Bit 7 6 5 4 3 2 1 0
+0x00 – – – – EVSEL[3:0]

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
 Bit 3:0 – EVSEL [3:0]: Event Channel Selection
These bits select the event channel source for the IRCOM receiver according to Table 22-1. If event input is selected for
the IRCOM receiver, the input from the USART’s RX pin is automatically disabled.
Table 22-1. Event Channel Selection
EVSEL[3:0] Group configuration Event source
0000 – None
0001 – (Reserved)
0010 – (Reserved)
0011 – (Reserved)
0100 – (Reserved)
0101 – (Reserved)
0110 – (Reserved)
0111 – (Reserved)
1nnn CHn Event system channel n; n = {0, …,7}
22.3.2 TXPLCTRL – Transmitter Pulse Length Control Register
Bit 7 6 5 4 3 2 1 0
+0x01 TXPLCTRL[7:0]
 Bit 7:0 – TXPLCTRL[7:0]: Transmitter Pulse Length Control

This 8-bit value sets the pulse modulation scheme for the transmitter. Setting this register will have no effect if IRCOM
mode is not selected by a USART.
By leaving this register value to zero, 3/16 of the baud rate period pulse modulation is used.
Setting this value from 1 to 254 will give a fixed pulse length coding. The 8-bit value sets the number of system clock
periods for the pulse. The start of the pulse will be synchronized with the rising edge of the baud rate clock.
Setting the value to 255 (0xFF) will disable pulse coding, letting the RX and TX signals pass through the IRCOM module
unaltered. This enables other features through the IRCOM module, such as half-duplex USART, loop-back testing, and
USART RX input from an event channel.
TXPCTRL must be configured before the USART transmitter is enabled (TXEN).
XMEGA E MANUAL 306

22.3.3 RXPLCTRL – Receiver Pulse Length Control Register
Bit 7 6 5 4 3 2 1 0
+0x02 RXPLCTRL[7:0]
 Bit 7:0 – RXPLCTRL[7:0]: Receiver Pulse Length Control

This 8-bit value sets the filter coefficient for the IRCOM transceiver. Setting this register will have no effect if IRCOM
mode is not selected by a USART.
By leaving this register value at zero, filtering is disabled. Setting this value between 1 and 255 will enable filtering, where
x+1 equal samples are required for the pulse to be accepted.
RXPCTRL must be configured before the USART receiver is enabled (RXEN).

+0x00 CTRL – – – – EVSEL[3:0] 306
+0x01 TXPLCTRL TXPLCTRL[7:0] 306
+0x02 RXPLCTRL RXPLCTRL[7:0] 307
XMEGA E MANUAL 307

23. XCL – XMEGA Custom Logic
23.1 Features
 Two independent 8-bit timer/counter with:
 Period or compare channel for each timer/counter
 Input capture for each timer
 Serial peripheral data length control for each timer
 Timer underflow interrupt/event
 Compare match or input capture interrupt/event for each timer
 One 16-bit timer/counter by cascading two 8-bit timer/counters with:
 Period or compare channel
 Input capture
 Timer underflow interrupt/event
 Compare match or input capture interrupt/event
 Programmable lookup table supporting multiple configurations:
 Two 2-input units
 One 3-input unit
 RS configuration
 Duplicate input with selectable delay on one input
 Connection to external I/O pins or event system
 Combinatorial logic functions using programmable truth table:
 AND, NAND, OR, NOR, XOR, XNOR, NOT, MUX
 Sequential logic functions:
 D-Flip-Flop, D Latch, RS Latch
 Input sources:
 From external pins or the event system
 One input source includes selectable delay or synchronization option
 Can be shared with selectable USART pin locations
 Outputs:
 Available on external pins or event system
 Includes selectable delay or synchronization option
 Can override selectable USART pin locations
 Operates in all power modes
23.2 Overview
Atmel AVR XMEGA E devices include the XMEGA Custom Logic (XCL). The module consists of two main sub-units,
timer/counter and glue logic.
 The timer/counter includes two 8-bit timer/counters BTCO and BTC1 respectively, allowing up to seven
configuration settings. Both timer/counters can be cascaded to create a 16-bit timer/counter with optional 16-bit
capture.
 The glue logic is made of two truth tables with configurable delay elements and sequential logic functions such as
D-type flip-flop or D-latch
An interconnect array enables a large amount of connections between a number of XCL elements and also allows
working with other peripherals such as USART, port pins, or event system.
XMEGA E MANUAL 308

Figure 23-1. XCL Block Diagram and Closely Related Peripherals
Event Port
System Pins USART
Interrupts
Periph.Counter
Truth
Interconnect Array
One Shot Table
8-bit T/C
Control Registers
PWM LUT0
Capture
D Q
Normal
BTC0
Interconnect Array
D Q
Normal BTC1
G
8-bit T/C
Capture
PWM LUT1
One Shot Truth

Table
Periph.Counter
Timer/Counter Glue Logic
The timer/counter configuration allows for two 8-bits timer/counter usage. Each timer/counter supports normal, input
capture, continuous and one shot pulse width modulations (PWM), with common flexible clock selections and event
channels. By cascading the two 8-bit timer/counters, the XMEGA custom logic (XCL) offers a 16-bit timer/counter.
In peripheral counter (PEC) configuration, the XCL is directly linked to one of USART modules. The selected USART
controls the counter operation, since the PEC can optionally control the data length within the USART frame.
If the glue logic configuration is enabled, the XCL implements two programmable lookup tables (LUT). Each LUT defines
the truth table corresponding to the logical condition between two inputs. Any combinatorial function logic is possible.
The LUT inputs can be connected to I/O pins or to event system channels. If the LUT is connected to USART or SPI I/O
pin locations (TxD/RxD/XCK or MOSI/MISO/SCK), serial data encoding/decoding is possible. Connecting together the
LUT units, RS Latch or any combinatorial logic between two operands can be enabled.
A delay element (DLY) can be enabled. Each DLY has a 2-stage digital flip-flop. The position of the DLY is software
selectable between either one input or the output. The size of the delay is software selectable, between 0-cycle delay (no
delay), 1-cycle delay or 2-cycle delay configurations.
The LUT works in all sleep modes. Combined with event system and one I/O pin, the LUT can wake-up the system if
condition on LUT inputs is true.
A block diagram of the programmable logic unit with extensions and closely related peripheral modules is shown in
Figure 23-1 on page 309.
23.2.1 Definitions
Table 23-1 on page 310 shows the definitions used throughout the documentation.
XMEGA E MANUAL 309

Table 23-1. Definitions of XMEGA Custom Logic
Name Description
XCL XMEGA custom logic.
BTC 8-bit timer/counter.
PEC Peripheral counter. Can work only with the serial peripheral module.
BOTTOM The counter reaches BOTTOM when it becomes zero.
MAX The counter reaches maximum when it becomes all ones.
The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value
TOP can be equal to the period (PER) or the compare channel A (CCA) register setting. This is selected by the
waveform generator mode.
The timer/counter signals an update when it reaches BOTTOM or TOP, depending on the waveform generator
UPDATE
mode.
CLEAR External peripheral, event system or CPU forces the (peripheral) timer/counter next value to BOTTOM.
CC Compare or capture.
LUT Lookup table including truth table register and decoder.
Delay element, created with a programmable number of flip-flops. Position is selectable by software, between
DLY
one LUT input or LUT output
GLUE Glue logic, including a LUT and DLY elements.
In general, the term “timer” is used when the timer/counter clock control is handled by an internal source, and the term
“counter” is used when the clock control is handled externally (e.g. counting external events). When the CC channels are
used for compare operations, they are referred to as “compare channels”. When used for capture operations, the CC
channels are referred to as “capture channels”.
23.3 Timer/counter Configuration

The XCL includes two 8-bit timer/counters. The two 8-bit timer/counters can be reconfirmed to work as:
 One 16-bit timer/counter
 One 8-bit timer/counter and one 8-bit peripheral counter
 Two 8-bit peripheral counters
 One 8-bit timer/counter and two 4-bit peripheral counters
Depending on the mode of operation, the timer/counter is reloaded or decremented at each timer/counter clock input.
23.4 Timer/counter Operation

The XCL includes up to two identical 8-bit timer/counters, named BTC0 and BTC1 respectively. Each of 8-bit
timer/counters has a compare channel.
The two 8-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked
and timed from the peripheral clock, with optional pre-scaling, or from the event system. The counters are always
counting down.
When the XCL configuration is set to 16-bit timer/counter, BTC0 and BTC1 are cascaded to create a true 16-bit
timer/counter (TC16) with 16-bit period, compare or capture registers.
A detailed block diagram of the timer/counters showing the base counter with its registers and the compare modules is
shown in Figure 23-2 on page 311.
XMEGA E MANUAL 310

The timer/counter will always operate in single slope decrementing mode. It will be counting down for each clock until it
reaches BOTTOM and then reloads the counter with the period register value.
Figure 23-2. Timer/counter Block Diagram

Base Counter
Period/Capture CTRLE
PERCAPTH PERCAPTL Clock INTFLAGS
BTC0 "count"
Counter BTC0 "underflow"
BTC0 "restart" Counter UNF0IF
BTC1 "count" Control
CNTH CNTL BTC1 "underflow"
BTC1 "restart" Logic UNF1IF
CTRLG
BTC0 "bottom"
I/O Data Bus
=0
=0
BTC1 "bottom" Events
CMPL
Waveform
Generator
OC0 Out
BTC0 INTFLAGS
Compare =
BTC0 "match"
CC0IF
Channel
CMPH
Waveform
Generator
OC1 Out
BTC1 INTFLAGS
Compare =
BTC1 "match"
CC1IF
Channel
23.4.1 Clock Sources

The timer/counters can be clocked from pre-scaled peripheral clock (clkPER) and from the event system, Figure 23-3
shows the clock and event selection logic.
Figure 23-3. Clock and Event Selection

clkPER
/
Common Event
clkPER Events
Prescaler System
Event Channels
Counter
Control Logic
CLKSEL
EVSEL CNT
EVACT (Encoding)
The peripheral clock is fed into the common pre-scaler (common for all timer/counters in a device). A selection of the pre-
scaler outputs is directly available for both timer/counters. In addition the whole range from 1 to 215 times pre-scaling is
available through the event system.
XMEGA E MANUAL 311

Clock selection (CLKSEL[3:0]) selects one of the pre-scaler outputs directly or an event channel as the counter (CNT)
input. This is referred to as normal operation of the counter. For details, refer to the “Normal Operation” on page 312”. By
using the event system, any event source, such as an external clock signal on any I/O pin, may be used as the clock
input. In addition, the timer/counter can be controlled via the event system. The event selection (EVSEL[1:0]) and event
action (EVACT[1:0]) settings are used to trigger an event action from one or more events. This is referred to as event
action controlled operation of the counter. When event action controlled operation is used, the clock selection must be
set to use an event channel as the counter input.
By default, no clock input is selected and the timer/counter is not running.
23.4.2 Normal Operation

In normal mode, the timer/counter will always operate in single slope decrementing mode. The counter will be counting
down for each clock until it reaches BOTTOM and then reloads the counter with the period register value.
Figure 23-4. Counter in Normal Operation
MAX
CNT “reload”
TOP
CNT PERCAPT
BOT
(CNT=x) (CNT=y) (CNT=z)

(higher than PERCAPT) (lower than PERCAPT) (lower than current CNT)
CNT “writte”
As shown in Figure 23-4, changing the counter value while the counter is running is possible. Write accesses have higher
priority than count, clear, or reload and will be immediate.
23.4.2.1 Changing the Period

The counter period is changed by writing a new TOP value to PERCAPT register.
Since the counter is counting down, PERCAPT register can be written at any time without affecting the current period as
shown in Figure 23-5. This prevents wraparound and generation of odd waveforms.
Figure 23-5. Changing the Period

MAX
CNT “reload”
PERCAPT
CNT TOP
BOT
(PERCAPT=x) (PERCAPT=y)
PERCAPT (higher than current CNT) (lower than current CNT)
“write”
XMEGA E MANUAL 312

23.4.3 Capture Operation
The PERCAPT register can be used as capture channel to capture external events and give them a time-stamp. To
perform a capture operation, the timer/counter operation must be set in capture mode. In capture mode, the counter will
count down every clock until it reaches BOTTOM and then it will be reloaded with the MAX value. The capture value will
be stored in the same register as the period value (the period is fixed to MAX and doesn’t need any more to be set in a
register).
Events are used to trigger the capture; i.e., any events from the event system, including pin change from any device pin,
can trigger a capture operation. The event source select setting selects which event channel will trigger the capture on
BTC0. The subsequent event channel then trigger the capture on BTC1, if configured. For example, setting the event
source select to event channel 2 results in BTC0 being triggered by event channel 2 and BTC1 triggered by event
channel 3.
Figure 23-6. Event Source Selection for Capture Operation
Event System
CH0 Mux. Event Channel 0 EVSEL Event for capture TC16
CH1 Mux. Event Channel 1 Event for capture BTC0
(EVSEL+1) %(n+1)
Event for capture BTC1
CHn Mux. Event Channel n
Rotate
EVSEL[2:0] Event Source Selection

The event action setting in the timer/counter will determine the type of capture that is done. The capture operation must
be enabled before capture can be done. When the capture condition occurs, the timer/counter will time-stamp the event
by copying the current CNT value of the count register into the PERCAPT register.
When an I/O pin is used as an event source for the capture, the pin must be configured for edge sensing. For details on
sense configuration on I/O pins, refer to “Input Sense Configuration” on page 144.
23.4.3.1 Input Capture Event Action

Selecting the input capture event action makes the enabled capture channel perform an input capture on an event. The
interrupt flag (CCxIF) is set and indicates that there is a valid capture result in the corresponding PERCAPT register.
The counter will continuously count from MAX to BOTTOM, and then restart at MAX, as shown in Figure 23-7. The figure
also shows three capture events for one capture channel.
Figure 23-7. Timer/counter in CAPT Configuration with INPUT Command
MAX
CNT
CNT “reload”
BOT
“capture n” “capture n+1” “capture n+2”
Events
Event action: ( [1:0] = b00)
XMEGA E MANUAL 313

23.4.3.2 Frequency Capture Event Action
Selecting the frequency capture event action makes the enabled capture timer/counter perform an input capture and
restart on positive edge events. This enables the timer/counter to measure the period of a signal directly.
Figure 23-8. Timer/counter in CAPT Configuration with FREQ Command
MAX
CNT “reload”
CNT
BOT
“capture n-1” “capture n” “capture n+1”
Events
Event action:
( [1:0] = b01)
Period (t0) Period (t1)
External Signal
The capture result will be the time (t) from the previous timer/counter restart until the event occurred (MAX-PERCAPT).
1
Frequency (f ): f 
t
23.4.3.3 Pulse Width Capture Event Action

Selecting the pulse width measure event action, makes the enabled compare channel perform the input capture action
on falling edge events and the restart action on rising edge events. The counter will then restart on positive edge events,
and the input capture will be performed on the negative edge events. The event source must be an I/O pin, and the sense
configuration for the pin must be set to generate an event on both edges. Figure 23-9 shows and example where the high
pulse width is measured three times for an external signal.
Figure 23-9. Timer/counter in CAPT Configuration with PW Command

CNT “reload”
MAX
CNT
BOT
“capture n” “capture n+1” “restart” “capture n+2”
“restart”
“restart”
Events
Event action:
( [1:0] = b10) PulseWidth PulseWidth PulseWidth
(pw0) (pw1) (pw2)
External Signal
XMEGA E MANUAL 314

23.4.4 PWM Generation
For PWM generation, the period time (t) is controlled by PERCAPT register, while the CMP register controls the duty
cycle of the waveform generator (OC) output. Figure 23-10 shows how the counter counts from TOP to BOTTOM, and
then restarts from TOP. OC output is set on the compare match between the CNT and CMP register, and cleared at
BOTTOM.
Figure 23-10.Single-slope Pulse Width Modulation
Period (t) CNT “reload”

MAX CNT “match”
TOP
CNT
CMP
BOT
OC Out
(CMP=TOP) (CMP=x) (CMP=BOT) (CMP=y)

CMP “write”
The PERCAPT register defines the PWM resolution. The minimum resolution is two bits (PERCAPT=0x03), and the
maximum resolution is PERCAPT=MAX.
The following equation is used to calculate the exact resolution for a single-slope PWM (RPWM) waveform:
log( PERCAPT  1)
RPWM 
log( 2)
The PWM frequency (fPWM) depends on the period setting (PERCAPT) and the peripheral clock frequency (fPERCAPT), and
it is calculated by using the following equation:
f PERCAPT
f PWM 
N ( PERCAPT  1)
Where N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).
When used in 16-bit configuration, the PERCAPT is automatically set to MAX value.
23.4.5 One-shot PWM Generation

In one-shot PWM generation (1SHOT), the start and stop timer/counter operation is controlled by external events or
software commands. If the operation is controlled by the external events, the event actions (EVACT) must be enabled
and configured accordingly.
When timer/counter is enabled (CLKSEL), the counting operation starts only when software restart or an event is
received. If no other command is provided to the timer/counter before the update condition is reached, the timer/counter
will stop the operation and waits for a new command. The waveform generation is similar to PWM mode.
If the software restart or restart event command is provided before the update condition is detected, the timer/counter
and waveform generation are restarted immediately.
If the stop event is provided before the update condition is detected, the timer/counter stops the operation immediately,
the waveform is cleared and waits for a new command before starting again.
XMEGA E MANUAL 315

Figure 23-11 and Figure 23-12 show the timer/counter operation when software RESTART and STOPSTART commands
are provided.
Figure 23-11.Timer/counter in 1SHOT Configuration with RESTART Command
CNT “reload”
MAX
CNT “match”
TOP
CNT
CMP
BOT
OC Out
Software “restart”
Events
Figure 23-12.Timer/counter in 1SHOT Configuration with STOPSTART Command
CNT “reload”
MAX
CNT “match”
TOP
CNT
CMP
BOT
OC Out
“start”
“start”
“start”
“stop”
Software “restart”
Events
23.4.6 Timer/counter Commands

A set of commands can be given to the timer/counter by software to immediately change the state of the module. These
commands give direct control of the Restart signals.
The software can force a restart of the current waveform period by issuing a restart command. In this case the counter is
set to TOP value and all compare outputs are set to zero.
XMEGA E MANUAL 316

23.4.7 16-bit Operation
Both timer/counters can be cascaded to enable 16-bit counter operation. All timer/counter modes will be then available
on a pure 16-bit timer/counter. Counter and output compare registers will be combined each into one 16-bit register.
In PWM and 1SHOT modes, the TOP of the count is always MAX.
23.4.8 Peripheral Counter Operation

A peripheral counter is used to customize an USART to be able to send or receive a frame with up to 256 bits. A detailed
block diagram of the peripheral counters is shown in Figure 23-13.
Figure 23-13.Peripheral Counter Block Diagram
Base Counter
clkPER
Peripheral Length Count
INTFLAGS
PLC
I/O Data Bus
PEC0 "underflow"
PEC0 "count"
PEC0IF
PEC0 "restart" PEC1 "underflow"
PEC1 "count"
PEC1IF
CNTH CNTL Control
PEC1 "restart"
Counter Logic
Rx "count"
Rx "restart"
PEC0 "bottom"
=0 Tx "count"
PEC1 "bottom" Tx "restart"
=0
TxShiftRegclk RxShiftRegclk
Serial Baud Rate Generator

Peripheral
Transmitter
Receiver
In peripheral counter configuration (PEC), the peripheral length control register (PLC) represents the TOP value and the
compare is always done with the BOTTOM.
The data length within serial peripheral frame is defined using formula:
Frame Lenght  PLC 1
The count (Rx/Tx ”count”) and restart (Rx/Tx ”restart”) commands are provided by each receiver and transmitter stage of
the selected serial peripheral and all CLKSEL clock settings are ignored in PEC configuration. If only one PEC is used,
the CLKSEL clock selection will be available for the other timer/counter.
While counting, the counter restarts from PLC if the restart command is received. When it reaches the BOTTOM value,
the counter restarts from PLC if restart or count command is received from the serial peripheral.
XMEGA E MANUAL 317

Figure 23-14.Peripheral Counter with UART/USART 12-bit Frame
MAX
PEC “reload”
TOP 11 11 11
10 10
9 9
8
7
6
5
4
x 3
2
1
BOT 0
“count” “count”
“restart” “restart”
idle start 0 1 2 3 4 5 6 7 8 9 10 11 stop idle start 0 1 2
idle start 0 1 2 3 4 5 6 7 8 9 10 11 stop idle start 0 1 2
Since the commands are provided by the serial peripheral, the event actions are ignored. Only software restart command
is available.
Figure 23-15.Peripheral Counter with SPI 10-bit Frame
PEC “reload”
MAX
TOP 9 9
8 8
PEC 7
6
7
5 PLC
4
3
2
1
BOT 0
“count” “count”
Rx/Tx“count”
Rx/Tx“restart” (*)
SCK (pin) SPI mode 0
MISO (pin) bit-0 bit-1 bit-2 bit-3 bit-4 bit-5 bit-6 bit-7 bit-8 bit-9 bit-0 bit-1 bit-
MOSI (pin) bit-0 bit-1 bit-2 bit-3 bit-4 bit-5 bit-6 bit-7 bit-8 bit-9 bit-0 bit-1 bit-
( )
* No Rx/Tx“restart”: During PEC initialization for SPI communication, set-up PEC=PLC.
The XCL supports up to two 8-bit peripheral counters, called PEC0 and PEC1 respectively.The receiver stage of serial
peripheral controls PEC0 operation, since the transmitter stage of the serial peripheral controls the PEC1 operation.
The XCL also supports two 4-bit peripheral counters, called PEC20 and PEC21 respectively. Both are mapped in one 8-
bit T/C. The receiver stage of serial peripheral controls PEC20 operation, since the transmitter stage of the serial
peripheral controls the PEC21 operation. This lets the opportunity to control serial frames up to 16 bits in reception and in
transmission, and still to have an 8-bit timer/counter available resource.
Cascading two peripheral counters is not available.
XMEGA E MANUAL 318

23.5 Glue Logic
The glue logic is made of two lookup tables and some sequential logic functions such as D-type flip-flop or D-latch. The
lookup tables can be cascaded to extend the input selection or to create advanced logic.
23.5.1 LUT Description

The XCL includes two lookup table units (LUT). Each LUT is composed by a 4-bit truth table and a decoder, allowing
generation of any logic expression OUT as a function of two inputs, as shown in Figure 23-16.
Figure 23-16.LUT Units Block Diagram
CTRLD
TRUTH0[0]
TRUTH0[1] Delay
TRUTH0[2] Block
OUT0
TRUTH0[3]
Delay Optional
IN0 Block
IN1
CTRLD
TRUTH1[0]
TRUTH1[1] Delay
TRUTH1[2] Block
OUT1
TRUTH1[3]
Delay Optional
IN2 Block
IN3
The combinatorial logic functions can be: AND, NAND, OR, NOR, XOR, XNOR, NOT.
The truth table for these functions is written to the CTRLD register of the LUT. Table 23-2 shows both truth table for 2-
input LUT units.
Table 23-2. 2-input LUT Truth Table (2LUTxIN Configuration)
IN1 IN0 OUT0 IN3 IN2 OUT1
0 0 TRUTH0[0] 0 0 TRUTH1[0]
0 1 TRUTH0[1] 0 1 TRUTH1[1]
1 0 TRUTH0[2] 1 0 TRUTH1[2]
1 1 TRUTH0[3] 1 1 TRUTH1[3]
Cascading both LUT units, the logic function OUT can be a function of three inputs. Table 23-3 on page 320 shows the
truth table for a 3-input LUT.
XMEGA E MANUAL 319

Table 23-3. 3-input LUT Truth Table (1LUT3IN Configuration)
IN0 IN3 IN2 OUT1 OUT0
=0 TRUTH0[0]
0 0 0 TRUTH1[0]
=1 TRUTH0[1]
=0 TRUTH0[0]
0 0 1 TRUTH1[1]
=1 TRUTH0[1]
=0 TRUTH0[0]
0 1 0 TRUTH1[2]
=1 TRUTH0[1]
=0 TRUTH0[0]
0 1 1 TRUTH1[3]
=1 TRUTH0[1]
=0 TRUTH0[2]
1 0 0 TRUTH1[0]
=1 TRUTH0[3]
=0 TRUTH0[2]
1 0 1 TRUTH1[1]
=1 TRUTH0[3]
=0 TRUTH0[2]
1 1 0 TRUTH1[2]
=1 TRUTH0[3]
=0 TRUTH0[2]
1 1 1 TRUTH1[3]
=1 TRUTH0[3]
23.5.2 Delay Description

The XCL has two delay units, one for each LUT. The delay can be configured from zero (no delay) and up to two
peripheral clock cycles delay, as shown in Figure 23-17.
Figure 23-17.Delay Block Diagram
DLYnCONF[1:0]
clkPER Logic
DLYSEL[1:0]
1-Cycle Delay
input D Q D Q
2-Cycle Delay output
No Delay
The insertion of a delay unit is selectable for each LUT, on the first of the two inputs or on the output. The insertion is
decided by the application purpose, but some examples are provided:
 Delay on input can be used as input synchronizer or as edge detector on input signal
 Delay on output can be used to filter glitches or to synchronize the LUT output when both inputs are asynchronous
XMEGA E MANUAL 320

23.5.3 Glue Logic Configurations
Figure 23-18 to Figure 23-25 on page 322 show the different glue logic configurations. Dashed boxes show the possible
places of the delay element.
Figure 23-18.Two Independent 2-input LUT (2LUT2IN)
IN0 Delay
Truth
Delay OUT0
Table 0
IN1 LUT0
IN2 Delay
Truth
Delay OUT1
Table 1
IN3 LUT1
Figure 23-19.Two Independent 2-input LUT with Duplicated Input (2LUT1IN)
IN0 Delay
Truth
Delay OUT0
Table 0
LUT0
IN2 Delay
Truth
Delay OUT1
Table 1
LUT1
Figure 23-20.Two 2-input LUT with One Common Input (2LUT3IN)
IN0 Delay
Truth
Delay OUT0
Table 0
LUT0
IN2 Delay
Truth
Delay OUT1
Table 1
IN3 LUT1
Figure 23-21.One 3-input LUT (1LUT3IN)
IN0 Delay
Truth
Delay OUT0
Table 0
IN2 Delay
Truth
Delay OUT1
Table 1
IN3 LUT
XMEGA E MANUAL 321

Figure 23-22.One 2-input Multiplexer Controlled by One 2-input LUT (MUX)
IN0 Delay
Delay OUT0
IN1
IN2 Delay
Truth
Delay OUT1
Table 1 Mux.
IN3
& LUT
Figure 23-23.One D-Latch Controlled by Two 2-input LUT (DLATCH)
IN0 Delay Delay D Q OUT0

Truth
Table 0
IN1 G
IN2 Delay
Truth
Delay OUT1
Table 1 D-Latch
IN3
& LUT
Figure 23-24.One RS-Latch LUT (RSLATCH)
IN0 Delay
Truth
Delay OUT0
Table 0
IN2 Delay
Truth
Delay OUT1
Table 1
RS-Latch
LUT
Figure 23-25.One DFF with Data Controlled by Two Independent 2-input LUT (DFF)
IN0 Delay
Truth
D Q OUT0
Delay
Table 0
IN1
clkPER
IN2 Delay
Truth
Delay OUT1
Table 1 DFF
IN3
& LUT
23.5.4 Glue Input and Output Description

The input selection includes selection from I/O pins, from event system or from internal XCL sub-modules, including TxD
line from the selectable USART module and timer/counter outputs.
When used with I/O pins, the LUT inputs are connected to digital input pins, as shown in Figure 23-26 on page 323. For
more details, refer to “I/O Ports” on page 139.
XMEGA E MANUAL 322

Figure 23-26.Input Connection
DIRn
OUTn
Pn INVEN (Inverted I/O)

Pn
Synchronizer
D Q D Q To Input Sensing
R R
INn
Digital Input Pin
The LUT outputs are connected to all strobe, asynchronous and synchronous event system data lines, as shown in
Figure 23-7. The connection depends on delay configuration, but it is up to the application to generate the correct
waveform or to use the correct event line.
Figure 23-27.LUT Output Connection
Truth
No Delay
Table
No Delay
Delay
Truth
Table
Delay
Truth
Table
INxSEL bits in CTRLB register decide the source of each input pin for each LUT0 and LUT1. Table 23-4 on page 324
shows the input selections for the LUT units. PORTSEL bits in CTRLA register select the port associated to LUT0 and
LUT1.
XMEGA E MANUAL 323

Table 23-4. LUT Input Pin Location Selection
INxSEL[1:0] IN3 (1) IN2 (1) IN1 (1) IN0 (1)
Event system EVSYS CH7 CH1 CH0 CH6

(2)
XCL XCL TxD OC0 out OC1 out OC0 out
I/O pin low PINL PIN3 PIN1 PIN0 PIN2
I/O pin high PINH PIN7 PIN5 PIN4 PIN6
Notes: 1. Figure 23-18 on page 321 to Figure 23-25 on page 322 show the active inputs.
2. In TC16 configuration, IN1 is the 16-bit Waveform Generation (OC0 out).
EVASYSELn bits in CTRLC register decides if the event system channel line selection is the strobe or the asynchronous
event line.
Only the LUT0 output can be connected to I/O pin. LUT0OUTEN bit in CTRLA register allows two LUT0 output pin
locations: PIN0 or PIN4.
Table 23-5 shows the consumers of the LUT outputs.
Table 23-5. LUT Output Consumers
OUT1 OUT0
Event Channel Event Channel
PIN0 LUT0OUTEN[1:0] = b01

No I/O output
PIN4 LUT0OUTEN[1:0] = b10
Inserted in TxD (MOSI) encoding logic Directly to RxD (MISO)

(1)
of the selected USART input of the selected USART (1)
Note: 1. Refer to “CTRLD – Control Register D” on page 301 in USART.

The XCL can generate both interrupts and events.
Each timer/counter can generate an interrupt on underflow, but the interrupt line is shared between timer/counter0 and
timer/counter1.
The CC channel has a separate interrupt that is used for compare or capture, but the interrupt line is shared between
BTC0 and BTC1.
timer/counter events will be generated for all conditions that can generate interrupts. For details on event generation and
available events refer to “Event System ” on page 79. The glue logic generates only events. For details, refers to “Glue
Input and Output Description” on page 322.
XMEGA E MANUAL 324

Bit 7 6 5 4 3 2 1 0
+0x00 LUT0OUTEN[1:0] PORTSEL[1:0] – LUTCONF[2:0]
 Bit 7:6 – LUT0OUTEN[1:0]: LUT0 Output Enable

Setting these bits enable LUT0 output to pin, according to table Table 23-6.
Table 23-6. LUT Output Pin Selection
LUT0OUTEN[1:0] Group configuration Description
00 DISABLE LUT0 output disabled
LUT0 output to PC0

01 PIN0 (1)
LUT0 output to PD0
LUT0 output to PC4

10 PIN4 (1)
LUT0 output to PD4
11 - Reserved
Note: 1. The port is defined by PORTSEL settings.
 Bit 5:4 – PORTSEL[1:0]: Port Selection

These bits select from which port I/O pins are used as input/output for LUT(s) or USART module used with PEC,
according to Table 23-7.
Table 23-7. Port Source Selection
PORTSEL[1:0] Group configuration Description
LUT(s) Port C
00 PC
PEC USARTC0
LUT(s) Port D
01 PD
PEC USARTD0
1x - Reserved
 Bit 2:0 – LUTCONF[2:0]: LUT Configuration
Setting these bits enables the configuration of the glue logic cells, according to Table 23-8 on page 326.
XMEGA E MANUAL 325

Table 23-8. LUT Configuration Mode
LUTCONF[2:0] Group configuration Description
000 2LUT2IN Two independent 2-input LUT
001 2LUT1IN Two independent 2-input LUT with duplicated input
010 2LUT3IN Two LUT with one common input
011 1LUT3IN One 3-input LUT
100 MUX One 2-input multiplexer controlled by one 2-input LUT
101 DLATCH One D-Latch controlled by two 2-input LUT
110 RSLATCH One RS-Latch LUT
111 DFF One DFF with data controlled by two independent 2-input LUT
Bit 7 6 5 4 3 2 1 0
+0x01 IN3SEL[1:0] IN2SEL [1:0] IN1SEL [1:0] IN0SEL [1:0]
 Bit 7:0 – INxSEL[1:0]: Input Selection

These bits decide source of input pins of LUT0 and LUT1, according to Table 23-9. Table 23-4 on page 324 also
shows LUT input pin location selection and Table 23-5 on page 324 shows LUT output consumers.
Table 23-9. LUT Input Pins Source Selection
INxSEL[1:0] Group configuration Description
00 EVSYS Event system selected as source
01 XCL XCL selected as source
10 PINL(1) LSB port pins selected as source
11 PINH(1) MSB port pins selected as source
Note: 1. The Port is defined by PORTSEL[1:0] settings.
Bit 7 6 5 4 3 2 1 0
+0x02 EVASYSEL1 EVASYSEL0 DLYSEL [1:0] DLY1CONF[1:0] DLY0CONF[1:0]
 Bit 7 - EVASYSEL1: LUT1 Asynchronous Event Line Selection

Setting this bit selects the asynchronous event line as possible input for LUT1. When cleared, the event strobe line
can be selected as input for LUT1.
 Bit 6 - EVASYSEL0: LUT0 Asynchronous Event Line Selection
Setting this bit selects the asynchronous event line as possible input for LUT0. When cleared, the event strobe line
can be selected as input for LUT0.
XMEGA E MANUAL 326

 Bit 5:4 – DLYSEL[1:0]: Delay Selection
These bits define the configuration of the delay logic cells, according to Table 23-10.
Table 23-10. Delay Selection
DLYSEL[1:0] Group configuration Description
00 DLY11 1-cycle delay for both LUT1 and LUT0
1-cycle delay for LUT1 and

01 DLY12
2-cycle delay for LUT0
2-cycle delay for LUT1 and

10 DLY21
1-cycle delay for LUT0
11 DLY22 2-cycle delay for both LUT1 and LUT0
 Bit 3:2 – DLY1CONF[1:0]: Delay Configuration on LUT1

These bits define the delay configuration for LUT1, according to Table 23-11.
 Bit 1:0 – DLY0CONF[1:0]: Delay Configuration on LUT0
These bits define the delay configuration for LUT0, according to Table 23-11.
Table 23-11. Delay Configuration
DLYxCONF[1:0] Group configuration Description
00 DISABLE No delay
01 IN (1) Delay enabled on LUT input
10 OUT (1) Delay enabled on LUT output
11 - Reserved
Note: 1. Figure 23-18 on page 321 to Figure 23-25 on page 322 show possible location of delay elements.

This register defines the truth tables for LUT0 and LUT1 units, as described in “LUT Description” on page 319.
Bit 7 6 5 4 3 2 1 0
+0x03 TRUTH1[3:0] TRUTH0[3:0]
 Bit 7:4 – TRUTH1[3:0]: LUT1 Truth Table

These bits hold the truth table definition for LUT1.
 Bit 3:0 – TRUTH0[3:0]: LUT0 Truth Table
These bits hold the truth table definition for LUT0.
XMEGA E MANUAL 327

Bit 7 6 5 4 3 2 1 0
+0x04 CMDSEL TCSEL[2:0] CLKSEL[3:0]
 Bit 7 – CMDSEL: Command Selection

This command bit is used for software control of timer/counter restart, according to Table 23-12. The command bit
is always read as zero. The CMD bit must be used together with CMDEN.
Table 23-12. Command Selection
CMDSEL Group configuration Description
0 NONE None
1 RESTART Force count restart
 Bit 6:4 – TCSEL[2:0]: Timer/Counter Selection

Setting these bits enables the configuration of the timer/counters, according to Table 23-13.
Table 23-13. Timer/counter Selection
TCSEL[2:0] Group configuration Description
000 TC16 16-bit timer/counter
001 BTC0 One 8-bit timer/counter (with period)
010 BTC01 Two 8-bit timer/counters
011 BTC0PEC1 One 8-bit timer/counter with period and one 8-bit transmitter peripheral counter
100 PEC0BTC1 One 8-bit timer/counter with period and one 8-bit receiver peripheral counter
101 PEC01 Two 8-bit transmitter/receiver peripheral counter
One 8-bit timer/counter with period and two 4-bit transmitter/receiver peripheral
110 BTC0PEC2
counter
111 - Reserved

Setting these bits enables the input clock of the timer/counters, according to Table 23-14.
CLKSEL[3:0] Group configuration Description
0001 DIV1 Prescaler: clkPER
0010 DIV2 Prescaler: clkPER/2
XMEGA E MANUAL 328

CLKSEL[3:0] Group configuration Description
1nnn EVCHn Event channel n, n={0,. ., 7)
23.7.6 CTRLF – Control Register F
Bit 7 6 5 4 3 2 1 0
+0x05 CMDEN[1:0] CMP1 CMP0 CCEN1 CCEN0 MODE[1:0]
 Bit 7:6 – CMDEN[1:0]: Command Enable

These bits are used to indicate for which timer/counter the command (CMD) is valid, according to Table 23-15.
Table 23-15. Command Selections
CMD[1:0] Group configuration Description
00 DISABLE Command ignored.
01 CMD0 Command valid for BTC0
10 CMD1 Command valid for BTC1
11 CMD01 Command valid for both BTC0 and BTC1
 Bit 5:4 – CMPx: Compare Output Value

These bits allow direct access to the waveform generator's output compare value when the timer/counter is set in
the OFF state. This is used to set or clear the WG output value when the timer/counter is not running.
 Bit 3:2 – CCENx: Compare or Capture Enable
Setting these bits in the compare or PWM waveform generation mode of operation will override the port output reg-
ister for the corresponding OCn output pin.
When input capture operation is selected, the CCxEN bits enable the capture operation for the corresponding CC
channel.
 Bit 1:0 – MODE[1:0]: Operation Mode
This bit selects the operation mode for the timer/counter according to Table 23-16. The clock select and operation
mode is identical to both BTC0 and BTC1.
Table 23-16. Operation Mode
MODE[1:0] Group configuration Description
00 NORMAL Normal mode
01 CAPT (1) Capture mode
10 PWM (1) Single-slope PWM
11 1SHOT (1) One-shot PWM
Note: 1. Not supported in PEC01 configuration. Refer to Table 23-13 on page 328 for more details.
XMEGA E MANUAL 329

23.7.7 CTRLG – Control register G
Bit 7 6 5 4 3 2 1 0
+0x06 EVACTEN EVACT1[1:0] EVACT0[1:0] EVSEL[2:0]
 Bit 7 – EVACTEN: Event Action Enable

This command bit is used to enable the event actions for both timer/counters.
 Bit 6:3 – EVACTx[1:0]: Event Action Selection
This bit defines the event action each timer/counter will perform on an event, according to Table 23-17. The
EVSRC setting will decide which event source has control. The settings are ignored if the EVACTEN bit is not set.
Table 23-17. Event Action Selection
EVACTx[1:0] Group configuration Description
INPUT CAPT(1) Input capture

00
OFF 1SHOT(1) Event action is disabled
FREQ CAPT(1) Frequency capture

01
OFF 1SHOT(1) Event action is disabled
PW CAPT Pulse width capture

10 - Stop on event if counter is counting or
STOPSTART 1SHOT
- Start on event if counter is stopped
11 RESTART All modes Restart counter
Note: 1. Refer to Table 23-16 on page 329 for more details.
 Bit 2:0 – EVSEL[2:0]: Event Source Selection

These bits select the event channel source for the timer/counter, according to Table 23-18. For the selected event
channel to have any effect, the event action bits (EVACT) must be set according to Table 23-17.
Table 23-18. Event Source Selection
EVSRC[2:0] Group configuration Description
n CHn Event channel n
Bit 7 6 5 4 3 2 1 0
(1)
UNF1IE UNF0IE CC1IE CC0IE
(2)
+0x08 PEC1IE PEC0IE - - UNFINTLVL[1:0] CCINTLVL[1:0]
(3)
PEC21IE - PEC20IE -
Notes: 1. Using TC16, BTC0 and/or BTC1.

2. Using PEC0 and/or PEC1.
XMEGA E MANUAL 330

 Bit 7 – UNF1IE: Underflow Interrupt 1 Enable
Setting this bit enables the underflow interrupt from BTC1.
 Bit 7 – PEC1IE: Peripheral Counter 1 Interrupt Enable
Setting this bit enables the interrupt from PEC1.
Setting this bit enables the interrupt from peripheral counter high when set in BTC0PEC2 configuration.
 Bit 6 – UNF0IE: Underflow Interrupt 0 Enable
Setting this bit enables the underflow interrupt from BTC0.
Setting this bit enables the interrupt from PEC0.
 Bit 5 – CC1IE: Capture or Compare 1 Interrupt Enable
Setting this bit enables the capture or compare interrupt on BTC1.
 Bit 5 – PEC20IE: Peripheral Counter 20 Low Interrupt Enable
Setting this bit enables the interrupt from peripheral counter low when set in BTC0PEC2 configuration.
 Bit 4 – CC0IE: Capture or Compare 0 Interrupt Enable
Setting this bit enables the capture or compare interrupt on BTC0.
 Bit 3:2 – UNFINTLVL[1:0]: Timer Underflow Interrupt Level
These bits enable the timer/counter interrupt and select the interrupt level as described in “PMIC – Interrupts and
Programmable Multilevel Interrupt Controller” on page 132.
 Bit 1:0 – CCINTLVL[1:0]: Timer Compare or Capture Interrupt Level
These bits enable the timer interrupt and select the interrupt level as described in “PMIC – Interrupts and Program-
Bit 7 6 5 4 3 2 1 0
(1)
UNF1IF UNF0IF CC1IF CC0IF - - - -
(2)
+0x08 PEC1IF PEC0IF - - - - - -
(3)
PEC21IF - PEC20IF - - - - -
Notes: 1. Using TC16, BTC0 and /or BTC1.

 Bit 7:6 – UNFxIF: Timer/Counter Underflow Interrupt Flag
This flag is set on a BOTTOM condition. The flag can be cleared by writing a one to its bit location.
 Bit 7:6 – PECxIF: Peripheral Counter Interrupt Flag
This flag is set on a BOTTOM condition on the 8-bit peripheral counter. The flag can be cleared by writing a one to
its bit location.
 Bit 7 – PEC21IF: Peripheral Counter High Interrupt Flag
This flag is set on a BOTTOM condition on the 4-bit peripheral high counter. The flag can be cleared by writing a
 Bit 5:4 – CCxIF: Compare or Capture Channel x Interrupt Flag
The compare or capture interrupt flag (CCxIF) is set on a compare match or on an input capture event on the cor-
responding CC channel.
For normal mode of operation, the CCxIF will be set when a compare match occurs between the count register
(CNT) and the corresponding compare register (CCx). The flag can be cleared by writing a one to its bit location.
For input capture operation, the CCxIF will be set if the corresponding compare register contains valid data. The
flag will be cleared when the CCx register is read.
XMEGA E MANUAL 331

 Bit 5 – PEC20IF: Peripheral Counter Low Interrupt Flag
This flag is set on a BOTTOM condition on the 4-bit peripheral low counter. The flag can be cleared by writing a
 Bit 3:0 - Reserved
23.7.10 PLC – Peripheral Length Control Register

When one or both peripheral counters are selected, this register is used to store the TOP value of the counter(s).
This register is used as TEMP register when reading 16-bit registers when TC16 configuration is selected.
Bit 7 6 5 4 3 2 1 0
(1)
PLC[7:0]
+0x09 (2)
– – – – PLC[3:0]
Notes: 1. Using PEC0 and/or PEC1.

 Bit 7:0 – PLC[7:0]: Peripheral Length Control Bits

These bits hold the TOP value of 8-bit peripheral counter(s).
 Bit 3:0 – PLC[3:0]: Peripheral Length Control Bits
These bits hold the TOP value of 4-bit peripheral counters.
23.7.11 CNTL – Count Register Low

When the timer/counter is in 16-bit timer/counter configuration, CNTL register contains the low byte of the 16-bit counter
value (CNT). For more details on reading and writing 16-bit registers, refer to “Accessing 16-bit Registers” on page 13.
When the timer/counter is in a configuration that enables CNT0, CNTL register contains the 8-bit counter 0 value
(BCNT0).
When the timer/counter is in a configuration that enables PCNT0, CNTL register contains the 8-bit peripheral counter 0
value (PCNT0).
CPU write access has priority over count or reload of the counter.
Bit 7 6 5 4 3 2 1 0
(1)
CNT[7:0]
(2)
+0x0A BCNT0[7:0]
(3)
PCNT0[7:0]
Notes: 1. Using TC16.

2. Using BTC0.
3. Using PEC0.
 Bit 7:0 – CNT[7:0]: Counter Low Byte

These bits hold the LSB count value of the 16-bit counter register.
 Bit 7:0 – BCNT0[7:0]: Counter 0 Byte
These bits hold the count value of the 8-bit timer/counter 0.
 Bit 7:0 – PCNT0[7:0]: Peripheral Counter 0 Byte
These bits hold the count value of the 8-bit peripheral counter 0. Writing this register requires special attention.
Any ongoing serial communication will be corrupted.
XMEGA E MANUAL 332

23.7.12 CNTH – Count Register High
When the timer/counter is in 16-bit timer/counter configuration, CNTH register contains the high byte of the 16-bit counter
value (CNT). For more details on reading and writing 16-bit registers, refer to “Accessing 16-bit Registers” on page 13.
When the timer/counter is in a configuration that enables CNT1, CNTH register contains the 8-bit counter 1 value
(BCNT1).
When the timer/counter is in a configuration that enables PCNT1, CNTH register contains the 8-bit peripheral counter 1
value (PCNT1).
When the timer/counter is in a configuration that enables PCNT2, CNTL register contains both values of the two 4-bit
peripheral counters (PCNT21 and PCNT20).
CPU write access has priority over count or reload of the counter.
Bit 7 6 5 4 3 2 1 0
(1)
CNT[15:8]
(2)
BCNT1[7:0]
+0x0B
(3)
PCNT1[7:0]
(4)
PCNT21[3:0] PCNT20[3:0]
Initial value 1 1 1 1 1 1 1

2. Using BTC1.
3. Using PEC1.
4. Using PEC2.
 Bit 7:0 – CNT[15:8]: Counter High Byte

These bits hold the LSB count value of the 16-bit counter register.
 Bit 7:0 – BCNT1[7:0]: Counter 1 Byte
These bits hold the count value of the 8-bit BTC1.
 Bit 7:0 – PCNT1[7:0]: Peripheral Counter 1 Byte
These bits hold the count value of the 8-bit peripheral counter 1. Writing this register requires special attention: any
ongoing serial communication will be corrupted.
 Bit 7:4 – PCNT21[3:0]: Peripheral Counter High Bits
These bits hold the count value of the 4-bit peripheral high counter. Writing this register requires special attention:
any ongoing serial communication will be corrupted.
 Bit 3:0 – PCNT20[3:0]: Peripheral Counter Low Bits
These bits hold the count value of the 4-bit peripheral low counter. Writing this register requires special attention:
any ongoing serial communication will be corrupted.
XMEGA E MANUAL 333

23.7.13 CMPL – Compare Register Low
When the timer/counter is in 16-bit timer/counter configuration, CMP register contains the low byte of the 16-bit compare
value (CMP). For more details on reading and writing 16-bit registers, refer to “Accessing 16-bit Registers” on page 13.
When the timer/counter is in a configuration that enables CNT0, CMPL register contains the 8-bit compare value
(BCMP0).
Bit 7 6 5 4 3 2 1 0
(1)
CMP[7:0]
+0x0C (2)
BCMP0[7:0]

2. Using BTC0.
 Bit 7:0 – CMP[7:0]: Compare Low Byte

These bits hold the LSB compare value of the 16-bit timer/counter when it is used in single slop PWM.
 Bit 7:0 – BCMP0[7:0]: Compare 0 Byte
These bits hold the compare value of the 8-bit BTC0 when it is used in single slop PWM.
23.7.14 CMPH – Compare Register High

When the timer/counter is in 16-bit timer/counter configuration, CMPH register contains the high byte of the 16-bit
compare value (CMP). For more details on reading and writing 16-bit registers, refer to “Accessing 16-bit Registers” on
page 13.
When the timer/counter is in a configuration that enables CNT1, CMPH register contains the 8-bit compare value
(BCMP1).
Bit 7 6 5 4 3 2 1 0
(1)
CMP[15:8]
+0x0D (2)
BCMP1[7:0]

2. Using BTC1.
 Bit 7:0 – CMP[15:8]: Compare High Byte

These bits hold the MSB compare value of the 16-bit timer/counter when it is used in single slop PWM.
 Bit 7:0 – BCMP1[7:0]: Compare 1 Byte
These bits hold the compare value of the 8-bit BTC1 when it is used in single slop PWM.
XMEGA E MANUAL 334

23.7.15 PERCAPTL – Period and Capture Register Low
When the timer/counter is in 16-bit timer/counter configuration, PERCAPTL register contains either the low byte of the
16-bit period value (PER[7:0]) or the low byte of the 16-bit capture value (CAPT[7:0]). For more details on reading and
writing 16-bit registers, refer to “Accessing 16-bit Registers” on page 13.
When the timer/counter is in a configuration that enables CNT0, PERCAPTL register contains either the 8-bit period
value (BPER0) or either the 8-bit capture value (BCAPT0).
Bit 7 6 5 4 3 2 1 0
(1)
PER[7:0]
CAPT[7:0]
+0x0E
(2)
BPER0[7:0]
BCAPT0[7:0]

2. Using BTC0.
 Bit 7:0 – PER[7:0]: Period Low Byte

These bits hold the LSB period value of the 16-bit timer/counter.
 Bit 7:0 – CAPT[7:0]: Capture Value Low Byte
These bits hold the LSB capture value of the 16-bit timer/counter when an event is received.
 Bit 7:0 – BPER0[7:0]: Period Byte 0
These bits hold the period value of the 8-bit BTC0.
 Bit 7:0 – BCAPT0[7:0]: Capture Value Byte 0
These bits hold the capture value of the 8-bit BTC0 when an event is received.
XMEGA E MANUAL 335

23.7.16 PERCAPTH – Period and Capture Register High
When the timer/counter is in 16-bit timer/counter configuration, PERCAPTH register contains either the high byte of the
16-bit period value (PER) or the high byte of the 16-bit capture value (CAPT). For more details on reading and writing 16-
bit registers, refer to “Accessing 16-bit Registers” on page 13.
When the timer/counter is in a configuration that enables CNT1, PERCAPTH register contains either the 8-bit period
value (BPER1) or either the 8-bit capture value (BCAPT1).
Bit 7 6 5 4 3 2 1 0
(1)
PER[15:8]
CAPT[15:8]
+0x0F
(2)
BPER1[7:0]
BCAPT1[7:0]

2. Using BTC1.
 Bit 7:0 – PER[15:8]: Period High Byte

These bits hold the MSB period value of the 16-bit timer/counter.
 Bit 7:0 – CAPT[15:8]: Capture Value High Byte
These bits hold the MSB capture value of the 16-bit timer/counter when an event is received.
 Bit 7:0 – BPER1[7:0]: Period Byte 1
These bits hold the period value of the 8-bit timer/counter 1.
 Bit 7:0 – BCAPT1[7:0]: Capture Value Byte 1
These bits hold the capture value of the 8-bit timer/counter 1 when an event is received.
XMEGA E MANUAL 336

+0x00 CTRLA LUT0OUT [1:0] PORTSEL[1:0] - LUTCONF[2:0] 325
+0x01 CTRLB IN3SEL[1:0] IN2SEL[1:0] IN1SEL[1:0] IN0SEL[1:0] 326
+0x02 CTRLC EVASYSEL1 EVASYSEL0 DLYSEL[1:0] DLYCONF1[1:0] DLYCONF0[1:0] 326
+0x03 CTRLD TRUTH1[3:0] TRUTH0[3:0] 327
+0x04 CTRLE CMDSEL TCSEL[2:0] CLKSEL[3:0] 328
+0x05 CTRLF CMDEN[1:0] CMP1 CMP0 CCEN1 CCEN0 MODE[1:0] 329
+0x06 CTRLG EVACTEN EVACT1[1:0] EVACT0[1:0] EVSRC[2:0] 330
23.8.1 Register Summary – One 16-bit T/C (TC16)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BIt 2 BIt 1 Bit 0 Page
+0x07 INTCTRL - UNF0IE - CC0IE UNFINTLVL[1:0] CCINTLVL[1:0] 330
+0x08 INTFLAGS - UNF0IF - CC0IF - - - - 331
23.8.1.1 T/C in Normal Mode with Programmable Period (NORMAL)

+0x09 Reserved - - - - - - - -
+0x0A CNTL CNT[7:0] 332
+0x0B CNTH CNT[15:8] 333
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E PERCAPTL PER[7:0] 335
+0x0F PERCAPTH PER[15:8] 336
23.8.1.2 T/C in Capture Mode (CAPT)

+0x09 Reserved - - - - - - - -
+0x0A CNTL CNT[7:0] 332
+0x0B CNTH CNT[15:8] 333
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E PERCAPTL CAPT[7:0] 335
+0x0F PERCAPTH CAPT[15:8] 336
23.8.1.3 T/C in PWM Modes with Period Fixed to MAX (PWM or SSPWM)
+0x09 Reserved - - - - - - - -
+0x0A CNTL CNT[7:0] 332
+0x0B CNTH CNT[15:8] 333
+0x0C CMPL CMP[7:0] 334
+0x0D CMPH CMP[15:8] 334
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
XMEGA E MANUAL 337

23.8.2 Register Summary – One 8-bit T/C (BTC0)
+0x07 INTCTRL - UNF0IE - CC0IE UNFINTLVL[1:0] CCINTLVL[1:0] 330
+0x08 INTFLAGS - UNF0IF - CC0IF - - - - 331

+0x09 Reserved - - - - - - - -
+0x0A CNTL BCNT0[7:0] 332
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E PERCAPTL BPER0[7:0] 335
+0x0F Reserved - - - - - - - -

+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E PERCAPTL BCAPT0[7:0] 335
+0x0F Reserved - - - - - - - -
23.8.2.3 T/C in PWM Modes with Programmable Period (PWM or SSPWM)

+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C CMPL BCPM0[7:0] 334
+0x0D Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
23.8.3 Register Summary – Two 8-bit T/C (BTC01)

Address Name Bit 7 Bit 6 BIt 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x07 INTCTRL UNF1IE UNF0IE CC1IE CC0IE UNFINTLVL[1:0] CCINTLVL[1:0] 330
+0x08 INTFLAGS UNF1IF UNF0IF CC1IF CC0IF - - - - 331

+0x09 Reserved - - - - - - - -
+0x0B CNTH BCNT1[7:0] 333
+0x0C Reserved - - - - - - - -
XMEGA E MANUAL 338

+0x0D Reserved - - - - - - - -
+0x0F PERCAPT BPER1[7:0] 336
+0x09 Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0F PERCAPT BCAPT1[7:0] 336
23.8.3.3 T/C in PWM Modes with Period Fixed to MAX (PWM or SSPWM)
+0x09 Reserved - - - - - - - -
+0x0C CMPL BCMP0[7:0] 334
+0x0D CMPH BCMP1[7:0] 334
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
23.8.4 Register Summary – One 8-bit T/C and one 8-bit Tx PEC (BTC0PEC1)
+0x07 INTCTRL PEC1IE UNF0IE - CC0IE UNFINTLVL[1:0] CCINTLVL[1:0] 330
+0x08 INTFLAGS PEC1IF UNF0IF - CC0IF - - - - 331
+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
XMEGA E MANUAL 339

+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0D PERCAPTL BCAPT0[7:0] 335
+0x0F Reserved - - - - - - - -

+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
23.8.4.4 Transmitter Peripheral Counter (PEC)

+0x09 PLC PLC[7:0] 332
+0x0A Reserved - - - - - - - -
+0x0B CNTH PCNT1[7:0] 333
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
23.8.5 Register Summary – One 8-bit T/C and One 8-bit Rx PEC (PEC0BTC1)
Address Name BIt 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 BIt 1 BIt 0 Page
+0x07 INTCTRL UNF1IE PEC0IE CC1IE - UNFINTLVL[1:0] CCINTLVL[1:0] 330
+0x08 INTFLAGS UNF1IF PEC0IF CC1IF - - - - - 331
23.8.5.1 Receiver Peripheral Counter (PEC)

+0x09 PLC PLC[7:0] 332
+0x0A CNTL PCNT0[7:0] 332
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
XMEGA E MANUAL 340

+0x09 Reserved - - - - - - - -
+0x0A Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F PERCAPTH BPER1[7:0] 336

+0x09 Reserved - - - - - - - -
+0x0A Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F PERCAPTH BCAPT1[7:0] 336

+0x09 Reserved - - - - - - - -
+0x0A Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D CMPH BCMP1[7:0] 334
+0x0E Reserved - - - - - - - -
+0x0F PERCAPTH BPER1[7:0] 336
23.8.6 Register Summary – Two 8-bit Tx/Rx PEC (PEC01)

Address Name BIt 7 Bit 6 Bit 5 Bit 4 Bit 3 BIt 2 Bit 1 Bit 0 Page
+0x07 INTCTRL PEC1IE PEC0IE - - UNFINTLVL[1:0] CCINTLVL[1:0] 330
+0x08 INTFLAGS PEC1IF PEC0IF - - - - - - 331
23.8.6.1 Transmitter/Receiver Peripheral Counter (PEC)

+0x09 PLC PLC[7:0] - (Same length for Tx & Rx) 332
+0x0A CNTL PCNT0[7:0] 332
+0x0B CNTH PCNT1[7:0] 333
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
XMEGA E MANUAL 341

23.8.7 Register Summary – One 8-bit T/C and Two 4-bit Tx/Rx PEC (BTC0PEC2)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 BIt 3 Bit 2 Bit 1 Bit 0 Page
+0x07 INTCTRL PEC2HIE UNF0IE PEC2LIE CC0IE UNFINTLVL[1:0] CCINTLVL[1:0] 330
+0x08 INTFLAGS PEC2HIF UNF0IF PEC2LIF CC0IF - - - - 331

+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -

+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
23.8.8 T/C in PWM Modes with Programmable Period (PWM or SSPWM)

+0x09 Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
23.8.8.1 Transmitter/Receiver Peripheral Counter (PEC)

+0x09 PLC - - - - PLC[3:0] - (Same length for Tx & Rx) 332
+0x0A Reserved - - - - - - - -
+0x0B CNTH PCNT21[3:0] PCNT20[3:0] 333
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
XMEGA E MANUAL 342

Table 23-19. XCL Interrupt Vectors and their Word Offset Address
0x00 UNF_vect Timer/counter underflow interrupt vector offset
0x02 CC_vect Timer/counter compare or capture interrupt vector offset
23.10 T/C and PEC Register Summary vs. Configuration and Mode
Config.
Mode
Mode
Mode
@Off.
@Off.
@Off.
Register Field Register Field Register Field
+0x09 Reserved +0x09 Reserved +0x09 Reserved
PWM & 1SHOT
+0x0A CNTL CNT[7:0] +0x0A CNTL CNT[7:0] +0x0A CNTL CNT[7:0]
NORMAL
+0x0B CNTH CNT[15:8] +0x0B CNTH CNT[15:8] +0x0B CNTH CNT[15:8]

TC16
CAPT
+0x0C Reserved +0x0C Reserved +0x0C CMPL CMP[7:0]
+0x0D Reserved +0x0D Reserved +0x0D CMPH CMP[15:8]
+0x0E PERCAPTL PER[7:0] +0x0E PERCAPTL CAPT[7:0] +0x0E Reserved
+0x0F PERCAPTH PER[15:8] +0x0F PERCAPTH CAPT[15:8] +0x0F Reserved
PWM & 1SHOT
+0x0A CNTL BCNT0[7:0] +0x0A CNTL BCNT0[7:0] +0x0A CNTL BCNT0[7:0]
NORMAL
+0x0B Reserved +0x0B Reserved +0x0B Reserved

CAPT
BTC0
+0x0C Reserved +0x0C Reserved +0x0C CMPL BCMP0[7:0]

+0x0D Reserved +0x0D Reserved +0x0D Reserved
+0x0E PERCAPTL BPER0[7:0] +0x0E PERCAPTL BCAPT0[7:0] +0x0E PERCAPTL BPER0[7:0]
+0x0F Reserved +0x0F Reserved +0x0F Reserved
PWM & 1SHOT
NORMAL
+0x0B CNTH BCNT1[7:0] +0x0B CNTH BCNT1[7:0] +0x0B CNTH BCNT1[7:0]

BTC01
CAPT

+0x0D Reserved +0x0D Reserved +0x0D CMPH BCMP1[7:0]
+0x0E PERCAPTL BPER0[7:0] +0x0E PERCAPTL BCAPT0[7:0] +0x0E Reserved
+0x0F PERCAPTH BPER1[7:0] +0x0F PERCAPTH BCAPT1[7:0] +0x0F Reserved
+0x09 PLC PLC[7:0] +0x09 PLC PLC[7:0] +0x09 PLC PLC[7:0]

PWM & 1SHOT

BTC0PEC1
NORMAL
+0x0B CNTH PCNT1[7:0] +0x0B CNTH PCNT1[7:0] +0x0B CNTH PCNT1[7:0]

CAPT


PWM & 1SHOT
+0x0A CNTL PCNT0[7:0] +0x0A CNTL PCNT0[7:0] +0x0A CNTL PCNT0[7:0]

PEC0BTC1
NORMAL
+0x0B CNTH BCNT1[7:0] +0x0B CNTH BCNT1[7:0] +0x0B CNTH BCNT1[7:0]

CAPT
+0x0C Reserved +0x0C Reserved +0x0C Reserved

+0x0D Reserved +0x0D Reserved +0x0D CMPH BCMP1[7:0]
+0x0E Reserved +0x0E Reserved +0x0E Reserved
+0x0F PERCAPTH BPER1[7:0] +0x0F PERCAPTH BCAPT1[7:0] +0x0F PERCAPTH BPER1[7:0]
+0x09 PLC PLC[7:0]

+0x0A CNT0 PCNT0[7:0]
NORMAL
+0x0B CNT1 PCNT1[7:0]

PEC01
+0x0C Reserved
+0x0D Reserved
+0x0E Reserved
+0x0F Reserved

PWM & 1SHOT

BTC0PEC2
NORMAL
+0x0B CNTH PCNT20‐21[3:0] +0x0B CNTH PCNT20‐21[3:0] +0x0B CNTH PCNT20‐21[3:0]

CAPT

XMEGA E MANUAL 343

24. CRC – Cyclic Redundancy Check Generator
24.1 Features
 Cyclic redundancy check (CRC) generation and checking for
 Communication data
 Program or data in flash memory
 Data in SRAM and I/O memory space
 Integrated with flash memory, EDMA controller, and CPU
 Continuous CRC on data going through an EDMA channel
 Automatic CRC of the complete or a selectable range of the flash memory
 CPU can load data to the CRC generator through the I/O interface
 CRC polynomial software selectable to
 CRC-16 (CRC-CCITT)
 CRC-32 (IEEE 802.3)
 Zero remainder detection
24.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data presence in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect the error and may take a corrective action, such as requesting the data to be sent again
or simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3).
 CRC-16:
Polynomial: x16+x12+x5+1
Hex value: 0x1021
 CRC-32:
Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value: 0x04C11DB7
24.3 Operation
The data source for the CRC module must be selected in software as either flash memory, the EDMA channels, or the
I/O interface. The CRC module then takes data input from the selected source and generates a checksum based on
these data. The checksum is available in the CHECKSUM registers in the CRC module. When CRC-32 polynomial is
used, the final checksum read is bit reversed and complemented (see Figure 24-1 on page 345).
For the I/O interface or EDMA controller, which CRC polynomial is used is software selectable, but the default setting is
CRC-16. CRC-32 is automatically used if Flash Memory is selected as the source. The CRC module operates on bytes
only.
XMEGA E MANUAL 344

Figure 24-1. CRC Generator Block Diagram
EDMA Flash
Controller Memory
DATAIN
CTRL
8 16 8 32
CRC-16 CRC-32
crc32
CHECKSUM
bit-reverse +
complement
Checksum read
24.4 CRC on Flash Memory

A CRC-32 calculation can be performed on the entire flash memory, on only the application section, on only the boot
section, or on a software selectable range of the flash memory. Other than selecting the flash as the source, all further
control and setup are done from the NVM controller. This means that the NVM controller configures the memory range to
perform the CRC on, and the CRC is started using NVM commands. Once completed, the result is available in the
checksum registers in the CRC module. For further details on setting up and performing CRC on flash memory, refer to
“Memory Programming” on page 411.
24.5 CRC on EDMA Data

CRC-16 or CRC-32 calculations can be performed on data passing through any EDMA channel. Once a EDMA channel
is selected as the source, the CRC module will continuously generate the CRC on the data passing through the EDMA
channel. The checksum is available for readout once the EDMA transaction is completed or aborted. A CRC can be
performed not only on communication data, but also on data in SRAM or I/O memory by passing these data through an
EDMA channel. If the latter is done, the destination register for the EDMA data can be the data input (DATAIN) register in
the CRC module. Refer to “EDMA – Enhanced Direct Memory Access” on page 50 for more details on setting up EDMA
transactions.
24.6 CRC using the I/O Interface

CRC can be performed on any data by loading them into the CRC module using the CPU and writing the data to the
DATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is
done continuously for each byte. New data can be written for each cycle. The CRC complete is signaled by writing the
BUSY bit in the STATUS register.
XMEGA E MANUAL 345

Bit 7 6 5 4 3 2 1 0
+0x00 RESET[1:0] CRC32 – SOURCE[3:0]
Read/Write R/W R/W R/W R R/W R/W R/W R/W
 Bit 7:6 – RESET[1:0]: Reset

These bits are used to reset the CRC module, and they will always be read as zero. The CRC registers will be
reset one peripheral clock cycle after the RESET[1] bit is set.
Table 24-1. CRC Reset
RESET[1:0] Group configuration Description
00 NO No reset
01 – Reserved
10 RESET0 Reset CRC with CHECKSUM to all zeros
11 RESET1 Reset CRC with CHECKSUM to all ones
 Bit 5 – CRC32: CRC-32 Enable

Setting this bit will enable CRC-32 instead of the default CRC-16. It cannot be changed while the BUSY flag is set.
 Bit 3:0 – SOURCE[3:0]: Input Source
These bits select the input source for generating the CRC. The selected source is locked until either the CRC gen-
eration is completed or the CRC module is reset. CRC generation complete is generated and signaled from the
selected source when used with the EDMA controller or flash memory.
Table 24-2. CRC Source Select
SOURCE[3:0] Group configuration Description
0000 DISABLE CRC disabled
0001 IO I/O interface
0010 FLASH Flash
0011 – Reserved for future use
0100 EDMACH0 EDMA controller channel 0
1xxx – Reserved for future use
XMEGA E MANUAL 346

Bit 7 6 5 4 3 2 1 0
+0x01 – – – – – – ZERO BUSY

 Bit 1 – ZERO: Checksum Zero
This flag is set if the CHECKSUM is zero when the CRC generation is complete. It is automatically cleared when a
new CRC source is selected.
When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum
should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little
endian) to the data, the final result in the checksum register will be zero.
See the description of CHECKSUM to read out different versions of the CHECKSUM.
 Bit 0 – BUSY: Busy
This flag is read as one when a source configuration is selected and as long as the source is using the CRC mod-
ule. If the I/O interface is selected as the source, the flag can be cleared by writing a one this location. If an EDMA
channel if selected as the source, the flag is cleared when the EDMA channel transaction is completed or aborted.
If flash memory is selected as the source, the flag is cleared when the CRC generation is completed.
24.7.3 DATAIN – Data Input Register
Bit 7 6 5 4 3 2 1 0
+0x03 DATAIN[7:0]
Read/Write W W W W W W W W
 Bit 7:0 – DATAIN[7:0]: Data Input

This register is used to store the data for which the CRC checksum is computed. A new CHECKSUM is ready one
clock cycle after the DATAIN register is written.
24.7.4 CHECKSUM0 – Checksum Register 0

CHECKSUM0, CHECKSUM1, CHECKSUM2, and CHECKSUM3 represent the 16- or 32-bit CHECKSUM value and the
generated CRC. The registers are reset to zero by default, but it is possible to write RESET to reset all bits to one. It is
possible to write these registers only when the CRC module is disabled. If NVM is selected as the source, reading
CHECKSUM will return a zero value until the BUSY flag is cleared. If CRC-32 is selected and the BUSY flag is cleared
(i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and
complemented result will be read from CHECKSUM. If CRC-16 is selected or the BUSY flag is set (i.e., CRC generation
is ongoing), CHECKSUM will contain the actual content.
Bit 7 6 5 4 3 2 1 0
+0x04 CHECKSUM[7:0]
 Bit 7:0 – CHECKSUM[7:0]: Checksum Byte 0

These bits hold byte 0 of the generated CRC.
XMEGA E MANUAL 347

Bit 7 6 5 4 3 2 1 0
+0x05 CHECKSUM[15:8]

These bits hold byte 1 of the generated CRC.
Bit 7 6 5 4 3 2 1 0

These bits hold byte 2 of the generated CRC when CRC-32 is used.
24.7.7 CHECKSUM3 – CRC Checksum Register 3
Bit 7 6 5 4 3 2 1 0

These bits hold byte 3 of the generated CRC when CRC-32 is used.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 bit 0 Page
+0x00 CTRL RESET[1:0] CRC32 – SOURCE[3:0] 346
+0x01 STATUS – – – – – – ZERO BUSY 347
+0x02 Reserved – – – – – – – –
+0x03 DATAIN DATAIN[7:0] 347
+0x04 CHECKSUM0 CHECKSUM[7:0] 347
XMEGA E MANUAL 348

25. ADC – Analog to Digital Converter
25.1 Features
 Up to 300 thousand samples per second
 Down to 2.3μs conversion time with 8-bit resolution
 Down to 3.35μs conversion time with 12-bit resolution
 Differential and single-ended input
 Up to 16 single-ended inputs
 16x8 differential input with programmable gain
 Built-in differential gain stage
 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
 Single, continuous and scan conversion options
 Four internal inputs
 Internal temperature sensor
 DAC output
 AVCC voltage divided by 10
 1.1V bandgap voltage
 Internal and external reference options
 Compare function for accurate monitoring of user defined thresholds
 Offset and gain correction
 Averaging
 oversampling and decimation
 Optional event triggered conversion for accurate timing
 Optional interrupt/event on compare result
 Optional EDMA transfer of conversion results
25.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300
thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential
measurements can be done. A programmable gain stage is available to increase the dynamic range. In addition, several
internal signal inputs are available. The ADC can provide both signed and unsigned results.
The ADC measurements can either be started by application software or an incoming event from another peripheral in
the device. The ADC measurements can be started with predictable timing, and without software intervention. It is
possible to use EDMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
When operation in noisy conditions, the average feature can be enabled to increase the ADC resolution. Up to 1024
samples can be averaged, enabling up to 16-bit resolution results. In the same way, using the oversampling and
decimation mode, the ADC resolution is increased up to 16-bits, which results in up to 4-bit extra LSB resolution. The
ADC includes various calibration options. In addition to standard production calibration, the user can enable the offset
and gain correction to improve the absolute ADC accuracy.
XMEGA E MANUAL 349

Figure 25-1. ADC Block Diagram
VIN VOUT
S&H Σ 2x
ADC DAC
ADC0
ADC1 2 bits
• CMP
•
•
ADC14 Stage Stage
ADC15
VINP
1 2
< Threshold
2 2
GAINCORR > (Int. Req.)
Internal clkADC
Signals
½x - 64x Adder/Multiplier
G RES
Digital Correction Logic
OFFSETCORR
ADC0 Averaging
•
•
•
VINN
ADC
ADC7 Number of
Correction Samples
Enable
Internal 1.00V
Internal AVCC /1.6 Enable Right Shift
Reference Start
Internal AVCC/2 Action
Voltage Select
AREFA Mode CORRCTRL AVGCTRL
AREFD Resolution
CTRL REFCTRL CTRLA EVCTRL

MUXCTRL CTRLB
25.3 Input Sources

Input sources are the voltage inputs that the ADC can measure and convert. Three types of measurements can be
selected:
 Differential input with programmable gain
 Single-ended input
 Internal input
The input pins are used for single-ended and differential input, while the internal inputs are directly available inside the
device. Port A and Port D pins can be input to ADC.
The ADC is differential, and so for single-ended measurements the negative input is connected to a fixed internal value.
The three types of measurements and their corresponding input options are shown in Figure 25-5 on page 352 to Figure
25-6 on page 353.
25.3.1 Differential Inputs

When differential inputs are enabled, all input pins can be selected as positive input, and input pins 0 to 7 can be selected
as negative input. For gain settings other than 1x, the differential input is first sampled and amplified by the gain stage
before the result is converted. The gain is selectable to 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain.
XMEGA E MANUAL 350

Figure 25-2. Differential Measurement
ADC0
ADC1 INPUTMODE = 10
•
•
•
ADC14
ADC15 Gain & Offset
½x - 64x
ADC Error
Correction
ADC0
•
• CORREN
ADC3
GND
INTGND
ADC0
ADC1 INPUTMODE = 11
•
•
•
ADC14
ADC15 Gain & Offset
½x - 64x
ADC Error
Correction
ADC4
•
• CORREN
ADC7
GND
INTGND
25.3.2 Single-ended Input

For single-ended measurements, all input pins can be used as inputs. Single-ended measurements can be done in both
signed and unsigned mode. For normal operation of the ADC, gain should be programmed by the application to 1x in this
mode.
The negative input is connected to internal ground in signed mode.
Figure 25-3. Single-ended Measurement in Signed Mode
ADC0
ADC1
•
•
• Gain & Offset
ADC14
ADC15
1x
ADC Error
Correction
CORREN
In unsigned mode, the negative input is connected to half of the voltage reference (VREF) voltage minus a fixed offset.
The nominal value for the offset is:
V = V REF  0.05
Since the ADC is differential, the input range is VREF to zero for the positive single-ended input. The offset enables the
ADC to measure zero crossing in unsigned mode.
XMEGA E MANUAL 351

Figure 25-4. Single-ended Measurement in Unsigned Mode
ADC0
ADC1
•
•
• Gain & Offset
ADC14
ADC15 VREF
1x
ADC Error
Correction
− ΔV
2
CORREN
25.3.3 Internal Inputs

These internal signals can be measured or used by the ADC.
 Temperature sensor
 Bandgap voltage
 AVCC scaled
 DAC output
 Pad ground and internal ground
The temperature sensor gives an output voltage that increases linearly with the internal temperature of the device. One
or more calibration points are needed to compute the temperature from a measurement of the temperature sensor. The
temperature sensor is calibrated at one point in production test, and the result is stored to TEMPESENSE0 and
TEMPSENSE1 in the production signature row. For more calibration condition details, refer to the device datasheet.
The bandgap voltage is an accurate internal voltage reference.
VCC can be measured directly by scaling it down by a factor of 10 before the ADC input. Thus, a VCC of 1.8V will be
measured as 0.18V, and VCC of 3.6V will be measured as 0.36V. This enables easy measurement of the VCC voltage.
The internal signals need to be enabled before they can be measured. Refer to their manual sections for Bandgap and
DAC for details of how to enable these. The sample rate for the internal signals is lower than that of the ADC. Refer to the
ADC characteristics in the device datasheets for details.
For differential measurement pad ground (GND) and internal ground (INTGND) can be selected as negative input. Pad
ground is the ground level on the pin and identical or very close to the external ground. Internal ground is the internal
device ground level. For normal operation of the ADC, gain should be programmed by the application to 1x in this mode.
Internal ground is used as the negative input when other internal signals are measured in single-ended signed mode.
Figure 25-5. Internal Measurement in Single-ended Signed Mode
TEMP REF
BANDGAP REF
AVCC SCALED Gain & Offset
DAC 1x
ADC Error
Correction
CORREN
To measure the internal signals in unsigned mode, the negative input is connected to a fixed value given by the formula
below, which is half of the voltage reference (VREF) minus a fixed offset, as it is for single-ended unsigned input. Refer to
Table 25-2 on page 355 for details.
V REF
V INN = -------------- – V
2
XMEGA E MANUAL 352

Figure 25-6. Internal Measurement in Unsigned Mode
TEMP REF
BANDGAP REF
AVCC SCALED Gain & Offset
DAC
VREF
1x
ADC Error
Correction
− ΔV
2
CORREN
25.4 Sampling Time Control

To support applications with high source output resistance, the sampling time can be increased by steps of a half ADC
clock cycle.
25.5 Voltage Reference Selection

The following voltages can be used as the reference voltage (VREF) for the ADC:
 Accurate internal 1.00V voltage generated from the bandgap
 Internal AVCC/1.6 voltage
 Internal AVCC/2 voltage
 External voltage applied to AREF pin on port A
 External voltage applied to AREF pin on port D
Figure 25-7. ADC Voltage Reference Selection

Internal 1.00V
Internal AVCC/1.6
AREFA VREF
AREFD
Internal AVCC/2
25.6 Conversion Result

The result of the analog-to-digital conversion is written to the channel result register. The ADC is either in signed or
unsigned mode. This setting is global for the ADC and for the ADC channel.
In signed mode, negative and positive results are generated. Signed mode must be used when the ADC channel is set
up for differential measurements. In unsigned mode, only single-ended or internal signals can be measured. With 12-bit
resolution, the TOP value of a signed result is 2047, and the results will be in the range -2048 to +2047
(0xF800 - 0x07FF).
The ADC transfer function can be written as:
V INP – V INN
RES = -------------------------------  GAIN   TOP + 1 
V REF
VINP and VINN are the positive and negative inputs to the ADC.
For differential measurements, GAIN is software selectable from 1/2 to 64. For single-ended and internal measurements,
GAIN must be set by software to 1x and VINP is the internal ground.
In unsigned mode, only positive results are generated. The TOP value of an unsigned result is 4095, and the results will
be in the range 0 to +4095 (0x0 - 0x0FFF).
The ADC transfer functions can be written as:
V INP –  – V 
RES = ---------------------------------   TOP + 1 
V REF
VINP is the single-ended or internal input.
XMEGA E MANUAL 353

The ADC can be configured to generate either an 8-bit or a 12-bit result. A result with lower resolution will be available
faster. See the “ADC Clock and Conversion Timing” on page 359 for a description on the propagation delay.
The result register is 16 bits wide, and data are stored as right adjusted 16-bit values. Right adjusted means that the
eight least-significant bits (lsb) are found in the low byte. A 12-bit result can be represented either left or right adjusted.
Left adjusted means that the eight most-significant bits (msb) are found in the high byte.
When the ADC is in signed mode, the msb represents the sign bit. In 12-bit right adjusted mode, the sign bit (bit 11) is
padded to bits 12-15 to create a signed 16-bit number directly. In 8-bit mode, the sign bit (bit 7) is padded to the entire
high byte.
Table 25-1 on page 354 to Table 25-2 on page 355 show the different input options, the signal input range, and the result
representation with 12-bit right adjusted mode.
Table 25-1. Signed Differential Input (with Gain), Input Voltage Versus Output Code
VINP Signed
Read code Decimal value
VINN + VREF / GAIN 0x07FF 2047
VINN + 0.9995 VREF / GAIN 0x07FE 2046
VINN + 0.9990 VREF / GAIN 0x07FD 2045
… … …
VINN + 0.5007 VREF / GAIN 0x0401 1025
VINN + 0.5002 VREF / GAIN 0x0400 1024
VINN + 0.4998 VREF / GAIN 0x03FF 1023
VINN + 0.4993 VREF / GAIN 0x03FE 1022
… … …
VINN + 0.0010 VREF / GAIN 0x0002 2
VINN + 0.0005 VREF / GAIN 0x0001 1
VINN 0x0000 0
VINN - 0.0005 VREF / GAIN 0xFFFF -1
VINN - 0.0010 VREF / GAIN 0xFFFE -2
… … …
VINN - 0.9990 VREF / GAIN 0xF802 -2046
VINN - 0.9995 VREF / GAIN 0xF801 -2047
VINN - VREF / GAIN 0xF800 -2048
XMEGA E MANUAL 354

Table 25-2. Single-ended, Input Voltage Versus Output Code
VINP Signed Unsigned
Read code Decimal value Read code Decimal value
VREF 0x07FF 2047 0x0FFF (saturation) 4095 (saturation)
0.9998 VREF - - 0x0FFF (saturation) 4095 (saturation)
0.9995 VREF 0x07FE 2046 0x0FFF (saturation) 4095 (saturation)
0.9993 VREF - - 0x0FFF (saturation) 4095 (saturation)
0.9990 VREF 0x07FD 2045 0x0FFF (saturation) 4095 (saturation)
… ... ... ... ...
0.9500 VREF 0x0799 1945 0x0FFF 4095
0.9498 VREF - - 0x0FFE 4094
0.9495 VREF 0x0798 1944 0x0FFD 4093
0.9493 VREF - - 0x0FFC 4092
0.9490 VREF 0x0797 1943 0x0FFB 4091
… ... ... ... ...
0.5005 VREF 0x0400 1024 0x08CE 2254
0.5002 VREF - - 0x08CD 2253
0.5000 VREF 0x03FF 1023 0x08CC 2252
0.4998 VREF - - 0x08CB 2251
0.4995 VREF 0x03FE 1022 0x08CA 2250
… … … … …
0.0005 VREF 0x0001 1 0x00CF 207
0.0002 VREF - - 0x00CE 206
GND 0x0000 0 0x00CD 205
-0.0002 VREF - - 0x00CC 204
-0.0005 VREF 0xFFFE -1 0x00CB 203
… … … … …
-0.0593 VREF 0xFF9B -101 0x0003 3
-0.0495 VREF - - 0x0002 2
-0.0498 VREF 0xFF9A -102 0x0001 1
-0.0500 VREF - - 0x0000 0
-0.0503 VREF 0xFF99 -103 0x0000 (saturation) 0 (saturation)
-0.0506 VREF - - 0x0000 (saturation) 0 (saturation)
-0,0508 VREF 0xFF98 -104 0x0000 (saturation) 0 (saturation)
XMEGA E MANUAL 355

25.7 Calibration and Correction
25.7.1 Production Test Calibration

The ADC has built-in linearity calibration. Values of electronic elements in ADC stage 1 and stage 2, as shown in Figure
25-1 on page 350, are adjusted by this calibration. The value from the production test calibration must be loaded from the
signature row and into the ADC calibration register (CAL) from software to achieve specified accuracy. The production
test calibration must be loaded prior to any other hardware correction.
25.7.2 Offset and Gain Correction

Inherent gain and offset errors affect the absolute accuracy of the ADC.
The offset error is defined as the deviation of the current ADC transfer function from ideal straight line at zero input
voltage. The offset error cancellation is handled by a 12-bit register (OFFSETCORR). The offset correction value is
subtracted from the data converted before writing the result (RES) register. The offset error calculation must be done
prior to any gain error correction.
The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line, after compensating
for offset error. The gain error cancellation is handled via 12-bit register (GAINCORR).
To correct these two errors, the bit CORREN must be set in CORRCTRL register. The equation that is implemented in
hardware for correcting the output is:
RES =  V IN – OFFSETCORR   GAINCORR
In single conversion, a latency of 13 peripheral clock cycles (clkPER) is added for the final conversion result availability.
Since the correction time is always less than propagation delay, in free running mode this latency affects only the first
conversion time. All the other conversions are done within the normal sampling rate.
Figure 25-8. ADC Offset Error

Output Code
Offset
-VREF error
Input Voltage
VREF
ADC with
corrected offset
ADC with
uncorrected offset
XMEGA E MANUAL 356

Figure 25-9. ADC Gain Error
Output Code
Gain error
-VREF
Input Voltage
VREF
ADC with
corrected gain
ADC with
uncorrected gain
25.7.3 Offset Error Measurement

a. Configure MUXPOS and MUXNEG to connect both the inputs of ADC to the same value (GND is recommended).
b. Start a conversion on the channel.
c. Wait for interrupt.
d. Read the value from channel result register (RES) which corresponds to OFFSETCORR value.
25.7.4 Gain Error Measurement

a. Configure MUXPOS and MUXNEG to connect each input of ADC to appropriate voltage levels to produce close to
maximum code taking into account the gain factor and a possible saturation.
b. Start a conversion on the channel.
c. Wait for interrupt.
d. Read the value from channel result register (RES) which corresponds to captured value (CapturedValue).
Gain correction is coded as:
GAINCORR = 2048  ----------------------------------------------------------------------------------------------

ExpectedValue
CapturedValue – OFFSETCORR
Notes: 1. GAINCORR precision is 1-bit integer + 11-bit fraction, implies 0.5 ≤ GAINCORR < 2.0.
2. GAINCORR range is from 0x0400 (0.5) up to 0x0FFF (1.99951171875).
3. No gain correction (1x gain) is set when GAINCORR = 0x0800 (1.0).
25.8 Starting a Conversion

Before a conversion is started, the desired input channel source must be selected. An ADC conversion can be started
either by the application software writing to the start conversion bit, or from any of the event triggers in the Event System.
XMEGA E MANUAL 357

25.8.1 Input Source Scan
It is possible to select a range of consecutive input sources that is automatically scanned and measured when a
conversion is started. This is done by setting the first (lowest) positive ADC channel input using the MUX control register,
and a number of consecutive positive input sources. When a conversion is started, the first selected input source is
measured and converted, then the positive input source selection is incremented after each conversion until it reaches
the specified number of sources to scan.
25.8.2 Compare Function

The ADC has a built-in 12-bit compare function. The ADC compare register can hold a 12-bit value that represents a
threshold voltage. The ADC channel can be configured to automatically compare its result with this compare value to
give an interrupt or event only when the result is above or below the threshold.
25.8.3 Averaging
The ADC has inherently 12-bit resolution but it is possible to obtain 16-bit results by averaging up to 1024 samples. The
numbers of samples to be averaged is specified in AVGCTRL register and the averaged output is written to channel
output register.
The number of samples to be averaged is set by the SAMPNUM bits in “ AVGCTRL – Average Control Register” on page
378. A maximum of 1024 samples can be averaged. The final result is rounded off to 16-bit value. After accumulating
programmed number of bits, division is achieved by automatic right shifting and result will be available in channel result
register (RES).
The output is calculated as per following formula:
Output =   2
SAMPNUM
16bitRoundOff >> RIGHTSHIFT
For SAMPNUM > 0, Table 25-3 shows the number of samples which will be accumulated and the automatic number of
right shifts internally performed.
Table 25-3. Final Result Versus Number of Samples to Average
Final result resolution Number of samples Number of automatic right shift for round-off
12-bits 1 0
13-bits 2 0
14-bits 4 0
15-bits 8 0
16-bits 16 0
16-bits 32 1
16-bits 64 2
16-bits 128 3
16-bits 256 4
16-bits 512 5
16-bits 1024 6
XMEGA E MANUAL 358

25.8.4 Oversampling and Decimation
Whilst averaging smooths out noise it doesn’t increase the resolution. It is possible to increase the resolution of the ADC
provided sufficient noise is present in the system and the sampling frequency is adequately higher than the signal
frequency. Refer application note AVR1629. In oversampling and decimation mode the ADC resolution is increased from
12-bit to programmed 13, 14, 15, or 16 bit. If n-bit resolution is to be increased, 4n samples are accumulated (added) and
the result is right shifted by n-bits. This method will result in n-bit extra LSB bit resolution
For this increased resolution to be valid, the following assumptions have to be met:
 Input to ADC is over-sampled input and the corresponding pre-scalar setting is already done
 The ADC sampling frequency fs > (4n * 2) * f i
(f i = highest frequency component of input signal, n = number of bits increased)
 Artificial noise addition is assumed to be added if required to input for minimum LSB toggling
 Range of over-sampled output is assumed to be between 13-bits and 16-bits
Table 25-4. Configuration Required for Averaging Function to Output Corresponding Over-sampled Output
Result resolution Number of samples to average SAMPNUM No. of automatic right shift RIGHTSHIFT
13-bit 41 = 4 0010 0 001
14-bit 42 = 16 0100 0 010

3
15-bit 4 = 64 0110 2 001
16-bit 44 = 256 1000 4 000
25.9 ADC Clock and Conversion Timing

The ADC is clocked from the peripheral clock (clkPER). The ADC can prescale the peripheral clock to provide an ADC
Clock (clkADC) that matches the application requirements and is within the operating range of the ADC.
Figure 25-10.ADC Prescaler
clk PER 9-bit ADC prescaler

clk PER /128
clkPER /256
clkPER /512
clkPER /16
clkPER /32
clkPER /64
clkPER /8
clkPER /4
PRESCALER[2:0]
clk ADC
The maximum ADC sample rate is given by:
f ADC
SampleRate = ----------------------------------------------------------------------------------------------------------------------------------------
0.5   RESOLUTION + SAMPVAL  + GAINFACTOR
The propagation delay of an ADC measurement is given by:
1
PropagationDelay = -------------------------------
SampleRate
where
XMEGA E MANUAL 359

 RESOLUTION is the resolution, 8 or 12 bits
 SAMPVAL is the value programmed in the Sampling Time Control register
 GAINFACTOR = 0 (1x gain), 1 (1/2x, 2x, 4x gain), 3 (32x, 64x gain)
The most-significant bit (msb) of the result is converted first, and the rest of the bits are converted during the next three
(for 8-bit results) or five (for 12-bit results) ADC clock cycles. Converting one bit takes a half ADC clock period. During the
last cycle, the result is prepared before the interrupt flag is set and the result is available in the result register for readout.
25.9.1 Single Conversion with 1x Gain

Figure 25-11 on page 360 shows the ADC timing for a single conversion with 1x gain. The writing of the start conversion
bit, or the event triggering the conversion (START), must occur at least one peripheral clock cycle before the ADC clock
cycle on which the conversion starts (indicated with the grey slope of the START trigger).
The input source is sampled in the first half of the first cycle.
Figure 25-11.ADC Timing for One Conversion with 1x Gain

1 2 3 4 5 6 7 8 9 10
clk ADC
START
ADC SAMPLE
IF
CONVERTING BIT msb 10 9 8 7 6 5 4 3 2 1 lsb
Figure 25-12.ADC Timing for One Conversion with Increased Sampling Time (SAMPVAL = 6)
1 2 3 4 5 6 7 8 9 10
clk ADC
START
ADC SAMPLE
IF
25.9.2 Single Conversion with Various Gain Settings

Figure 25-13 on page 361 to Figure 25-15 on page 361 show the ADC timing for one single conversion with various gain
settings. As seen in the “Overview” on page 349, the gain stage is built into the ADC. Gain is achieved by running the
signal through a pipeline stage without converting. Compared to a conversion without gain, each gain multiplication of 2
adds one half ADC clock cycle.
XMEGA E MANUAL 360

Figure 25-13.ADC Timing for One Single Conversion with 2x Gain
1 2 3 4 5 6 7 8 9 10
clkADC
START
ADC SAMPLE
AMPLIFY
IF

1 2 3 4 5 6 7 8 9 10
clk ADC
START
ADC SAMPLE
AMPLIFY
IF
1 2 3 4 5 6 7 8 9 10
clk ADC
START
ADC SAMPLE
AMPLIFY
IF
XMEGA E MANUAL 361

25.10 ADC Input Model
The voltage input must charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy.
Seen externally, the ADC input consists of an input resistance (Rin = Rchannel + Rswitch) and the S/H capacitor (Csample).
Figure 25-16 and Figure 25-17 show the ADC input channel.
Figure 25-16.ADC Input for Single-ended Measurements

CC
sample
channel switch
Figure 25-17.ADC Input for Differential Measurements and Differential Measurement with Gain
CC CC
sample
channel switch
sample
channel switch
In order to achieve n bits of accuracy, the source output resistance, Rsource, must be less than the ADC input resistance
on a pin:
Ts
R source  --------------------------------------------------------
-–R
channel – R switch
C sample  In  2 n + 1 
where the ADC sample time, TS is one-half the ADC clock cycle given by:
Ts
T s  ----------------------
2  f ADC
For details on Rchannel, Rswitch, and Csample, refer to the ADC electrical characteristic in the device datasheet.
25.11 EDMA Transfer

The EDMA controller can be used to transfer ADC conversion results to memory or other peripherals. A new conversion
result for the ADC channel can trigger an EDMA transaction for the ADC channel. Refer to “EDMA – Enhanced Direct
Memory Access” on page 50 for more details on EDMA transfers.

The ADC can generate interrupt requests and events. The ADC channel has individual interrupt settings and interrupt
vectors. Interrupt requests and events can be generated when an ADC conversion is complete or when an ADC
measurement is above or below the ADC compare register value.
XMEGA E MANUAL 362

25.13 Synchronous Sampling
Starting an ADC conversion can cause an unknown delay between the start trigger or event and the actual conversion
since the peripheral clock is faster than the ADC clock. To start an ADC conversion immediately on an incoming event, it
is possible to flush the ADC of all measurements, reset the ADC clock, and start the conversion at the next peripheral
clock cycle (which then will also be the next ADC clock cycle). If this is done, the ongoing conversions in the ADC will be
lost.
The ADC can be flushed from software, or an incoming event can do this automatically. When this function is used, the
time between each conversion start trigger must be longer than the ADC propagation delay to ensure that one
conversion is finished before the ADC is flushed and the next conversion is started.
It is also important to clear pending events or start ADC conversion commands before doing a flush. If not, pending
conversions will start immediately after the flush.
In devices with two ADC peripherals, it is possible to start two ADC samples synchronously in the two ADCs by using the
same event channel to trigger both ADC.
XMEGA E MANUAL 363

25.14 Register Description – ADC
Bit 7 6 5 4 3 2 1 0
+0x00 – – – – – START FLUSH ENABLE

 Bits 2 – START: Start Single Conversion
Setting this bit will start an ADC conversion. This bit is cleared by hardware when the conversion has started. Writ-
ing this bit is equivalent to writing the START bit inside the ADC channel register.
 Bit 1 – FLUSH: Flush
Writing this bit to one will flush the ADC. When this is done, the ADC clock will be restarted on the next peripheral
clock edge and the conversion in progress is aborted and lost.
After the flush and the ADC clock restart, the ADC will resume where it left off. I.e. if a sweep was in progress or
any conversions was pending, these will enter the ADC complete.
Setting this bit enables the ADC.
Bit 7 6 5 4 3 2 1 0
+0x01 – CURRLIMIT[1:0] CONVMODE FREERUN RESOLUTION[1:0] –
Read/Write R R/W R/W R/W R/W R/W R/W R
 Bits 6:5 – CURRLIMIT[1:0]: Current Limitation
These bits can be used to limit the current consumption of the ADC by reducing the maximum ADC sample rate.
The available settings are shown in Table 25-5. The indicated current limitations are nominal values. Refer to the
device datasheet for actual current limitation for each setting.
Table 25-5. ADC Current Limitations
CURRLIMIT[1:0] Group configuration Description
00 NO No limit
01 LOW Low current limit, max. sampling rate 225kSPS
10 MED Medium current limit, max. sampling rate 150kSPS
11 HIGH High current limit, max. sampling rate 75kSPS
 Bit 4 – CONVMODE: Conversion Mode

This bit controls whether the ADC will work in signed or unsigned mode. By default, this bit is cleared and the ADC
is configured for unsigned mode. When this bit is set, the ADC is configured for signed mode.
XMEGA E MANUAL 364

 Bit 3 – FREERUN: Free Run Mode
This bit controls the free running mode for the ADC. Once a conversion is finished, the next input will be sampled
and converted.
 Bits 2:1 – RESOLUTION[1:0]: Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12- or 8-bit result resolution. They also define
whether the 12-bit result is left or right adjusted within the 16-bit result registers. See Table 25-6 for possible
settings.
Table 25-6. ADC Conversion Result Resolution
RESOLUTION[1:0] Group configuration Description
00 12BIT 12-bit result, right adjusted
More than 12-bit right adjusted result, then oversampling or

01 MT12BIT
averaging is used (SAPNUM>0)
10 8BIT 8-bit result, right adjusted
11 LEFT12BIT 12-bit result, left adjusted
25.14.3 REFCTRL – Reference Control Register
Bit 7 6 5 4 3 2 1 0
+0x02 – REFSEL[2:0] – – BANDGAP TEMPREF
Read/Write R R/W R/W R/W R R R/W R/W
 Bits 6:4 – REFSEL[2:0]: Reference Selection
These bits set the reference settings and conversion range for the ADC according to Table 25-7.
Table 25-7. ADC Reference Control
REFSEL[2:0] Group configuration Description
000 INT1V Internal 1.0 V
001 INTVCC Internal Vcc/1.6
010 (1) AREFA External reference from AREF on port A
011 (2) AREFD External reference from AREF on port D
100 INTVCC2 Internal VCC/2
101-111 – Reserved
Notes: 1. Only available if AREF exists on port A.

2. Only available if AREF exists on port D.
XMEGA E MANUAL 365

 Bit 1 – BANDGAP: Bandgap Enable
Setting this bit enables the bandgap for ADC measurement. Note that if any other functions are already using the
bandgap, this bit does not need to be set when the internal 1.00V reference is used for another ADC or if the
brownout detector is enabled.
 Bit 0 – TEMPREF: Temperature Reference Enable
Setting this bit enables the temperature sensor for ADC measurement.
25.14.4 EVCTRL – Event Control Register
Bit 7 6 5 4 3 2 1 0
+0x03 – – EVSEL[2:0] EVACT[2:0]

 Bits 5:3 – EVSEL[2:0]: Event Line Input Select
These bits define which event channel is used as trigger source for a conversion. See Table 25-8.
Table 25-8. ADC Event Line Select
EVSEL[2:0] Group configuration Selected event lines
000 0 Event channel 0 as selected input
 Bits 2:0 – EVACT[2:0]: Event Action

These bits select and limit how many of the selected event input channels are used, and also further limit the ADC
channels triggers. They also define more special event triggers as defined in Table 25-9 on page 367.
XMEGA E MANUAL 366

Table 25-9. ADC Event Mode Select
EVACT[2:0] Group configuration Event input operation mode
000 NONE No event inputs
Event channel with the lowest number defined by EVSEL

001 CH0
triggers conversion on ADC channel
010 – Reserved
011 – Reserved
100 – Reserved
101 – Reserved
110 SYNCSWEEP The ADC is flushed and restarted for accurate timing
111 – Reserved
25.14.5 PRESCALER – Clock Prescaler Register
Bit 7 6 5 4 3 2 1 0
+0x04 – – – – – PRESCALER[2:0]

 Bits 2:0 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock according to Table 25-10.
Table 25-10. ADC Prescaler Settings
PRESCALER[2:0] Group configuration Peripheral clock division factor
000 DIV4 4
001 DIV8 8
010 DIV16 16
011 DIV32 32
100 DIV64 64
101 DIV128 128
110 DIV256 256
111 DIV512 512
XMEGA E MANUAL 367

Bit 7 6 5 4 3 2 1 0
+0x06 – – – – – – – CH0IF

These bits are reserved and will always read as zero. For compatibility with future devices, always write these bits
to zero when this register is written.
 Bit 0 – CH0IF: Interrupt Flag
This flag is set when the ADC conversion is complete. If the ADC is configured for compare mode, the correspond-
ing flag will be set if the compare condition is met. CH0IF is automatically cleared when the ADC interrupt vector is
executed. The flag can also be cleared by writing a one to its bit location.
25.14.7 TEMP – Temporary Register
Bit 7 6 5 4 3 2 1 0
+0x07 TEMP[7:0]
 Bits 7:0 – TEMP: Temporary Bits

This register is used when reading 16-bit registers in the ADC controller. The high byte of the 16-bit register is
stored here when the low byte is read by the CPU. This register can also be read and written from the user
software.
For more details on 16-bit register access refer to“Accessing 16-bit Registers” on page 13.
25.14.8 SAMPCTRL – Sampling Time Control Register
Bit 7 6 5 4 3 2 1 0
+0x08 – – SAMPVAL[5:0]

 Bits 5:0 – SAMPVAL: Sampling Time Value
These bits control the ADC sampling time in number of half ADC prescaled clock cycles (depends of PRESCALER
settings), thus controlling the ADC input impedance. Sampling time is set according to the formula:
SamplingTime =  SAMPVAL + 1    clk ADC  2 
XMEGA E MANUAL 368

25.14.9 CALL – Calibration Register Low
The CALL register pair represent the 12-bit value, CAL. The ADC is calibrated during production programming, and the
calibration value must be read from the signature row and written to the CAL register from software, prior to gain and
offset correction.
For more details on 16-bit register access refer to “Accessing 16-bit Registers” on page 13.
Bit 7 6 5 4 3 2 1 0
+0x0C CAL[7:0]
 Bits 7:0 – CAL[7:0]: ADC Calibration Value Low Byte

These are the eight lsbs of the 12-bit CAL value.
25.14.10 CH0RESL – Channel 0 Result Register Low

The CH0RESHand CH0RESL register pair represent the 12-bit value, CH0RES.
Bit 7 6 5 4 3 2 1 0
8-bit/12-bit, right CH0RES[7:0]
+0x10
12-bit, left CH0RES[3:0] – – – –
25.14.10.1 8-bit Mode/12-bit Mode, Right Adjusted

 Bits 7:0 – CH0RES[7:0]: Channel Result Low Byte
These are the eight lsbs of the ADC result.
25.14.10.2 12-bit Mode, Left Adjusted

 Bits 7:4 – CH0RES[3:0]: ADC Channel Result Low Byte
These are the four lsbs of the 12-bit ADC result.
25.14.11 CH0RESH – Channel 0 Result Register High
Bit 7 6 5 4 3 2 1 0
12-bit, left CH0RES[11:4]
+0x11
12-bit, right – – – – CH0RES[11:8]
8-bit – – – – – – – –

 Bits 7:0 – CH0RES[11:4]: ADC Channel Result High Byte
These are the eight msbs of the 12-bit ADC result.
XMEGA E MANUAL 369

25.14.11.2 12-bit Mode, Right Adjusted
These bits will in practice be the extension of the sign bit CH0RES11 when ADC works in differential mode and set
to zero when ADC works in signed mode.
 Bits 3:0 – CH0RES[11:8]: ADC Channel Result High Byte
These are the four msbs of the 12-bit ADC result.
25.14.11.3 8-bit Mode

These bits will in practice be the extension of the sign bit CH0RES7 when ADC works in signed mode and set to
zero when ADC works in single-ended mode.
25.14.12 CMPL – Compare Register Low

The CMPL and CMPH register pair represent the 16-bit value, CMP.
Bit 7 6 5 4 3 2 1 0
+0x18 CMP[7:0]
 Bits 7:0 – CMP[7:0]: Compare Value Low Byte

These are the eight lsbs of the 16-bit ADC compare value. In signed mode, the number representation is 2's
complement.
25.14.13 CMPH – Compare Register High
Bit 7 6 5 4 3 2 1 0
+0x19 CMP[15:8]
 Bits 7:0 – CMP[15:0]: Compare Value High Byte

These are the eight msbs of the 16-bit ADC compare value. In signed mode, the number representation is 2's com-
plement and the msbs is the sign bit.
XMEGA E MANUAL 370

25.15 Register Description - ADC Channel
Bit 7 6 5 4 3 2 1 0
+0x00 START – – GAIN[2:0] INPUTMODE[1:0]
Read/Write R/W R R R/W R/W R/W R/W R/W
 Bit 7 – START: START Conversion

Writing this to one will start a conversion on the channel. The bit is cleared by hardware when the conversion has
started. Writing this bit to one when it already is set will have no effect. Writing this bit is equivalent to writing the
START bit in “ CTRLA – Control Register A on page 364”.
 Bits 4:2 – GAIN [2:0]: Gain Factor
These bits define the gain factor in order to amplify input signals before ADC conversion. See Table 25-11 for dif-
ferent gain factor settings. Gain is only valid in differential mode settings, as shown in Table 25-16 on page 373
and Table 25-17 on page 374. In single-ended mode of operation, the gain factor must be set to zero.
Table 25-11. ADC Gain Factor
GAIN[2:0] Group configuration Gain factor
000 1X 1x
001 2X 2x
010 4X 4x
011 8X 8x
100 16X 16 x
101 32X 32 x
110 64X 64 x
111 DIV2 ½x
 Bits 1:0 – INPUTMODE[1:0]: Channel Input Mode

These bits define the channel mode. This setting is independent of the ADC CONVMODE (signed/unsigned mode)
setting, but differential input mode can only be done in ADC signed mode. In single ended input mode, the nega-
tive input to the ADC will be connected to a fixed value, both for ADC signed and unsigned mode.
Table 25-12. Channel Input Modes, CONVMODE = 0 (Unsigned Mode)
INPUTMODE[1:0] Group configuration Description
00 INTERNAL Internal positive input signal
01 SINGLEENDED Single-ended positive input signal
10 – Reserved
11 – Reserved
XMEGA E MANUAL 371

Table 25-13. Channel Input Modes, CONVMODE = 1 (Signed Mode)
INPUTMODE[1:0] Group configuration Description
00 INTERNAL Internal positive input signal
01 SINGLEENDED Single-ended positive input signal
10 DIFFWGAINL Differential input signal with gain, 4 LSB pins available for MUXNEG selection
11 DIFFWGAINH Differential input signal with gain, 4 MSB pins available for MUXNEG selection
25.15.2 MUXCTRL – MUX Control Register
Bit 7 6 5 4 3 2 1 0
+0x01 – MUXPOS[3:0] MUXNEG[2:0]
 Bits 6:3 – MUXPOS[3:0]: MUX Selection on Positive ADC Input
These bits define the MUX selection for the positive ADC input. Table 25-14 and Table 25-15 on page 373 shows
the possible input selection for the different input modes.
Table 25-14. ADC MUXPOS Configuration when INPUTMODE[1:0] = 00 (Internal) is used
MUXPOS[3:0] Group configuration Analog input
0000 TEMP Temperature Reference
0001 BANDGAP Bandgap
0010 SCALEDVCC 1/10 scaled VCC
0011 DAC DAC Output
XMEGA E MANUAL 372

Table 25-15. ADC MUXPOS Configuration, INPUTMODE[1:0] = 01, 10, 11 (Single-ended or Differential with Programma-
ble Gain)
MUXPOS[3:0] Group configuration Analog input (1)
0000 PIN0 ADC0 pin
0001 PIN1 ADC1 pin
0010 PIN2 ADC2 pin
0011 PIN3 ADC3 pin
0100 PIN4 ADC4 pin
0101 PIN5 ADC5 pin
0110 PIN6 ADC6 pin
0111 PIN7 ADC7 pin
1000 PIN8 ADC8 pin
1001 PIN9 ADC9 pin
1010 PIN10 ADC10 pin
Note: 1. Depending on the device pin count and feature configuration, the actual number of analog input pins may be less than 16. Refer to the device data-
sheet and pin-out description for details.
 Bits 2:0 – MUXNEG[2:0]: MUX Selection on Negative ADC Input

These bits define the MUX selection for the negative ADC input when differential measurements are done. For
internal or single-ended measurements, these bits are not in use. Table 25-16 and Table 25-17 on page 374
shows the possible input sections.
Table 25-16. ADC MUXNEG Configuration, INPUTMODE[1:0] = 10 (Differential with Programmable Gain)
MUXNEG[2:0] Group configuration Analog input
000 PIN0 ADC0
001 PIN1 ADC1
010 PIN2 ADC2
011 PIN3 ADC3
100 – Reserved
101 GND PAD ground
110 – Reserved
111 INTGND Internal ground
XMEGA E MANUAL 373

Table 25-17. ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, (Differential with Programmable Gain)
MUXNEG[2:0] Group configuration Analog input
000 PIN4 ADC4
001 PIN5 ADC5
010 PIN6 ADC6
011 PIN7 ADC7
100 – Reserved
101 – Reserved
110 – Reserved
111 GND PAD ground
Bit 7 6 5 4 3 2 1 0
+0x02 – – – – INTMODE[1:0] INTLVL[1:0]

 Bits 3:2 – INTMODE[1:0]: Interrupt Mode
INTMODE bits define the interrupt mode according to Table 25-18.
Table 25-18. ADC Interrupt Mode
INTMODE[1:0] Group configuration Interrupt mode
00 COMPLETE Conversion Complete
01 BELOW Compare Level Below Threshold
10 – Reserved
11 ABOVE Compare Level Above Threshold
 Bits 1:0 – INTLVL[1:0]: Interrupt Priority Level and Enable

These bits enable the ADC channel interrupt and select the interrupt level as described in “PMIC – Interrupts and
Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will be triggered when IF is set in
the INTFLAGS register.
XMEGA E MANUAL 374

Bit 7 6 5 4 3 2 1 0
+0x03 – – – – – – – IF

 Bit 0 – IF: Interrupt Flag
The interrupt flag is set when the ADC conversion is complete. If the channel is configured for compare mode, the
flag will be set if the compare condition is met. IF is automatically cleared when the ADC channel interrupt vector is
executed. The bit can also be cleared by writing a one to the bit location.
25.15.5 RESL – Result Register Low

The RESH and RESL register pair represent the 12-bit value, RES.
Bit 7 6 5 4 3 2 1 0
8-bit/12-bit, right RES[7:0]
+0x04
12-bit, left RES[3:0] – – – –
25.15.5.1 8-bit Mode/12-bit Mode, Right Adjusted

 Bits 7:0 – RES[7:0]: Check Police
These are the eight lsbs of the ADC result.

 Bits 7:4 – RES[3:0]: Check Police
These are the four lsbs of the 12-bit ADC result.
XMEGA E MANUAL 375

25.15.6 RESH – Result Register High
Bit 7 6 5 4 3 2 1 0
12-bit, left RES[11:4]
+0x05
12-bit, right – – – – RES[11:8]
8-bit – – – – – – – –

 Bits 7:0 – RES[11:4]: Channel Result High Byte
These are the eight msbs of the 12-bit ADC result.
25.15.6.2 12-bit Mode, Right Adjusted

These bits will in practice be the extension of the sign bit RES11 when ADC works in differential mode and set to
zero when ADC works in signed mode.
 Bits 3:0 – RES[11:8]: Channel Result High Byte
These are the four msbs of the 12-bit ADC result.
25.15.6.3 8-bit Mode

These bits will in practice be the extension of the sign bit RES7 when ADC works in signed mode and set to zero
when ADC works in single-ended mode.
25.15.7 SCAN – Scan Register
Bit 7 6 5 4 3 2 1 0
+0x06 INPUTOFFSET[3:0] INPUTSCAN[3:0]
 Bits 7:4 – INPUTOFFSET[3:0]: Positive MUX Setting Offset

The channel scan is enabled when INPUTSCAN is not equal to 0 and this register contains the offset for the next
input source to be converted on ADC channel. The actual MUX setting for positive input equals MUXPOS +
INPUTOFFSET. The value is incremented after each conversion until it reaches the maximum value given by
INPUTSCAN. When INPUTOFFSET is equal to INPUTSCAN, INPUTOFFSET will be cleared on the next
conversion.
 Bits 3:0 – INPUTSCAN[3:0]: Number of Input Channels Included in Scan
This register gives the number of input sources included in the channel scan. The number of input sources
included is INPUTSCAN + 1. The input channels included are the range from MUXPOS + INPUTOFFSET to
MUXPOS + INPUTOFFSET + INPUTSCAN.
25.15.8 CORRCTRL - Correction Control Register
Bit 7 6 5 4 3 2 1 0
+0x07 – – – – – – – CORREN

XMEGA E MANUAL 376

 Bit 0 – CORREN: Correction Enable
Writing one to this bit enables the offset and gain correction. When enabled, 13 clkPER latency for the final output is
added. In free running mode, the latency is added on the first conversion only.
When disabled, the ADC output result is not corrected for offset and gain.
25.15.9 OFFSETCORR0 – Offset Correction Register 0

The OFFSETCORR1 and OFFSETCORR0 register pair stores the 12-bit value, OFFSETCORR. This pair has no 16-bit
register access type.
There register values are ignored if the CORREN bit is cleared.
Bit 7 6 5 4 3 2 1 0
+0x08 OFFSETCORR[7:0]
 Bits 7:0 – OFFSETCORR[7:0] – Offset Correction Byte 0

These bits are the eight lsbs of the 12-bit offset correction value.
25.15.10 OFFSETCORR1 – Offset Correction Register 1
Bit 7 6 5 4 3 2 1 0
+0x09 – – – – OFFSETCORR[11:8]

 Bits 3:0 – OFFSETCORR[11:8] – Offset Correction Byte 1
These bits are the four msbs of the 12-bit offset correction value.
25.15.11 GAINCORR0 – Gain Correction Register 0

The GAINCORR1 and GAINCORR0 register pair stores the 12-bit value, GAINCORR. This pair has no 16-bit register
access type.
There register values are ignored if the CORREN bit is cleared.
Bit 7 6 5 4 3 2 1 0
+0x0A GAINCORR[7:0]
 Bits 7:0 – GAINCORR[7:0] – Gain Correction Byte 0

These bits are the eight lsbs of the 12-bit gain correction value.
XMEGA E MANUAL 377

25.15.12 GAINCORR1 – Gain Correction Register 1
Bit 7 6 5 4 3 2 1 0
+0x0B – – – – GAINCORR[11:8]

 Bits 3:0 – GAINCORR[11:8] – Gain Correction Byte 1
These bits are the four msbs of the 12-bit gain correction value.
25.15.13 AVGCTRL – Average Control Register
Bit 7 6 5 4 3 2 1 0
+0x0C – RIGHTSHIFT[2:0] SAMPNUM3:0]
This bit is reserved and will always read as zero. For compatibility with future devices, always write this bit to zero
 Bit 6:4 – RIGHTSHIFT[2:0] – Right Shift
This value is effective only if SAMPNUM > 0. Output value will be in RES 16-bit register. Accumulated value will be
right shifted by the value specified by this bits. Right shift is from 0-shift till 7-shift.
 Bit 3:0 – SAMPNUM[3:0] - Averaged Number of Samples

If SAMPNUM > 0, then MT 12BIT bits register must be selected. The below table specify the number of samples
which will be accumulated and result will be available in RES 16-bit register.
Table 25-19. Number of Samples
SAMPNUM[3:0] Group configuration Number of samples

0000 1X 1
0001 2X 2
0010 4X 4
0011 8X 8
0100 16X 16
0101 32X 32
0110 64X 64
0111 128X 128
1000 256X 256
1001 512X 512
1010 1024X 1024
XMEGA E MANUAL 378

25.16 Register Summary – ADC
+0x00 CTRLA – – – – – START FLUSH ENABLE 364
+0x01 CTRLB – CURRLIMIT[1:0] CONVMODE FREERUN RESOLUTION[1:0] – 364
+0x02 REFCTRL – REFSEL[2:0] – – BANDGAP TEMPREF 365
+0x03 EVCTRL – – EVSEL[2:0] EVACT[2:0] 366
+0x04 PRESCALER – – – – – PRESCALER[2:0] 367
+0x05 Reserved – – – – – – – –
+0x06 INTFLAGS – – – – – – – CH0IF 368
+0x07 TEMP TEMP[7:0] 368
+0x08 SAMPCTRL – – SAMPVAL[5:0] 368
+0x09 Reserved – – – – – – – –
+0x0A Reserved – – – – – – – –
+0x0B Reserved – – – – – – – –
+0x0C CALL CAL[7:0] 369

+0x0D Reserved – – – – – – – –
+0x0E Reserved – – – – – – – –
+0x0F Reserved – – – – – – – –
+0x10 CH0RESL CH0RES[7:0] 369

+0x11 CH0RESH CH0RES[15:8] 369
+0x12 Reserved – – – – – – – –
+0x13 Reserved – – – – – – – –
+0x14 Reserved – – – – – – – –
+0x15 Reserved – – – – – – – –
+0x16 Reserved – – – – – – – –
+0x17 Reserved – – – – – – – –
+0x18 CMPL CMP[7:0] 370
+0x19 CMPH CMP[15:8] 370
+0x1A Reserved – – – – – – – –
+0x1B Reserved – – – – – – – –
+0x1C Reserved – – – – – – – –
+0x1D Reserved – – – – – – – –
+0x1E Reserved – – – – – – – –
+0x1F Reserved – – – – – – – –
+0x20 CH0 Offset Offset address for ADC Channel
+0x28 Reserved – – – – – – – –
+0x30 Reserved – – – – – – – –
+0x38 Reserved – – – – – – – –
XMEGA E MANUAL 379

25.17 Register Summary – ADC Channel
+0x00 CTRL START – – GAIN[2:0] INPUTMODE[1:0] 371
+0x01 MUXCTRL – MUXPOS[3:0] MUXNEG[2:0] 372
+0x02 INTCTRL – – – – INTMODE[1:0] INTLVL[1:0] 374
+0x03 INTFLAGS – – – – – – – IF 375
+0x04 RESL RES[7:0] 375
+0x05 RESH RES[15:8] 376
+0x06 SCAN INPUTOFFSET[3:0] INPUTSCAN[3:0] 376
+0x07 CORRCTRL – – – – – – – CORREN 376
+0x08 OFFSETCORR0 OFFSETCORR[7:0] 377
+0x09 OFFSETCORR1 – – – – OFFSETCORR[11:8] 377
+0x0A GAINCORR0 GAINCORR[7:0] 377
+0x0B GAINCORR1 – – – – GAINCORR[11:8] 378
+0x0C AVGCTRL – RIGHTSHIFT[2:0] SAMPNUM[3:0] 378
+0x0D Reserved – – – – – – – –
+0x0E Reserved – – – – – – – –
+0x0F Reserved – – – – – – – –
Table 25-20. Analog-to-Digital Convertor Interrupt Vectors and their Word Offset Address
0x00 CH0_vect Analog-to-digital convertor channel 0 interrupt vector
XMEGA E MANUAL 380

26. DAC – Digital to Analog Converter
26.1 Features
 Two independent, continuous-drive output channels
 Up to one million samples per second conversion rate per DAC channel
 Built-in calibration that removes:
 Offset error
 Gain error
 Multiple conversion trigger sources
 On new available data
 Events from the event system
 High drive capabilities and support for:
 Resistive loads
 Capacitive loads
 Combined resistive and capacitive loads
 Internal and external reference options
 DAC output available as input to analog comparator and ADC
 Low-power mode, with reduced drive strength
 Optional EDMA transfer of data
26.2 Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with12-bit
resolution, and is capable of converting up to one million samples per second (MSPS) on each channel. The built-in
calibration system can remove offset and gain error when loaded with calibration values from software.
Figure 26-1 illustrates the basic functionality of the DAC. Not all functions are shown.
Figure 26-1. DAC Overview

EDMA req
(Data Empty)
D
12 A Output
CH0DATA T Driver
A
Int. To
Trigger Select Enable driver AC/ADC
AVCC Reference
Internal 1.00V voltage
AREFA CTRLB CTRLA
AREFD Internal Output enable
Trigger Select Enable
D
12 A Output
CH1DATA T Driver
A
EDMA req
(Data Empty)
XMEGA E MANUAL 381

A DAC conversion is automatically started when new data to be converted are available. Events from the event system
can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and
other peripherals, such as a timer/counter. The EDMA controller can be used to transfer data to the DAC.
The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, as well as loads which
combine both. A low-power mode is available, which will reduce the drive strength of the output.
Internal and external voltage references can be used. The DAC output is also internally available for use as input to the
analog comparator or ADC.
26.3 Voltage Reference Selection

The following can be used as the reference voltage (VREF) for the DAC:
 AVCC voltage
 Accurate internal 1.00V voltage
 External voltage applied to AREF pin on PORTA
 External voltage applied to AREF pin on PORTD
26.4 Starting a Conversion

By default, conversions are started automatically when new data are written to the channel data register. It is also
possible to enable events from the event system to trigger conversion starts. When enabled, a new conversion is started
when the DAC channel receives an event and the channel data register has been updated. This enables conversion
starts to be synchronized with external events and/or timed to ensure regular and fixed conversion intervals.
26.5 Output and Output Channels

The two DAC channels have fully independent outputs and individual data and conversion control registers. This enables
the DAC to create two different analog signals. The channel 0 output can also be made internally available as input for
the Analog Comparator and the ADC.
The output voltage from a DAC channel (VDAC) is given as:
CHnDATA
V DACn = ----------------------------  VREF
0xFFF
26.6 DAC Output Model

Each DAC output channel has a driver buffer with feedback to ensure that the voltage on the DAC output pin is equal to
the DACs internal voltage. Section 26-2 shows the DAC output model. For details on Rchannel, refer to the DAC
characteristics in the device data sheet.
Figure 26-2. DAC Output Model
R feedback
DAC voltage DAC out

Buffer DAC output
R channel
26.7 DAC Clock

The DAC is clocked directly from the peripheral clock (clkPER), and this puts a limitation on how fast new data can be
clocked into the DAC data registers.
XMEGA E MANUAL 382

26.8 Low Power Mode
To reduce the power consumption in DAC conversions, the DAC may be set in a low power mode. Conversion time will
be longer if new conversions are started in this mode. This increases the DAC conversion time per DAC channel by a
factor of two.
26.9 Calibration
For improved accuracy, it is possible to calibrate for gain and offset errors in the DAC.
To get the best calibration result, it is recommended to use the same DAC configuration during calibration as will be used
in the final application. The theoretical transfer function for the DAC was shown in the equation in “Output and Output
Channels” on page 382. Including gain and offset errors, the DAC output value can be expressed as:
Equation 26-1. Calculation of DAC Output Value
V DAC = VREF   ------------------  ERROR GAIN + V OFFSET

DATA
 0xFFF 
To calibrate for offset error, output the DAC channel's middle code (0x800) and adjust the offset calibration value until the
measured output value is as close as possible to the middle value (VREF / 2). The formula for the offset calibration is
given by the Equation 26-2 on page 383, where OCAL is OFFSETCAL and GCAL is GAINCAL.
Equation 26-2. Offset Calibration

OCAL  6  OCAL  5  OCAL  4  OCAL  3  OCAL  2  OCAL  1  OCAL  0 
V OCAL = VREF   2.OCAL  7  – 1    ------------------------ + ------------------------ + ------------------------ + ------------------------ + ------------------------ + ------------------------ + ------------------------
 64 128 256 512 1024 2048 4096 
To calibrate for gain error, output the DAC channel's maximum code (0xFFF) and adjust the gain calibration value until
the measured output value is as close as possible to the top value (VREF x 4095 / 4096). The gain calibration controls
the slope of the DAC characteristic by rotating the transfer function around the middle code. The formula for gain
calibration is given by the Equation 26-3 on page 383.
Equation 26-3. Gain Calibration

GCAL  6  GCAL  5  GCAL  4  GCAL  3  GCAL  2  GCAL  1  GCAL  0 
V GCAL =  V DAC –  ---------------    1 – 2.G CAL  7     ------------------------ + ------------------------ + ------------------------ + ------------------------ + ------------------------ + ------------------------ + ------------------------
VREF
2 16 32 64 128 256 512 1024
Including calibration in the equation, the DAC output can be expressed by Equation 26-4 on page 383.
Equation 26-4. DAC Output Calculation
VDAC_out = VDAC + VOCAL + VGCAL
XMEGA E MANUAL 383

Bit 7 6 5 4 3 2 1 0
+0x00 – – – IDOEN CH1EN CH0EN LPMODE ENABLE

These bite are unused and reserved for future use. For compatibility with future devices, always write these bits to
 Bit 4 – IDOEN: Internal Output Enable
Setting this bit will enable the internal DAC channel 0 output to be used by the Analog Comparator and ADC. This
will then also disable the output pin for DAC Channel 0.
 Bit 3 – CH1EN: Channel 1 Output Enable
Setting this bit will make channel 1 available on the output pin.
 Bit 2 – CH0EN: Channel 0 Output Enable
Setting this bit will make channel 0 available on the output pin unless IDOEN is set to 1.
 Bit 1 – LPMODE: Low Power Mode
Setting this bit enables the DAC low-power mode. The DAC is turned off between each conversion to save current.
Conversion time will be doubled when new conversions are started in this mode.
This bit enables the entire DAC.
Bit 7 6 5 4 3 2 1 0
+0x01 – CHSEL[1:0] – – – CH1TRIG CH0TRIG
Read/Write R R/W R/W R R R R/W R/W
 Bit 6:5 – CHSEL[1:0]: Channel Selection
These bits control which DAC channels are enabled and operating. Table 26-1 shows the available selections.
Table 26-1. DAC Channel Selection
CHSEL[1:0] Group configuration Description
00 SINGLE Single-channel operation on channel 0
01 SINGLE1 Single-channel operation on channel 1
10 DUAL Dual-channel operation
11 – Reserved

XMEGA E MANUAL 384

 Bit 1 – CH1TRIG: Auto Trigged Mode Channel 1
If this bit is set, an event on the configured event channel, set in EVCTRL, will trigger a conversion on DAC chan-
nel 1 if its data register, CH1DATA, has been updated.
 Bit 0 – CH0TRIG: Auto Trigged Mode Channel 0
If this bit is set, an event on the configured event channel, set in EVCTRL, will trigger a conversion on DAC chan-
nel 0 if its data register, CH0DATA, has been updated.
Bit 7 6 5 4 3 2 1 0
+0x02 – – – REFSEL[1:0] – – LEFTADJ
Read/Write R R R R/W R/W R R R/W

 Bit 4:3 – REFSEL[1:0]: Reference Selection
These bits select the reference voltage for the DAC according to Table 26-2 on page 385.
Table 26-2. DAC Reference Selection
CHSEL[1:0] Group configuration Description
00 INT1V Internal 1.00V
01 AVCC AVCC
10 AREFA AREF on PORTA
11 AREFD AREF on PORTD

 Bit 0 - LEFTADJ: Left-Adjust Value
If this bit is set, CH0DATA and CH1DATA are left-adjusted.
26.10.4 EVCTRL – Event Control Register
Bit 7 6 5 4 3 2 1 0
+0x03 – – – – EVSEL[3:0]

 Bit 3 – EVSEL[3]: Event Selection Bit 3
Setting this bit to 1 enables event channel EVSEL[2:0]+1 as the trigger source for DAC Channel 1. When this bit is
0, the same event channel is used as the trigger source for both DAC channels.
 Bit 2:0 – EVSEL[2:0]: Event Channel Input Selection
These bits select which Event System channel is used for triggering a DAC conversion. Table 26-3 on page 386
shows the available selections.
XMEGA E MANUAL 385

Table 26-3. DAC Reference Selection
EVSEL[2:0] Group configuration Description
000 0 Event channel 0 as input to DAC
Bit 7 6 5 4 3 2 1 0
+0x05 – – – – – – CH1DRE CH0DRE

 Bit 1 – CH1DRE: Channel 1 Data Register Empty
This bit when set indicates that the data register for channel 1 is empty, meaning that a new conversion value may
be written. Writing to the data register when this bit is cleared will cause the pending conversion data to be over-
written. This bit is directly used for EDMA requests.
 Bit 0 – CH0DRE: Channel 0 Data Register Empty
This bit when set indicates that the data register for channel 0 is empty, meaning that a new conversion value may
be written. Writing to the data register when this bit is cleared will cause the pending conversion data to be over-
written. This bit is directly used for EDMA requests.
26.10.6 CH0GAINCAL – Gain Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x08 CH0GAINCAL[7:0]
 Bit 7:0 – CH0GAINCAL[7:0]: Gain Calibration Value

These bits are used to compensate for the gain error in DAC channel 0. See “Calibration” on page 383 for details.
26.10.7 CH0OFFSETCAL – Offset Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x09 CH0OFFSETCAL[7:0]
XMEGA E MANUAL 386

 Bit 7:0 – CH0OFFSETCAL[7:0]: Offset Calibration Value
These bits are used to compensate for the offset error in DAC channel 0. See “Calibration” on page 383 for details.
26.10.8 CH1GAINCAL – Gain Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x0A CH1GAINCAL[7:0]
 Bit 7:0 – CH1GAINCAL[7:0]: Gain Calibration Value

These bits are used to compensate for the gain error in DAC channel 1. See “Calibration” on page 383 for details.
26.10.9 CH1OFFSETCAL – Offset Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x0B CH1OFFSETCAL[7:0]
 Bit 7:0 – CH1OFFSETCAL[7:0]: Offset Calibration Value

These bits are used to compensate for the offset error in DAC channel 1. See “Calibration” on page 383 for details.
26.10.10CH0DATAH – Channel 0 Data Register High

These two channel data registers, CHnDATAH and CHnDATAL, are the high byte and low byte, respectively, of the 12-
bit CHnDATA value that is converted to a voltage on DAC channel n. By default, the 12 bits are distributed with 8 bits in
CHnDATAL and 4 bits in the four lsb positions of CHnDATAH (right-adjusted).To select left-adjusted data, set the
LEFTADJ bit in the CTRLC register.
When left adjusted data is selected, it is possible to do 8-bit conversions by writing only to the high byte of CHnDATA,
i.e., CHnDATAH. The TEMP register should be initialized to zero if only 8-bit conversion mode is used.
Bit 7 6 5 4 3 2 1 0
Right-adjust – – – – CHDATA[11:8]
+0x19
Left-adjust CHDATA[11:4]
Right-adjust Read/Write R R R R R/W R/W R/W R/W
Left-adjust Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Right-adjust Initial Value 0 0 0 0 0 0 0 0
Left-adjust Initial Value 0 0 0 0 0 0 0 0
26.10.10.1Right-adjusted
 Bit 3:0 – CHDATA[11:8]: Conversion Data Channel 0, Four MSB Bits
These bits are the four msbs of the 12-bit value to convert to channel 0 in right-adjusted mode.
26.10.10.2Left-adjusted
 Bits 7:0 –- CHDATA[11:4]: Conversion Data Channel 0, Eight MSB Bits
These bits are the eight msbs of the 12-bit value to convert to channel 0 in left-adjusted mode
XMEGA E MANUAL 387

26.10.11CH0DATAL – Channel 0 Data Register Low
Bit 7 6 5 4 3 2 1 0
Right-adjust CHDATA[7:0]
+0x18
Left-adjust CHDATA[3:0] – – – –
Right-adjust Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Left-adjust Read/Write R/W R/W R/W R/W R R R R
 Bit 7:0 – CHDATA[7:0]: Conversion Data Channel 0, eight LSB Bits
These bits are the eight lsbs of the 12-bit value to convert to channel 0 in right-adjusted mode.
 Bit 7:4 – CHDATA[3:0]: Conversion Data Channel 0, four LSB Bits
These bits are the four lsbs of the 12-bit value to convert to channel 0 in left-adjusted mode.
26.10.12CH1DATAH – Channel 1 Data Register High
Bit 7 6 5 4 3 2 1 0
Right-adjust – – – – CHDATA[11:8]
+0x1B
Left-adjust CHDATA[11:4]
Right-adjust Read/Write R R R R R/W R/W R/W R/W
Left-adjust Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
 Bit 3:0 – CHDATA[11:8]: Conversion Data Channel 1, four MSB Bits
These bits are the four msbs of the 12-bit value to convert to channel 1 in right-adjusted mode.
 Bit 7:0 – CHDATA[11:4]: Conversion Data Channel 1, eight MSB Bits
These bits are the eight msbs of the 12-bit value to convert to channel 1 in left-adjusted mode.
XMEGA E MANUAL 388

26.10.13CH1DATAL – Channel 1 Data Register Low
Bit 7 6 5 4 3 2 1 0
Right-adjust CHDATA[7:0]
+0x1A
Left-adjust CHDATA[3:0] – – – –
Right-adjust Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Left-adjust Read/Write R/W R/W R/W R/W R R R R
 Bit 7:0 – CHDATA[7:0]: Conversion Data Channel 1, eight LSB Bits
These bits are the eight lsbs of the 12-bit value to convert to channel 1 in right-adjusted mode.
 Bits 7:4 – CHDATA[3:0]: Conversion Data Channel 1, four LSB Bits
These bits are the four lsbs of the 12-bit value to convert to channel 1 in left-adjusted mode.
XMEGA E MANUAL 389

This is the I/O summary when the DAC is configured to give standard 12-bit results. The I/O summary for 12-bit left-
adjusted results will be similar, but with some changes in the CHnDATAL and CHnDATAH data registers.
+0x00 CTRLA – – – IDOEN CH1EN CH0EN LPMODE ENABLE 384
+0x01 CTRLB – CHSEL[1:0] – – – CH1TRIG CH0TRIG 384
+0x02 CTRLC – – – REFSEL[1:0] – – LEFTADJ 385
+0x03 EVCTRL – – – – EVSEL[3:0] 385
+0x04 Reserved – – – – – – – –
+0x05 STATUS – – – – – – CH1DRE CH0DRE 386
+0x06 Reserved – – – – – – – –
+0x07 Reserved – – – – – – – –
+0x08 CH0GAINCAL CH0GAINCAL[7:0] 386
+0x09 CH0OFFSETCAL CH0OFFSETCAL[7:0] 386
+0x0A CH1GAINCAL CH1GAINCAL[7:0] 387
+0x0B CH1OFFSETCAL CH1OFFSETCAL[7:0] 387
+0x12 Reserved – – – – – – – –
+0x13 Reserved – – – – – – – –
+0x14 Reserved – – – – – – – –
+0x15 Reserved – – – – – – – –
+0x16 Reserved – – – – – – – –
+0x17 Reserved – – – – – – – –
+0x18 CH0DATAL CHDATA[7:0] 388
+0x19 CH0DATAH – – – – CHDATA[11:8] 387
+0x1A CH1DATAL CHDATA[7:0] 389
+0x1B CH1DATAH – – – – CHDATA[11:8] 388
XMEGA E MANUAL 390

27. AC – Analog Comparator
27.1 Features
 Selectable hysteresis
 None
 Small
 Large
 Analog comparator output available on pin
 Flexible input selection
 All pins on the port
 Output from the DAC
 Bandgap reference voltage
 A 64-level programmable voltage scaler of the internal AVCC voltage
 Interrupt and event generation on:
 Rising edge
 Falling edge
 Toggle
 Window function interrupt and event generation on:
 Signal above window
 Signal inside window
 Signal below window
 Constant current source with configurable output pin selection
 Source of asynchronous event
27.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or synchronous/
asynchronous events upon several different combinations of input change.
The important property of the analog comparator’s dynamic behavior is the hysteresis. It can be adjusted in order to
achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
XMEGA E MANUAL 391

Figure 27-1. Analog Comparator Overview
Pin Input
+
AC0OUT
Pin Input
-
Hysteresis
DAC Enable
Interrupt Interrupts
Interrupt Sensititivity
Voltage Mode Control
Scaler
ACnMUXCTRL ACnCTRL WINCTRL &
Window Events
Function
Enable
Bandgap
Hysteresis
+
Pin Input
AC1OUT
Pin Input
27.3 Input Sources

Each analog comparator has one positive and one negative input. Each input may be chosen from a selection of analog
input pins and internal inputs such as a AVCC voltage scaler. The digital output from the analog comparator is one when
the difference between the positive and the negative input voltage is positive, and zero otherwise.
27.3.1 Pin Inputs

Any of analog input pins on the port can be selected as input to the analog comparator.
27.3.2 Internal Inputs

Three internal inputs are available for the analog comparator:
 Output from the DAC
 Bandgap reference voltage
 Voltage scaler, which provides a 64-level scaling of the internal AVCC voltage
27.4 Signal Compare

In order to start a signal comparison, the analog comparator must be configured with the preferred properties and inputs
before the module is enabled. The result of the comparison is continuously updated and available for application
software and the event system.

The analog comparator can be configured to generate interrupts when the output toggles, when the output changes from
zero to one (rising edge), or when the output changes from one to zero (falling edge). Synchronous/ asynchronous
events are generated at all times for the same condition as the interrupt, regardless of whether the interrupt is enabled or
not. Each analog comparator output is source of asynchronous event.
XMEGA E MANUAL 392

27.6 Window Mode
Two analog comparators on the same port can be configured to work together in window mode. In this mode, a voltage
range is defined, and the analog comparators give information about whether an input signal is within this range or not.
Figure 27-2. Analog Comparators in Window Mode
+
AC0
Upper limit of window -
Interrupts
Interrupt
Input signal sensitivity
Events
control
+
AC1
Lower limit of window
-
27.7 Input Hysteresis

Application software can select between no-, low-, and high hysteresis for the comparison. Applying a hysteresis will help
prevent constant toggling of the output that can be caused by noise when the input signals are close to each other.
XMEGA E MANUAL 393

27.8.1 ACnCTRL – Analog Comparator n Control Register
Bit 7 6 5 4 3 2 1 0
+0x00 / +0x01 INTMODE[1:0] INTLVL[1:0] – HYSMODE[2:0] ENABLE
 Bit 7:6 – INTMODE[1:0]: Interrupt Modes

These bits configure the interrupt mode for analog comparator n according to Table 27-1.
Table 27-1. Interrupt Settings
INTMODE[1:0] Group configuration Description
00 BOTHEDGES Comparator interrupt or event on output toggle
01 – Reserved
10 FALLING Comparator interrupt or event on falling output edge
11 RISING Comparator interrupt or event on rising output edge

These bits enable the analog comparator n interrupt and select the interrupt level, as described in “PMIC – Inter-
rupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will trigger according
to the INTMODE setting.
 Bit 2:1 – HYSMODE[1:0]: Hysteresis Mode Select
These bits select the hysteresis mode according to Table 27-2. For details on actual hysteresis levels, refer to the
device datasheet.
Table 27-2. Hysteresis Settings
HYSMODE[1:0] Group configuration Description
00 NO No hysteresis
01 SMALL Small hysteresis
10 LARGE Large hysteresis
11 – Reserved

Setting this bit enables analog comparator n.
XMEGA E MANUAL 394

27.8.2 ACnMUXCTRL – Analog Comparator n MUX Control Register
Bit 7 6 5 4 3 2 1 0
+0x02 / +0x03 – – MUXPOS[2:0] MUXNEG[2:0]

 Bit 5:3 – MUXPOS[2:0]: Positive Input MUX Selection
These bits select which input will be connected to the positive input of analog comparator n according to Table 27-
3.
Table 27-3. Positive Input MUX Selection
MUXPOS[2:0] Group configuration Description
000 PIN0 Pin 0
001 PIN1 Pin 1
010 PIN2 Pin 2
011 PIN3 Pin 3
100 PIN4 Pin 4
101 PIN5 Pin 5
110 PIN6 Pin 6
111 DAC DAC output
 Bit 2:0 – MUXNEG[2:0]: Negative Input MUX Selection

These bits select which input will be connected to the negative input of analog comparator n according to Table
27-4.
Table 27-4. Negative Input MUX Selection
MUXNEG[2:0] Group configuration Negative input MUX selection
000 PIN0 Pin 0
001 PIN1 Pin 1
010 PIN3 Pin 3
011 PIN5 Pin 5
100 PIN7 Pin 7
101 DAC DAC output
110 BANDGAP Internal bandgap voltage
111 SCALER AVCC voltage scaler
XMEGA E MANUAL 395

Bit 7 6 5 4 3 2 1 0
+0x04 – – – – AC1INVEN AC0INVEN AC1OUT AC0OUT

 Bit 3 – AC1INVEN: Analog Comparator 1 Output Invert Enable
Setting this bit inverts the analog comparator 1 output. When enabled, the output to pin and event generation will
be directly affected.
 Bit 2 – AC0INVEN: Analog Comparator 0 Output Invert Enable
Setting this bit inverts the analog comparator 0 output. When enabled, the output to pin and event generation will
be directly affected.
 Bit 1 – AC1OUT: Analog Comparator 1 Output
Setting this bit makes the output of AC1 available on port pin. For details on port selection, refers to “ACEVOUT –
Analog Comparator and Event Output Register” on page 155. For details on available pins for each port, refer to each
device datasheet.
 Bit 0 – AC0OUT: Analog Comparator 0 Output
Setting this bit makes the output of AC0 available on port pin. For details on port selection, refers to “ACEVOUT –
Analog Comparator and Event Output Register” on page 155. For details on available pins for each port, refer to each
device datasheet.
Bit 7 6 5 4 3 2 1 0
+0x05 – – SCALEFAC[5:0]

 Bit 5:0 – SCALEFAC[5:0]: Voltage Scaling Factor
These bits define the scaling factor for the AVcc voltage scaler. The input to the analog comparator, VSCALE, is:
V CC   SCALEFAC + 1 
V SCALE = ------------------------------------------------------------
64
27.8.5 WINCTRL – Window Function Control Register
Bit 7 6 5 4 3 2 1 0
+0x06 – – – WEN WINTMODE[1:0] WINTLVL[1:0]

 Bit 4 – WEN: Window Mode Enable
Setting this bit enables the analog comparator window mode.
XMEGA E MANUAL 396

 Bits 3:2 – WINTMODE[1:0]: Window Interrupt Mode Settings
These bits configure the interrupt mode for the analog comparator window mode according to Table 27-5.
Table 27-5. Window Mode Interrupt Settings
WINTMODE[1:0] Group configuration Description
00 ABOVE Interrupt on signal above window
01 INSIDE Interrupt on signal inside window
10 BELOW Interrupt on signal below window
11 OUTSIDE Interrupt on signal outside window
 Bits 1:0 – WINTLVL[1:0]: Window Interrupt Enable

These bits enable the analog comparator window mode interrupt and select the interrupt level, as described in
ger according to the WINTMODE setting.
Bit 7 6 5 4 3 2 1 0
+0x07 WSTATE[1:0] AC1STATE AC0STATE – WIF AC1IF AC0IF
 Bits 7:6 – WSTATE[1:0]: Window Mode Current State

These bits show the current state of the signal if window mode is enabled according to Table 27-6.
Table 27-6. Hysteresis Settings
WSTATE[1:0] Group configuration Description
00 ABOVE Signal is above window
01 INSIDE Signal is inside window
10 BELOW Signal is below window
11 OUTSIDE Signa is outside window
 Bit 5 – AC1STATE: Analog Comparator 1 Current State

This bit shows the current state of the output signal from AC1.
 Bit 4 – AC0STATE: Analog Comparator 0 Current State
This bit shows the current state of the output signal from AC0.
 Bit 2 – WIF: Analog Comparator Window Interrupt Flag
This is the interrupt flag for the window mode. WIF is set according to the WINTMODE setting in the “WINCTRL –
Window Function Control Register” on page 396.
This flag is automatically cleared when the analog comparator window interrupt vector is executed. The flag can
also be cleared by writing a one to its bit location.
XMEGA E MANUAL 397

 Bit 1 – AC1IF: Analog Comparator 1 Interrupt Flag
This is the interrupt flag for AC1. AC1IF is set according to the INTMODE setting in the corresponding “ACnCTRL
– Analog Comparator n Control Register” on page 394.
This flag is automatically cleared when the analog comparator 1 interrupt vector is executed. The flag can also be
 Bit 0 – AC0IF: Analog Comparator 0 Interrupt Flag
This is the interrupt flag for AC0. AC0IF is set according to the INTMODE setting in the corresponding “ACnCTRL
– Analog Comparator n Control Register” on page 394.
This flag is automatically cleared when the analog comparator 0 interrupt vector is executed. The flag can also be
27.8.7 CURRCTRL – Current Source Control Register
Bit 7 6 5 4 3 2 1 0
+0x08 CURRENT CURRMODE – – – – AC1CURR AC0CURR
Read/Write R/W R/W R R R R R/W R/W
 Bit 7 – CURRENT: Current Source Enable

Setting this bit to one will enable the constant current source.
 Bit 6 – CURRMODE: Current Mode
Setting this bit to one will combine the two analog comparator current sources in order to double the output current
for each analog comparator.
 Bit 1 – AC1CURR: AC1 Current Source Output Enable
Setting this bit to one will enable the constant current source output on the pin selected by MUXNEG in
AC1MUXTRL.
 Bit 0 – AC0CURR: AC0 Current Source Output Enable
Setting this bit to one will enable the constant current source output on the pin selected by MUXNEG in
AC0MUXTRL.
27.8.8 CURRCALIB – Current Source Calibration Register
Bit 7 6 5 4 3 2 1 0
+0x09 – – – – CALIB[3:0]

 Bit 3:0 – CALIB[3:0]: Current Source Calibration
The constant current source is calibrated during production. A calibration value can be read from the signature row
and written to the CURRCALIB register from software. Refer to device data sheet for default calibration values and
user calibration range.
XMEGA E MANUAL 398

+0x00 AC0CTRL INTMODE[1:0] INTLVL[1:0] – HYSMODE[1:0] ENABLE 394
+0x01 AC1CTRL INTMODE[1:0] INTLVL[1:0] – HYSMODE[1:0] ENABLE 394
+0x02 AC0MUXCTRL – – MUXPOS[2:0] MUXNEG[2:0] 395
+0x03 AC1MUXCTRL – – MUXPOS[2:0] MUXNEG[2:0] 395
+0x04 CTRLA – – – – AC1INVEN ACINVEN0 AC1OUT ACOOUT 396
+0x05 CTRLB – – SCALEFAC5:0] 396
+0x06 WINCTRL – – – WEN WINTMODE[1:0] WINTLVL[1:0] 396
+0x07 STATUS WSTATE[1:0] AC1STATE AC0STATE – WIF AC1IF AC0IF 397
+0x08 CURRCTRL CURRENT CURRMODE – – – – AC1CURR AC0CURR 398
+0x09 CURRCALIB – – – – CALIB[3:0] 398
Table 27-7. Analog Comparator Interrupt Vectors
0x00 COMP0_vect Analog comparator 0 interrupt vector
0x02 COMP1_vect Analog comparator 1 interrupt vector
0x04 WINDOW_vect Analog comparator window interrupt vector
XMEGA E MANUAL 399

28. PDI – Program and Debug Interface
28.1 Features
 Programming
 External programming through PDI interface
 Minimal protocol overhead for fast operation
 Built-in error detection and handling for reliable operation
 Boot loader support for programming through any communication interface
 Debugging
 Non-intrusive, real-time, on-chip debug system
 No software or hardware resources required from device except pin connection
 Program flow control
 Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
 Unlimited number of user program breakpoints
 Unlimited number of user data breakpoints, break on:
 Data location read, write, or both read and write
 Data location content equal or not equal to a value
 Data location content is greater or smaller than a value
 Data location content is within or outside a range
 No limitation on device clock frequency
 Program and Debug Interface (PDI)
 Two-pin interface for external programming and debugging
 Uses the Reset pin and a dedicated pin
 No I/O pins required during programming or debugging
28.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row. This is done by accessing the NVM controller and executing NVM controller commands, as described in
“Memory Programming” on page 411.
Debug is supported through an on-chip debug system that offers non-intrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer,
which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one
other dedicated pin for data input and output (PDI_DATA). Any external programmer or on-chip debugger/emulator can
be directly connected to this interface.
XMEGA E MANUAL 400

Figure 28-1. The PDI with PDI Physical Layers and Closely Related Modules (grey)
PDIBUS Internal Interfaces
Program and Debug Interface (PDI)
OCD
PDI_CLK PDI Physical PDI NVM

PDI_DATA (physical layer) Controller Memories
NVM
Controller
28.3 PDI Physical

The PDI physical layer handles the low-level serial communication. It uses a bidirectional, half-duplex, synchronous
serial receiver and transmitter (just as a USART in USRT mode). The physical layer includes start-of-frame detection,
frame error detection, parity generation, parity error detection, and collision detection.
In addition to PDI_CLK and PDI_DATA, the PDI_DATA pin has an internal pull resistor, VCC and GND must be
connected between the External Programmer/debugger and the device. Figure 28-2 shows a typical connection.
Figure 28-2. PDI Connection
VCC
PDI Connector
PDI_CLK
PDI_DATA
GND
The remainder of this section is intended for use only by third parties developing programmers or programming support
for Atmel AVR XMEGA devices.
28.3.1 Enabling
The PDI physical layer must be enabled before use. This is done by first forcing the PDI_DATA line high for a period
longer than the equivalent external reset minimum pulse width (refer to device datasheet for external reset pulse width
data). This will disable the RESET functionality of the Reset pin, if not already disabled by the fuse settings.
Next, continue to keep the PDI_DATA line high for 16 PDI_CLK cycles. The first PDI_CLK cycle must start no later than
100µs after the RESET functionality of the Reset pin is disabled. If this does not occur in time, the enabling procedure
must start over again. The enable sequence is shown in Figure 28-3 on page 402.
XMEGA E MANUAL 401

Figure 28-3. PDI Physical Layer Enable Sequence
Disable RESET function on Reset (PDI_CLK) pin Activate PDI
PDI_DATA
PDI_CLK
The Reset pin is sampled when the PDI interface is enabled. The reset register is then set according to the state of the
Reset pin, preventing the device from running code after the reset functionality of this pin is disabled.
28.3.2 Disabling
If the clock frequency on PDI_CLK is lower than approximately 10kHz, this is regarded as inactivity on the clock line. This
will automatically disable the PDI. If not disabled by a fuse, the reset function of the Reset (PDI_CLK) pin is enabled
again. This also means that the minimum programming frequency is approximately 10kHz.
28.3.3 Frame Format and Characters

The PDI physical layer uses a frame format defined as one character of eight data bits, with a start bit, a parity bit, and
two stop bits.
Figure 28-4. PDI Serial Frame Format
FRAME
(IDLE) St 0 1 2 3 4 5 6 7 P Sp1 Sp2 (St/IDLE)
St Start bit, always low

(0-7) Data bits (0 to 7)
P Parity bit, even parity used
Sp1 Stop bit 1, always high
Sp2 Stop bit 2, always high
Three different characters are used, DATA, BREAK, and IDLE. The BREAK character is equal to a 12-bit length of low
level. The IDLE character is equal to a 12-bit length of high level. The BREAK and IDLE characters can be extended
beyond the 12-bit length.
Figure 28-5. Characters and Timing for the PDI Physical Layer
1 DATA character
START 0 1 2 3 4 5 6 7 P STOP
1 BREAK character
BREAK
1 IDLE character
IDLE
XMEGA E MANUAL 402

28.3.4 Serial Transmission and Reception
The PDI physical layer is either in transmit (TX) or receive (RX) mode. By default, it is in RX mode, waiting for a start bit.
The programmer and the PDI operate synchronously on the PDI_CLK provided by the programmer. The dependency
between the clock edges and data sampling or data change is fixed. As illustrated in Figure 28-6, output data (either from
the programmer or the PDI) is always set up (changed) on the falling edge of PDI_CLK and sampled on the rising edge
of PDI_CLK.
Figure 28-6. Changing and Sampling of Data
PDI_CLK
PDI_DATA
Sample Sample Sample
28.3.5 Serial Transmission

When a data transmission is initiated, by the PDI controller, the transmitter simply shifts out the start bit, data bits, parity
bit, and the two stop bits on the PDI_DATA line. The transmission speed is dictated by the PDI_CLK signal. While in
transmission mode, IDLE bits (high bits) are automatically transmitted to fill possible gaps between successive DATA
characters. If a collision is detected during transmission, the output driver is disabled, and the interface is put into RX
mode waiting for a BREAK character.
28.3.6 Serial Reception

When a start bit is detected, the receiver starts to collect the eight data bits. If the parity bit does not correspond to the
parity of the data bits, a parity error has occurred. If one or both of the stop bits are low, a frame error has occurred. If the
parity bit is correct, and no frame error is detected, the received data bits are available for the PDI controller.
When the PDI is in TX mode, a BREAK character signaled by the programmer will not be interpreted as a BREAK, but
will instead cause a generic data collision. When the PDI is in RX mode, a BREAK character will be recognized as a
BREAK. By transmitting two successive BREAK characters (which must be separated by one or more high bits), the last
BREAK character will always be recognized as a BREAK, regardless of whether the PDI was in TX or RX mode initially.
This is because in TX mode the first BREAK is seen as a collision. The PDI then shifts to RX mode and sees the second
BREAK as break.
28.3.7 Direction Change

In order to ensure correct timing for half-duplex operation, a guard time mechanism is used. When the PDI changes from
RX mode to TX mode, a configurable number of IDLE bits are inserted before the start bit is transmitted. The minimum
transition time between RX and TX mode is two IDLE cycles, and these are always inserted. The default guard time
value is 128 bits.
Figure 28-7. PDI Direction Change by Inserting IDLE bits
1 DATA character Dir. change 1 DATA character
St PDI DATA Receive (RX) P Sp1 Sp2 IDLE bits St PDI DATA Transmit (TX) P Sp1 Sp2
Data from Guard time Data from

Programmer to # IDLE bits PDI interface
PDI interface inserted to Programmer
XMEGA E MANUAL 403

The external programmer will loose control of the PDI_DATA line at the point where the PDI changes from RX to TX
mode. The guard time relaxes this critical phase of the communication. When the programmer changes from RX mode to
TX mode, a single IDLE bit, at minimum, should be inserted before the start bit is transmitted.
28.3.8 Drive Contention and Collision Detection

In order to reduce the effect of drive contention (the PDI and the programmer driving the PDI_DATA line at the same
time), a mechanism for collision detection is used. The mechanism is based on the way the PDI drives data out on the
PDI_DATA line. As shown in Figure 28-8, the PDI output driver is active only when the output value changes (from 0-1 or
1-0). Hence, if two or more successive bit values are the same, the value is actively driven only on the first clock cycle.
After this point, the PDI output driver is automatically tri-stated, and the PDI_DATA pin has a bus keeper responsible for
keeping the pin value unchanged until the output driver is re-enabled due to a change in the bit value.
Figure 28-8. Driving Data out on the PDI_DATA using a Bus Keeper
PDI_CLK
Output enable
PDI Output
PDI_DATA
1 0 1 1 0 0 1
If the programmer and the PDI both drive the PDI_DATA line at the same time, drive contention will occur, as illustrated
in Figure 28-9. Every time a bit value is kept for two or more clock cycles, the PDI is able to verify that the correct bit
value is driven on the PDI_DATA line. If the programmer is driving the PDI_DATA line to the opposite bit value to what
the PDI expects, a collision is detected.
Figure 28-9. Drive Contention and Collision Detection on the PDI_DATA Line
PDI_CLK
PDI Output
Programmer
output
PDI_DATA
1 0 X 1 X 1 1
Collision detect
= Collision
As long as the PDI transmits alternating ones and zeros, collisions cannot be detected, because the PDI output driver will
be active all the time, preventing polling of the PDI_DATA line. However, the two stop bits should always be transmitted
as ones within a single frame, enabling collision detection at least once per frame.
XMEGA E MANUAL 404

28.4 PDI Controller
The PDI controller performs data transmission/reception on a byte level, command decoding, high-level direction control,
control and status register access, exception handling, and clock switching (PDI_CLK or TCK). The interaction between
an external programmer and the PDI controller is based on a scheme where the programmer transmits various types of
requests to the PDI controller, which in turn responds according to the specific request. A programmer request comes in
the form of an instruction, which may be followed by one or more byte operands. The PDI controller response may be
silent (e.g., a data byte is stored to a location within the device), or it may involve data being returned to the programmer
(e.g., a data byte is read from a location within the device).
28.4.1 Accessing Internal Interfaces

After an external programmer has established communication with the PDI, the internal interfaces are not accessible, by
default. To get access to the NVM controller and the nonvolatile memories for programming, a unique key must be
signaled by using the KEY instruction. The internal interfaces are accessed as one linear address space using a
dedicated bus (PDIBUS) between the PDI and the internal interfaces. The PDIBUS address space is shown in Figure 29-
3 on page 425. The NVM controller must be enabled for the PDI controller to have any access to the NVM interface. The
PDI controller can access the NVM and NVM controller in programming mode only. The PDI controller does not need to
access the NVM controller's data or address registers when reading or writing NVM.
28.4.2 NVM Programming Key

The key that must be sent using the KEY instruction is 64 bits long. The key that will enable NVM programming is:
0x1289AB45CDD888FF.
28.4.3 Exception Handling

There are several situations that are considered exceptions from normal operation. The exceptions depend on whether
the PDI is in RX or TX mode.
While the PDI is in RX mode, the exceptions are:
 The physical layer detects a parity error
 The physical layer detects a frame error
 The physical layer recognizes a BREAK character (also detected as a frame error)
While the PDI is in TX mode, the exception is:

 The physical layer detects a data collision
Exceptions are signaled to the PDI controller. All ongoing operations are then aborted, and the PDI is put in ERROR
state. The PDI will remain in ERROR state until a BREAK is sent from the external programmer, and this will bring the
PDI back to its default RX state.
Due to this mechanism, the programmer can always synchronize the protocol by transmitting two successive BREAK
characters.
28.4.4 Reset Signalling

Through the reset register, the programmer can issue a reset and force the device into reset. After clearing the reset
register, reset is released, unless some other reset source is active.
28.4.5 Instruction Set

The PDI has a small instruction set used for accessing both the PDI itself and the internal interfaces. All instructions are
byte instructions. The instructions allow an external programmer to access the PDI controller, the NVM controller and the
nonvolatile memories.
XMEGA E MANUAL 405

28.4.5.1 LDS - Load Data from PDIBUS Data Space using Direct Addressing
The LDS instruction is used to load data from the PDIBUS data space for read out. The LDS instruction is based on direct
addressing, which means that the address must be given as an argument to the instruction. Even though the protocol is
based on byte-wise communication, the LDS instruction supports multiple-byte addresses and data access. Four
different address/data sizes are supported: single-byte, word (two bytes), three-byte, and long (four bytes). Multiple-byte
access is broken down internally into repeated single-byte accesses, but this reduces protocol overhead. When using the
LDS instruction, the address byte(s) must be transmitted before the data transfer.
28.4.5.2 STS - Store Data to PDIBUS Data Space using Direct Addressing
The STS instruction is used to store data that are serially shifted into the physical layer shift register to locations within
the PDIBUS data space. The STS instruction is based on direct addressing, which means that the address must be given
as an argument to the instruction. Even though the protocol is based on byte-wise communication, the ST instruction
supports multiple-bytes addresses and data access. Four different address/data sizes are supported: single-byte, word
(two bytes), three-byte, and long (four bytes). Multiple-byte access is broken down internally into repeated single-byte
accesses, but this reduces protocol overhead. When using the STS instruction, the address byte(s) must be transmitted
before the data transfer.
28.4.5.3 LD - Load Data from PDIBUS Data Space using Indirect Addressing
The LD instruction is used to load data from the PDIBUS data space into the physical layer shift register for serial read
out. The LD instruction is based on indirect addressing (pointer access), which means that the address must be stored in
the pointer register prior to the data access. Indirect addressing can be combined with pointer increment. In addition to
reading data from the PDIBUS data space, the LD instruction can read the pointer register. Even though the protocol is
based on byte-wise communication, the LD instruction supports multiple-byte addresses and data access. Four different
address/data sizes are supported: single-byte, word (two bytes), three-byte, and long (four bytes). Multiple-byte access is
broken down internally into repeated single-byte accesses, but this reduces the protocol overhead.
28.4.5.4 ST - Store Data to PDIBUS Data Space using Indirect Addressing

The ST instruction is used to store data that is serially shifted into the physical layer shift register to locations within the
PDIBUS data space. The ST instruction is based on indirect addressing (pointer access), which means that the address
must be stored in the pointer register prior to the data access. Indirect addressing can be combined with pointer
increment. In addition to writing data to the PDIBUS data space, the ST instruction can write the pointer register. Even
though the protocol is based on byte-wise communication, the ST instruction supports multiple-bytes address - and data
access. Four different address/data sizes are supported; byte, word, three bytes, and long (four bytes). Multiple-bytes
access is internally broken down to repeated single-byte accesses, but it reduces the protocol overhead.
28.4.5.5 LDCS - Load Data from PDI Control and Status Register Space
The LDCS instruction is used to load data from the PDI control and status registers into the physical layer shift register
for serial read out. The LDCS instruction supports only direct addressing and single-byte access.
28.4.5.6 STCS - Store Data to PDI Control and Status Register Space
The STCS instruction is used to store data that are serially shifted into the physical layer shift register to locations within
the PDI control and status registers. The STCS instruction supports only direct addressing and single-byte access.
28.4.5.7 KEY - Set Activation Key

The KEY instruction is used to communicate the activation key bytes required for activating the NVM interfaces.
28.4.5.8 REPEAT - Set Instruction Repeat Counter

The REPEAT instruction is used to store count values that are serially shifted into the physical layer shift register to the
repeat counter register. The instruction that is loaded directly after the REPEAT instruction operand(s) will be repeated a
number of times according to the specified repeat counter register value. Hence, the initial repeat counter value plus one
gives the total number of times the instruction will be executed. Setting the repeat counter register to zero makes the
following instruction run once without being repeated.
XMEGA E MANUAL 406

The REPEAT instruction cannot be repeated. The KEY instruction cannot be repeated, and will override the current value
of the repeat counter register.
28.4.6 Instruction Set Summary

The PDI instruction set summary is shown in Figure 28-10.
Figure 28-10.PDI Instruction Set Summary

Cmd Size A Size B
Cmd
0 0 0 LDS
LDS 0 0 0 0
0 0 1 LD
0 1 0 STS
0 1 1 ST
STS 0 1 0 0
1 0 0 LDCS (LDS Control/Status)
1 0 1 REPEAT
1 1 0 STCS (STS Control/Status)
Cmd Ptr Size A/B
1 1 1 KEY
LD 0 0 1 0
Size A - Address size (direct access)
0 0 Byte
0 1 Word (2 Bytes)
ST 0 1 1 0
1 0 3 Bytes
1 1 Long (4 Bytes)
CS Address
Ptr - Pointer access (indirect access)
0 0 *(ptr)
LDCS 1 0 0 0
0 1 *(ptr++)
1 0 ptr
STCS
1 1 ptr++ - Reserved
1 1 0 0
Size B - Data size

Size B
0 0 Byte
0 1 Word (2 Bytes)
REPEAT 1 0 3 Bytes
1 0 1 0 0 0
1 1 Long (4 Bytes)
CS Address (CS - Control/Status reg.)

0 0 0 0 Register 0
KEY
0 0 0 1 Register 1
1 1 1 0 0 0 0 0
0 0 1 0 Register 2
0 0 1 1 Reserved
......
1 1 1 1 Reserved
28.5 Register Description – PDI Instruction and Addressing Registers

The PDI instruction and addressing registers are internal registers utilized for instruction decoding and PDIBUS
addressing. None of these registers are accessible as registers in a register space.
28.5.1 Instruction Register

When an instruction is successfully shifted into the physical layer shift register, it is copied into the instruction register.
The instruction is retained until another instruction is loaded. The reason for this is that the REPEAT command may force
the same instruction to be run repeatedly, requiring command decoding to be performed several times on the same
instruction.
XMEGA E MANUAL 407

28.5.2 Pointer Register
The pointer register is used to store an address value that specifies locations within the PDIBUS address space. During
direct data access, the pointer register is updated by the specified number of address bytes given as operand bytes to an
instruction. During indirect data access, addressing is based on an address already stored in the pointer register prior to
the access itself. Indirect data access can be optionally combined with pointer register post-increment. The indirect
access mode has an option that makes it possible to load or read the pointer register without accessing any other
registers. Any register update is performed in a little-endian fashion. Hence, loading a single byte of the address register
will always update the LSB while the most-significant bytes are left unchanged.
The pointer register is not involved in addressing registers in the PDI control and status register space (CSRS space).
28.5.3 Repeat Counter Register

The REPEAT instruction is always accompanied by one or more operand bytes that define the number of times the next
instruction should be repeated. These operand bytes are copied into the repeat counter register upon reception. During
the repeated executions of the instruction immediately following the REPEAT instruction and its operands, the repeat
counter register is decremented until it reaches zero, indicating that all repetitions have completed. The repeat counter is
also involved in key reception.
28.5.4 Operand Count Register

Immediately after an instruction (except the LDCS and STCS instructions) a specified number of operands or data bytes
(given by the size parts of the instruction) are expected. The operand count register is used to keep track of how many
bytes have been transferred.
XMEGA E MANUAL 408

28.6 Register Description – PDI Control and Status Registers
The PDI control and status registers are accessible in the PDI control and status register space (CSRS) using the LDCS
and STCS instructions. The CSRS contains registers directly involved in configuration and status monitoring of the PDI
itself.
Bit 7 6 5 4 3 2 1 0
+0x00 – – – – – – NVMEN –
Read/Write R R R R R R R/W R

 Bit 1 – NVMEN: Nonvolatile Memory Enable
This status bit is set when the key signalling enables the NVM programming interface. The external programmer
can poll this bit to verify successful enabling. Writing the NVMEN bit disables the NVM interface.
28.6.2 RESET – Reset Register
Bit 7 6 5 4 3 2 1 0
+0x01 RESET[7:0]
 Bit 7:0 – RESET[7:0]: Reset Signature

When the reset signature, 0x59, is written to RESET, the device is forced into reset. The device is kept in reset
until RESET is written with a data value different from the reset signature. Reading the lsb will return the status of
the reset. The seven msbs will always return the value 0x00, regardless of whether the device is in reset or not.
Bit 7 6 5 4 3 2 1 0
+0x02 – – – – – GUARDTIME[2:0]

 Bit 2:0 – GUARDTIME[2:0]: Guard Time
These bits specify the number of IDLE bits of guard time that are inserted in between PDI reception and transmis-
sion direction changes. The default guard time is 128 IDLE bits, and the available settings are shown in Table 28-
1. In order to speed up the communication, the guard time should be set to the lowest safe configuration accepted.
No guard time is inserted when switching from TX to RX mode.
XMEGA E MANUAL 409

Table 28-1. Guard Time Settings
GUARDTIME Number of IDLE bits
000 128
001 64
010 32
011 16
100 8
101 4
110 2
111 2

+0x00 STATUS – – – – – – NVMEN – 409
+0x01 RESET RESET[7:0] 409
+0x02 CTRL – – – – – GUARDTIME[2:0] 409
+0x03 Reserved – – – – – – – –
XMEGA E MANUAL 410

29. Memory Programming
29.1 Features
 Read and write access to all memory spaces from
 External programmers
 Application software self-programming
 Self-programming and boot loader support
 Any communication interface can be used for program upload/download
 External programming
 Support for in-system and production programming
 Programming through serial PDI interface
 High security with separate boot lock bits for:
 External programming access
 Boot loader section access
 Application section access
 Application table access
 Reset fuse to select reset vector address to the start of the:
 Application section, or
 Boot loader section
29.2 Overview
This section describes how to program the nonvolatile memory (NVM) in Atmel AVR XMEGA devices, and covers both
self-programming and external programming. The NVM consists of the flash program memory, user signature and
production signature rows, fuses and lock bits, and EEPROM data memory. For details on the actual memories, how
they are organized, and the register description for the NVM controller used to access the memories, refer to “Memories”
on page 20.
The NVM can be accessed for read and write from application software through self-programming and from an external
programmer. Accessing the NVM is done through the NVM controller, and for the flash memory the two methods of
programming are similar. Memory access is done by loading address and/or data to the selected memory or NVM
controller and using a set of commands and triggers that make the NVM controller perform specific tasks on the
nonvolatile memory.
From external programming, all memory spaces can be read and written, except for the production signature row, which
can only be read. The device can be programmed in-system and is accessed through the PDI using the PDI physical
interface. “External Programming” on page 424 describes PDI in detail.
Self-programming and boot loader support allows application software in the device to read and write the flash, user
signature row and EEPROM, write the lock bits to a more secure setting, and read the production signature row and
fuses. When programming, the CPU is halted, waiting for the flash operation to complete. “Self-programming and Boot
Loader Support” on page 415 describes this in detail.
For both self-programming and external programming, it is possible to run a CRC check on the flash or a section of the
flash to verify its content after programming.
The device can be locked to prevent reading and/or writing of the NVM. There are separate lock bits for external
programming access and self-programming access to the boot loader section, application section, and application table
section.
29.3 NVM Controller

Access to the nonvolatile memories is done through the NVM controller. It controls NVM timing and access privileges,
and holds the status of the NVM, and is the common NVM interface for both external programming and self-
programming. For more details, refer to “Register Description” on page 429.
XMEGA E MANUAL 411

29.4 NVM Commands
The NVM controller has a set of commands used to perform tasks on the NVM. This is done by writing the selected
command to the NVM command register. In addition, data and addresses must be read/written from/to the NVM data and
address registers for memory read/write operations.
When a selected command is loaded and address and data are set up for the operation, each command has a trigger
that will start the operation. Based on these triggers, there are three main types of commands.
29.4.1 Action-triggered Commands

Action-triggered commands are triggered when the command execute (CMDEX) bit in the NVM control register A
(CTRLA) is written. Action-triggered commands typically are used for operations which do not read or write the NVM,
such as the CRC check.
29.4.2 NVM Read-triggered Commands

NVM read-triggered commands are triggered when the NVM is read, and this is typically used for NVM read operations.
29.4.3 NVM Write-triggered Commands

NVM write-triggered commands are triggered when the NVM is written, and this is typically used for NVM write
operations.
29.4.4 Write/execute Protection

Most command triggers are protected from accidental modification/execution during self-programming. This is done
using the configuration change protection (CCP) feature, which requires a special write or execute sequence in order to
change a bit or execute an instruction. For details on the CCP, refer to “Configuration Change Protection” on page 13.
29.5 NVM Controller Busy Status

When the NVM controller is busy performing an operation, the busy flag in the NVM status register is set and the
following registers are blocked for write access:
 NVM command register
 NVM control A register
 NVM control B register
 NVM address registers
 NVM data registers
This ensures that the given command is executed and the operations finished before the start of a new operation. The
external programmer or application software must ensure that the NVM is not addressed when it is busy with a
programming operation.
Programming any part of the NVM will automatically block:
 All programming to other parts of the NVM
 All loading/erasing of the flash and EEPROM page buffers
 All NVM reads from external programmers
 All NVM reads from the application section
During self-programming, interrupts must be disabled or the interrupt vector table must be moved to the boot loader
sections, as described in “PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132.
29.6 Flash and EEPROM Page Buffers

The flash memory is updated page by page. The EEPROM can be updated on a byte-by-byte and page-by-page basis.
flash and EEPROM page programming is done by first filling the associated page buffer, and then writing the entire page
buffer to a selected page in flash or EEPROM.
XMEGA E MANUAL 412

The size of the page and page buffers depends on the flash and EEPROM size in each device, and details are described
in the device’s datasheet.
29.6.1 Flash Page Buffer

The flash page buffer is filled one word at a time, and it must be erased before it can be loaded. When loading the page
buffer with new content, the result is a binary AND between the existing content of the page buffer location and the new
value. If the page buffer is already loaded once after erase the location will most likely be corrupted.
Page buffer locations that are not loaded will have the value 0xFFFF, and this value will then be programmed into the
corresponding flash page locations.
The page buffer is automatically erased after:
 A device reset
 Executing the write flash page command
 Executing the erase and write flash page command
 Executing the signature row write command
 Executing the write lock bit command
29.6.2 EEPROM Page Buffer

The EEPROM page buffer is filled one byte at a time, and it must be erased before it can be loaded. When loading the
page buffer with new content, the result is a binary AND between the existing content of the page buffer location and the
new value. If the EEPROM page buffer is already loaded once after erase the location will most likely be corrupted.
EEPROM page buffer locations that are loaded will get tagged by the NVM controller. During a page write or page erase,
only targeted locations will be written or erased. Locations that are not targeted will not be written or erased, and the
corresponding EEPROM location will remain unchanged. This means that before an EEPROM page erase, data must be
loaded to the selected page buffer location to tag them. When performing an EEPROM page erase, the actual value of
the tagged location does not matter.
The EEPROM page buffer is automatically erased after:
 A system reset
 Executing the write EEPROM page command
 Executing the erase and write EEPROM page command
 Executing the write lock bit and write fuse commands.
29.7 Flash and EEPROM Programming Sequences

For page programming, filling the page buffers and writing the page buffer into flash or EEPROM are two separate
operations. The sequence is same for both self-programming and external programming.
29.7.1 Flash Programming Sequence

Before programming a flash page with the data in the flash page buffer, the flash page must be erased. Programming an
un-erased flash page will corrupt its content.
The flash page buffer can be filled either before the erase flash Page operation or between a erase flash page and a
write flash page operation:
Alternative 1:
 Fill the flash page buffer
 Perform a flash page erase
 Perform a flash page write
XMEGA E MANUAL 413

Alternative 2:
 Perform an atomic page erase and write
Alternative 3, fill the buffer after a page erase:
 Perform a flash page erase
 Perform a flash page write
The NVM command set supports both atomic erase and write operations, and split page erase and page write
commands. This split commands enable shorter programming time for each command, and the erase operations can be
done during non-time-critical programming execution. If alternative 3 is used, it is not possible to read the old data while
loading, since the page is already erased. The page address must be the same for both page erase and page write
operations when using alternative 1 or 3.
29.7.2 EEPROM Programming Sequence

Before programming an EEPROM page with the tagged data bytes stored in the EEPROM page buffer, the selected
locations in the EEPROM page must be erased. Programming an un-erased EEPROM page will corrupt its content. The
EEPROM page buffer must be loaded before any page erase or page write operations:
Alternative 1:
 Fill the EEPROM page buffer with the selected number of bytes
 Perform a EEPROM page erase
 Perform a EEPROM page write
Alternative 2:
 Fill the EEPROM page buffer with the selected number of bytes
 Perform an atomic EEPROM page erase and write
29.8 Protection of NVM

To protect the flash and EEPROM memories from write and/or read, lock bits can be set to restrict access from external
programmers and the application software. Refer to “LOCKBITS – Lock Bit Register” on page 29 for details on the
available lock bit settings and how to use them.
29.9 Preventing NVM Corruption

During periods when the VCC voltage is below the minimum operating voltage for the device, the result from a flash
memory write can be corrupt, as supply voltage is too low for the CPU and the flash to operate properly.To ensure that
the voltage is sufficient enough during a complete programming sequence of the flash memory, a voltage detector using
the POR threshold (VPOT+) level is enabled. During chip erase and when the PDI is enabled the brownout detector (BOD)
is automatically enabled at its configured level.
Depending on the programming operation, if any of these VCC voltage levels are reached, the programming sequence
will be aborted immediately. If this happens, the NVM programming should be restarted when the power is sufficient
again, in case the write sequence failed or only partly succeeded.
29.10 CRC Functionality

It is possible to run an automatic cyclic redundancy check (CRC) on the flash program memory. When NVM is used to
control the CRC module, an even number of bytes are read, at least in the flash range mode. If the user selects a range
with an odd number of bytes, an extra byte will be read, and the checksum will not correspond to the selected range.
Refer to “CRC – Cyclic Redundancy Check Generator” on page 344 for more details.
XMEGA E MANUAL 414

29.11 Self-programming and Boot Loader Support
Reading and writing the EEPROM and flash memory from the application software in the device is referred to as self-
programming. A boot loader (application code located in the boot loader section of the flash) can both read and write the
flash program memory, user signature row, and EEPROM, and write the lock bits to a more secure setting. Application
code in the application section can read from the flash, user signature row, production signature row, and fuses, and read
and write the EEPROM.
29.11.1 Flash Programming

The boot loader can use any available communication interface and associated protocol to read code and write
(program) that code into the flash memory, or read out the program memory code. It has the capability to write into the
entire flash, including the boot loader section. The boot loader can thus modify itself, and it can also erase itself from the
flash if the feature is not needed anymore.
29.11.1.1 Application and Boot Loader Sections

The application and boot loader sections in the flash are different when it comes to self-programming.
 When erasing or writing a page located inside the application section, the boot loader section can be read
during the operation, but the CPU is halted during the entire operation, and cannot execute from the boot
loader section
 When erasing or writing a page located inside the boot loader section, the CPU is halted during the entire
operation, and code cannot execute
The user signature row section has the same properties as the boot loader section.
Table 29-1. Summary of Self-programming Functionality
Section being addressed during programming Section that can be read during programming CPU halted?
Application section Boot loader section Yes
Boot loader section None Yes
User signature row section None Yes
29.11.1.2 Addressing the Flash

The Z-pointer is used to hold the flash memory address for read and write access. For more details on the Z-pointer,
refer to “The X-, Y-, and Z-registers” on page 11.
Since the flash is word accessed and organized in pages, the Z-pointer can be treated as having two sections. The least-
significant bits address the words within a page, while the most-significant bits address the page within the flash. This is
shown in Figure 29-1 on page 416. The word address in the page (FWORD) is held by the bits [WORDMSB:1] in the Z-
pointer. The remaining bits [PAGEMSB:WORDMSB+1] in the Z-pointer hold the flash page address (FPAGE). Together
FWORD and FPAGE holds an absolute address to a word in the flash.
For flash read operations (ELPM and LPM), one byte is read at a time. For this, the least-significant bit (bit 0) in the Z-
pointer is used to select the low byte or high byte in the word address. If this bit is 0, the low byte is read, and if this bit is
1 the high byte is read.
The size of FWORD and FPAGE will depend on the page and flash size in the device. Refer to each device’s datasheet
for details.
Once a programming operation is initiated, the address is latched and the Z-pointer can be updated and used for other
operations.
XMEGA E MANUAL 415

Figure 29-1. Flash Addressing for Self-programming
BIT PAGEMSB WORDMSB 1 0
Z-Pointer FPAGE FWORD 0/1
Low/High Byte select for (E)LPM
PAGE ADDRESS WORD ADDRESS

WITHIN THE FLASH WITHIN A PAGE
FPAGE PROGRAM MEMORY PAGE FWORD

00 PAGE INSTRUCTION WORD 00
01 01
02 02
PAGEEND
FLASHEND
29.11.2 NVM Flash Commands

The NVM commands that can be used for accessing the flash program memory, signature row and production signature
row are listed in Table 29-2 on page 417.
For self-programming of the flash, the trigger for action-triggered commands is to set the CMDEX bit in the NVM CTRLA
register (CMDEX). The read-triggered commands are triggered by executing the (E)LPM instruction (LPM). The write-
triggered commands are triggered by executing the SPM instruction (SPM).
The Change Protected column indicates whether the trigger is protected by the configuration change protection (CCP) or
not. This is a special sequence to write/execute the trigger during self-programming. For more details, refer to “CCP –
Configuration Change Protection Register” on page 15. CCP is not required for external programming. The two last
columns show the address pointer used for addressing and the source/destination data register.
“ Application and Boot Loader Sections” on page 415 through “ Read User Signature Row / Production Signature Row”
on page 420 explain in detail the algorithm for each NVM operation.
XMEGA E MANUAL 416

Table 29-2. Flash Self-programming Commands
configuration
Data register
Description
CPU halted
NVM busy
CMD[6:0]
Address
Change
Trigger
pointer
Group
0x00 NO_OPERATION No operation / read flash -/(E)LPM -/N N -/N -/ Z-pointer -/Rd
Flash Page Buffer
0x23 LOAD_FLASH_BUFFER Load flash page buffer SPM N N N Z-pointer R1:R0
0x26 ERASE_FLASH_BUFFER Erase flash page buffer CMDEX N Y Y Z-pointer -
Flash
0x2B ERASE_FLASH_PAGE Erase flash page SPM N/Y(2) Y Y Z-pointer -

(2)
0x02E WRITE_FLASH_PAGE Write flash page SPM N/Y Y Y Z-pointer -
0x2F ERASE_WRITE_FLASH_PAGE Erase and write flash page SPM N/Y(2) Y Y Z-pointer -
(3) (1)
0x3A FLASH_RANGE_CRC Flash range CRC CMDEX Y Y Y DATA/ADDR DATA
Application Section
0x20 ERASE_APP Erase application section SPM Y Y Y Z-pointer -
0x22 ERASE_APP_PAGE Erase application section page SPM N Y Y Z-pointer -
0x24 WRITE_APP_PAGE Write application section page SPM N Y Y Z-pointer -
0x25 ERASE_WRITE_APP_PAGE Erase and write application section page SPM N Y Y Z-pointer -
0x38 APP_CRC Application section CRC CMDEX Y Y Y - DATA
Boot Loader Section
0x2C WRITE_BOOT_PAGE Write boot loader section page SPM Y Y Y Z-pointer -
0x2D ERASE_WRITE_BOOT_PAGE Erase and write boot loader section page SPM Y Y Y Z-pointer -
0x39 BOOT_CRC Boot loader section CRC CMDEX Y Y Y - DATA
User Signature Row
0x01(4) READ_USER_SIG_ROW Read user signature row LPM N N N Z-pointer Rd
0x18 ERASE_USER_SIG_ROW Erase user signature row SPM Y Y Y - -
0x1A WRITE_USER_SIG_ROW Write user signature row SPM Y Y Y - -
Production Signature (Calibration) Row(5)
0x02(4) READ_CALIB_ROW Read calibration row LPM N N N Z-pointer Rd
Notes: 1. The flash range CRC command used byte addressing of the flash.
2. Will depend on the flash section (application or boot loader) that is actually addressed.
3. This command is qualified with the lock bits, and requires that the boot lock bits are unprogrammed.
4. When using a command that changes the normal behavior of the LPM command; READ_USER_SIG_ROW and READ_CALIB_ROW; it is recommended to
disable interrupts to ensure correct execution of the LPM instruction.
5. For consistency the name Calibration Row has been renamed to Production Signature Row throughout the document.
XMEGA E MANUAL 417

29.11.2.1 Read Flash
The (E)LPM instruction is used to read one byte from the flash memory.
1. Load the Z-pointer with the byte address to read.
2. Load the NVM command register (NVM CMD) with the no operation command.
3. Execute the LPM instruction.
The destination register will be loaded during the execution of the LPM instruction.
29.11.2.2 Erase Flash Page Buffer

The erase flash page buffer command is used to erase the flash page buffer.
1. Load the NVM CMD with the erase flash page buffer command.
2. Set the command execute bit (CMDEX) in the NVM control register A (NVM CTRLA). This requires the timed CCP
sequence during self-programming.
The NVM busy (BUSY) flag in the NVM status register (NVM STATUS) will be set until the page buffer is erased.
29.11.2.3 Load Flash Page Buffer

The load flash page buffer command is used to load one word of data into the flash page buffer.
1. Load the NVM CMD register with the load flash page buffer command.
2. Load the Z-pointer with the word address to write.
3. Load the data word to be written into the R1:R0 registers.
4. Execute the SPM instruction. The SPM instruction is not protected when performing a flash page buffer load.
Repeat step 2-4 until the complete flash page buffer is loaded. Unloaded locations will have the value 0xFFFF.
29.11.2.4 Erase Flash Page

The erase flash page command is used to erase one page in the flash.
1. Load the Z-pointer with the flash page address to erase. The page address must be written to FPAGE. Other bits
in the Z-pointer will be ignored during this operation.
2. Load the NVM CMD register with the erase flash page command.
3. Execute the SPM instruction. This requires the timed CCP sequence during self-programming.
The BUSY flag in the NVM STATUS register will be set until the erase operation is finished. The flash section busy
(FBUSY) flag is set as long the flash is busy, and the application section cannot be accessed.
29.11.2.5 Write Flash Page

The write flash page command is used to write the flash page buffer into one flash page in the flash.
1. Load the Z-pointer with the flash page to write. The page address must be written to FPAGE. Other bits in the Z-
pointer will be ignored during this operation.
2. Load the NVM CMD register with the write flash page command.
The BUSY flag in the NVM STATUS register will be set until the write operation is finished. The FBUSY flag is set as long
the flash is busy, and the application section cannot be accessed.
29.11.2.6 Flash Range CRC

The flash range CRC command can be used to verify the content in an address range in flash after a self-programming.
1. Load the NVM CMD register with the flash range CRC command.
2. Load the start byte address in the NVM address register (NVM ADDR).
3. Load the end byte address in NVM data register (NVM DATA).
4. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming.
The BUSY flag in the NVM STATUS register will be set, and the CPU is halted during the execution of the command.
The CRC checksum will be available in the NVM DATA register.
XMEGA E MANUAL 418

In order to use the flash range CRC command, all the boot lock bits must be unprogrammed (no locks). The command
execution will be aborted if the boot lock bits for an accessed location are set.
29.11.2.7 Erase Application Section / Boot Loader Section Page

The erase application section page erase and erase boot loader section page commands are used to erase one page in
the application section or boot loader section.
1. Load the Z-pointer with the flash page address to erase. The page address must be written to ZPAGE. Other bits
in the Z-pointer will be ignored during this operation.
2. Load the NVM CMD register with the erase application/boot section page command.
The BUSY flag in the NVM STATUS register will be set until the erase operation is finished. The FBUSY flag is set as
long the flash is busy, and the application section cannot be accessed.
29.11.2.8 Application Section / Boot Loader Section Page Write

The write application section page and write boot loader section page commands are used to write the flash page buffer
into one flash page in the application section or boot loader section.
2. Load the NVM CMD register with the write application section/boot loader section page command.
The BUSY flag in the NVM STATUS register will be set until the write operation is finished. The FBUSY flag is set as long
An invalid page address in the Z-pointer will abort the NVM command. The erase application section page command
requires that the Z-pointer addresses the application section, and the erase boot section page command requires that
the Z-pointer addresses the boot loader section.
29.11.2.9 Erase and Write Application Section / Boot Loader Section Page
The erase and write application section page and erase and write boot loader section page commands are used to erase
one flash page and then write the flash page buffer into that flash page in the application section or boot loader section in
one atomic operation.
2. Load the NVM CMD register with the erase and write application section/boot loader section page command.
The BUSY flag in the NVM STATUS register will be set until the operation is finished. The FBUSY flag is set as long as
An invalid page address in the Z-pointer will abort the NVM command. The erase and write application section command
requires that the Z-pointer addresses the application section, and the erase and write boot section page command
requires that the Z-pointer addresses the boot loader section.
29.11.2.10 Application Section / Boot Loader Section CRC

The application section CRC and boot loader section CRC commands can be used to verify the application section and
boot loader section content after self-programming.
1. Load the NVM CMD register with the application section/ boot load section CRC command.
The BUSY flag in the NVM STATUS register will be set, and the CPU is halted during the execution of the CRC
command. The CRC checksum will be available in the NVM data registers.
XMEGA E MANUAL 419

29.11.2.11 Erase User Signature Row
The erase user signature row command is used to erase the user signature row.
1. Load the NVM CMD register with the erase user signature row command.
The BUSY flag in the NVM STATUS register will be set, and the CPU will be halted until the erase operation is finished.
The user signature row is NRWW.
29.11.2.12 Write User Signature Row

The write signature row command is used to write the flash page buffer into the user signature row.
1. Set up the NVM CMD register to write user signature row command.
The BUSY flag in the NVM STATUS register will be set until the operation is finished, and the CPU will be halted during
the write operation. The flash page buffer will be cleared during the command execution after the write operation, but the
CPU is not halted during this stage.
29.11.2.13 Read User Signature Row / Production Signature Row

The read user signature row and read production signature (calibration) row commands are used to read one byte from
the user signature row or production signature (calibration) row.
1. Load the Z-pointer with the byte address to read.
2. Load the NVM CMD register with the read user signature row / production signature (calibration) row command.
3. Execute the LPM instruction.
The destination register will be loaded during the execution of the LPM instruction.
To ensure that LPM for reading flash will be executed correctly it is advised to disable interrupt while using either of these
commands.
29.11.3 NVM Fuse and Lock Bit Commands

The NVM flash commands that can be used for accessing the fuses and lock bits are listed in Table 29-3 on page 420.
For self-programming of the fuses and lock bits, the trigger for action-triggered commands is to set the CMDEX bit in the
NVM CTRLA register (CMDEX). The read-triggered commands are triggered by executing the (E)LPM instruction (LPM).
The write-triggered commands are triggered by a executing the SPM instruction (SPM).
The Change Protected column indicates whether the trigger is protected by the configuration change protection (CCP)
during self-programming or not. The last two columns show the address pointer used for addressing and the
source/destination data register.
Section 29.11.3.1 “ Write Lock Bits” on page 421 through Section 29.11.3.2 “ Read Fuses” on page 421 explain in detail
the algorithm for each NVM operation.
Table 29-3. Fuse and Lock Bit Commands
CPU Change NVM Address Data

CMD[6:0] Group configuration Description Trigger halted protected busy pointer register
0x00 NO_OPERATION No operation - - - - - -
Fuses and lock bits
0x07 READ_FUSES Read fuses CMDEX Y N Y ADDR DATA
0x08 WRITE_LOCK_BITS Write lock bits CMDEX N Y Y ADDR -
XMEGA E MANUAL 420

29.11.3.1 Write Lock Bits
The write lock bits command is used to program the boot lock bits to a more secure settings from software.
1. Load the NVM DATA0 register with the new lock bit value.
2. Load the NVM CMD register with the write lock bit command.
The BUSY flag in the NVM STATUS register will be set until the command is finished. The CPU is halted during the
complete execution of the command.
This command can be executed from both the boot loader section and the application section. The EEPROM and flash
page buffers are automatically erased when the lock bits are written.
29.11.3.2 Read Fuses

The read fuses command is used to read the fuses from software.
1. Load the NVM ADDR register with the address of the fuse byte to read.
2. Load the NVM CMD register with the read fuses command.
The result will be available in the NVM DATA0 register. The CPU is halted during the complete execution of the
command.
29.11.4 EEPROM Programming

The EEPROM can be read and written from application code in any part of the flash. Its is both byte and page accessible.
This means that either one byte or one page can be written to the EEPROM at once. One byte is read from the EEPROM
during a read.
29.11.4.1 Addressing the EEPROM

The EEPROM is memory mapped into the data memory space to be accessed similar to SRAM.
For EEPROM page programming, the ADDR register can be treated as having two sections. The least-significant bits
address the bytes within a page, while the most-significant bits address the page within the EEPROM. This is shown in
Figure 29-2 on page 422. The byte address in the page (E2BYTE) is held by the bits [BYTEMSB:0] in the ADDR register.
The remaining bits [PAGEMSB:BYTEMSB+1] in the ADDR register hold the EEPROM page address (E2PAGE).
Together E2BYTE and E2PAGE hold an absolute address to a byte in the EEPROM. The size of E2WORD and E2PAGE
will depend on the page and flash size in the device. Refer to the device datasheet for details on this.
XMEGA E MANUAL 421

Figure 29-2. EEPROM Addressing
BIT PAGEMSB BYTEMSB 0
NVM ADDR E2PAGE E2BYTE
PAGE ADDRESS BYTE ADDRESS

WITHIN THE EEPROM WITHIN A PAGE
E2PAGE EEPROM MEMORY PAGE E2BYTE
00 PAGE DATA BYTE 00
01 01
02 02
E2END E2PAGEEND
Loading a data byte into the EEPROM page buffer can be performed through direct or indirect store instructions. Only the
least-significant bits of the EEPROM address are used to determine locations within the page buffer, but the complete
memory mapped EEPROM address is always required to ensure correct address mapping. Reading from the EEPROM
can be done directly using direct or indirect load instructions. When an EEPROM page buffer load operation is
performed, the CPU is halted for two cycles before the next instruction is executed.
29.11.5 NVM EEPROM Commands

The NVM flash commands that can be used for accessing the EEPROM through the NVM controller are listed in Table
29-4 on page 423.
For self-programming of the EEPROM, the trigger for action-triggered commands is to set the CMDEX bit in the NVM
CTRLA register (CMDEX). The read-triggered command is triggered by reading the NVM DATA0 register (DATA0).
The Change Protected column indicates whether the trigger is protected by the configuration change protection (CCP)
during self-programming or not. CCP is not required for external programming. The last two columns show the address
pointer used for addressing and the source/destination data register.
Section 29.11.5.1 “ Load EEPROM Page Buffer” on page 423 through Section 29.11.5.7 “ Read EEPROM” on page 424
explain in detail the algorithm for each EEPROM operation.
XMEGA E MANUAL 422

Table 29-4. EEPROM Self-programming Commands
CPU Change NVM Address Data

CMD[6:0] Group configuration Description Trigger halted protected busy pointer register
0x00 NO_OPERATION No operation - - - - - -
EEPROM Page Buffer
0x36 ERASE_EEPROM _BUFFER Erase EEPROM page buffer CMDEX N Y Y - -
EEPROM
0x32 ERASE_EEPROM_PAGE Erase EEPROM page CMDEX N Y Y ADDR -
0x34 WRITE_EEPROM_PAGE Write EEPROM page CMDEX N Y Y ADDR -
0x35 ERASE_WRITE_EEPROM_PAGE Erase and write EEPROM page CMDEX N Y Y ADDR -
0x30 ERASE_EEPROM Erase EEPROM CMDEX N Y Y - -
29.11.5.1 Load EEPROM Page Buffer

To load EEPROM page buffer, direct or indirect store instruction must be used and repeated until the arbitrary number of
bytes are loaded into the page buffer.
29.11.5.2 Erase EEPROM Page Buffer

The erase EEPROM page buffer command is used to erase the EEPROM page buffer.
1. Load the NVM CMD register with the erase EEPROM buffer command.
The BUSY flag in the NVM STATUS register will be set until the operation is finished.
29.11.5.3 Erase EEPROM Page

The erase EEPROM page command is used to erase one EEPROM page.
1. Set up the NVM CMD register to the erase EEPROM page command.
2. Load the NVM ADDR register with the address of the EEPROM page to erase.
The page erase commands will only erase the locations that are loaded and tagged in the EEPROM page buffer.
29.11.5.4 Write EEPROM Page

The write EEPROM page command is used to write all locations loaded in the EEPROM page buffer into one page in
EEPROM. Only the locations that are loaded and tagged in the EEPROM page buffer will be written.
1. Load the NVM CMD register with the write EEPROM page command.
2. Load the NVM ADDR register with the address of the EEPROM page to write.
XMEGA E MANUAL 423

29.11.5.5 Erase and Write EEPROM Page
The erase and write EEPROM page command is used to first erase an EEPROM page and then write the EEPROM
page buffer into that page in EEPROM in one atomic operation.
1. Load the NVM CMD register with the erase and write EEPROM page command.
2. Load the NVM ADDR register with the address of the EEPROM page to write.
29.11.5.6 Erase EEPROM

The erase EEPROM command is used to erase all locations in all EEPROM pages that are loaded and tagged in the
EEPROM page buffer.
1. Set up the NVM CMD register to the erase EPPROM command.
29.11.5.7 Read EEPROM

The direct or indirect load command must be used to read one byte from the EEPROM.
29.12 External Programming

External programming is the method for programming code and nonvolatile data into the device from an external
programmer or debugger. This can be done by both in-system or in mass production programming.
For external programming, the device is accessed through the PDI and PDI controller, and using the PDI physical
connection. For details on PDI and how to enable and use the physical interface, refer to “PDI – Program and Debug
Interface” on page 400. The remainder of this section assumes that the correct physical connection to the PDI is enabled.
Doing this all data and program memory spaces are mapped into the linear PDI memory space. Figure 29-3 on page 425
shows the PDI memory space and the base address for each memory space in the device.
XMEGA E MANUAL 424

Figure 29-3. Memory Map for PDI Accessing the Data and Program Memories
TOP=0x1FFFFFF
FLASH_BASE = 0x0800000
EPPROM_BASE = 0x08C0000
FUSE_BASE = 0x08F0020
DATAMEM_BASE = 0x1000000
DATAMEM
16 MB
APP_BASE = FLASH_BASE (mapped IO/SRAM)
BOOT_BASE = FLASH_BASE + SIZE_APPL
PROD_SIGNATURE_BASE = 0x008E0200
USER_SIGNATURE_BASE = 0x008E0400
0x1000000
FUSES
0x08F0020
SIGNATURE ROW
0x08E0200
0x08C1000
EEPROM
0x08C0000
BOOT SECTION
APPLICATION
SECTION
0x0800000 16 MB
0x0000000
1 BYTE
29.12.1 Enabling External Programming Interface

NVM programming from the PDI requires enabling using the following steps:
1. Load the RESET register in the PDI with 0x59.
2. Load the NVM key in the PDI.
3. Poll NVMEN in the PDI status register (PDI STATUS) until NVMEN is set.
When the NVMEN bit in the PDI STATUS register is set, the NVM interface is enabled and active from the PDI.
XMEGA E MANUAL 425

29.12.2 NVM Programming
When the PDI NVM interface is enabled, all memories in the device are memory mapped in the PDI address space. The
PDI controller does not need to access the NVM controller's address or data registers, but the NVM controller must be
loaded with the correct command (i.e., to read from any NVM, the controller must be loaded with the NVM read command
before loading data from the PDIBUS address space). For the reminder of this section, all references to reading and
writing data or program memory addresses from the PDI refer to the memory map shown in Figure 29-3 on page 425.
The PDI uses byte addressing, and hence all memory addresses must be byte addresses. When filling the flash or
EEPROM page buffers, only the least-significant bits of the address are used to determine locations within the page
buffer. Still, the complete memory mapped address for the flash or EEPROM page is required to ensure correct address
mapping.
During programming (page erase and page write) when the NVM is busy, the NVM is blocked for reading.
29.12.3 NVM Commands

The NVM commands that can be used for accessing the NVM memories from external programming are listed in Table
29-5 on page 426. This is a super set of the commands available for self-programming.
For external programming, the trigger for action-triggered commands is to set the CMDEX bit in the NVM CTRLA register
(CMDEX). The read-triggered commands are triggered by a direct or indirect load instruction (LDS or LD) from the PDI
(PDI read). The write-triggered commands are triggered by a direct or indirect store instruction (STS or ST) from the PDI
(PDI write).
Section 29.12.3.1 “ Chip Erase” on page 427 through Section 29.12.3.11 “ Write Fuse / Lock Bit” on page 429 explain in
detail the algorithm for each NVM operation. The commands are protected by the lock bits, and if read and write lock is
set, only the chip erase and flash CRC commands are available.
Table 29-5. NVM Commands Available for External Programming
CMD[6:0] Commands/operation Trigger Change protected NVM busy
0x00 No operation - - -
0x40 Chip erase (1) CMDEX Y Y
0x43 Read NVM PDI read N N
Flash Page Buffer
0x23 Load flash page buffer PDI write N N
0x26 Erase flash page buffer CMDEX Y Y
Flash
0x2B Erase flash page PDI write N Y
0x2E Write flash page PDI write N Y
0x2F Erase and write flash page PDI write N Y
0x78 Flash CRC CMDEX Y Y
Application Section
0x20 Erase application section PDI write N Y
0x22 Erase application section page PDI write N Y
0x24 Write application section page PDI write N Y
0x25 Erase and write application section page PDI write N Y
XMEGA E MANUAL 426

CMD[6:0] Commands/operation Trigger Change protected NVM busy
0x38 Application section CRC CMDEX Y Y
Boot Loader Section
0x68 Erase boot section PDI write N Y
0x2A Erase boot loader section page PDI write N Y
0x2C Write boot loader section page PDI write N Y
0x2D Erase and write boot loader section page PDI write N Y
0x39 Boot loader section CRC CMDEX Y Y
Production Signature (Calibration)(2) and User Signature Sections
0x01 Read user signature row PDI read N N
0x18 Erase user signature row PDI write N Y
0x1A Write user signature row PDI write N Y
0x02 Read calibration row PDI read N N
Fuses and Lock Bits
0x07 Read fuse PDI read N N
0x4C Write fuse PDI write N Y
0x08 Write lock bits PDI write Y Y
EEPROM Page Buffer
0x33 Load EEPROM page buffer PDI write N N
0x36 Erase EEPROM page buffer CMDEX Y Y
EEPROM
0x30 Erase EEPROM PDI write Y Y
0x32 Erase EEPROM page PDI write N Y
0x34 Write EEPROM page PDI write N Y
0x35 Erase and write EEPROM page PDI write N Y
0x06 Read EEPROM PDI read N N

Notes: 1. If the EESAVE fuse is programmed, the EEPROM is preserved during chip erase.
2. For consistency the name Calibration Row has been renamed to Production Signature Row throughout the document.
29.12.3.1 Chip Erase

The chip erase command is used to erase the flash program memory, EEPROM and lock bits. Erasing of the EEPROM
depends on EESAVE fuse setting. Refer to “FUSEBYTE5 – Fuse Byte 5” on page 32 for details. The user signature row,
production signature (calibration) row, and fuses are not affected.
1. Load the NVM CMD register with the chip erase command.
Once this operation starts, the PDI bus between the PDI controller and the NVM is disabled, and the NVMEN bit in the
PDI STATUS register is cleared until the operation is finished. Poll the NVMEN bit until this is set, indicating that the PDI
bus is enabled.
XMEGA E MANUAL 427

29.12.3.2 Read NVM

The read NVM command is used to read the flash, EEPROM, fuses, and signature and production signature (calibration)
row sections.
1. Load the NVM CMD register with the read NVM command.
2. Read the selected memory address by executing a PDI read operation.
Dedicated read EEPROM, read fuse, read signature row and read production signature (calibration) row commands are
also available for the various memory sections. The algorithm for these commands are the same as for the read NVM
command.
29.12.3.3 Erase Page Buffer

The erase flash page buffer and erase EEPROM page buffer commands are used to erase the flash and EEPROM page
buffers.
1. Load the NVM CMD register with the erase flash/EEPROM page buffer command.
2. Set the CMDEX bit in the NVM CTRLA register.
The BUSY flag in the NVM STATUS register will be set until the operation is completed.
29.12.3.4 Load Page Buffer

The load flash page buffer and load EEPROM page buffer commands are used to load one byte of data into the flash and
EEPROM page buffers.
1. Load the NVM CMD register with the load flash/EEPROM page buffer command.
2. Write the selected memory address by doing a PDI write operation.
Since the flash page buffer is word accessed and the PDI uses byte addressing, the PDI must write the flash page buffer
in the correct order. For the write operation, the low byte of the word location must be written before the high byte. The
low byte is then written into the temporary register. The PDI then writes the high byte of the word location, and the low
byte is then written into the word location page buffer in the same clock cycle.
The PDI interface is automatically halted before the next PDI instruction can be executed.
29.12.3.5 Erase Page

The erase application section page, erase boot loader section page, erase user signature row, and erase EEPROM page
commands are used to erase one page in the selected memory space.
1. Load the NVM CMD register with erase application section/boot loader section/user signature row/EEPROM page
command.
29.12.3.6 Write Page

The write application section page, write boot loader section page, write user signature row, and write EEPROM page
commands are used to write a loaded flash/EEPROM page buffer into the selected memory space.
1. Load the NVM CMD register with write application section/boot loader section/user signature row/EEPROM page
command.
2. Write the selected page by doing a PDI write. The page is written by addressing any byte location within the page.
29.12.3.7 Erase and Write Page

The erase and write application section page, erase and write boot loader section page, and erase and write EEPROM
page commands are used to erase one page and then write a loaded flash/EEPROM page buffer into that page in the
selected memory space in one atomic operation.
XMEGA E MANUAL 428

1. Load the NVM CMD register with erase and write application section/boot loader section/user signature
row/EEPROM page command.
2. Write the selected page by doing a PDI write. The page is written by addressing any byte location within the page.
29.12.3.8 Erase Application / Boot Loader/ EEPROM Section

The erase application section, erase boot loader section, and erase EEPROM section commands are used to erase the
complete selected section.
1. Load the NVM CMD register with Erase Application/ Boot/ EEPROM Section command.
2. Write the selected memory section by doing a PDI write operation.
29.12.3.9 Application / Boot Section CRC

The application section CRC and boot loader section CRC commands can be used to verify the content of the selected
section after programming.
1. Load the NVM CMD register with application/ boot loader section CRC command.
The BUSY flag in the NVM STATUS register will be set until the operation is finished. The CRC checksum will be
available in the NVM DATA register.
29.12.3.10 Flash CRC

The flash CRC command can be used to verify the content of the flash program memory after programming. The
command can be executed independently of the lock bit state.
1. Load the NVM CMD register with flash CRC command.
Once this operation starts, the PDI bus between the PDI controller and the NVM is disabled, and the NVMEN bit in the
PDI STATUS register is cleared until the operation is finished. Poll the NVMEN bit until this is set again, indicting the PDI
bus is enabled.
The BUSY flag in the NVM STATUS register will be set until the operation is finished. The CRC checksum will be
available in the NVM DATA register.
29.12.3.11 Write Fuse / Lock Bit

The write fuse and write lock bit commands are used to write the fuses and the lock bits to a more secure setting.
1. Load the NVM CMD register with the write fuse/ lock bit command.
2. Write the selected fuse or lock bits by doing a PDI write operation.
The BUSY flag in the NVM STATUS register will be set until the command is finished.
For lock bit write, the lock bit write command can also be used.

Refer to “Register Description – NVM Controller” on page 26 for a complete register description of the NVM controller.
Refer to “Register Description – PDI Control and Status Registers” on page 409 for a complete register description of the
PDI.

Refer to “Register Summary – NVM Controller” on page 46 for a complete register summary of the NVM controller.
Refer to “Register Summary” on page 410 for a complete register summary of the PDI.
XMEGA E MANUAL 429

30. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA. All peripherals and modules are
not present in all XMEGA devices, refer to device data sheet for the peripherals module address map for a specific
device.
Table 30-1. Peripheral Module Address Map
Base address Name Description Page
0x0000 GPIO General purpose IO registers 42
0x0010 VPORT0 Virtual Port A
0x0014 VPORT1 Virtual Port C

157
0x0018 VPORT2 Virtual Port D
0x001C VPORT3 Virtual Port R
0x0030 CPU CPU 19
0x0040 CLK Clock control 111
0x0048 SLEEP Sleep controller 116
0x0050 OSC Oscillator control 111
0x0060 DFLLRC32M DFLL for the 32 MHz internal RC oscillator 111
0x0070 PR Power reduction 117
0x0078 RST Reset controller 126
0x0080 WDT Watch-dog timer 131
0x0090 MCU MCU control 49
0x00A0 PMIC Programmable multilevel interrupt controller 138
0x00B0 PORTCFG Port configuration 158
0x00D0 CRC CRC module 348
0x0100 EDMA Enhanced DMA controller 75
0x0180 EVSYS Event system 93
0x01C0 NVM Non volatile memory (NVM) controller 46
0x0200 ADCA Analog to digital converter on port A 379
0x0300 DACA Digital to analog converter on port A 390
0x0380 ACA Analog comparator pair on port A 399
0x0400 RTC Real time counter 233
0x0460 XCL XMEGA Custom Logic 337
0x0480 TWIC Two wire interface on port C 260
XMEGA E MANUAL 430

Base address Name Description Page
0x0600 PORTA Port A
0x0640 PORTC Port C

159
0x0660 PORTD Port D
0x07E0 PORTR Port R
0x0800 TCC4 Timer/counter 4 on port C

194
0x0840 TCC5 Timer/counter 5 on port C
0x0880 FAULTC4 Fault Extension on TCC4

224
0x0890 FAULTC5 Fault Extension on TCC5
0x08A0 WEXC Waveform extension on port C 206
0x08B0 HIRESC High resolution extension on port C 208
0x08C0 USARTC0 USART 0 on port C 303
0x08E0 SPIC Serial peripheral interface on port C 278
0x08F8 IRCOM Infrared communication module 307
0x0940 TCD5 Timer/counter 5 on port D 194
0x09C0 USARTD0 USART 0 on port D 303
XMEGA E MANUAL 431

31. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd  Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd  Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd  Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd  Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd  Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd  Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd  Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd  Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd  Rd  Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd  Rd  K Z,N,V,S 1
OR Rd, Rr Logical OR Rd  Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd  Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd  Rd  Rr Z,N,V,S 1
COM Rd One’s Complement Rd  $FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd  $00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd  Rd  ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd  Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd  Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd  Rd  Rd Z,N,V,S 1
CLR Rd Clear Register Rd  Rd  Rd Z,N,V,S 1
SER Rd Set Register Rd  $FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0  Rd x Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0  Rd x Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0  Rd x Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0  Rd x Rr<<1 (UU) Z,C 2
FMULS Rd,Rr Fractional Multiply Signed R1:R0  Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0  Rd x Rr<<1 (SU) Z,C 2
Branch instructions
RJMP k Relative Jump PC  PC + k + 1 None 2
PC(15:0)  Z,
IJMP Indirect Jump to (Z) None 2
PC(21:16)  0
PC(15:0)  Z,
EIJMP Extended Indirect Jump to (Z) None 2
PC(21:16)  EIND
JMP k Jump PC  k None 3
RCALL k Relative Call Subroutine PC  PC + k + 1 None 2 / 3(1)
XMEGA E MANUAL 432

PC(15:0)  Z,
ICALL Indirect Call to (Z) None 2 / 3(1)
PC(21:16)  0
PC(15:0)  Z,
EICALL Extended Indirect Call to (Z) None 3(1)
PC(21:16)  EIND
CALL k call Subroutine PC  k None 3 / 4(1)
RET Subroutine Return PC  STACK None 4 / 5(1)
RETI Interrupt Return PC  STACK I 4 / 5(1)
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC  PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC  PC + 2 or 3 None 1/2/3
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC  PC + 2 or 3 None 2/3/4
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC  PC + 2 or 3 None 2/3/4
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC  PC + k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC  PC + k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1/2
BRLT k Branch if Less Than, Signed if (N  V= 1) then PC  PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC  PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if (I = 0) then PC  PC + k + 1 None 1/2
Data transfer instructions
MOV Rd, Rr Copy Register Rd  Rr None 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd  Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd  K None 1
XMEGA E MANUAL 433

LDS Rd, k Load Direct from data space Rd  (k) None 2(1)(2)
LD Rd, X Load Indirect Rd  (X) None 1(1)(2)
Rd  (X)
LD Rd, X+ Load Indirect and Post-Increment None 1(1)(2)
X  X+1
X  X - 1,  X-1
LD Rd, -X Load Indirect and Pre-Decrement None 2(1)(2)
Rd  (X)  (X)
LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1(1)(2)
Rd  (Y)
LD Rd, Y+ Load Indirect and Post-Increment None 1(1)(2)
Y  Y+1
Y  Y-1
LD Rd, -Y Load Indirect and Pre-Decrement None 2(1)(2)
Rd  (Y)
LDD Rd, Y+q Load Indirect with Displacement Rd  (Y + q) None 2(1)(2)
LD Rd, Z Load Indirect Rd  (Z) None 1(1)(2)
Rd  (Z),
LD Rd, Z+ Load Indirect and Post-Increment None 1(1)(2)
Z  Z+1
Z  Z - 1,
LD Rd, -Z Load Indirect and Pre-Decrement None 2(1)(2)
Rd  (Z)
LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2(1)(2)
STS k, Rr Store Direct to Data Space (k)  Rd None 2(1)
ST X, Rr Store Indirect (X)  Rr None 1(1)
(X)  Rr,
ST X+, Rr Store Indirect and Post-Increment None 1(1)
X  X+1
X  X - 1,
ST -X, Rr Store Indirect and Pre-Decrement None 2(1)
(X)  Rr
ST Y, Rr Store Indirect (Y)  Rr None 1(1)
(Y)  Rr,
ST Y+, Rr Store Indirect and Post-Increment None 1(1)
Y  Y+1
Y  Y - 1,
ST -Y, Rr Store Indirect and Pre-Decrement None 2(1)
(Y)  Rr
STD Y+q, Rr Store Indirect with Displacement (Y + q)  Rr None 2(1)
ST Z, Rr Store Indirect (Z)  Rr None 1(1)
(Z)  Rr
ST Z+, Rr Store Indirect and Post-Increment None 1(1)
Z  Z+1
ST -Z, Rr Store Indirect and Pre-Decrement Z  Z-1 None 2(1)
STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2(1)
LPM Load Program Memory R0  (Z) None 3
LPM Rd, Z Load Program Memory Rd  (Z) None 3
Rd  (Z),
LPM Rd, Z+ Load Program Memory and Post-Increment None 3
Z  Z+1
ELPM Extended Load Program Memory R0  (RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd  (RAMPZ:Z) None 3
Extended Load Program Memory and Post- Rd  (RAMPZ:Z),

ELPM Rd, Z+ None 3
Increment Z  Z+1
SPM Store Program Memory (RAMPZ:Z)  R1:R0 None -
XMEGA E MANUAL 434

(RAMPZ:Z)  R1:R0,
SPM Z+ Store Program Memory and Post-Increment by 2 None -
Z  Z+2
IN Rd, A In From I/O Location Rd  I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A)  Rr None 1
PUSH Rr Push Register on Stack STACK  Rr None 1(1)
POP Rd Pop Register from Stack Rd  STACK None 2(1)
Temp  Rd,
XCH Z, Rd Exchange RAM location Rd  (Z), None 2
(Z)  Temp
Temp  Rd,
LAS Z, Rd Load and Set RAM location Rd  (Z), None 2
(Z)  Temp v (Z)
Temp  Rd,
LAC Z, Rd Load and Clear RAM location Rd  (Z), None 2
(Z)  ($FFh – Rd)  (Z)
Temp  Rd,
LAT Z, Rd Load and Toggle RAM location Rd  (Z), None 2
(Z)  Temp  (Z)
Bit and bit-test instructions
Rd(n+1)  Rd(n),
LSL Rd Logical Shift Left Rd(0)  0, Z,C,N,V,H 1
C  Rd(7)
Rd(n)  Rd(n+1),
LSR Rd Logical Shift Right Rd(7)  0, Z,C,N,V 1
C  Rd(0)
Rd(0)  C,
ROL Rd Rotate Left Through Carry Rd(n+1)  Rd(n), Z,C,N,V,H 1
C  Rd(7)
Rd(7)  C,
ROR Rd Rotate Right Through Carry Rd(n)  Rd(n+1), Z,C,N,V 1
C  Rd(0)
ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)  Rd(7..4) None 1
BSET s Flag Set SREG(s)  1 SREG(s) 1
BCLR s Flag Clear SREG(s)  0 SREG(s) 1
SBI A, b Set Bit in I/O Register I/O(A, b)  1 None 1
CBI A, b Clear Bit in I/O Register I/O(A, b)  0 None 1
BST Rr, b Bit Store from Register to T T  Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b)  T None 1
SEC Set Carry C  1 C 1
CLC Clear Carry C  0 C 1
SEN Set Negative Flag N  1 N 1
CLN Clear Negative Flag N  0 N 1
SEZ Set Zero Flag Z  1 Z 1
CLZ Clear Zero Flag Z  0 Z 1
SEI Global Interrupt Enable I  1 I 1
XMEGA E MANUAL 435

CLI Global Interrupt Disable I  0 I 1
SES Set Signed Test Flag S  1 S 1
CLS Clear Signed Test Flag S  0 S 1
SEV Set Two’s Complement Overflow V  1 V 1
CLV Clear Two’s Complement Overflow V  0 V 1
SET Set T in SREG T  1 T 1
CLT Clear T in SREG T  0 T 1
SEH Set Half Carry Flag in SREG H  1 H 1
CLH Clear Half Carry Flag in SREG H  0 H 1
MCU control instructions
BREAK Break (See specific descr. for BREAK) None 1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep) None 1
WDR Watchdog Reset (see specific descr. for WDR) None 1
Notes: 1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
XMEGA E MANUAL 436

32. Revision History
Note that the referring page numbers in this section are referring to this document. The referring revision in this section
are referring to the document revision.
32.1 42005E – 11/2014

1. Changed NVMAA to CMDEX and changed Write lock bits and Erase EEPROM to “PDI write” in Table 29-5 on page
426.
2. Changed text in point 2 in Section 29.12.3.8 on page 429.
3. Changed NVMEX to CMDEX in Section 29. “Memory Programming” on page 411.
4. Added note on initial value for production signature rows in Section 4.15 “Register Description – Production
Signature Row” on page 36.
5. Chapter “TWI SMBUS L1 Compliance” has been added.
32.2 42005D – 08/2014

1. Changed footnote in Table 13-8 on page 176.
2. In Table 12-7 on page 154 the value for RTCOUT[1:0] on the last line has been changed from 1x to 11.
3. In Table 12-9 on page 155 PORTE in the last line has been changed to PORTR (there is no PORTE in XMEGA E
devices).
4. Removed information on CALH register.
5. Changed Vcc to AVcc in the section“AC – Analog Comparator” on page 391 and onwards, and in “Voltage Reference
Selection” on page 353.
6. Changed footnote text from BCT0 toBTC0 and BCT1 to BTC1 in tables in Section 23.7 “Register Description” on
page 325.
7. Added footnote on AVcc and Vcc power supply to Table 2-1 on page 4.
7. Updated footer and last page according to new template.
XMEGA E MANUAL 437

32.3 42005C – 08/2013
1. ADC:
 “Optional gain” replaced with “Programmable gain” in:
 “Features” on page 349, “Overview” on page 349, “Input Sources” on page 350
 Headings of Table 25-15, Table 25-16 and Table 25-17
 “Differential Inputs” on page 350 updated
 “Single-ended Input” on page 351 updated
 “Internal Inputs” on page 352 updated
 “Single Conversion with 1x Gain” on page 360: Heading updated from saying “Single conversion
without gain”
 “Single Conversion with Various Gain Settings” on page 360: Heading updated from saying “Single
conversion with gain”
2. DAC register and bit updates:

“CH0GAINCAL – Gain Calibration Register” on page 386: Removed “+0x0A” address.
“CH0OFFSETCAL – Offset Calibration Register” on page 386: Corrected name of Bit 7:0 to CH0OFFSETCAL[7:0].
“CH1GAINCAL – Gain Calibration Register” on page 387: Corrected name of Bit 7:0 to CH1GAINCAL[7:0].
32.4 42005B – 04/2013

1. Updated “ADC Clock and Conversion Timing” on page 359.
32.5 42005A – 04/2013

1. Initial revision.
XMEGA E MANUAL 438

Table of Contents
1. About the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 Reading the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Atmel AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.9 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.10 RAMP and Extended Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.11 Accessing 16-bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.12 Configuration Change Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.13 Fuse Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.14 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.15 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Fuses and Lockbits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6 Internal SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.8 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.9 Data Memory and Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.10 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.11 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.12 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.13 Register Description – NVM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.14 Register Descriptions – Fuses and Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.15 Register Description – Production Signature Row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.16 Register Description – General Purpose I/O Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.17 Register Descriptions – MCU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.18 Register Summary – NVM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.19 Register Summary – Fuses and Lockbits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.20 Register Summary – Production Signature Row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.21 Register Summary – General Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.22 Register Summary – MCU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.23 Interrupt Vector Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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5. EDMA – Enhanced Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3 EDMA Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4 Transfer Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.5 Addressing and Transfer Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.6 Priority Between Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.7 Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.8 Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.9 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.11 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.13 Register Description – EDMA Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.14 Register Description – Peripheral Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.15 Register Description – Standard Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.16 Register Summary – EDMA Controller in PER0123 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.17 Register Summary – EDMA Controller in STD0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.18 Register Summary – EDMA Controller in STD2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.19 Register Summary – EDMA Controller in STD02 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.20 Register Summary – EDMA Peripheral Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.21 Register Summary – EDMA Standard Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.22 Interrupt Vector Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.4 Signalling Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.5 Data Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.6 Peripheral Clock Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.7 Software Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.8 Event Routing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.9 Event Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.10 Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.11 Quadrature Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.12 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.13 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7. System Clock and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.3 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.4 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.5 System Clock Selection and Prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.6 PLL with 1x-31x Multiplication Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.7 DFLL 32MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.8 PLL and External Clock Source Failure Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.9 Register Description – Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.10 Register Description – Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.11 Register Description – DFLL32M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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7.12 Register Summary - Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.13 Register Summary - Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.14 Register Summary – DFLL32M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.15 Interrupt Vector Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.3 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.4 Power Reduction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.5 Minimizing Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.6 Register Description – Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.7 Register Description – Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8.8 Register Summary – Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.9 Register Summary – Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9. Reset System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.6 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.3 Normal Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.4 Window Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10.5 Watchdog Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10.6 Configuration Protection and Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11. PMIC – Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . 132

11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.5 Interrupt Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11.6 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
11.7 Interrupt Vector Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.3 I/O Pin use and Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.4 Reading the Pin Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.5 Input Sense Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.6 Port Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
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12.7 Port Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.8 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.9 Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10 Clock and Event Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.11 Multi-pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.12 Virtual Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.13 Register Descriptions – Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.14 Register Descriptions – Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.15 Register Descriptions – Virtual Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.16 Register Summary – Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.17 Register Summary – Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.18 Register Summary – Virtual Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.19 Interrupt Vector Summary – Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
13. TC4/5 – 16-bit Timer/Counter Type 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
13.4 Clock and Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.5 Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.6 Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.7 Capture Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.8 Compare Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.9 Interrupts and Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.10 EDMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.11 Timer/Counter Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13.12 Register Description – Standard Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.13 Register Description – Byte Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.14 Register Summary – Standard Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.15 Interrupt Vector Summary – Standard Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
13.16 Register Summary – Byte Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.17 Interrupt Vector Summary – Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14. WeX – Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.3 Port Override. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
14.4 Output Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
14.5 Dead-time Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
14.6 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.7 Change Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
15. Hi-Res – High-Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
16. Fault Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
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16.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
16.3 Timer/counter Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
16.4 Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
17. RTC – Real Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
17.3 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
17.5 Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
18. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
18.3 General TWI Bus Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
18.4 TWI Bus State Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
18.5 TWI Master Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
18.6 TWI Slave Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
18.7 Enabling External Driver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
18.8 Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
18.9 SMBUS L1 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
18.10 Register Description – TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
18.11 Register Description – TWI master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
18.12 Register Description – TWI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
18.13 Register Description – TWI Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
18.14 Register Summary - TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.15 Register Summary - TWI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.16 Register Summary - TWI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.17 Register Summary – TWI Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
19. TWI SMBUS L1 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
19.2 TWI SMBUS L1 Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
19.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
19.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
19.5 Register Description – TWI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
19.6 Register Description – TWI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
19.7 Register Description – TWI Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
19.8 Register Summary – TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
19.9 Register Summary – TWI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
19.10 Register Summary – TWI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
19.11 Register Summary – TWI Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
20. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
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20.3 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
20.4 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
20.5 Buffer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
20.6 Data Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
20.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
20.8 EDMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
21. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
21.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
21.3 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
21.4 Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
21.5 USART Full-duplex Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
21.6 USART One-wire Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
21.7 Data Transmission - The USART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
21.8 Data Reception - The USART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
21.9 Asynchronous Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
21.10 Fractional Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
21.11 USART in Master SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
21.12 USART SPI vs. SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
21.13 Multiprocessor Communication Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
21.14 One-wire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
21.15 Data Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
21.16 IRCOM Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
21.17 EDMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
21.20 Interrupt Vector Summary – USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
22. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
22.3 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
23. XCL – XMEGA Custom Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
23.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
23.3 Timer/counter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
23.4 Timer/counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
23.5 Glue Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
23.10 T/C and PEC Register Summary vs. Configuration and Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
24. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
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24.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
24.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
24.4 CRC on Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
24.5 CRC on EDMA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
24.6 CRC using the I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
25. ADC – Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
25.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
25.3 Input Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
25.4 Sampling Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
25.5 Voltage Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
25.6 Conversion Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
25.7 Calibration and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
25.8 Starting a Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
25.9 ADC Clock and Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
25.10 ADC Input Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
25.11 EDMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
25.13 Synchronous Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
25.14 Register Description – ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
25.15 Register Description - ADC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
25.16 Register Summary – ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
25.17 Register Summary – ADC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
26. DAC – Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
26.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
26.3 Voltage Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
26.4 Starting a Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
26.5 Output and Output Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
26.6 DAC Output Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
26.7 DAC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
26.8 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
26.9 Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
27. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
27.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
27.3 Input Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
27.4 Signal Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
27.6 Window Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
27.7 Input Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
XMEGA E MANUAL vii

28. PDI – Program and Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
28.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
28.3 PDI Physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
28.4 PDI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
28.5 Register Description – PDI Instruction and Addressing Registers . . . . . . . . . . . . . . . . . . . . . . . . . 407
28.6 Register Description – PDI Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
29. Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
29.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
29.3 NVM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
29.4 NVM Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
29.5 NVM Controller Busy Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
29.6 Flash and EEPROM Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
29.7 Flash and EEPROM Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
29.8 Protection of NVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
29.9 Preventing NVM Corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
29.10 CRC Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
29.11 Self-programming and Boot Loader Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
29.12 External Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
30. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

31. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
32. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
32.1 42005E – 11/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
32.2 42005D – 08/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
32.3 42005C – 08/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
32.4 42005B – 04/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
32.5 42005A – 04/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
XMEGA E MANUAL viii

XXXXXX
Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2014 Atmel Corporation. / Rev.: Atmel-8201E-AVR-XMEGA E Manual_11/2014.
Atmel®, Atmel logo and combinations thereof, AVR®, Enabling Unlimited Possibilities®, QTouch®, XMEGA®, and others are registered trademarks or trademarks of
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8/16-bit Atmel AVR XMEGA Microcontrollers

1.1 Reading the Manual

1.3 Recommended Reading

Figure 2-1. XMEGA E Block Diagram

PR[0..1] Power Programming, debug, test

PORT R (2) Oscillator

DATA BUS Watchdog

Event System Oscillator

USARTD0 DATA BUS

EVENT ROUTING NETWORK

Table 2-1. XMEGA E Feature Summary Overview

Feature Details / sub-family E5

Program memory (KB) 8 - 32

Boot memory (KB) 2-4

Memory SRAM (KB) 1-4

EEPROM (Bytes) 512

General purpose registers 4

QTouch® Sense channels 56

EDMA Controller Channels 4

Event System QDEC 1

0.4 - 16MHz XOSC Yes

8MHz calibrated Yes

32MHz calibrated Yes

Internal Oscillator 128MHz PLL Yes

32.768kHz calibrated Yes

32kHz ULP Yes

XMEGA Custom Logic BTC1 - 8-bit, 1 CC 1

LUT, 2-input, one output 2

Oversampling extra resolution (bits) 4

Sampling speed (kbps) 300

Offset/gain error correction Yes

Averaging (samples) 1 - 1024

Output channels per DAC 2

Analog Comparator (AC) 2

Program and Debug Interface (PDI) PDI Yes

3.3 Architectural Overview

Figure 3-1. Block Diagram of the AVR CPU Architecture

3.4 ALU - Arithmetic Logic Unit

3.4.1 Hardware Multiplier

3.6 Instruction Execution Timing

Figure 3-2. The Parallel Instruction Fetches and Instruction Executions

1st Instruction Fetch

2nd Instruction Execute

Figure 3-3. Single Cycle ALU Operation

Register Operands Fetch

ALU Operation Execute

Result Write Back

3.8 Stack and Stack Pointer

3.9 Register File

3.9.1 The X-, Y-, and Z-registers

Figure 3-5. The X-, Y-, and Z-registers

Bit (individually) 7 R27 0 7 R26 0

Bit (individually) 7 R29 0 7 R28 0

Bit (individually) 7 R31 0 7 R30 0

3.10.1 RAMPX, RAMPY, and RAMPZ Registers

Figure 3-6. The Combined RAMPX + X, RAMPY + Y, and RAMPZ + Z Registers

3.10.2 RAMPD Register

Figure 3-7. The Combined RAMPD + K Register

3.10.3 EIND - Extended Indirect Register

Figure 3-8. The Combined EIND + Z Register