Basic Verilog Coding &

Sequential Logic

謝東佑
國立中山大學電機系

Office: F7038
07-5252000 Ext. 4114
[email protected]
PDSD Unit6-1 NSYSUEE-TYHSIEH
 Objective, Outline &
Application
 Objective
 Understand how to design a sequential
circuit using Verilog
 Outline
 Basics of sequential circuits
 Models for designing sequential circuits
design
 Applications
 Homework assignment
 Project

PDSD Unit6-2 NSYSUEE-TYHSIEH

 Sequential Circuits
 Combinational circuits
 Contain no memory elements.
 The outputs entirely depends on the current inputs.
 Sequential circuits
 Consist of a combinational circuit to which storage
elements are connected to form a feedback path
 The binary information stored in the storage elements at any
given time defines the state of the sequential circuit.
 The outputs are a function of the external inputs and the
present state of the sequential circuit.

PDSD Unit6-3 NSYSUEE-TYHSIEH

 Synchronous Sequential
Circuit
 Synchronization is achieved by a timing device called a
clock generator
 Provide a clock signal having the form of a periodic train of
clock pulses
 The activity within the circuit and the resulting updating
of stored values is synchronized to the occurrence of
clock pulses.
 The memory elements commonly used are flip-flops.

PDSD Unit6-4 NSYSUEE-TYHSIEH

 Timing Specification
 The period of the clock of a synchronous sequential circuit
must be long enough.
 To allow all transients activated by a transition of the clock to
settle at the outputs of the next-state combinational logic
before the next active edge occurs.
 The inputs to the state register’s flip-flops must remain stable
for a sufficient interval before and after the active edge of the
clock. (setup-time and hold-time constraints)
 This defines a minimum cycle time (period) of the clock.

PDSD Unit6-5 NSYSUEE-TYHSIEH

 Timing Check in Verilog
 Setup-time check
 $setup(data_event, reference_event, limit);
 Hold-time check
 $hold (reference_event, data_event, limit);

//Setup check is set. //Hold check is set.

//clock is the reference //clock is the reference
//data is being checked for violations //data is being checked for violations
/*Violation reported if /* Violation reported if
Tposedge_clk-Tdata < 3*/ Tdata - Tposedge_clk < 5 */

specify specify
$setup(data, posedge clock, 3); $hold(posedge clock, data, 5);
endspecify endspecify
PDSD Unit6-6 NSYSUEE-TYHSIEH
 Verilog RTL Coding for
Sequential Logic
 Non-blocking assignments are usually
used.
 Allow scheduling of assignments without
blocking execution of the statements that
follow in a sequential block
 Can model several concurrent data transfers
that take place after a common event
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1; //The old value of reg1
end
PDSD Unit6-7 NSYSUEE-TYHSIEH
 Concurrent Data Transfer
always @(posedge clock)
always @(posedge clock) a<=b;
a=b; always @(posedge clock)
always @(posedge clock) b<=a;
b=a;
always @(posedge clock)
begin
The race condition occur. The temp_a = a;
result depends on the temp_b = b;
simulation process. a = temp_b;
b = temp_a;
end

The race condition is

eliminated. The values can be
correctly swapped.
PDSD Unit6-8 NSYSUEE-TYHSIEH
 Flip-Flop

 Synchronous reset  Asynchronous reset

module D_FF (Q,D,Clk,Rst); module D_FF (Q,D,Clk,Rst);

output Q; output Q;
input D,Clk,Rst; input D,Clk,Rst;
reg Q; reg Q;
always @ (posedge Clk) always @ (posedge Clk or
if (~Rst) Q<=0; negedge Rst)
else Q<=D; if (~Rst) Q<=0;
endmodule else Q<=D;
endmodule

PDSD Unit6-9 NSYSUEE-TYHSIEH

 Register
module register(Q,D,Clk, Rst, Set);
output[7:0] Q;
input[7:0] D;
input Clk,Rst,Set;
reg[7:0] Q;
always @(posedge Clk or negedge Rst or negedge Set)
if(~ Rst)
Q<=0;
else if(~Set)
Q<=8′b1111_1111;
else
Q<=D;
endmodule

PDSD Unit6-10 NSYSUEE-TYHSIEH

 D Latch
 D_latch
always @(enable or data)
if(enable)
q<=data;

 D_latch with asynchronous reset

always @(data or enable or reset)
if (reset)
q<=1′b0;
else if(enable)
q<=data;

PDSD Unit6-11 NSYSUEE-TYHSIEH

 Synchronous Counter
module bcd_count(count,ripple_out,clr,clk); //0-9 Counter
output [3:0] count;
output ripple_out;
reg [3:0] count;
input clr,clk;
wire ripple_out=(count==4′b1001)?1:0; //combinational
always @(posedge clk or posedge clr) //sequential
if(clr)
count<=0;
else if(count==4′b1001)
count<=0;
else
count<=count+1;
endmodule

PDSD Unit6-12 NSYSUEE-TYHSIEH

 Four-Bit Up/Down Binary
Counter
 The counter can count up or count down.
module bcd_count(count,ripple_out,clr,clk);
output [3:0] count;
output ripple_out;
reg [3:0] count;
input clr,clk;
// additional input control signal declaration
wire ripple_out=(count==4′b1001)?1:0;
always @(posedge clk or posedge clr)
if(clr)
count<=0;
else if(count==4′b1001)
count<=0;
else // need some modification (?)
count<=count+1;
endmodule
PDSD Unit6-13 NSYSUEE-TYHSIEH
 Four-Bit Binary Counter with
Parallel Load
 The content of the counter can be arbitrarily
specified.
module bcd_count(count,ripple_out,clr,clk);
output [3:0] count;
output ripple_out;
reg [3:0] count;
input clr,clk;
// additional input data/control signal declaration
wire ripple_out=(count==4′b1001)?0:1;
always @(posedge clk or posedge clr)
if(clr)
count<=0;
else if(count==4′b1001)
count<=0;
else // need some modification (?)
count<=count+1;
endmodule
PDSD Unit6-14 NSYSUEE-TYHSIEH
 Inefficient Description
module count(clock,reset,and_bits,or_bits,xor_bits);
input clock,reset;
output and_bits,or_bits,xor_bits;
reg and_bits,or_bits,xor_bits;
reg [2:0] count;
always @(posedge clock) begin
if(reset)
count=0;
else
count=count+1;
and_bits=&count;
or_bits=|count;
xor_bits=^count;
end
endmodule
PDSD Unit6-15 NSYSUEE-TYHSIEH
 Six Implied Flip-Flops

PDSD Unit6-16 NSYSUEE-TYHSIEH

 Efficient Description
 Separate combinational and sequential
descriptions
module count (clock,reset, and_bits,or_bits,xor_bits);
input clock,reset;
output and_bits,or_bits,xor_bits;
reg and_bits,or_bits,xor_bits, [2:0] count;
// registers
always @ (posedge clock) begin
if(reset) count<=0;
else count<=count+1;
end
// combinational circuits
always @ (count) begin
and_bits=&count;
or_bits=|count;
xor_bits=^count;
end
endmodule
PDSD Unit6-17 NSYSUEE-TYHSIEH
 Three Flip-Flops Are Used

SET
D Q

SET
D Q LCLR Q

LCLR Q
SET
D Q

LCLR Q

PDSD Unit6-18 NSYSUEE-TYHSIEH

 Shifter
module shifter(so,si,d,clk,ld_,clr_);
output so;
input [7:0] d;
input si,clk,ld_,clr_; //asynchronous clear & synchronous load
reg [7:0] q;
assign so = q[7];
always @ (posedge clk or negedge clr_)
if(~clr_) ld_ d
q<=0;
else if (~ld_)
q<=d;
si shifter so
else
q[7:0]<={q[6:0],si}; clk
endmodule
PDSD Unit6-19 NSYSUEE-TYHSIEH
 Memory

 A memory in Verilog is declared as a

one-dimensional array of registers.
 reg [31:0] MEM [0:1023]; //1K x 32-bit memory
array
 reg [7:0] PREP [`hFFFC:`hFFFF]; // 4x8-bit
memory array
 reg [0:wordsize-1] MEM3 [memsize-1:0]; //
Memory array declared using parameters

 MEM [511] // access a memory element

PDSD Unit6-20 NSYSUEE-TYHSIEH

 Parameters
 Use parameters to declare RUN-TIME
constants.
 Syntax: parameter <list-of-assignments>
module module1 (c, a, b);
…
parameter length=15,
real_const=3.14,
x_word=16`bx;
…
wire [length:0] w1;
…
endmodule

PDSD Unit6-21 NSYSUEE-TYHSIEH

 Overriding the Value of
Parameters
 defparam statement

module module1 (c, a, b); module module2;

… …
parameter length=15, module1 m1 (c, a, b);
real_const=3.14, …
x_word=16’bx; defparam
… m1.length=8,
wire [length:0] w1; m1.real_const=2.14;
… …
endmodule endmodule

PDSD Unit6-22 NSYSUEE-TYHSIEH

 Overriding the Value of
Parameters (cont.)
 Module Instance Parameter Value Assignment
 Parameter values can be assigned new values within a
module instance using the “#” character.
 The order of assignment of the parameters follows the order
of declaration of parameters in the module.
 It is not necessary to assign new values to all parameters,
but it is not allowed to skip over a parameter.

module module2;
module module1 (c, a, b); …
… module1 #(8, 2.14) m1 (c, a, b);
parameter length=15, /* length=8
real_const=3.14, real_const=2.14
x_word=16’bx; x_word=16’bx */
… module1 #(.real_const (2.14), .x_word
wire [length:0] w1; (8’bx)) m2 (c, a, b);
… …
endmodule endmodule
PDSD Unit6-23 NSYSUEE-TYHSIEH
 Initialize A Memory
 Assigning values to each word of the
memory array.
 Call $readmemb or $readmemh system
task
 $readmemb("<file_name>",
<memory_name>);
 $readmemb("<file_name>", <memory_name>,
<start_addr>);
 $readmemb("<file_name>", <memory_name>,
<start_addr>,<finish_addr>);
 Identical syntax for $readmemh

PDSD Unit6-24 NSYSUEE-TYHSIEH

 Example of Loading A
Memory
module test;
reg [7:0] memory[0:7]; //declare an 8-byte memory
integer i;
initial
begin
$readmemb("init.dat", memory); Memory [0] = xxxxxxxx
for(i=0; i < 8; i = i + 1) Memory [1] = xxxxxxxx
$display("Memory [%d] = %b", i, memory[i]); Memory [2] = 11111111
end Memory [3] = 01010101
endmodule Memory [4] = 00000000
Memory [5] = 10101010
Content of init.dat
Memory [6] = 1111zzzz
@002 /* Addresses are specified as
Memory [7] = 00001111
hexadecimal numbers */
11111111 01010101
00000000 10101010
@006
1111zzzz 00001111 /*Data can contain x or z.
Uninitialized locations default to x. */
PDSD Unit6-25 NSYSUEE-TYHSIEH
 Another Example of Loading
A Memory

Content of init.dat
0000_0000
0110_0001 0011_0010
//addresses 3-255 are not defined
@100
1111_1100
//addresses 257-1022 are not defined
@3FF
1110_0010

PDSD Unit6-26 NSYSUEE-TYHSIEH

 Pipelines for Performance
Enhancement
10ns 10ns Cycle C1 C2
In,…, I2, I1 C1 C2 1 I 1 I1
Dff Dff
2 I 2 I2
clk
(non-pipelined) 3 I 3 I3
Total: (20ns)x3=60ns
10ns 10ns Cycle C1 C2
In,…, I2, I1 Dff C1 Dff C2 Dff 1 I1
2 I 2 I1
clk
(pipelined) 3 I 3 I2
• An example 4 I3
Total: (10ns)x4=40ns
assign n_sum=a+b;
assign p=sum*d_c;
always @(posedge clk) begin
sum <= n_sum;
out <= p;
d_c <= c;
end

PDSD Unit6-27 NSYSUEE-TYHSIEH

 Finite State Machine (FSM)
 Moore model: The output is a function of only the present
state.

 Mealy model: The output is a function of both the present

state and the input.

PDSD Unit6-28 NSYSUEE-TYHSIEH

 An FSM Example of Traffic
Light Controller

Farmroad

HL FL

Highway

Highway

HL
FL
Farmroad

PDSD Unit6-29 NSYSUEE-TYHSIEH

 Traffic Light Controller
Specifications
Input Signals Description State Transition Diagram
reset place FSM in initial state of the controller (mealy
C detect vehicle on farmroad
meachine)
TS short time interval expired
TL long time interval expired
state
Output Signals Description input output
HG,HY,HR assert green/yellow/red highway light
FG,FY,FR assert green/yellow/red farmroad light
ST start timing for a short or long interval

States Description
S0 HG Highway green (farmroad red)
S1 HY Highway yellow (farmroad red)
S2 FG Farmroad green (highway red)
S3 FY Farmroad yellow (highway red)

PDSD Unit6-30 NSYSUEE-TYHSIEH

 Verilog Description
module traffic_light(HG,HY,HR,FG,FY,FR,ST_out,tl,ts,clk,reset,c);
output HG,HY,HR,FG,FY,FR,ST_out;
input TL,TS,clk,reset,C;
reg ST_out,ST; // Start timer, similar to state and next_state
reg[0:1] state,next_state;

parameter S0=2’b00,S1=2’b01,S2=2’b10,S3=2’b11;
assign HG=(state==S0);
assign HY=(state==S1);
assign HR=((state==S2)||(state==S3));
assign FG=(state==S2);
assign FY=(state==S3);
assign FR=((state==S0)||(state==S1));

// flip-flops
always @(posedge clk or posedge reset)
if(reset) // an asynchronous reset
begin
state<=S0;
ST_out<=0;
end
else begin
state<=next_state;
ST_out<=ST;
end
PDSD Unit6-31 NSYSUEE-TYHSIEH
 Verilog Description (cont.)
// Combinational circuit
always @(state or c or tl or ts)

case(state) // state transition

S0:if(TL&C) begin
next_state=S1;
ST=1;
end
else begin
next_state=S0;
ST=0;
end
S1:if(TS) begin
next_state=S2;
ST=1;
end
else begin
next_state=S1;
ST=0;
PDSD end Unit6-32 NSYSUEE-TYHSIEH
 Verilog Description (cont.)
S2:if(TL|!C) begin
next_state=S3;
ST=1;
end
else begin
next_state=S2;
ST=0;
end
S3:if(TS) begin
next_state=S0;
ST=1;
end
else begin
next_state=S3;
ST=0;
end
endcase
endmodule

PDSD Unit6-33 NSYSUEE-TYHSIEH

 Example Testbench for
Traffic Controller
module tb_traffic_light; initial begin
reg tl,ts, clk,reset,c; #20 reset=1'b1;
wire HG,HY,HR,FG,FY,FR, ST_out; #40 reset=1'b0;
#100 c=1'b1;
#800 c=1'b0;
traffic_light TL (HG,HY,HR,FG,FY,FR, ST_out, tl,ts, #400 $finish;
clk,reset,c) end
always begin
initial begin #30 ts=1'b1;
clk=1'b0; #20;
ts=1'b0;
reset=1'b0; end
tl=1'b0; always begin
ts=1'b0; #70 tl=1'b1;
c=1'b0; #20;
end tl=1'b0;
end
always begin
#10 clk=~clk; initial begin
end $dumpfile("traffic_light.vcd");
$dumpvars;
end
endmodule

PDSD Unit6-34 NSYSUEE-TYHSIEH

 Simulation Results

PDSD Unit6-35 NSYSUEE-TYHSIEH

 Moore Machine Example
 The output is included under a slash below the
state in a circle of the state transition diagram.

state input output

PDSD Unit6-36 NSYSUEE-TYHSIEH

 Summary

 Concepts of a sequential circuit

 Sequential memory elements
 Synchronous counter
 Shifter
 Memory
 Pipelined design modeling
 Finite state machine
PDSD Unit6-37 NSYSUEE-TYHSIEH