ECE 218A Lab 3 Report

1.6GHz Low Noise Amplifier

Pen-Chin Pan
(6064612)

Luis Chen
(5977160)

December 5, 2005

0
 Introduction
Narrow band tuned Low-Noise Amplifiers are commonly used in wireless
communication front-ends due to its amplification with low noise performance. It is
commonly known that in a receiver system, the first stages within a receiving chain need
to provide substantial gain and low noise figure in order for the entire system to have
adequate noise performance. Designing and building a 1.6GHz LNA requires
investigation into both in-band and out of band stability analysis, bilateral gain and noise
match with microstrip matching network, DC bias design, and finally PCB parasitic
modeling.

Approach:
Upon receiving the specifications, we first evaluate the small-signal model of
NE34018 in ADS in terms of stability, gain circles, and noise circles. After determining
good bilateral matching impedance, we designed a shut-series microstrip lossless
matching network. Then we design the active bias circuit and test the amplifier design
with NE34018’s large-signal model with added PCB parasitics (component and via
holes) for full evaluation.

Specification:
Goal Accomplishment
Gain > 15dB 15.23dB
Bandwidth (3 dB) > 100MHz 439MHz
|S22| < -10dB @ 1.6GHz -13.1dB @ 1.6GHz
Noise Figure < 1.6dB 1.88dB
Power Supply +3.5V, -2.5V +3.5V, -2.5V
Vds 2V 1.96V
Id 10mA 10.36mA
S-parameter Measurement vs. Simulation
20 m1
m6
m1 f req=1.608GHz
m7 m8 dB(S(2,1))=15.232
S21 m6
10 f req=1.600GHz
dB(large_signal_bias..SP1.SP.S(2,1))=16.498

0 S11
m3
dB(large_signal_bias..SP1.SP.S(2,2))
dB(large_signal_bias..SP1.SP.S(2,1))
dB(large_signal_bias..SP1.SP.S(1,1))

f req=1.608GHz
m5 dB(S(2,2))=-13.093
m2 m4
-10 m3 f req=1.600GHz
dB(S(2,2))
dB(S(2,1))
dB(S(1,1))

dB(large_signal_bias..SP1.SP.S(2,2))=-18.481
m4
S22
-20
m2
f req=1.608GHz
dB(S(1,1))=-10.959
-30 m5
f req=1.600GHz
dB(large_signal_bias..SP1.SP.S(1,1))=-8.860

-40 m8
f req=1.749GHz
dB(S(2,1))=13.274
3dB BW = ~400MHz
m7
-50 f req=1.398GHz
1E8 1E9 5E9
dB(S(2,1))=13.637

freq, Hz 1
Design Procedure
Stability Evaluation:

We observe that the transistor is

unstable at frequencies below 4.5GHz
(K < 1). From the Load stability circle,
we could calculated the required
stabilizing resistor value

2
By picking a constant conductance point at the Load stability circle, we could derive a
load-side shunt stabilizing resistor of 60 Ohm using smith chart.

After placing the load-side shunt

stabilizing resistor (60Ohm), we could
see the circuit is stable above 1.6GHz.
However, there remains some
instability at lower frequencies, which
would require low-frequency
stabilizing resistors.

3
Gain and Noise Circles:

Here we plotted the source gain circles (gacir), load gain circles (gpcir), and noise figure
circles (nfcir).

4
 We assume the load is
conjugately matched to
output for all gamma_S ,
so we plot noise circles
and gacir on source plane.

We picked a point on
gacir2 that is furthest from
the source stability circle
and within the 1.5dB NF
circle. This way, we only
gave up 2dB of gain in
exchange for <1.5dB
Noise Figure and stability.

After picking gamma_S

point on gacir, we could
plug into equations to
calculate gamma_L,
which would lead to the
design of matching
network.

The calculated gamma_L

value landed inside -1dB
gpcir.

5
Matching Network:
From the above gain circles and NF circles, we found out:

Gamma_L = -0.181 + j*0.292, Z_L= 50*(0.596 + j*0.395)

Gamma_S = 0.550 + j*0.512, Z_S = 50*(0.935 + j*2.204)

Using Smith chart, we obtained the lengths of shunt-series microstrip matching network.
We could verify it by using the following testbench:

Gamma_S, Gamma_L,
Z_Source Z_Load

Designed value: Z_S = 50*(0.935 + j*2.204) Z_L= 50*(0.596 + j*0.395)

6
System Simulation with Ideal Linear Model:

With linear and ideal microstrip lines, we achieved:

Gain 17.07 dB
Bandwidth (3 dB) 390 MHz
|S22| -45.2 dB
Noise Figure 0.72 dB

7
System Simulation with NON-Ideal Linear Model:
Now we replace ideal microstrip into MSUB model and calculate their physical
dimension from LineCalc. Ground via models are included to accurately model the
inductive parasitic. Also T-junctions models are employed to increase modeling accuracy
as well.

With linear and NON-ideal microstrip lines, we achieved:

Gain 17.99 dB
Bandwidth (3 dB) 400 MHz
|S22| -26.9 dB
Noise Figure 0.97 dB
Comparing to ideal T-line simulation, this result provides more realistic insight
considering possible parasitics. For example, increase in NF and decrease in S22 may be
results of including real-world parasitic models.

8
System Simulation with NON-Ideal NON-Linear Model:
In order to fully and accurately account for non-ideality and non-linearity existing within
the device or PCB/components, we must verify our design with simulation of a non-linear
transistor model. First of all, the non-linear transistor requires DC bias circuits.

Active DC Bias:
The biasing is implemented with active bias circuit in order to provide a stable bias point
to the LNA. From the device’s Spec sheet, we found the transconductance gm of the
GaAs FET to be 30mS and threshold voltage Vth to be -0.69V, thus from Id=gm(Vgs-
Vth), we determined that the Vgs required for an Id of 10mA to be -0.36V. We tested the
bias point in ADS, and determined Vgs to be -0.52V. We then chose Ic of the bias circuit
to be 1mA. With Vgs, Ic and Vds known, we chose bias resistors to give the correct bias
point.

9
LNA (excluding biasing network) with non-linear model and non-linear microstrip
models:

System simulation testbench (including DC biasing):

DC Active Biasing
Network

These two short T-line section is to

model Microstrip line connecting
from matching network to SMA
connector. Ideally, they should not
change the result.

10
Result:

With NON-linear model and NON-ideal microstrip lines, we achieved:

Gain 15.14dB
Bandwidth (3 dB) 310 MHz
|S22| -17.4 dB
Noise Figure 1.06dB

The NON-linear transistor model caused our gain to degrade by almost 3dB, yet it seems
to provide better overall stability than the linear model. In fact, the amplifier is
overstablized (min K value = 1.4) and we could gain more S21 headroom by adjusting
stability resistor value.

Stabilizing
resistor
changed to
100 Ohm
from 60
Ohm.

11
New result after increasing stabilizing resistor:

After adjusting stabilizing resistor value, we achieved:

Gain 16.6dB
Bandwidth (3 dB) 310 MHz
|S22| -19.2 dB
Noise Figure 1.03dB

The amplifier now has adequate gain margin (1.6dB above spec) to handle any other
unexpected non-ideality within the final circuit assembly. We would proceed to PCB
fabrication and assembly with this design.

12
PCB Layout

DC bias is fed through the

matching network’s inductive Also notice the long GND via’s
shunt stubs. Such implementation along the end of shunt stubs.
avoids addition RF choke which These “sliders” could be used to
introduces additional parasitic and fine-tune stub length to account
costs. for via’s length and inductance.

Fabricated and Assembled PCB:

13
Test Result
Stability

Spectrum Analyzer setup

Cable Loss -2.28dB

Input -30dBm
Span 2Ghz
Attenuation 10-dB
Res BW 100kHz

RF_in = -30dBm, Attenuation = -10dBm, cable loss = -2.5dB

-72.5

m1 m1
-73.0
freq=1.512GHz
TraceA=-72.930

-73.5

-74.0

-74.5

-75.0
TraceA

-75.5

-76.0

-76.5

-77.0

-77.5

-78.0
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6

freq, GHz

We can see that with the signal generator off, the LNA output is very low across the
entire desired frequency range. The highest output was at -72.93 dB.

14
 -25
m2
m2
-30 freq=1.605GHz
SA_span_2ghz..TraceA=-27.550
-35

-40
SA_span_2ghz..TraceA

-45

-50

-55

-60

-65

-70
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6

freq, GHz

With the signal generator on at 1.6Ghz, the only signal present at the output is detected at
1.6Ghz with no other signals in the neighborhood.

-25 m3
-30
m3
-35 freq=800.4kHz
SA_low_freq_spur..TraceA=-27.930
-40
SA_low_freq_spur..TraceA

-45

-50

-55

-60

-65

-70

-75

-80

-85
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55

freq, MHz

We then took a closer look at the output spectrum, and did a sweep across all interested
frequencies. We found an output at about 800Khz, which we suspect that it is due to the
SA’s local oscillator generating a signal at the output.

15
 S Parameter Measurements

S21 (Gain) 15.232 dB

S22 -13.093 dB
Bandwidth 439 MHz

m8 m7 m10 m9
freq=1.608GHz freq=1.608GHz freq=1.359GHz freq=1.798GHz
dB(S(2,2))=-13.093 dB(S(2,1))=15.232 dB(S(2,1))=12.641 dB(S(2,1))=12.574
20
m7
15 m10 m9

10 S21

5
S11
0

-5

-10 m8
S22
-15
dB(S(2,2))
dB(S(2,1))
dB(S(1,2))
dB(S(1,1))

-20

-25

-30

-35

-40 S12
-45

-50

-55

-60

-65
1E8 1E9 1E10 2E10

freq, Hz
S-parameter Measurement vs. Simulation

20 m1
m6
m1 freq=1.608GHz
S21 dB(S(2,1))=15.232
m6
10 freq=1.600GHz
dB(large_signal_bias..SP1.SP.S(2,1))=16.584

S11
0
m3
freq=1.608GHz
dB(large_signal_bias..SP1.SP.S(2,2))
dB(large_signal_bias..SP1.SP.S(2,1))
dB(large_signal_bias..SP1.SP.S(1,1))

S22 dB(S(2,2))=-13.093
m5
m2 m4
-10 m3 freq=1.600GHz
dB(large_signal_bias..SP1.SP.S(2,2))=-19.222
dB(S(2,2))
dB(S(2,1))
dB(S(1,1))

m4
-20
m2
freq=1.608GHz
dB(S(1,1))=-10.959
-30 m5
freq=1.600GHz
dB(large_signal_bias..SP1.SP.S(1,1))=-8.980

-40

-50
1E8 1E9 1E10

freq, Hz

We met the spec for gain and bandwidth as well as S22. Our measurements came out to
be very close to the simulated results as shown in the illustration above.

16
Noise Figure

Frequency NF NF vs Frequency
(Mhz) (dB)
1600 2.28 3
1590 2.1
2.5
1580 1.86
2
1570 1.92

NF (dB)
1560 1.96 1.5
1550 1.95 1
1540 1.98 0.5
1530 2.08
0
1520 2.16
1480 1500 1520 1540 1560 1580 1600 1620
1510 2.18
Frequency (Mhz)
1500 2.71

Our measurements for Noise Figure came out to be little bit high. The lowest NF is at
1580Mhz. The measured NF is higher than our simulated result. Variations in the testing
environment are probably the cause to this discrepancy. Wires to the supply voltage could
inject extra unwanted noise to the circuit as well.

Gain Compression

Pin Pout Gain

(dBm) (dBm)
-50 -46.8 -5.7 Pout vs P in
-45 -41.8 -5.7
-40 -36.9 -5.6 0

-35 -31.9 -5.6 -5

-30 -26.9 -5.6
-10
-25 -21.9 -5.6
-15
-20 -16.9 -5.6
-19 -15.9 -5.6 -20
Pout(dBm)

-18 -14.9 -5.6 -25

-17 -13.9 -5.6 -30
-16 -13.05 -5.45
-35
-15 -12.3 -5.2
-40
-14 -11.62 -4.88
-13 -11.11 -4.39 -45

-12 -10.7 -3.8 -50

-11 -10.4 -3.1 -60 -50 -40 -30 -20 -10 0 10

-10 -10.19 -2.31 Pin(d Bm)

P1dB = -13dBm
-5 -9.46 1.96
0 -8.77 6.27
5 -8.06 0.56

Our measured P1dB input power is at -13dBm, shown on the table above.

17
Cost Analysis and Power Dissipation
Bill of Materials:
Amplifier
Price
Component Part Number Quantity (1000+)
NEC 34018 GaAs
HJ-FET NE85639RTR-ND 1 $2.57
Chip capacitors GRM155R61A154KE19-ND 4 $0.12
Chip resistors ERJ-S02F2000X-ND 2 $0.60
Leaded resistor 2 $0.05
Tantulum capacitor 3 $0.30
Variable Resistor 2 $0.30
2N3906 BJT 2N3906TFR 2 $0.17

SUBTOTAL $5.59
Eval board
PCB board PCB Express Mini Board 1 $51
SMA Connector SMA 4959-ND 2 $14.64
SUBTOTAL $74.64

GRAND TOTAL $71.23

The cost of this amplifier would be dominated by the PCB, and SMA connector’s costs.
However, at large scale manufacturing, the costs of PCB would drastically decrease.

Power Dissipation:
To measure DC power dissipation, we measured the voltage drop at resistor R12 and
R10. Then we calculate the total DC current from these measurements, and therefore
calculate the DC dissipation.

Total DC current: 11.3mA+.505mA=11.805mA

DC voltage: 3.5V
Power Dissipated: 3.5V x 11.805mA = 41.32mW

18
Sensitivity of Circuit Under Device/Supply Variations
Since the discrete component count is greatly reduced by lumped microstrip matching
network, the amplifier is less prone to critical component (discrete matching network)
variation under the assumption of adequate PCB fabrication precision (ie. PCB trace
dimensions). Thus, we will only perform test on varying supply voltages.

Varying Supply Voltage

We test our circuit with 10% supply voltage variation:
V_positive = 3.5V + 0.35V = 3.85V
V_negative = -2.5V – 0.25V = -2.75V

Such variation yields the

following DC bias:
Id = 11.8mA
(18% deviation from ideal
10mA)

Vd = 2.17V
(8.5% deviation from ideal
2V)

S-parameter performance was not affected much

under supply variation. S-parameters overlap for
before and after 10% variation.
Noise and stability were not jeopardized with 10%
supply voltage variation.

Conclusion: our LNA could withstand 10% change in

supply without degrading gain, noise, S22
performances. This also proves that our failure in
meeting the 1.6dB NF spec is most likely due to
measurement setup and environment interferences.
Original bias point
freq ...e_signal_bias..SP2.MaxGain1 ...ge_signal_bias..SP2.SP.nf(2) ...e_signal_bias..SP2.SP.NFmin ...e_signal_bias..SP2.StabFact1 mag_delta
1.600 GHz 17.551 1.030 0.457 1.254 0.378

After 10% supply variation

f req SP2.MaxGain1 SP2.SP.nf (2) SP2.SP.NFmin SP2.StabFact1 mag_delta
1.600 GHz 17.683 1.012 0.445 1.259 0.378

19
Conclusion
The design and fabrication of 1.6GHz Low Noise Amplifier requires thorough
understanding of narrow-band tuned microwave amplifier design principles and sgreat
care in modeling circuit parasitic (device non-linearity, non-ideality, and PCB parasitic
such as vias and discrete components). After several iteration of ADS simulation and
optimization of circuit parameters, our LNA performs up to all specifications with the
exception of noise figure. As illustrated in above sections, this failure is most likely due
to environmental interference and could be improved by applying shielding to avoid
interferer during future noise figure measurements.

20