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MP Online Examination Unit 1 MCQ’s

ID 1
Question The 80386 accesses __________ of physical memory.
A 1 GB
B 64 TB
C 4 GB
D 4 TB
Answer C
Marks 1
Unit 1

ID 2
Question The 80386 accesses ___________ of memory in virtual mode.
A 64 TB
B 1 TB
C 2 TB
D 10 TB
Answer A
Marks 1
Unit 1

ID 3
Question What do the symbols [ ] indicate?
A Direct addressing
B Register Addressing
C Indirect addressing
D None of the above
Answer C
Marks 1
Unit 1

ID 4
Question The ________ unit of 80386 provides four levels of protection for isolating
and protecting applications and the operating system from each other.
A Memory Management
B Segment Translation
C Paging Translation
D Instruction Translation
Answer A
Marks 1
Unit 1

ID 5
Question The 80386DX processor has ________ bit data bus.

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A 14
B 16
C 64
D 32
Answer D
Marks 1
Unit 1

Id 6
Question In 80386, instruction queue is of _____ bytes.
A 8
B 16
C 4
D 01
Answer B
Marks 2
Unit 1

Id 7
Question 80386 consist of _____ &_____ ,__________where _____ handles prefetching operation.
A Segmentation Unit, Execution Unit, Bus Interface Unit, Bus Interface Unit
B Segmentation Unit, Page Unit, Bus Interface Unit, Segmentation Unit
C Bus Interface Unit, Execution Unit, Segmentation Unit, Execution Unit
D Bus Interface Unit, Execution Unit, Bus Interface Unit, all
Answer A
Marks 2
Unit 1

Id 8
Question Which of the following option is false?
A In 80386, BIU is responsible for outside world communication by the microprocessor.
B In 80386, Segmentation Unit is used to support segmentation.
C In 80386, EU is used to support paging.
D In 80386, Paging Unit is used to support paging.
Answer C
Marks 2
Unit 1

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Id 9
Question The memory is logically divided into code, data, extra data, and stack segments of ---------
-----Size.
A 64KB
B 1MB
C 4GB
D Variable
Answer D
Marks 1
Unit 1

Id 10
Question In 80386, Parity flag is set when ____________
A The lower byte of result contains odd number of 1's
B The higher byte of result contains even number of 1's
C The lower byte of result contains even number of 1's
D Both B &C
Answer C
Marks 2
Unit 1

Id 11
Question Which of the following function/s BIU performs?
A To support instruction queuing
B To send the address of memory or I/O
C To fetch instruction from memory
D All of the above
Answer D
Marks 2
Unit 1

Id 12
Question In the 80386, the flag register consist of ___ bits, out of which ___ bits are active.
A 16, 10
B 16, 6
C 32, 14
D 16, 7

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Answer C
Marks 2
Unit 1

Id 13
Question 80386DX is _____ bit processor because Its ----------- is/are ------------bits
A 32, Address bus , 32
B 32, data bus , 32
C 32, Address and data bus, 32
D 32, ALU , 32
Answer D
Marks 2
Unit 1

Id 14
Question The Intel386 DX consists of _______.
A a central processing unit
B a memory management unit
C a bus interface unit
D All of these
Answer D
Marks 2
Unit 1

Id 15
Question The central processing unit in 80386DX consist of _____ and _____.
A Segmentation Unit and Paging Unit
B Execution Unit and Instruction Unit
C Execution Unit and Segmentation Unit
D None of these
Answer B
Marks 2
Unit 1

Id 16
Question The central processing unit in 80386DX consist of _____ bit barrel shifter used to speed
____, _____, ______ and _____ operations.
A 64, add, subtract, multiply and divide
B 64, shift, rotate, multiply and divide
C 32, add, subtract, multiply and divide
D 32, shift, rotate, multiply and divide
Answer B

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Marks 2
Unit 1

Id 17
Question In 80386DX, the _______ decodes the instruction opcodes and stores them in the
_______ for immediate use by the ______.
A decoder, instruction queue, instruction unit
B instruction unit, instruction queue, segmentation unit
C instruction unit, decoded instruction queue, execution unit
D None of these
Answer C
Marks 2
Unit 1

Id 18
Question In 80386DX, the memory management unit (MMU) consists of _________.
A a segmentation unit and a paging unit.
B a segmentation unit and a memory address unit
C a paging unit and bus interface unit
D None of these
Answer A
Marks 2
Unit 1

Id 19
Question
A
B
C
D
Answer
Marks 2
Unit 1

Id 20
Question In 80386DX, BIU accepts internal request for code fetch from the _____ and data
transfers from the _____, and prioritize the requests.
A Decode Unit, Execution Unit
B Code prefetch unit, page unit
C Code prefecth unit, execution unit
D Decode unit, page unit
Answer C

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Marks 2
Unit 1

Id 21
Question In 80386DX, Execution Unit consists of _____ , _______ and ______ .
A Segmentation Unit, Paging Unit, Bus Interface Unit
B Control Unit, Data Unit and Protection test unit
C Control Unit, Segmentation Unit and Paging Unit
D None of these
Answer B
Marks 2
Unit 1

ID 22
Question The ______ pair gives the address of the next instruction to be executed in the program
sequence.
A CS:EIP
B DS:EIP
C ES:EIP
D SS:EIP
Correct A
Answer
Marks 1
Unit 1

ID 23
Question The ______ pair gives the address of the top of the stack.
A SS:ESP
B DS:EIP
C ES:EIP
D SS:EBP
Correct A
Answer
Marks 1
Unit 1

ID 24
Question The ____ pair is used as a pointer into the stack.
A CS:EIP
B DS:EIP

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C ES:EIP
D SS:EBP
Correct D
Answer
Marks 1
Unit 1

ID 25
Question The ____ pair is used as a source pointer for string instructions.
A DS:ESI
B DS:EDI
C ES:ESI
D ES:EDI
Correct A
Answer
Marks 1
Unit 1

ID 26
Question The ____ pair is used as a destination pointer for string instructions.
A ES:ESI
B ES:EDI
C DS:ESI
D DS:EDI
Correct B
Answer
Marks 1
Unit 1

ID 27
Question A flag is a _________.
A Flipflop
B Register
C Both (A) and (B)
D None of these
Correct C
Answer
Marks 1
Unit 1

ID 28
Question Setting _____ puts the processor into single step mode for debugging.
A Sign Flag(SF)
B Interrupt Flag(IF)
C Direction Flag(DF)
D Trap Flag(TF)

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Correct D
Answer
Marks 1
Unit 1

ID 29
Question _____ bit is specifically for string instructions.
A Sign flag(SF)
B Interrupt flag(IF)
C Direction flag(DF)
D Trap flag(TF)
Correct C
Answer
Marks 1
Unit 1

ID 30
Question The system address registers are associated with the _______ mode operation of the
80386DX.
A Protected
B Real
C Both (A) and (B)
D None of these
Correct A
Answer
Marks 1
Unit 1

ID 31
Question Which of the following is not 32 bit register?
A EAX
B R15D
C ECX
D None of these
Correct Answer D
Marks 1
Unit 1

ID 32
Question Which of the following is not 64bit register?
A RAX
B RBX
C R8
D None of these

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Correct Answer D
Marks 1
Unit 1

ID 33
Question Which of the following is not 16 bit register?
A AX
B BX
C R8W
D None of these
Correct Answer D
Marks 1
Unit 1

ID 34
Question Which of the following is not 8 bit register?
A AL
B CS
C BL
D CH
Correct Answer B
Marks 1
Unit 1

ID 35
Question Which of the following is not 32 bit register?
A EAX
B R15
C ECX
D None of these
Correct Answer B
Marks 1
Unit 1

ID 36
Question Which of the following is not 64 bit register?
A RAX
B R15D
C RCX
D None of these
Correct Answer B
Marks 1
Unit 1

ID 37
Question Which of the following is not 16 bit register?

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A AX
B CX
C R15D
D None of these
Correct Answer C
Marks 1
Unit 1

ID 38
Question Which of the following is not 8 bit register?
A AL
B CL
C R10W
D None of these
Correct Answer C
Marks 1
Unit 1

ID 39
Question In 80386, ____ is used to hold count during execution of LOOP instruction.
A CL
B ECX
C CH
D ECX
Correct Answer B
Marks 1
Unit 1

ID 40
Question In 80386, ____ is used to hold count during execution of LOOP instruction.
A CX
B CL
C ECX
D None of the above
Correct Answer C
Marks 1
Unit 1
ID 41

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Question The contents of different registers are given below. Form Effective addresses for different
addressing modes are as follow :
Offset = 5000H [AX]- 1000H,
[BX]- 2000H, [SI]- 3000H,
[DI]- 4000H, [BP]- 5000H,
[SP]- 6000H,
[CS]- 0000H, [DS]- 1000H,
[SS]- 2000H,
[IP]- 7000H.
I. MOV AX, [5000H]

A 5000 H
B 15000H
C 10500H
D None of these
Answer B
Marks 2
Unit 1
Id 42
Question The contents of different registers are given below. Form Effective addresses for different
addressing modes are as follow :
Offset = 5000H [AX]- 1000H,

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[BX]- 2000H, [SI]- 3000H,

[DI]- 4000H, [BP]- 5000H,
[SP]- 6000H,
[CS]- 0000H, [DS]- 1000H,
[SS]- 2000H,
[IP]- 7000H.
MOV AX, [BX] [SI]
A 13000H
B 15000H
C 12000H
D 11000H
Answer C
Marks 2
Unit 1
Id 106
Question The contents of different registers are given below. Form Effective addresses for different
addressing modes are as follow :
Offset = 5000H [AX]- 1000H,
[BX]- 2000H, [SI]- 3000H,
[DI]- 4000H, [BP]- 5000H,
[SP]- 6000H,
[CS]- 0000H, [DS]- 1000H,
[SS]- 2000H,
[IP]- 7000H.
MOV AX, 5000H [BX] [SI]
A 20000H
B 1A000H
C 1A00H
D 10A00H
Answer B
Marks 2
Unit 1

Id 43
Question If the number of address bits in a memory is reduced by 2 and the

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address-ability is doubled, the size of the memory (i.e., the number of bits stored in the
memory)
A Doubles
B remains unchanged
C Halves
D increases by 2^(address bits)/addressability
Answer C
Marks 2
Unit 1

Id 44
Question In immediate addressing the operand is placed
A in the CPU register
B after OP code in the instruction
C in memory
D in stack
Answer B
Marks 1
Unit 1
Question In ________ the effective address is taken from the displacement field of the instruction.

A Register addressing mode

B Direct addressing mode

C Based addressing mode

D Indexed addressing mode

Answer B

Marks 1

Unit I

Id 154

Question In _______ a base or index register contains the operand's effective address.

A Direct addressing mode

B Immediate addressing mode

C Registeraddressing mode

D Register indirect addressing mode

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Answer D

Marks 1

Unit I

Id 45

Question In ______ mode, the contents of a base register are added to displacement, in order to
obtain the operand's effective address.

A Based mode

B Scaled mode

C Indexed mode

D All of these

Answer A

Marks 1

Unit I

Id 46

Question In ______ mode, the contents of an index register are added to displacement, in order to
obtain the operand's effective address.

A Direct addressing mode

B Indirect addressing mode

C Indexed mode

D Based mode

Answer C

Marks 1

Unit I

Id 47

Question In ______ mode, the contents of an index register are multiplied by a scaling factor
(1,2,4,8) which is then added to the displacement, in order to obtain the operand's

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effective address.

A Scaled indexed mode with displacement

B Indexed mode

C Based mode

D Direct addressing mode

Answer A

Marks

Unit

Id 48

Question If the source operand is a part of the instruction instead of register or memory, it is
referred as ______ addressing mode

A Immediate addressing mode

B Register addressing mode

C Direct addressing mode

D Based addressing mode

Answer A

Marks 1

Unit I

Id 49

Question In _______ addressing mode the operand is located in one of the 8, 16 or 32-bit general
purpose registers of 80386DX.

A Register Addressing

B Immediate Addressing

C Memory Addressing

D All of these

Answer A

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Marks 1

Unit I

Id 50

Question Which of the following are main components of physical address?

A Opcode

B Segment base address

C Effective address

D Both Segment base &Effective address

Answer D

Marks 1

Unit I

Id 51

Question Which of the following address elements are used to generate effective address?

A Base

B Index

C Scale

D All of these

Answer D

Marks 1

Unit I

Marks 1

Unit I

Id 52

Question When an immediate byte value is added to a word or double-word operand, the immediate
value is first______

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A Sign extended to other operand size

B Doubled

C Quadrupled

D None of these

Answer A

Marks 1

Unit I

Id 53

Question ______ converts signed word in AX to a signed double-word in DX:AX.

A CMPS

B CLC

C CWD

D CDQ

Answer C

Marks 1

Unit I

Id 54

Question _______ instruction subtracts source and carry flag (i.e. borrow) from destination

A ADD

B DAS

C SUB

D SBB

Answer D

Marks 1

Unit I

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Id 55

Question _____ instruction compares a double-word/ word/ byte from source with double- word/
word/ byte from destination

A CMC

B CMP

C XLAT

D BSWAP

Answer B

Marks 1

Unit I

Id 56

Question The source and destination both cannot be ____ for AND instruction

A Byte

B Word

C Nibble

D Double word

Answer C

Marks 1

Unit I

Id 57

Question BSF affects which of the following flag/flags.

A SF

B PF

C ZF

D All of these

Answer C

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Marks 1

Unit I

Id 58

Question _____ instruction saves and complements bits value indicated by base and bit offset in
____

A BT,CF

B BTS,CF

C BTC,CF

D BTC,PF

Answer C

Marks 1

Unit I

Id 59

Question CMC reverses the setting of ____ flag.

A Parity

B Zero

C Carry

D Overflow

Answer C

Marks 1

Unit I

Id 60

Question _____ instruction will cause the processor to stop fetching and executing instructions.

A WAIT

B NOP

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C ESC

D HLT

Answer D

Marks 1

Unit I

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