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UNIT-IIII: CONTROL UNIT

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Key Points
✓ The execution of an instruction involves the execution of a sequence of substeps,
generally called cycles.
✓ Each cycle is in turn made up of a sequence of more fundamental operations, called
micro-operations.
✓ A single micro-operation generally involves a transfer between registers, a transfer
between a register and an external bus, or a simple ALU operation.
✓ The control unit of a processor performs two tasks:
✓ (1) It causes the processor to step through a series of micro-operations in the proper
sequence, based on the program being executed.
✓ (2) it generates the control signals that cause each micro-operation to be executed.
✓ The control signals generated by the control unit cause the opening and closing of
2 logic gates, resulting in the transfer of data to and from registers and the operation of
the ALU.
✓ One technique for implementing a control unit is referred to as hardwired
implementation, in which the control unit is a combinatorial circuit. Its input logic
signals, governed by the current machine instruction, are transferred into a set of
output control signals.

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MICRO-OPERATIONS
✓ Each instruction cycle is made up of a number of smaller units. One subdivision that we
found is fetch, indirect, execute, and interrupt, with only fetch and execute cycles
always occurring.
✓ each of the smaller cycles involves a series of steps, each of which involves the processor
registers. We will refer to these steps as micro-operations.
✓ The prefix micro refers to the fact that each step is very simple and accomplishes very
little. Micro-operations are the functional, or atomic, operations of a processor.

Fig1: Constituent Elements of a Program Execution

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The Fetch Cycle

The fetch cycle, which occurs at the beginning of each instruction cycle and causes an
instruction to be fetched from memory.
Memory address register (MAR): Is connected to the address lines of the system bus. It specifies
the address in memory for a read or write operation.
Memory buffer register (MBR): Is connected to the data lines of the system bus. It contains the
value to be stored in memory or the last value read from memory.
Program counter (PC): Holds the address of the next instruction to be fetched.
Instruction register (IR): Holds the last instruction fetched.

At the beginning of the fetch cycle, the address of the next instruction to be executed
is in the program counter (PC)
4 Step-1: Move that address to the memory address register (MAR) because this is the only
register connected to the address lines of the system bus.
Step-2: The desired address (in the MAR) is placed on the address bus, the control unit issues
a READ command on the control bus, and the result appears on the data bus and is copied
into the memory buffer register (MBR).
Step-3: Move the contents of the MBR to the instruction register (IR).

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Thus, the simple fetch cycle actually consists of three steps and four
microoperations.
t1: MAR ← (PC)
t2: MBR ← Memory
PC ← (PC) + I
t3: IR ← (MBR)

where I is the instruction length.

First time unit: Move contents of PC to MAR.
Second time unit: Move contents of memory location specified by MAR to MBR.
5 Increment by I the contents of the PC.
Third time unit: Move contents of MBR to IR.

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The Indirect Cycle

Once an instruction is fetched, the next step is to fetch source operands. If the instruction
specifies an indirect address, then an indirect cycle must precede the execute cycle.
t1: MAR ← (IR(Address))
t2: MBR ← Memory
t3: IR(Address) ← (MBR(Address))
The address field of the instruction is transferred to the MAR. This is then used to fetch the
address of the operand. Finally, the address field of the IR is updated from the MBR, so that it
now contains a direct rather than an indirect address.
The Interrupt Cycle
At the completion of the execute cycle, a test is made to determine whether any enabled
6 interrupts have occurred. If so, the interrupt cycle occurs.
t1: MBR ← (PC)
t2: MAR ← Save_Address
PC ← Routine_Address
t3: Memory ← (MBR)

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The Execute Cycle
The fetch, indirect, and interrupt cycles are simple and predictable. Each involves a small,
fixed sequence of micro-operations and, in each case, the same micro-operations are
repeated each time around.
This is not true of the execute cycle. Because of the variety opcodes, there are a number of
different sequences of micro-operations that can occur.
Ex1: ADD R1, X
which adds the contents of the location X to register R1.
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: R1 ← (R1) + (MBR)
Ex2: ISZ X
The content of location X is incremented by 1. If the result is 0,
7 the next instruction is skipped.
t1: MAR ← (IR(address))
t2: MBR ← Memory
t3: MBR ← (MBR) + 1
t4: Memory ← (MBR)
If ((MBR) = 0) then (PC ← (PC) + I)

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The Instruction Cycle

Each phase of the instruction cycle can be decomposed into a sequence of elementary micro-
operations. There is one sequence each for the fetch, indirect, and interrupt cycles, and, for the
execute cycle, there is one sequence of micro-operations for each opcode.
We assume a new 2-bit register called the instruction cycle code (ICC).The ICC designates the
state of the processor in terms of which portion of the cycle it is in:
00: Fetch
01: Indirect
10: Execute
11: Interrupt
At the end of each of the four cycles, the ICC is set appropriately. The indirect cycle is always
followed by the execute cycle. The interrupt cycle is always followed by the fetch cycle . For both
8 the fetch and execute cycles, the next cycle depends on the state of the system.

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Fig2: Flowchart for Instruction Cycle

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CONTROL OF THE PROCESSOR

Functional Requirements
The execution of a program consists of operations involving these processor elements.
These operations consist of a sequence of micro-operations. All micro-operations fall into
one of the following categories.
✓ Transfer data from one register to another.
✓ Transfer data from a register to an external interface (e.g., system bus).
✓ Transfer data from an external interface to a register.
✓ Perform an arithmetic or logic operation, using registers for input and output.
The control unit performs two basic tasks:
Sequencing: The control unit causes the processor to step through a series of micro-
operations in the proper sequence, based on the program being executed.
10 Execution: The control unit causes each micro-operation to be performed.

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11

Fig3: Block Diagram of the Control Unit

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The inputs are
Clock: This is how the control unit “keeps time.” The control unit causes one micro-operation (or a
set of simultaneous micro-operations) to be performed for each clock pulse. This is sometimes
referred to as the processor cycle time, or the clock cycle time.
Instruction register: The opcode and addressing mode of the current instruction are used to
determine which micro-operations to perform during the execute cycle.
Flags: These are needed by the control unit to determ ine the status of the processor and the
outcome of previous ALU operations. For example, for the increment-and-skip-if-zero (ISZ)
instruction, the control unit will increment the PC if the zero flag is set.
Control signals from control bus: The control bus portion of the system bus provides signals to the
control unit.
The outputs are

12 Control signals within the processor: These are two types: those that cause data to be moved from
one register to another, and those that activate specific ALU functions.
Control signals to control bus: These are also of two types: control signals to memory, and control
signals to the I/O modules.

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Three types of control signals are used: those that activate an ALU function, those that activate
a data path, and those that are signals on the external system bus or other external interface. All
of these signals are ultimately applied directly as binary inputs to individual logic gates.

13

Fig-4:Data Paths and Control Signals

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The control unit receives inputs from the clock, the instruction register, and flags. With each
clock cycle, the control unit reads all of its inputs and emits a set of control signals. Control
signals go to three separate destinations:
Data paths: The control unit controls the internal flow of data. For example, on instruction fetch,
the contents of the memory buffer register are transferred to the instruction register. For each
path to be controlled, there is a switch. A control signal from the control unit temporarily opens
the gate to let data pass.
ALU: The control unit controls the operation of the ALU by a set of control signals. These signals
activate various logic circuits and gates within the ALU.
System bus: The control unit sends control signals out onto the control lines of the system bus
(e.g., memory READ).
The control unit must maintain knowledge of where it is in the instruction cycle. Using this
14 knowledge, and by reading all of its inputs, the control unit emits a sequence of control signals
that causes micro-operations to occur.

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15

Fig 5: Micro-operations and Control Signals

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Internal Processor Organization

16

Fig-6: CPU with Internal Bus

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HARDWIRED IMPLEMENTATION
In a hardwired implementation, the control unit is essentially a state machine circuit. Its input logic
signals are transformed into a set of output logic signals, which are the control signals.
Control Unit Inputs
The control unit makes use of the opcode and will perform different actions for different instructions.
To simplify the control unit logic, there should be a unique logic input for each opcode. This function
can be performed by a decoder, which takes an encoded input and produces a single output. In
general, a decoder will have n binary inputs and 2n binary outputs. Each of the 2n different input
patterns will activate a single unique output.
The clock portion of the control unit issues a repetitive sequence of pulses. This is useful for measuring
the duration of micro-operations. The control unit emits different control signals at different time units
17
within a single instruction cycle. Thus, we would like a counter as input to the control unit, with a
different control signal being used for T1 and T2 and so forth. At the end of an instruction cycle, the
control unit must feed back to the counter to reinitialize it at T1.

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18

Fig-7: Control Unit with Decoded Inputs

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Control Unit Logic

the internal logic of the control unit that produces output control signals as a function of
its input signals.
for each control signal, to derive a Boolean expression of that signal as a function of the
inputs.
Ex: C5 This signal causes data to be read from the external data bus into the MBR. Let us
define two new control signals, P and Q
PQ = 00
PQ = 01
PQ = 10
PQ = 11

19 That is, the control signal C5 will be asserted during the second time unit of both the
fetch and indirect cycles.
This expression is not complete.C5 is also needed during the execute cycle. Let us
assume that there are only three instructions that read from memory: LDA,ADD, and
AND. Now we can define C5 as

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Microprogrammed Control
Control signals are generated by a program similar to machine language programs.
Control Word (CW); microroutine; microinstruction .
A control word (CW) is a word whose indiv idual bits represent the various control signals.
Each of the control steps in the control sequence of an instruction defines a unique
combination of 1s and 0s in the CW. A sequence of CWs corresponding to the control
sequence of a machine instruction constitutes the microroutine for that instruction, and
the individual control words in this microroutine are referred to as microinstructions.
The microroutines for all instructions in the instruction set of a computer are stored in a
special memory called the control store.
The control unit can generate the control signals for any instruction by sequentially reading
20 the CWs of the corresponding microroutine from the control store. To read the control
words sequentially from the control store, a micro-program counter (µPC) is used.
Every time a new instruction is loaded into the IR, the output of the block labeled "starting
address generator" is loaded into the µPC. The µPC is then automatically incremented by
the clock, causing successive microinstructions to be read from the control store. Hence,
the control signals are delivered to various parts of the processor in the correct sequence.
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Fig-8:An Example of Microinstructions

21
Fig-10: Basic organization of a
microprogrammed control unit.

Fig-9:Control Sequencer for execution of the instruction ADD

(R3),R1
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22
Fig-11: Organization of the control unit to allow conditional
branching in the microprogram.

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Microinstructions
✓ A straightforward way to structure microinstructions is to assign one bit position to each
control signal.
✓ However, this is very inefficient.
✓ The length can be reduced: most signals are not needed simultaneously, and many signals
are mutually exclusive.
✓ All mutually exclusive signals are placed in the same group in binary coding.

23

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Partial Format for the Microinstructions

24

Fig-12: An example of partial format for field-

encoded micro instructions

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Microprogram Sequencing

If all microprograms require only straightforward sequential execution of microinstructions except

for branches, letting a μPC governs the sequencing would be efficient.
However, two disadvantages:
➢Having a separate microroutine for each machine instruction results in a large total number of
microinstructions and a large control store.
➢Longer execution time because it takes more time to carry out the required branches.
Example: Add src, Rdst
Four addressing modes: register, autoincrement, autodecrement, and indexed (with indirect
forms).
25

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26

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Fig13: Microinstruction for Add (Rsrc)+,Rdst.

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Microinstructions with Next-Address Field

The microprogram we discussed requires several branch microinstructions, which
perform no useful operation in the datapath.
A powerful alternative approach is to include an address field as a part of every
microinstruction to indicate the location of the next microinstruction to be
fetched.
Pros: separate branch microinstructions are virtually eliminated; few limitations in
assigning addresses to microinstructions.
Cons: additional bits for the address field (around 1/6)

28

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29

Fig-14:Microinstruction sequencing
organization
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Fig-15: Format of Microinstructions

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Implementation of the Microroutine

31

Fig-16:Implementation of microroutine
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Prefetching Microinstructions
One drawback of microprogrammed control is that it leads to a slower operating speed because of
the time it takes to fetch microinstructions from the control store. Faster operation is achieved if the
next microinstruction is prefetched while the current one is being executed. In this way, the execution
time can be overlapped with the fetch time.
Prefetching m icroinstructions presents some organizational difficulties. Sometimes the status flags and
the results of the currently executed microinstruction are needed to determ ine the address of the
next microinstruction. Thus, straightforward prefetching occasionally prefetches a wrong
microinstruction. In these cases, the fetch must be repeated with the correct address, which requires
more complex hardware. However, the disadvantages are minor, and the prefetching technique is
often used.
32

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