Lecture Notes on

COMPUTER ORGANIZATION AND ARCHITECTURE-17EC13

(B.Tech V Semester)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING

(Autonomous), Mylavaram-521230

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 UNIT-II Notes
Addition and Subtraction of Signed Numbers
Figure-1 shows the truth table for the sum and carry-out functions for adding equally weighted
bits xi and yi in two numbers X and Y. The figure also shows logic expressions for these functions,
along with an example of addition of the 4-bit unsigned numbers 7 and 6. Each stage of the addition
process must accommodate a carry-in bit. We use ci to represent the carry-in to stage i, which is the
same as the carry-out from stage (i − 1).
The logic expression for si in Figure-1 can be implemented with a 3-input XOR gate. The carry-out
function, ci+1, is implemented with an AND-OR circuit, as shown in Figure-2

Figure-1: Logic specification for a stage of binary addition.

A cascaded connection of n full-adder blocks can be used to add two n-bit numbers, as shown in Figure
2. Since the carries must propagate, or ripple, through this cascade, the configuration is called a ripple-
carry adder.

Figure-2: Logic for a single stage

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 Figure-3: An n-bit ripple-carry adder
Addition/Subtraction Logic Unit:
The n-bit adder can be used to add 2’s-complement numbers X and Y , where the xn−1 and yn−1 bits are
the sign bits.
In order to perform the subtraction operation X − Y on 2’s-complement numbers X and Y , we form
the 2’s-complement of Y and add it to X . The logic circuit shown in Figure-4 can be used to perform
either addition or subtraction based on the value applied to the Add/Sub input control line.
This line is set to 0 for addition, applying Y unchanged to one of the adder inputs along with a carry-
in signal, c0, of 0. When the Add/Sub control line is set to 1, the Y number is 1’s-complemented (that
is, bit-complemented) by the XOR gates and c0 is set to 1 to complete the 2’s-complementation of Y .
An XOR gate can be added to the Figure to detect the overflow condition cn ⊕ cn−1.

Figure-4: Binary addition/subtraction logic circuit.

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Design of Fast Adders:
If an n-bit ripple-carry adder is used in the addition/subtraction circuit of Figure-4, it may have too
much delay in developing its outputs, s0 through sn−1 and cn.
cn−1 is available in 2(n−1) gate delays, and sn−1 is correct one XOR-gate delay later. The final carry-out,
cn, is available after 2n gate delays. Therefore, if a ripple-carry adder is used to implement the
addition/subtraction unit shown in Figure-4, all sum bits are available in 2n gate delays, including the
delay through the XOR gates on the Y input.

Figure- 5: Computing the Add time

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Carry-Lookahead Addition:
A fast adder circuit must speed up the generation of the carry signals. The logic expressions
for si (sum) and ci+1 (carry-out) of stage i are

si = xi ⊕ yi ⊕ ci
and

ci+1 = xiyi + xici + yici

Factoring the second equation into

ci+1 = xiyi + (xi + yi)ci

we can write

ci+1 = Gi + Pici
where

Gi = xiyi and Pi = xi + yi
 The expressions Gi and Pi are called the generate and propagate functions for stage i.
 If the generate function for stage i is equal to 1, then ci+1 = 1, independent of the input carry ci .
This occurs when both xi and yi are 1.
 The propagate function means that an input carry will produce an output carry when either xi is
1 or yi is 1.
 All Gi and Pi functions can be formed independently and in parallel in one logic-gate delay
after the X and Y operands are applied to the inputs of an n-bit adder.
 Each bit stage contains an AND gate to form Gi , an OR gate to form Pi , and a three-input XOR
gate to form si .
A simpler circuit can be derived by observing that an adequate propagate function can be realized as
Pi = xi ⊕ yi , which differs from Pi = xi + yi only when xi = yi = 1. But, in this case Gi = 1, so it does
not matter whether Pi is 0 or 1. Then, using a cascade of two 2-input XOR gates to realize the 3-input
XOR function for si , the basic B cell in Figure-6 can be used in each bit stage.
Thus, all carries can be obtained three gate delays after the input operands X , Y , and c0 are applied
because only one gate delay is needed to develop all Pi and Gi signals, followed by two gate delays in
the AND-OR circuit for ci+1. After a further XOR gate delay, all sum bits are available. In total, the n-
bit addition process requires only four gate delays, independent of n.

Figure-6: Bit-stage cell

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Let us consider the design of a 4-bit adder. The carries can be implemented as

The complete 4-bit adder is shown in Figure-7. The carries are produced in the block labelled carry-
lookahead logic. An adder implemented in this form is called a carry-lookahead adder. Delay through
the adder is 3 gate delays for all carry bits and 4 gate delays for all sum bits. In comparison, a 4-bit
ripple-carry adder requires 7 gate delays for s3 and 8 gate delays for c4.

Figure-7: 4-bit Adder.

Multiplication of Unsigned Numbers:
The product of two, unsigned, n-digit numbers can be accommodated in 2n digits. In the binary system,
multiplication of the multiplicand by one bit of the multiplier is easy. If the multiplier bit is 1, the
multiplicand is entered in the appropriate shifted position. If the multiplier bit is 0, then 0s are entered,.
The product is computed one bit at a time by adding the bit columns from right to left and propagating
carry values between columns.

Figure-8: Manual Multiplication.

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Array Multiplier:
Binary multiplication of unsigned operands can be implemented in a combinational, two dimensional,
logic array, as shown in Figure-9 for the 4-bit operand case. The main component in each cell is a full
adder, FA. The AND gate in each cell determines whether a multiplicand bit, mj is added to the
incoming partial-product bit, based on the value of the multiplier bit, qi .
Each row i, where 0 ≤ i ≤ 3, adds the multiplicand (appropriately shifted) to the incoming partial
product, PPi, to generate the outgoing partial product, PP(i + 1), if qi = 1. If qi = 0, PPi is passed
vertically downward unchanged. PP0 is all 0s, and PP4 is the desired product.
The multiplicand is shifted left one position per row by the diagonal signal path. We note that the row-
by-row addition done in the array circuit differs from the manual multiplication, which is done column-
by-column.

Figure-9: Array implementation.

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  The worst-case signal propagation delay path is from the upper right corner of the array to the
high-order product bit output at the bottom left corner of the array.
 This critical path consists of the staircase pattern that includes the two cells at the right end of
each row, followed by all the cells in the bottom row. Assuming that there are two gate delays
from the inputs to the outputs of a full-adder block, FA, the critical path has a total of 6(n − 1) −
1 gate delays, including the initial AND gate delay in all cells, for an n × n array.
Sequential Circuit Multiplier:
The combinational array multiplier just uses a large number of logic gates for multiplying numbers
of practical size, such as 32- or 64-bit numbers. Multiplication of two n-bit numbers can also be
performed in a sequential circuit that uses a single n-bit adder.

Figure-10: Register configuration

The block diagram in Figure-10 shows the hardware arrangement for sequential multiplication. This
circuit performs multiplication by using a single n-bit adder n times to implement the spatial addition
performed by the n rows of ripple-carry adders in Figure-9.
Registers A and Q are shift registers, concatenated. Together, they hold partial product PPi while
multiplier bit qi generates the signal Add/Noadd. This signal causes the multiplexer MUX to select 0
when qi = 0, or to select the multiplicand M when qi = 1, to be added to PPi to generate PP(i + 1). The
product is computed in n cycles.
The carry-out from the adder is stored in flip-flop C, shown at the left end of register A.
At the start, the multiplier is loaded into register Q, the multiplicand into register M, and C and A are
cleared to 0. At the end of each cycle, C, A, and Q are shifted right one bit position to allow for growth
of the partial product as the multiplier is shifted out of register Q.

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After n cycles, the high-order half of the product is held in register A and the low-order half is in register
Q. The multiplication example of Figure-10 is shown in Figure-11 as it would be performed by this
hardware arrangement.

Figure-11: Multiplication Example.

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Booth Algorithm:
If the numbers are represented in signed 2’s complement then we can multiply them by using Booth
algorithm. The strings of 0's in the multiplier need no addition but just shifting, and a string of l's in the
multiplier from bit weight 2k to weight 2m can be treated as 2k+1 - 2m. For example, the binary number
001111 (+15) has a string of 1's from 23 to 20(k = 3, m = 0).
Booth algorithm needs examination of the multiplier bits and shifting of the partial product. Prior to
the shifting, the multiplicand added to the partial product, subtracted from the partial product, or left
unchanged by the following rules:
1. The multiplicand is subtracted from the partial product upon encountering the first least significant
1in a string of l's in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0 (provided that there
was a previous 1 in a string of 0's in the multiplier.
3. The partial product does not change when the multiplier bit is identical to the previous multiplier bit.

Figure-12: Hardware for booth algorithm

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 Figure-13: Flow Chart for Multiplication

Figure-14: Example of Multiplication with booth algorithm

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Integer Division:
A circuit that implements division by this longhand method operates as follows: It positions the divisor
appropriately with respect to the dividend and performs a subtraction.
If the remainder is zero or positive, a quotient bit of 1 is determined, the remainder is extended by
another bit of the dividend, the divisor is repositioned, and another subtraction is performed. If the
remainder is negative, a quotient bit of 0 is determined, the dividend is restored by adding back the
divisor, and the divisor is repositioned for another subtraction. This is called the restoring division
algorithm.

Figure-15: Circuit arrangement for binary division.

An n-bit positive divisor is loaded into register M and an n-bit positive dividend is loaded into register
Q at the start of the operation. Register A is set to 0. After the division is complete, the n-bit quotient
is in register Q and the remainder is in register A.
The required subtractions are facilitated by using 2’s-complement arithmetic. The extra bit position at
the left end of both A and M accommodates the sign bit during subtractions. The following algorithm
performs restoring division.
Do the following three steps n times:
1. Shift A and Q left one-bit position.
2. Subtract M from A, and place the answer back in A.
3. If the sign of A is 1, set q0 to 0 and add M back to A (that is, restore A); otherwise, set q0 to 1.

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 Figure-16: A restoring division example.
Non-Restoring Division:
The restoring division algorithm can be improved by avoiding the need for restoring A after an
unsuccessful subtraction. Subtraction is said to be unsuccessful if the result is negative.
Consider the sequence of operations that takes place after the subtraction operation in the preceding
algorithm. If A is positive, we shift left and subtract M, that is, we perform 2A− M. If A is negative,
we restore it by performing A+ M, and then we shift it left and subtract M. This is equivalent to
performing 2A+ M. The q0 bit is appropriately set to 0 or 1 after the correct operation has been
performed. We can summarize this in the following algorithm for non-restoring division.
Stage 1: Do the following two steps n times:
1. If the sign of A is 0, shift A and Q left one bit position and subtract M from A; otherwise, shift A
and Q left and add M to A.
2. Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
Stage 2: If the sign of A is 1, add M to A.
Stage 2 is needed to leave the proper positive remainder in A after the n cycles of Stage 1.

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 Figure-17: A non-restoring division example.

IEEE Standard for Floating Point Numbers

With a fixed-point notation (e.g., twos complement) it is possible to represent a range of positive and
negative integers centered on 0. By assuming a fixed binary or radix point, this format allows the
representation of numbers with a fractional component. as well.
We can represent a number in the form
±𝑆 × 𝐵 ±
This number can be stored in a binary word with three fields:
 Sign: plus or minus
 Significand S
 Exponent E

Figure-18: Typical 32-Bit Floating-Point Format

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The base B is implicit and need not be stored because it is the same for all numbers.
Figure-18 shows a typical 32-bit floating-point format. The leftmost bit stores the sign of the number
(0 = positive, 1 = negative). The exponent value is stored in the next 8 bits. The representation used is
known as a biased representation. A fixed value, called the bias, is subtracted from the field to get the
true exponent value. Typically, the bias equals (2k-1 - 1) where k is the number of bits in the binary
exponent. In this case, the 8-bit field yields the numbers 0 through 255.With a bias of (27 – 1) the true
exponent values are in the range -127 +128. In this example, the base is assumed to be 2.
The most important floating-point representation is defined in IEEE Standard 754, adopted in 1985.
The IEEE standard defines both a 32-bit single and a 64-bit double format (Figure-19), with 8-bit and
11-bit exponents, respectively.
The implied base is 2. In addition, the standard defines two extended formats, single and double, whose
exact format is implementation dependent. The extended formats include additional bits in the exponent
(extended range) and in the significand (extended precision). The extended formats are to be used for
intermediate calculations.

Figure-19: IEEE 754 Formats

Table-1: IEEE 754 Format Parameters

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Table-2 indicates the values assigned to various bit patterns. The extreme exponent values of all zeros
(0) and all ones (255 in single format, 2047 in double format) define special values. The following
classes of numbers are represented:
 For exponent values in the range of 1 through 254 for single format and 1 through 2046 for
double format, normalized nonzero floating-point numbers are represented. The exponent is
biased, so that the range of exponents is -126 through +127 for single format and -1022 through
+1023. A normalized number requires a 1 bit to the left of the binary point; this bit is implied,
giving an effective 24-bit or 53-bit significand (called fraction in the standard).
 An exponent of zero together with a fraction of zero represents positive or negative zero,
depending on the sign bit. As was mentioned, it is useful to have an exact value of 0 represented.
 An exponent of all ones together with a fraction of zero represents positive or negative infinity,
depending on the sign bit. It is also useful to have a representation of infinity. This leaves it up
to the user to decide whether to treat overflow as an error condition or to carry the value and
proceed with whatever program is being executed.
 An exponent of zero together with a nonzero fraction represents a denormalized number. In this
case, the bit to the left of the binary point is zero and the true exponent is -126 or -1022. The
number is positive or negative depending on the sign bit.
 An exponent of all ones together with a nonzero fraction is given the value NaN, which means
Not a Number, and is used to signal various exception conditions.

Table-2: Interpretation of IEEE 754 Floating-Point Numbers

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