Computer

Organization
(Solutions for Vol‐1_Classroom Practice Questions)

05. Ans: (d)

1. Computer Arithmetic
10
Sol: Implicit Normalized form is 1.11101×2
M = 11101000, e = 10 b = 64
01. Ans: (b) E = 74 = 1001010
Sol: 128 64 32 16 8 4 2 1 0100 1010 11101 000 = 4AE8
S
1 1 0 0 0 1 1 1 E M
0 –1 0 0 +1 0 0 –1
06. Ans: (b)
02. Ans: (d) Sol: Four number of carries are needed to design CLG
Sol: Sign extension is used for converting For C1, one AND gate + one OR gate
smaller size signed data to larger size by For C2, two AND gates + one OR gate
padding the sign bit to left. For C3, three AND gates + one OR gate
For C4, four AND gates + one OR gate are
03. Ans: (b) required
Sol: In given data EX-OR gate is not available so So total ten AND gates are needed and four
for one EX-OR gate 2 level network is OR gates are needed
needed because complemented and
un-complemented inputs are available. 07. Ans (a)
So, total delay = 2 + 2 + 2 = 6 Sol: S = 1e = Original Exponent
In the above, first 2 is for first EX-OR gate E = Biased Exponent, b = biasing amount
Second 2 is for CLG 14.25 = 1110.01  2 0 = 1.11001  2 3
Third 2 is for 2nd EX-OR gate e = 3, E = 3 + 127 = 130
130 = 10000010
04. Ans (d)
M = 1100100…0 (23 bits)
Sol: In non normalized form, 0.239  213 is
13
0.001111012 × 2 32 bits
e = 13, b = 64, so E = 77 = 1001101
M = 00111101 1100 0001 0110 0100 00........0
S = 1 bit E = 8 bits M = 23 bits
C 1 6 4 00......
0100110100111101 = 4D3D
S C1640000H
E M

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: 2 : Computer Organization

06. Ans: (c)
2. Memory Organization
Sol: T = 200 ns
 word frequency
Memory Basics
1
=  5  106 words / sec
200  10 9
01. Ans: (d)
Sol: A memory has 16 bit Address i.e. it’s
07. Ans: (a)
Starting Address = 0000H
Sol: ROM is used for function table with large
Ending Address = FFFFH
size because after program; ROM content is
 Maximum number of memory locations it
not possible to destroy and design cost is
can address is 216 = 64K
cheap.
= 64  1024
= 65536. 08. Ans: (c)
Sol: Remain same because it is non-volatile
02. Ans: (d) memory
Sol: Number of memory locations  size of one
location.
Cache Concept

03. Ans: (c)

01. Ans: (a)
Sol: DRAM needs refresh logic CKT to avoid
Sol: Physical Address = 32 bits
the discharge of capacitor but capacitor is
Cache size = 256 KB = 218 B
not needed in SRAM.
Associativity = 4
Block size = 16 B
04. Ans: (b)
Number of cache blocks = 218 B/24 B
Sol: 2048  8 = 211  8
= 214 = 16 K
 Number of Address lines = 11
214
Number of cache sets =  212
4
05. Ans: (a) 16 12 4
Sol: Number of chips needed 32

T arg et size
=
Basic size 02. Ans: (c)
Sol: Number of tag comparators needed
64  8
 = Associativity = 4
16  4
Size of each comparator
=8
= number of tag bits = 16
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03. Ans: (c) 08. Ans: (a)
Sol: Memory size = 4 K 16 = 212  16 Sol: Number of blocks = 256 KB/32B = 8 K
 Number of Address lines = 12 Number of Sets with 4-way set-associative
Data lines = 16 = 8 K/4 = 2 K
8 K(16+1+2+1)-bits =160 K-bits
04. Ans: (b)
Sol: Number of cache blocks = 2c
09. Ans: 20
Associativity = 2
Sol: Associativity = 4
Mapping expression is K mod S
Cache Size = 16 KB
Where, K = M.M block Number and
Block size = 8 words = 32 bytes
S = Number of cache sets
Number of Cache sets Word size = 32 bits
Number of cache blocks  Number of cache blocks
=
Associativity 16KB 214 B
=  5 = 29
2c 32B 2 B
c =
2 29
 Number of cache sets =  27
 K mod c 2 2

 Block size = 8  4 Bytes = 32 B = 25 B

05. Ans: 31
Sol: Word size = 16 bit, Physical Address size = 32 bits
So memory size = 231 words= 232 bytes Physical Address format:
= 4 GB
20 7 5
 31 address bits are needed.
Tag Offset Set Offset Byte Offset
32
06. Ans: (d)
Sol: Direct-Mapping
Total Blocks=256 10. Ans: (d)
Number of Tag bits = 19 Sol: If associativity is doubled, then number of
Tag Directory size = (19+1+1) × 256 tag bits will be increased and set offset size
= 5376 is reduced and size of MUX is directly
proportional to associativity only Physical
07. Ans: (c)
address size and Data bus size are not
256 KB
Sol: Number of cache blocks = = 213 altered.
32 B
Associativity = 4
11. Ans: (a)
213
Number of Sets = = 211 Sol: First cache organization: 32 KB with 2-way
4
set associative cache.
Tag size = 32 – 11 – 5 = 16.
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: 4 : Computer Organization

The size of address = 32 bits. Set 1 contains the blocks with │ main
memory block / 4│ = 1
Tag Set offset Word offset Set 2 contains the blocks with │ main
(18-bits) (9-bits) (5-bits)
memory block / 4│ = 2
Set 3 contains the blocks with │ main
Multiplexer latency = 0.6 ns and k-bit memory block / 4│ = 3
comparator latency is (K/10) ns Set 0: 0, 4, 8, 216, 48, 32, 92
The hit latency of this cache = 0.6 + (18/10) Set 1: 1, 129, 73
= 2.4 ns. Set 2:
Set 3: 255, 3, 159, 63, 155
12. Ans: (d) So 216 will not be in cache if LRU is used.
Sol: Second cache organization: 32 KB with
direct mapped cache. 15. Ans: (b)
The size of address = 32 bits. Sol: Physical Address formats for the given
Block number and Tag number 6 are
Tag Set offset Word offset
(17-bits) (10-bits) (5-bits) Tag Block work work Ranges
10 00 xxxx128 to 147
Only one TAG comparator & no. 10 01 xxxx144 to 159
multiplexer
00 10 xxxx32 to 47
The hit latency of this cache = (17/10)
01 11 xxxx112 to 127
= 1.7 ns.
128 64 32 16 8421

13. Ans: (b)  150 and 132 are available

Sol:
Tag set word 16. Ans: (b)
6 6 4
Sol: Cache accepts only 8 blocks and it uses
LRU.
16
H = Hit, M = Miss Block arrival Address
 Number of tag bits = 6 0 4 45
1 3 22
2 25
14. Ans: (d) 3 8
Sol: The cache consists of 4 sets with each set 4 19 3
5 6 7
consists of 4 blocks. 6 16
Set 0 contains the blocks with │ main 7 35

memory block / 4│ = 0 Cache Block number 5 consists 7

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17. Ans: (c) 21. Ans: (a)
Sol: All blocks are mapped to set 0 only, but Sol: The lines 4 to 11 gets conflict misses
each set permits only 2 blocks frequently.

Total Number of misses= 4 22. Ans: 24

8 12 0 12 8 Sol: Cache
M M M H M
Tag 219 Bytes

18. Ans: 14
40
Sol: HC + (1 – H)M = (0.8  5) + (0.2  50)
It uses 8 way set associative
= 14 ns
 Tag size = 24 bits.
19. Ans: (a)
Sol: Final Tag
Tag Line offset Word offset
Tag 3 216
1110 001000000001 1111
21
40
Tag = E16 line = 20116

23. Ans: 76
20. Ans: (c)
Sol: When a block is referred first time in cache
Sol: The cache and main memory are divided
memory, it is known as compulsory miss
into blocks of 64 bytes each. The direct
and it will be loaded in the cache memory,
mapped cache consists of 32 blocks (mod
when a same block is referred in future i.e.
block i/32). The array is stored from main
2nd time onwards; then it is considered as
memory locations 1100 H. The array is
conflict miss.
placed in MM from 68 Block onwards. The
For first iteration, 4 conflict misses and for
total array consists of 2500 bytes, so they
each iteration from 2nd time onwards
require a total of 40 blocks. In the cache all
8 conflict misses occur.
the 32 blocks are filled and the remaining 8
Total number of conflict misses occur for
blocks are replacing the previous blocks. A
10 times = 4+ (89) = 76.
total of 40 data misses will occur during first
access. During the second access once again Conflict misses in first iteration
the 16 blocks are replaced for conflict 0, 128, 256, 128, (0), 128, (256), 128, 1,
misses, so 16 cache misses occur.
129, 257, 129, (1), 129, (257), 129.
Total numbers of cache misses
Total 4 times
= 40 + 16 = 56

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: 6 : Computer Organization

Conflict misses in second time iteration
3. Pipeline Organization
(0), 128, (256), 128, (0), 128, (256), 128,
(1), 129, (257), 129, (1), 129, (257), 129,
Total 8 times 01. Ans: (c)
Sol: Max. stage delay = 160 s
24. Ans: 59 Buffer delay = 5 s
Sol: Number of rows in a chip = 214 = 16384 Pipeline clock = 165 s
One refresh time = 50  10–9 sec T1000 = (K + n – 1) Tp clock
Chip refresh time = 16384  50  10–9 sec  165 495 
= (4+999) * 165 =   s
= 819200  10–9 sec  1000 
= 0.8192 msec = 165.5 s
Given refresh period = 2 msec
02. Ans: (d)
Amount of time required for RD/WR Sol: (i) The (j+1)th instruction uses the result of
operation the jth instruction as an operand,
comes under data dependency and it
= 2 – 0.8192
causes data hazard. (RAW).
= 1.1808 msec (ii) The execution of a conditional jump
Amount of time used for RD/WR operation instruction comes under conditional
in percentage dependency and it causes control
hazard.
1.1808 m sec
  100  59.04 (iii) The jth and j +1 instruction require the
2 m sec
ALU at the same time comes under
 Closest integer value = 59 structural hazard. (WAR).

03. Ans: (c)

25. Ans: (b)
Sol: Number of bits required for addressing a 04. Ans: (c)
byte in physical memory = P Sol: 2 Stall cycles
Number of bits required for addressing a CPU clock frequency = 1GHz
byte in cache = N Out of 109 instructions 20% of instructions
In Direct Map, Tag field size = P – N are branch instructions, which requires 3
In K-way Block Set Associative mapping, clock cycles. The remaining 80%
instructions require only one clock pulse for
Tag field size = (P – N) + log 2 K
their completion.
Total execution time
=109(80/100)10–9+109(20/100)3 10 9
= 0.8 + 0.6 = 1.4 sec
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05. Ans: 33.33
Sol: Old pipeline maximum delay = 800 ns
New pipeline maximum delay = 600 ns
800 : 600 = 4:3
43
Increasing throughput   33.33%
3

06. Ans: (b)

Sol:
1 2 3 4 5 6 7
IF ID OF PO WO
MUL
R0, R1 R0 * R1 R2 8 9 10 11 12 13
IF ID OF PO WO
DIV
R3, R4 R3/R4 R5 14
IF ID OF PO WO
ADD
R2 R2 15
SUB IF ID OF OF R2 PO WO

07. Ans: (b) 09. Ans: (d)

Sol: Non-pipelined system delay = 30 ns Sol: Number of stages = 5
Max. Pipeline delay = 12 ns One stage delay = 2 ns
S = 30 ns / 12 ns = 2.5  While executing more number of
instructions only one stage delay is
08. Ans: (b) sufficient for executing one instruction
when there is no Hazard.
Sol: Pipeline clock = Max (stage delay + Overhead)
 Number of Non Hazard instructions
= Max (5,7, 10, 8, 6) + 1 = 11ns
= 80%
CPU gets target address after completion of
 it’s Average time = 0.8  2 ns = 1.6 ns
branch instruction in EX stage only. For executing one Hazard instruction it takes
(n+k–1)  11ns + stall delay (3) all stage delays i.e., 10 ns.
= ((8 + 5 – 1)  11ns) + (3  11)ns  It’s average time is 0.2  10 ns = 2 ns
= 165 ns Average instruction time
= 1.6 ns + 2 ns = 3.6 ns
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: 8 : Computer Organization

10. Ans: (c) Only one clock cycle time is sufficient to
Sol: Let total number of instructions = 100 execute one instruction.
Non branch time = 80  2 = 160 ns S  tn
tp
Total Branch instructions = 20% = 20
In 20; 80% are conditional and remaining  1.6 ns  3.2
0.5 ns
20% are unconditional 20  20 % = 4.
It’s time = 4  10 ns = 40 ns 14. Ans: 13
Time needed for 50% instructions, Branch Sol:
20  4
taken =  8  2 ns = 16 IF OF PO WB
2
MUL 1 2 5 6
Time needed for 50% instructions, Branch
DIV 2 3 10 11
not taken = 8  10 ns = 80 ns
ADD 3 4 11 12
Total time = 160 + 40 + 80 + 16 = 296 ns
SUB 4 5 12 13
 Average time = 2.96 ns.

15. Ans: (b)

11. Ans: (c)
Sol: It is also known as W.A.R Hazard.
S
Sol: Efficiency  Anti-dependence Hazard creates Hazard
K
Where S = speed up, K = number of stages (i.e. needs stall) when a low latency
S instruction is completed before a longer
K
efficiency latency instruction that appears earlier in the
program only BUT NOT ALWAYS.
 6 .6  7 .5
.88
So, minimum 8 stages are needed 16. Ans: 4
Sol: For ‘n’ number of instructions
12. Ans: (c) tn = 6  n clks ( k = 6).
Highest speed up k = 6 if there is no stall
13. Ans: 3.2 cycle and all stage delays are equal but
Sol: Non-pipeline CPU frequency = 2.5 GHz 25% of instructions need 2 stalls.
T = 0.4 ns tp = (0.75 n  1) + ( 0.25 n  (2 + 1))
 One instruction time = 4  0.4 ns =1.5 n clks.
tn = 1.6 ns tn 6 n clks
S= = 4
Pipeline CPU frequency = 2 GHz tp 1.5 n clks
 T = 0.5 ns = tp
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17. Ans: (c) 19. Ans: (b)
Sol: f  1/T Sol: For D1 processor, maximum Tseg = 4 ns,
Minimum clock time gives highest clock n = 100, k = 5
frequency for the given pipelined processor.
Time = 104  4 ns = 416 ns
For P1 Largest clock time is 2 ns.
For P2 Largest clock time is 1.5 ns.
For P3 Largest clock time is 1 ns. For D2 processor,
For P4 Largest clock time is 1.1 ns. n = 100, k = 8, Tseg = 2 ns
So, P3 gives highest peak clock frequency. Time = 107  2 ns = 214 ns
Hence, 202 ns time will be saved
18. Ans: 1.54
Sol: ‘P’ has 5 stages
20. Ans: (b)

IF ID/RF EX MEM WB Sol: tn = 12 ns, maximum Tseg = 6 ns

 S = tn / t p = 2
1 2.2 2 1 0.75 ns
‘Q’ has 8 stages
21. Ans: 1.51
IF ID RF1 RF2 EX1 EX2 MEM WB
Sol: For Naive pipelined CPU
1 2.2/3 2.2/3 2.2/3 1 1 1 0.75 K = 5, Tseg = 20 + 2 = 22 ns, n = 20.

P - highest clock cycle time = 2.2 ns. Total time needed for 20 instructions
Q - highest clock cycle time = 1 ns. = (5 + 20 –1)  22 ns = 24  22 ns
In ‘P’ pipeline new instruction fetching is
= 528 ns
stopped for 2 stage delays
Where in ‘Q’ pipeline new instruction For Efficient pipelined processor
fetching is stopped for 5 stage delays Tseg = 12 + 2 = 14 ns; k = 6, n = 20
Number of branch instructions = 20%.
Total time for 20 instructions
 ‘P’ total time is (0.8  2.2 ns)
(6 + 20 – 1)  14 ns = 350 ns.
+ (0.2  (2 +1))2.2 ns = 3.08 ns
‘Q’ total time is 0.8  1 ns tn 528
Speed up = =
te 350
+ (0.2 (5+1)) 1 ns = 2 ns
P 3.08 ns = 1.50857
 =
Q 2 ns  1.51
= 1.54.
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: 10 : Computer Organization

22. Ans: 219 03. Ans: (d)
Sol: Number of stages = 5(IF, ID, OF, PO, WR), Sol: The given program is:
k=5 Instruction
n = 100, except PO, all stages take one clock Instruction Operation Size
In P.O stage (No. of words)
40 instructions take 3 clocks MOV R1,(3000) R1←M[3000] 2
LOOP:
35 instructions take 2 clocks R2←M[R3] 1
MOV R2,(R3)
and remaining 25 instructions take 1 clk ADD R2, R1 R2←R2+R1 1
If all instructions requires one clock in all MOV(R3), R2 M[R3]←R2 1
stages, total clocks required = (k + n – 1) INC R3 R3←R3+1 1
= 5 + 100 – 1 = 104 DEC R1 R1←R11 1
But, 40 instructions requires 3 clocks each Branch on not
BNZ LOOP 2
i.e. 40 instructions execution requires '80' zero
HALT Stop
more clocks and 35 instructions requires 2
clocks i.e. 35 instructions required 35 more
Let the data at memory 3000 is 10.
clocks.
So, total number of clocks required The contents of R3 are 2000.
= 104 + 80 + 35 = 219 The content of memory locations from 2000
to 2010 is 100.
4. CPU Organization The number of memory references for
accessing the data is
01. Ans: (b) Instruction Operation No. of memory references
Sol: The Value in register A is rotated through MOV R1(3000) R1←M[3000] 1

right 8 times. During each rotation MOV R2, (R3) R2←M[R3] 10(Loop is repeated 10 times)

operation, if carry flag is set the value of MOV (R3), R2 M[R3]←R2 10 (loop is repeated 10 times)
register B is incremented. After 8 rotations
B register contains the number of 1’s in Total number of memory references are: 21
register A.
04. Ans: (a)
02. Ans: (a)
Sol: As the memory locations are incremented 10
Sol: Extending the previous question, if the
times from 2000 to 2009, when the loop is
contents of register A is rotated right once
again, and then register A will retain its terminated R3 consists of 2010, whose value
value. Therefore the instruction at X will be will be 100(previous value) only.
RRC A, #1.

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05. Ans: (c) 07. Ans: (c)
Sol: The program is loaded from memory Sol: Stack works on LIFO.
location 1000 onwards. The word size is 32
bits and the memory is byte addressable. 08. Ans: (b)
Word Sol: Relative Addressing mode is used to
Address Instruction
size
relocate the program from one memory
1000 to 1007 MOV R1, (3000) R1←M[3000] 2
segment to other segment–without–change
1008 to 1011 LOOP: MOV R2, (R3) R2←M[R3] 1
in code so, it is knows as Position
1012 to 1015 ADD R2, R1 R2←R2+R1 1
Independence Addressing mode.
1016 to 1019 MOV(R3),R2 M[R3]←R2 1

1020 to 1023 INC R3 R3←R3+1 1

09. Ans: (c)
1024 to 1027 DEC R1 R1←R11 1

1028to 1035 BNZ LOOP Branch on not zero 2

10. Ans: (b)
1036 to 1039 HALT Stop 1
Sol: In instruction execution cycle, to get the first
If the interrupt occurs at INC R3 instruction, operand through index addressing mode it
then first the instruction is executed and the takes one machine cycle. To get the second
program counter consists of 1024, which is operand through indirect addressing mode
stored in stack. (B), it takes two more machine cycles
because B is the address.
06. Ans: (d) After the addition is completed the result is
Sol: Opcode size = 13-bit needed to send to the destination by using
the index addressing mode, which requires
Control memory size = 7-bit
one more machine cycle.
= 128 word = 27
So a total of four machine cycles are
Maximum number of one address
required to execute the above instruction.
instructions to be formulated
(Except fetch cycle)
operation Address
6 7 11. Ans: (d)
13 Sol: R1  M (100)
M(100)  R2
6
= 2 = 64 M(100)  R3
 Remaining number of zero address The above instructions are used for
instructions to be formulated transferring R1 content to R2 and R3 through
= (64 – 32)  27 memory address 100.
= 4096 So, option ‘d’ is correct.

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: 12 : Computer Organization

12. Ans: (a) Instruction Opcode size is 32-bits.
Sol: Address field in the instruction is used to Number of supporting Instructions = 45, so
specify Memory Address or One of the minimum 6 bits are needed.
processor Register Address. Instruction is having with operation part,
For example to specify R5 in a processor Reg1, Reg2 and Immediate operand
which is having 16 bit Register from R0 to
R15, it’s Address field is ‘0101’, and for 6 6 6 14
implied Register; no address is specified in Operation R1 R2 Immediate Operand
the instruction. 32
The Range of unsigned operand with 14-bit
13. Ans: (d)
Sol:  Stack grows upword means SP is is 0 to 214–1
incremented for PUSH operation and  Max unsigned integer is 16383.
decremented for POP operation.
17. Ans: (d)
 One Memory location can store only
Sol: Max. number of two address instructions = 24.
one word (i.e., one byte)
When it uses only ‘n’, two address
 After ‘CALL’ execution; to store PC
instructions then remaining (24 – n) with ‘6’
and PSW content; SP is incremented by
bit combinations are used for one address
‘4’
instructions.
016E16 + 4 = (0172)H
 Max. number of one address instructions:
(24 – n) × 26
14. Ans: (a)
Sol: Non-pipelined system requires 18. Ans: 16
(2+2+1+1+1)500+2 = 3502 cycles Sol:
DMA clock need = 20 + (2  500) 32

= 1020 cycles
Operation A1 A2 Operand
Speed up = 3502/1020 = 3.44
log2 40 log2 24 log2 24
15. Ans: (d) 6 5 5 xxx
Sol: Here R 2 will act as base or indexed register
and 20 is the displacement.  32 – 16 = 16

16. Ans: 16383 19. Ans: 500

Sol: Word size = 32 bit Sol: One instruction needs 34 bits,
Number of CPU Registers = 64 = 26 So number of bytes needed = 5
So, for addressing a Register 6 bits are Program size = 100
needed.
 Size of the memory in bytes = 500
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20. Ans: –16
5. Control Unit Design
Sol: While executing the i + 3 instruction, the PC
content will be the starting address of the
i+4. If the target of the branch instruction is 01. Ans: (d)
‘i’ then processor takes 4 instructions
addresses back (Backward jump) 02. Ans: (a, b, c, d)
Hence the displacement value is –4*4 =– 16,
because each instruction opcode size is 03. Ans: (d)
4 bytes. Sol: To execute interrupt cycle, the present
content of PC will be pushed to stack with
21. Ans: (d) the help of MBR and MAR before placing
Sol: Max one Address instruction = 26 = 64 ISR address in PC. (Always only MAR and
But number of one addresses instructions
MBR are used to address in Basic
used = 32.
computer).
Max Number of zero Addresses instructions
04. Ans: (a)
= 32  128 = 4096
Sol: Total Size of micro-instructions = 26 bits

22. Ans: (c) Size of micro-operation = 13 bits

Sol: If 63 one address instructions are used then Total inputs for the multiplexer (Status bits)
Number of zero addressing instructions inputs = 8
= (64 – 63)  128 = 128 So the multiplexer selection lines field(Y)
= 3 bits (23 = 8)
23. Ans: (a)
The number of bits in the next address field
Sol: After issuing an interrupt, while processing
size(X) = 13 – 3 = 10 bits
L is under execution.
Processor follows the below steps: Size of control memory = 210 = 1024
Step 1: Completion of current instruction
execution 05. Ans: (d)
Step 2: Pushes the result of the current Sol: S8 = I1T4 + I2T4 + I3T4 + I4T4
instruction status on stack = I  T4 = T4
Step 3: Gets the new address to PC for  I  ( I1  I 2  I 3  I 4 )
starting ISR and executes the ISR.
S7 = (I1T3 + I2T3+I3T3+I4T3)
Step 4: Pops the status from stack to
continue the interrupted + (I3T1 + I3T2+ I3T3 + I3T4)+(T4I3+T4I4)
instruction.  S7 = T3 + I3 + T4  I4
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: 14 : Computer Organization

06. Ans: (b) 05. Ans: (b)
Sol: Fastest Control unit is hard-wired control Sol: In single line interrupt system contains a single
unit and vertical micro-programming control interrupt request line and an interrupt grant
unit is slowest. line. In this system it may be possible for
more than one I/O device request interrupt at
07. Ans: (d) the same time. By using 8259 IC it is possible to
connect more number of IO devices. So in
08. Ans: (d) single interrupt system vectored interrupts are
Sol: All the given characteristics are belonging to not possible but multiple interrupting devices
RISC processor. are possible

6. I/O Organization 06. Ans: (b)

Sol: 10 KBPS = 10 KB is transferred in 1 sec = 104 B
1 byte takes = 0.1 ms = 100 µs
01. Ans: (b) Minimum waiting time needed is 100 µs
Sol: For vectored hardware interrupt, the for system
interrupting device supplies the respective Programmed I/O takes 100 s
address with additional hardware. Interrupt driven takes 4 s
100 s
02. Ans: 456 Gain =  25
4 s
Sol: Terminal Count Register size = 16 bit.
So, for one transfer operation of 64 KB, the
07. Ans: (d)
register content will become zero, so,
Sol: CPU first takes care about it’s temperature.
number of times the content of the register
to be filled is
29154 KB
 456
64 KB

03. Ans: (b)

04. Ans: (a)

Sol: CPU gives highest priority for high speed
devices and least priority for low speed
devices. Hard disk has higher priority than
others because it is fastest secondary
memory.
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: 15 : CSIT‐Postal Coaching Solutions

03. Ans: (c)
7. Secondary Memories
Sol: The address (400,16,29) corresponds to the
Sector number
01. Ans: (P = 12.5), (Q = 2500000) =(cylinder number×number of sectors/cylinder)
+(surface number×number of sectors/track)
Sol: T = 200, RPM = 2400, RPS = 40
+ Present sector number
Track capacity = 62500 bits = (400 × 20 × 63) + (16 × 63) + 29
One revolution time is 25 ms = 505037
 Average latency time = 12.5 ms
04. Ans: (c)
 P = 12.5 ms
1039
Q = Data Transfer rate = no.of bits/sec. Sol: : 0th cylinder
63  20
In one second it can complete 40 tracks. 1039
: 16th surface and remainder gives
 Q = 40 × 62500 bits/sec 63
sector number: 31 (0, 16, 31)
= 2500000 bits/sec

05. Ans: (b)

02. Ans: (d) Sol: Given seek time = 10 ms
Sol: Transfer rate = 10 K.K bytes/sec RPM = 6000, RPS = 100.
For 10K bytes it takes 1 msec One revolution takes 10 ms
 Average rotational Delay = 5 ms
For 20K bit takes = 2 ms
Transfer delay is neglected.
CPU frequency is 600 MHz,
Taccess/one library = tseek+ t rotational+t transfer
10 6 10 = 10 ms + 5 ms + 0
T=  ns
600 6 = 15 ms
For initializing it takes 300 clk So, for 100 libraries loading;
it takes (15 ms × 100) = 1500 ms
10
= 500 ns (  300) = 1.5 sec
6
10 06. Ans: (d)
For completing 900 clk = 1500ns (  900)
6
Sol: Size of the data to be transferred=42,797 KB
Total CPU time is 2000ns = 2 s One sector capacity = 512 B
Processor consumes 2 s for each 2 msec. Number of Sectors to store 42797 KB
 In percentage it is 0.1% 42797  1024
=  85,594
512
One cylinder has 64 ×16 = 1024 sectors

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: 16 : Computer Organization

83 cylinders can store 83 × 1024 08. Ans: 6.1
= 84,992 sectors Sol: Transfer rate = 50  106 Bytes/sec
 Remaining number of sectors = 602 So, 0.5 KB takes 0.1 ms
602 sectors occupy more than half of one RPM = 15000; RPS = 250
cylinder capacity 1 rotation takes 4 milliseconds
But the given cylinder has started with Average rotational delay is 2 ms;
<1200, 9, 40> means more than half of that Seek time is 4 ms
cylinder, so next cylinder is also needed for  Average time = transfer time + seek time
storing complete data. + rotational delay
 Last cylinder number = 0.1 ms + 4 ms + 2 ms
= 1200 + 83 + next one = 6.1 ms
= 1284

07. Ans: 14020

Sol: Seek time = 4 milli seconds per each sector
Reading
RPM = 10000 i.e.,
1 Track rotation time = 6 ms
 Average rotational delay is 3 ms.
One Track has 600 sectors.
So, one sector transfer time is
6 ms
 0.01 ms
600
 One sector Access time = 0.01 + 4 + 3
= 7.01 ms
So, 2000 sectors time = 2000  7.01
= 14,020 ms

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