10292020214439ECET Computer Science - 2020
10292020214439ECET Computer Science - 2020
Computer Science
1) Simplest Registers only consists of
(A) Counter (B) EPROM (C) latch (D) flip-flop
Solution: (D)
2) Which of the following is a Universal Gate?
(A) AND gate (B) OR gate (C) NAND gate (D) NOR gate
Solution: (C)
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3) (𝑥 ′ ) is a
(A) complement (B) dual complement (C) reflection (D) duality
Solution: (D)
4) A Multiplexer is also called as a
(A) Coder (B) parallel adder (C) Data selector (D) NOR gate
Solution: (C)
5) A Binary variable can take the values
(A) 0 only (B) 0 and -1 (C) 0 and 1 (D) 1 and 2
Solution: (C)
6) (1010.011)2 =
(A) (10.365)10 (B) (10.375)10 (C) (11.365)10 (D) (11.375)10
Solution: (B)
7) Each square in a Karnaugh map represents a
(A) Point (B) value (C) minterm (D) maxterm
Solution: (C)
8) Circuit whose output depends on directly present input is called
(A) combinational circuit (B) sequential circuit
(C) combinational sequence (D) series
Solution: (A)
9) The purpose of the microprocessor is to control _______________
(A) Processing (B) Memory (C) Switches (D) Tasks
Solution: (B)
10) If segment address = 1005H, offset address = 5555H, then the physical address is __________
(A) 155AH (B) 4550H (C) 155A5H (D) 56555H
Solution: (C)
11) Which of the following instruction is not valid?
(A) MOV AX,BX (B) MOV AX,500 (C) MOV DS,5000H (D) PUSH AX
Solution: (C)
12) The addressing mode that is used in unconditional branch instruction is
(A) Intra segment direct addressing mode
(B) Intra segment indirect addressing mode
(C) Intra segment direct and indirect addressing mode
(D) Inter segment direct addressing mode
Solution: (B)
13) During comparison operation, the result of comparing or subtracting is stored in
(A) Memory (B) Registers (C) Stack (D) no where
Solution: (D)
14) The BIU contains FIFO register of size 6 bytes is called as
(A) Queue (B) Stack (C) Segment (D) Register
Solution: (A)
15) The fetching of the program from secondary memory to place it in physical memory during the executing
of CPU is called ________________
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(A) Mapping (B) swapping in (C) swapping out (D) pipelining
Solution: (B)
16) The instruction “JUMP’” belongs to
(A) sequential control flow instructions (B) data transfer instructions
(C) branch instructions (D) control transfer & branch instructions
Solution: (D)
17) The first processor with an inbuilt floating point unit is ______________
(A) 80386 (B) 80486 (C) 8086 (D) 80286
Solution: (B)
18) Which group of instructions do not affect the flags?
(A) Arithmetic operations (B) Logic operations
(C) Branch operations (D) Data transfer operations
Solution: (D)
19) The delay between the time an interrupt request is received and the start of executing of the Interrupt
service routine is called _________________
(A) Interrupt latency (B) Interrupt back (C) Interrupt hold (D) Interrupt service
Solution: (A)
20) The DMA controller may be given exclusive access to the main memory to transfer a block of data without
interruption is known as ________________
(A) Block (or) burst mode (B) Stealing mode
(C) Bus master (D) Bus slave
Solution: (A)
21) The addressing mode which makes use of in-direction pointers is
(A) Indirect addressing mode (B) Index addressing mode
(C) Relative addressing mode (D) Offset addressing mode
Solution: (A)
22) What is the highest speed memory between the main memory and the CPU called?
(A) Register memory (B) Cache memory
(C) Storage memory (D) Virtual memory
Solution: (B)
23) Which one of the following can produce the final product of machine processing in a form usable by
humans
(A) Storage (B) Control (C) Input device (D) Output device
Solution: (D)
24) In the case of, Zero-address instruction method the operands are stored in -----------
(A) Registers (B) Stack (C) Accumulators (D) Cache
Solution: (B)
25) The memory which is used to store the copy of data (or) instructions stored in larger memories inside the
CPU is called ______________
(A) Level 1 cache (B) Level 2 cache (C) Registers (D) TLB
Solution: (A)
26) In the following indexed addressing mode instruction, MOV 5(R1), LOC the Effective Address is
(A) EA = 5+R1 (B) EA = R1 (C) EA = [R1] (D) EA = 5 + [R1]
Solution: (D)
27) Which technique is preferable for transferring a large amount of data to and from a memory in a short
time
(A) DMA (B) Interrupt Driven I/o
(C) Programmed I/o (D) BUS
Solution: (A)