MIC502

Fan Management IC

General Description Features

The MIC502 is a thermal and fan management IC which • Temperature-proportional fan speed control
supports the features for NLX/ATX power supplies and • Low-cost, efficient PWM fan drive
other control applications.
• 4.5V to 13.2V IC supply range
Fan speed is determined by an external temperature
• Controls any voltage fan
sensor, typically a thermistor-resistor divider, and (option-
ally) a second signal, such as the NLX “FanC” signal. The • Overtemperature detection with fault output
MIC502 produces a low-frequency pulse-width modulated • Integrated fan startup timer
output for driving an external motor drive transistor. Low- • Automatic user-specified sleep mode
frequency PWM speed control allows operation of • Supports low-cost NTC/PTC thermistors
standard brushless dc fans at low duty cycle for reduced
acoustic noise and permits the use of a very small power • 8-pin DIP and SOIC packages
transistor. The PWM time base is determined by an
external capacitor. Applications
An open-collector overtemperature fault output is asserted
• NLX and ATX power supplies
if the primary control input is driven above the normal
control range. • Personal computers
The MIC502 features a low-power sleep mode with a user- • File servers
determined threshold. Sleep mode completely turns off the • Telecom and networking hardware
fan and occurs when the system is asleep or off (both • Printers, copiers, and office equipment
control inputs very low). A complete shutdown or reset can
• Instrumentation
also be initiated by external circuitry as desired.
• Uninterruptible power supplies
The MIC502 is available as 8-pin plastic DIP and SOIC
packages in the –40°C to +85°C industrial temperature • Power amplifiers
range.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
___________________________________________________________________________________________________________

Typical Application
12V

T1 R1 Fan
MIC502
1 8
VT1 VDD RB A S E
2 7
R3 R2 CF OUT Q1
3 6
V S L P OT F
4 5
R4 GND VT2
Overtemperature
CF Fault Output

Secondary
Fan-contro l
Input

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

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Ordering Information
Part Number Temperature Range Package Lead Finish
MIC502BN –40° to +85°C 8-Pin Plastic DIP Standard
MIC502YN –40° to +85°C 8-Pin Plastic DIP Pb-Free
MIC502BM –40° to +85°C 8-Pin SOIC Standard
MIC502YM –40° to +85°C 8-Pin SOIC Pb-Free

Pin Configuration

VT1 1 8 VDD

CF 2 7 OUT

VSLP 3 6 OTF
GND 4 5 VT2

8-Pin SOIC (M)

8-Pin DIP (N)

Pin Description
Pin Number Pin Name Pin Function
1 VT1 Thermistor 1 (Input): Analog input of approximately 30% to 70% of VDD
produces active duty cycle of 0% to 100% at driver output (OUT). Connect to
external thermistor network (or other temperature sensor). Pull low for shutdown.
2 CF PWM Timing Capacitor (External Component): Positive terminal for the PWM
triangle-wave generator timing capacitor. The recommended CF is 0.1µF for
30Hz PWM operation.
3 VSLP Sleep Threshold (Input): The voltage on this pin is compared to VT1 and VT2.
When VT1 < VSLP and VT2 < VSLP the MIC502 enters sleep mode until VT1 orVT2
rises above VWAKE. (VWAKE = VSLP + VHYST). Grounding VSLP disables the sleep-
mode function.
4 GND Ground.
5 VT2 Thermistor 2 (Input): Analog input of approximately 30% to 70% of VDD
produces active duty cycle of 0% to 100% at driver output (OUT). Connect to
motherboard fan control signal or second temperature sensor.
6 /OTF Overtemperature Fault (Output): Open-collector output (active low).Indicates
overtemperature fault condition (VT1 > VOT) when active.
7 OUT Driver Output: Asymmetrical-drive active-high complimentary PWM output.
Typically connect to base of external NPN motor control transistor.
8 VDD Power Supply (Input): IC supply input; may be independent of fan power supply.

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Absolute Maximum Ratings(1) Operating Ratings(2)

Supply Voltage (VDD)....................................................+14V Supply Voltage (VDD)....................................... +4V to 13.2V
Output Sink Current (IOUT(sink)) .....................................10mA Sleep Voltage (VSLP).......................................... GND to VDD
Output Source Current (IOUT(source)) ..............................25mA Temperature Range (TA)............................. –40°C to +85°C
Input Voltage (any pin) .......................... –0.3V to VDD +0.3V Power Dissipation at 25°C
Junction Temperature (TJ) ....................................... +125°C SOIC ..................................................................800mW
Lead Temperature (soldering, 5 sec.)........................ 260°C DIP.....................................................................740mW
Storage Temperature (TA).........................–65°C to +150°C Derating Factors
ESD Rating(3) SOIC ..............................................................8.3mW/°C
Plastic DIP .....................................................7.7mW/°C

Electrical Characteristics
4.5V ≤ VDD ≤ 13.2V, Note 4; TA = 25°C, bold values indicate –40°C ≤ TA < +85°C, unless noted.
Symbol Parameter Condition Min Typ Max Units
IDD Supply Current, Operating VSLP = GND, OTF, OUT = open, 1.5 mA
CF = 0.1µF, VT1 = VT2 = 0.7 VDD
IDD(slp) Supply Current, Sleep VT1 = GND, VSLP, OTF, OUT = open, 500 µA
CF = 0.1µF
Driver Output
tR Output Rise Time, Note 5 IOH = 10mA 50 µs
tF Output Fall Time, Note 5 IOL = 1mA 50 µs
IOL Output Sink Current VOL = 0.5V 0.9 mA
IOH Output Source Current 4.5V ≤ VDD ≤ 5.5V, VOH = 2.4V 10 mA
10.8V ≤ VDD ≤ 13.2V, VOH = 3.2V 10 mA
IOS Sleep-Mode Output Leakage VOUT = 0V 1 µA
Thermistor and Sleep Inputs
VPWM(max) 100% PWM Duty Cycle Input 67 70 73 %VDD
Voltage
VPWM(span) VPWM(max) – VPWM(min) 37 40 43 %VDD
VHYST Sleep Comparator Hysteresis 8 11 14 %VDD
VIL VT1 Shutdown Threshold 0.7 V
VIH VT1 Startup Threshold 1.1 V
VOT VT1 Overtemperature Fault Note 6 74 77 80 %VDD
Threshold
IVT, IVSLP VT1, VT2, VSLP Input Current –2.5 1 µA
tRESET Reset Setup Time minimum time VT1 < VIL, to guarantee reset, 30 µs
Note 5
Oscillator
f Oscillator Frequency, Note 7 4.5V ≤ VDD ≤ 5.5V, CF = 0.1µF 24 27 30 Hz
10.8V ≤ VDD ≤ 13.2V, CF = 0.1µF 27 30 33 Hz
fMIN, fMAX Oscillator Frequency Range Note 7 15 90 Hz
tSTARTUP Startup Interval 64/f S

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Symbol Parameter Condition Min Typ Max Units

Overtemperature Fault Output
VOL Active (Low) Output Voltage IOL = 2mA 0.3 V
IOH Off-State Leakage V/OTF = VDD 1 µA
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Part is functional over this VDD range; however, it is characterized for operation at 4.5V ≤ VDD ≤ 5.5V and 10.8V ≤ VDD ≤ 13.2V ranges. These ranges
correspond to nominal VDD of 5V and 12V, respectively.
5. Guaranteed by design.
6. VOT is guaranteed by design to always be higher than VPWM(max).
0.1µF
7. Logic time base and PWM frequency. For other values of CF, f(Hz) = 30Hz , where C is in µF.
C

Timing Diagrams

VO T
0.7VDD 100%
VT 1 80% Input
70% Signal
VT 2
50% Range
40% 40%
VS L P 30%

0.3VDD 0%

VIH
VIL
0V

VO H
VO T F
VOL
0V

F
A tPW M B C D E tS T A R T U P G
VO H
VOU T
VOL
0V Output
50% 80% 40% 70% 0% 100% 40% Duty Cycle

Figure 1. Typical System Behavior

Note A. Output duty-cycle is initially determined by VT1, as it is greater than VT2.

Note B. PWM duty-cycle follows VT1 as it increases.
Note C. VT1 drops below VT2. VT2 now determines the output duty-cycle.
Note D. The PWM duty-cycle follows VT2 as it increases.
Note E. Both VT1 and VT2 decrease below VSLP but above VIL. The device enters sleep mode.
Note F. The PWM ‘wakes up’ because one of the control inputs (VT1 in this case) has risen above VWAKE. The startup timer is triggered, forcing OUT
high for 64 clock periods. (VWAKE = VSLP + VHYST. See “Electrical Characteristics”).
Note G. Following the startup interval, the PWM duty-cycle is the higher of VT1 and VT2.

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VOT
0.7VDD 100%
VT1
60% PWM
VT2
30% Range
40%
VS L P 20%
0.3VDD 0%

VIH
VIL
0V

L M
VOH
VOTF
VO L
0V

H I
tS T A R T U P tPW M J K N O
VOH
VOU T
VO L
0V Output
100% 40% 60% 100% 30% 0% Duty Cycle

VDD
VDD
0V

Figure 2. MIC502 Typical Power-Up System Behavior

Note H. At power-on, the startup timer forces OUT on for 64 PWM cycles of the internal timebase (tPWM). This insures that the fan will start from a dead
stop.
Note I. The PWM duty-cycle follows the higher of VT1 and VT2, in the case, VT1.
Note J. The PWM duty-cycle follows VT1 as it increases.
Note K. PWM duty-cycle is 100% (OUT constantly on) anytime VT1 > VPWM(max).
Note L. /OTF is asserted anytime VT1 > VOT. (The fan continues to run at 100% duty-cycle).
Note M. /OTF is deasserted when VT1 falls below VOT; duty-cycle once again follows VT1.
Note N. Duty-cycle follows VT1 until VT1 < VT2, at which time VT2 becomes the controlling input signal. Note that VT1 is below VSLP but above VIH; so
normal operation continues. (Both VT1 and VT2 must be below VSLP to active sleep mode).
Note O. All functions cease when VT1 < VIL; this occurs regardless of the state of VT2.

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Typical Characteristics

Supply Current Supply Current IDD SLEEP vs.

vs. Temperature vs. Supply Voltage Temperature
0.9 0.9 0.3
0.8 VDD = 12V 0.8
0.25 VDD = 12V
0.7 0.7

IDDSL E EP(mA)
0.6 0.6 0.2

ID D (mA)
IDD(mA)

0.5 0.5
VDD = 5V 0.15 VDD = 5V
0.4 0.4
0.3 0.3 0.1
0.2 0.2
0.05
0.1 0.1
0 0 0
-40 -20 0 20 40 60 80 100 0 2 4 6 8 10 12 14 -40 -20 0 20 40 60 80 100
TEMPERATURE °C)
( VDD (V) TEMPERATURE °C)
(

VOL vs. VOL vs.

Supply Voltage Supply Voltage
0.20 35
0.18
30
0.16
0.14 25
0.12

VOL (mV)
20
VOL (V)

0.10
0.08 15
0.06 10
0.04
5
0.02 I = 0.9mA IOL = 100µA
OL
0 0
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
VDD (V) VDD (V)

VOL VOH vs.

vs. Temperature Supply Voltage
0.25 4
VDD = 5V
3.5
0.20
3

0.15 VDD =12V 2.5

VOH(V)
VOL (V)

2
0.10 1.5
1
0.05
0.5
IOH = 10mA
0 0
-40 -20 0 20 40 60 80 100 0 2 4 6 8 10 12 14
TEMPERATURE °C)
( VDD (V)

VOH vs. VOH vs.

Supply Voltage Temperature
4.5 4.5
4 4
VDD = 12V
3.5 3.5
3 3 VDD = 5V
VOH(V)

VOH(V)

2.5 2.5
2 2
1.5 1.5
1 1
0.5 I = 100µA 0.5
OH
0 0
0 2 4 6 8 10 12 14 -40 -20 0 20 40 60 80 100
VDD (V) TEMPERATURE °C)
(

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Typical Characteristics (cont.)

PWM Frequency (normalized) PWM Frequency vs.

vs. Temperature Timing Capacitor Value
1.2 3000
VDD = 12V
1 1000

FPW M (NORMALIZED)
VDD = 5V

FREQUENCY (Hz)
0.8
100
0.6

0.4
10
0.2

0 1
-40 -20 0 20 40 60 80 100 0.001 0.01 0.1 1
TEMPERATURE °C)
( CAPACITANCE µ( F)

VPWM(max) VOT vs.

vs. Temperature Supply Voltage
9 10
8 VDD =12V 9
7 8
6 7
VPW M (M AX)(V)

VO T (V)
5
5
4
4
3 VDD = 5V 3
2 2
1 1
0 0
-40 -20 0 20 40 60 80 100 0 2 4 6 8 10 12 14
TEMPERATURE °C)
( VDD (V)

VOT
vs. Temperature
10
9 VDD = 12V
8
7
6
VO T(V)

5
4
3 VDD = 5V
2
1
0
-40 -20 0 20 40 60 80 100
TEMPERATURE °C)
(

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Functional Diagram

VT2
5 PWM
Driver
OUT
7

VT1
1

C L K Start-Up
Timer OUT
CF RE S E T
Oscillator
2

Sleep

VSLP
Sleep
3 Control

VDD Power-On
8 Reset Bias
Reset
ENABLE
VIL

Overtemperature OTF
6

4
GND

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Functional Description 70% of VDD by > 7% of VDD. Note that VOT is guaranteed
by design to always be higher than VPWM(max).
Oscillator
A capacitor connected to CF determines the frequency Sleep Mode
of the internal time base which drives the state-machine When VT1 and VT2 fall below VSLP, the system is deemed
logic and determines the PWM frequency. This operating capable of operating without fan cooling and the MIC502
frequency will be typically 30Hz to 60Hz. (CF = 0.1µF for enters sleep mode and discontinues fan operation. The
30Hz.) threshold where the MIC502 enters sleep mode is deter-
mined by VSLP. Connecting the VSLP pin to ground
Pulse-Width Modulator disables sleep mode.
A triangle-wave generator and threshold detector Once in sleep mode, all device functions cease (/OTF in-
comprise the internal pulse-width modulator (PWM). The active, PWM output off) unless VT1 or VT2 rise above
PWM’s output duty-cycle is determined by the higher of VWAKE. (VWAKE = VSLP + VHYST). VHYST is a fixed amount of
VT1 or VT2. A typical voltage range of 30% to 70% of VDD hysteresis added to the sleep comparator which
applied to the V T1 and V T2 pins corresponds to 0% to prevents erratic operation around the VSLP operating
100% duty-cycle. Since at least one of the control point. The result is stable and predictable thermostatic
voltage inputs is generally from a thermistor-resistor action: whenever possible the fan is shut down to reduce
divider connected to VDD, the PWM out-put duty cycle energy consumption and acoustic noise, but will always
will not be affected by changes in the supply voltage. be activated if the system temperature rises.
Driver Output If the device powers-up or exits its reset state, the fan
will not start unless VT1 or VT2 rises above VWAKE.
OUT is a complementary push-pull digital output with
asymmetric drive (approximately 10mA source, 1mA System Operation
sink, see “Electrical Characteristics”). It is optimized for
directly driving an NPN transistor switch in the fan’s Power Up
ground-return. See “Applications Information” for circuit • A complete reset occurs when power is applied.
details.
• OUT is off (low) and /OTF is inactive (high/floating).
Shutdown/Reset • If VT1 < VIL, the MIC502 remains in shutdown.
Internal circuitry automatically performs a reset of the • The startup interval begins. OUT will be on (high) for
MIC502 when power is applied. The MIC502 may be 64 clock cycles (64 × tPWM).
shut down at anytime by forcing VT1 below its VIL • Following the startup interval, normal operation
threshold. This is typically accomplished by connecting begins.
the VT1 pin to open-drain or open-collector logic and
P OW E R ON
results in an immediate and asynchronous shutdown of
the MIC502. The OUT and /OTF pins will float while V T1
is below VIL. Reset Startup Timer;
Deassert /OTF;
OUT Off (Low).
If V T1 then rises above VIH, a device reset occurs. Reset
YES
is equivalent to a power-up condition: the state of /OTF
is cleared, a startup interval is triggered, and normal fan V T1 < VIL
?
operation begins. NO

Startup Interval V T1 > VOT Assert /OTF While

? YES V T1 > VOT
Any time the fan is started from the off state (power-on
or coming out of sleep mode or shutdown mode), the NO NO

PWM output is automatically forced high for a startup OUT Held On (High)
interval of 64× tPWM. Once the startup interval is During Startup
Interval.

complete, PWM operation will commence and the duty-

cycle of the output will be determined by the higher of
VT1 or VT2. Startup Interval
Finished
?

Overtemperature Fault Output YES

/OTF is an active-low, open-collector logic output. An Deassert OUT NO RMAL

over-temperature condition will cause /OTF to be (OUT = Low) OP E RA T I ON

asserted. An overtemperature condition is determined by

VT1 exceeding the normal operating range of 30% to Figure 3. Power-Up Behavior

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Normal Operation • Sleep: If VT1 and VT2 fall below VSLP, the device
Normal operation consists of the PWM operating to enters sleep mode. All internal functions cease
control the speed of the fan according to VT1 and VT2. unless VT1 or VT2 rise above VWAKE. (VWAKE = VSLP +
Exceptions to this otherwise indefinite behavior can be VHYST). The /OTF output is unconditionally inactive
caused by any of three conditions: VT1 exceeding VOT, (high/floating) and the PWM is disabled during sleep
an overtemperature condition; VT1 being pulled below VIL (OUT will float).
initiating a device shutdown and reset; or both VT1 and
Sleep Mode
VT2 falling below VSLP, activating sleep mode. Each of
these exceptions is treated as follows: During normal operation, if VT1 and VT2 fall below VSLP,
the device will go into sleep mode and fan operation will
NORMAL stop. The MIC502 will exit sleep mode when VT1 or VT2
O P E RA T IO N
rise above VSLP by the hysteresis voltage, VHYST. When
this occurs, normal operation will resume. The
resumption of normal operation upon exiting sleep is
Reset ?
V T1 < VIL YES P O W E R ON indistinguishable from a power-on reset. (See “Sleep:
? Normal Operation,” above.)
NO

SLEEP

V T1 and VT2
YES SLEEP
< VS L E E P
?
NO
Disable PWM

Overtemp? Assert /OTF while

YES V T1 > VOT
V T1 > VOT
?

NO

Reset Initiated NO
V T1 < VIL
OUT Duty Cycle
Proportional to ?
Greater of VT1, VT2 YES

NO

Figure 4. Normal System Behavior Reset Released

V T1 > VIH
• Overtemperature: If the system temperature rises ?

typically 7% above the 100% duty-cycle operating YES

point, /OTF will be activated to indicate an

overtemperature fault. (VT1 > VOT) Overtemperature
Wake Up?
detection is essentially independent of other VT1 or V T2 > NO
VS L P+VH Y S T
operations — the PWM continues its normal ?
behavior; with VT1 > VPWM(max), the output duty-cycle YES
will be 100%. If VT1 falls below VOT, the
overtemperature condition is cleared and /OTF is no
POWER ON
longer asserted. It is assumed that in most systems,
the /OTF output will initiate power supply shutdown.
Figure 5. Sleep-Mode Behavior
• Shutdown/Reset: If VT1 is driven below VIL an
immediate, asynchronous shutdown occurs. While in
shutdown mode, OUT is off (low), and /OTF is
unconditionally inactive (high/floating). If VT1
subsequently rises above VIH, a device reset will
occur. Reset is indistinguishable from a power-up
condition. The state of /OTF is cleared, a startup
interval is triggered, and normal fan operation
begins.

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Application Information somewhat higher than 0.3VDD (or >VPWM(min)). It is

assumed that the system will be in sleep mode rather
The Typical Application drawing on page 1 illustrates a than operate the fan at a very low duty cycle (<25%).
typical application circuit for the MIC502. Interfacing the Operation at very low duty cycle results in relatively little
MIC502 with a system consists of the following steps: airflow. Sleep mode should be used to reduce acoustic
1. Selecting a temperature sensor noise when the system is cool. For a given minimum
2. Interfacing the temperature sensor to the VT1 input desired fan speed, a corresponding VT1(min) can be
determined via the following observation:
3. Selecting a fan-drive transistor, and base-drive
current limit resistor since
4. Deciding what to do with the Secondary Fan- VPWM(max) = 70% of VDD ∝ 100% RPM
Control Input and
5. Making use of the Overtemperature Fault Output VPWM(min) = 30% of VDD ∝ 0% RPM
Temperature Sensor Selection then
Temperature sensor T1 is a negative temperature VPWM(span) = 40% of VDD ∝ 100% RPM range.
coefficient (NTC) thermistor. The MIC502 can be Figure 6 shows the following linear relationship between
interfaced with either a negative or positive tempco the voltage applied to the VT1 input, motor drive duty
thermistor; however, a negative temperature coefficient cycle, and approximate motor speed.
thermistor typically costs less than its equivalent positive since
tempco counterpart. While a variety of thermistors can
be used in this application, the following paragraphs VT1 = 0.7VDD ∝ 100% PWM
reveal that those with an R25 rating (resistance at 25°C) then
of from about 50kΩ to 100kΩ lend themselves nicely to VT1 = 0.6VDD ∝ 75% PWM
an interface network that requires only a modest current
drain. Keeping the thermistor bias current low not only and
indicates prudent design; it also prevents self-heating of VT1 = 0.5VDD ∝ 50% PWM
the sensor from becoming an additional design and
consideration. It is assumed that the thermistor will be
located within the system power supply, which most VT1 = 0.4VDD ∝ 25% PWM
likely also houses the speed-controlled fan. In addition to the R25 thermistor rating, sometimes a
datasheet will provide the ratio of R25/R50 (resistance at
Temperature Sensor Interface 25°C divided by resistance at 50°C) is given. Sometimes
As shown by the Electrical Characteristics table, the this is given as an R0/R50 ratio. Other datasheet
working voltage for input VT1 is specified as a contents either specify or help the user determine device
percentage of VDD. This conveniently frees the designer resistance at arbitrary temperatures. The thermistor
from having to be concerned with interactions resulting interface to the MIC502 usually consists of the thermistor
from variations in the supply voltage. By design, the and two resistors.
operating range of VT1 is from about 30%of VDD to about
70% of VDD. 100
VPWM(min) = V PWM(min) – VPWM(span)
When VT1 = VPWM(max) ≈ 0.7VDD, a 100% duty-cycle 80
DUTY CYCLE (%)

motor-drive signal is generated. Conversely, when VT1 =

VPWM(min) ≈ 0.3VDD, the motor-drive signal has a 0% duty 60
cycle. Resistor voltage divider R1 || T1, R2 in the Typical
Application diagram is designed to preset VT1 to a value 40
of VPWM that corresponds to the slowest desired fan
speed when the resistance of thermistor T1 is at its
20
highest (cold) value. As temperature rises the resistance
of T1 decreases and VT1 increases because of the
parallel connection of R1 and T1. 0
0 20 40 60 80 100
Since VT1 = VPWM(min) represents a stopped fan (0% duty- VT1 /SUPPLY VOLTAGE (%)
cycle drive), and since it is foreseen that at least some
cooling will almost always be required, the lowest Figure 6. Control Voltage vs. Fan Speed
voltage applied to the VT1 input will normally be

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Design Example Recalling from above discussion that the desired VT for
The thermistor-resistor interface network is shown in the 25°C should be about 40% of VDD, the above value of
Typical Application drawing. The following example 24.8% is far too low. This would produce a voltage that
describes the design process: A thermistor datasheet would stop the fan (recall from the above that this occurs
specifies a thermistor that is a candidate for this design when VT is about 30% of VDD. To choose an appropriate
as having an R25 resistance of 100kΩ. The datasheet value for R1 we need to learn what the parallel
also supports calculation of resistance at arbitrary tem- combination of RT1 and R1 should beat 25°C:
peratures, and it was discovered the candidate again
thermistor has a resistance of 13.6k at 70°C (R70). VDD × R2
Accuracy is more important at the higher temperature VT =
end of the operating range (70°C) than the lower end (R T1 || R1 + R2)
because we wish the overtemperature fault output R2
(/OTF) to be reasonably accurate — it may be critical to 0.4 =
operating a power supply crowbar or other shutdown
(R T1 || R1 + R2)
mechanism, for example. The lower temperature end of 0.4(RT1 || R1) + 0.4R2 = R2
the range is less important because it simply establishes 0.4(RT1 || R1) = 0.6R2
minimum fan speed, which is when less cooling is
and
required.
RT1 || R1 = 1.5R2 = 1.5 × 33k = 49.5k
Referring to the “Typical Application,” the following
approach can be used to design the required thermistor since
interface network: RT1 = 100k
let and
R1 = ∞ RT1 || R1 = 49.5k ≈ 50k
RT1 = 13.6k (at 70°C) let
and R1 = 100k
VT = 0.7VDD (70% of VDD) While that solves the low temperature end of the range,
since there is a small effect on the other end of the scale. The
new value of VT for 70°C is 0.734, or about 73% of VDD.
VDD × R2
VT = This represents only a 3% shift from the design goal of
(R T1 || R1 + R2) 70% of VDD. In summary, R1 = 100k, and R2 = 33k. The
candidate thermistor used in this design example is the
R2
0.7 = RL2010-54.1K-138-D1, manufactured by Keystone
(R T1 + R2) Thermometrics.
0.7RT1 + 0.7R2 = R2 The R25 resistance (100kΩ) of the chosen thermistor is
0.7RT1 = 0.3R2 probably on the high side of the range of potential
thermistor resistances. The result is a moderately high-
and
impedance network for connecting to the VT1 and/or VT2
R2 = 2.33RT1 = 2.33 × 13.6k = 31.7k ≈ 33k input(s). Because these inputs can have up to 1µA of
Let’s continue by determining what the temperature- leakage current, care must be taken if the input network
proportional voltage is at 25°C. impedance becomes higher than the example. Leakage
let current and resistor accuracy could require consideration
in such designs. Note that the VSLP input has this same
R1 = ∞
leakage current specification.
and
RT1 = 100k (at 25°C). Secondary Fan-Control Input
from The above discussions also apply to the secondary fan-
control input, VT2, pin 5. It is possible that a second
VDD × R2 thermistor, mounted at another temperature-critical
VT =
(R T1 + R2) location outside the power supply, may be appropriate.
There is also the possibility of accommodating the NLX
VDD × 33k
VT = “FanC” signal via this input. If a second thermistor is the
(100k + 33k ) desired solution, the VT2 input may be treated exactly
VT = 0.248VDD like the VT1 input. The above discussions then apply
directly. If, however, the NLX FanC signal is to be

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 Micrel, Inc. MIC502

incorporated into the design then the operating voltage Overtemperature Fault Output
(VDD = 5V vs. VDD = 12V) becomes a concern. The FanC The /OTF output, pin 6, is an open-collector NPN output.
signal is derived from a 12V supply and is specified to It is compatible with CMOS and TTL logic and is
swing at least to 10.5V. A minimum implementation of intended for alerting a system about an overtemperature
the FanC signal would provide the capability of asserting condition or triggering a power supply crowbar circuit. If
full-speed operation of the fan; this is the case when VDD for the MIC502 is 5V the output should not be pulled
10.5V ≤ FanC ≤ 12V. This FanC signal can be applied to a higher voltage. This output can sink up to 2mA and
directly to the VT2 input of the MIC502, but only when its remain compatible with the TTL logic-low level.
VDD is 12V. If this signal is required when the MIC502
VDD = 5V a resistor divider is necessary to reduce this Timing Capacitors vs. PWM Frequency
input voltage so it does not exceed the MIC502 VDD The recommended CF (see first page) is 0.1µF for
voltage. A good number is 4V (80%VDD). operation at a PWM frequency of 30Hz. This frequency
Because of input leakage considerations, the impedance is factory trimmed within ±3Hz using a 0.1% accurate
of the resistive divider should be kept at ≤ 100kΩ. A capacitor. If it is desired to operate at a different
series resistor of 120kΩ driven by the FanC signal and a frequency, the new value for CF is calculated as follows:
100kΩ shunt resistor to ground make a good divider for 3
driving the VT2 input. C= , where C is in µF and f is in Hz
f
Transistor and Base-Drive Resistor Selection The composition, voltage rating, ESR, etc., parameters
The OUT motor-drive output, pin 7, is intended for of the capacitor are not critical. However, if tight control
driving a medium-power device, such as an NPN of frequency vs. temperature is an issue, the
transistor. A rather ubiquitous transistor, the 2N2222A, is temperature coefficient may become a consideration.
capable of switching up to about 400mA. It is also Keystone Thermonics
5V 12V
available as the PN2222A in a plastic TO-92 package. RL2010-54.1K-138-D1
or similar
Since 400mA is about the maximum current for most
Yate Loon
popular computer power supply fans (with many drawing YD80SM-12
substantially less current) and since the MIC502 T1 R 1
100k MIC502
47k or similar fan
1 8
provides a minimum of 10mA output current, the VT1 VDD
RB A S E
R3 R2 2 7
PN2222A, with its minimum β of 40, is the chosen motor- 56k 33k
3
CF OUT
6 180
Q1
VSLP OTF
drive transistor. R4 4 5
56k GND VT2
Overtemperature
The design consists solely of choosing the value RBASE in CF Fault Output
0.1µF
Figures 7 and 8. To minimize on-chip power dissipation
120k 100k
in the MIC502, the value of RBASE should be determined
NLX FanC
by the power supply voltage. The Electrical Signal Input
Characteristics table specifies a minimum output current
of 10mA. However, different output voltage drops (VDD – Figure 7. Typical 5V VDD Application Circuit
VOUT) exist for 5V vs.12V operation. The value RBASE
should be as high as possible for a given required
Keystone Thermonics
transistor base-drive current in order to reduce on-chip RL2010-54.1K-138-D1 12V 5V
or similar
power dissipation.
Referring to the “Typical Application” and to the Yate Loon
T1 R 1 47k YD80SM-12
“Electrical Characteristics” table, the value for RBASE is 100k
1
MIC502
8
or similar fan
calculated as follows. For VDD = 5V systems, IOH of OUT VT1 VDD
R3 R2 2 7
RB A S E
CF OUT Q1
(pin 7) is guaranteed to be a minimum of 10mA with a 56k 33k
3 6 280
V S L P OTF
VOH of 2.4V. R4 4
GND VT2
5
56k Overtemperature
RBASE then equals (2.4V – VBE) ÷ 10mA = 170Ω. CF
0.1µF
Fault Output
4.7k
For VDD = 12V systems, RBASE = (3.4 – 0.7) ÷ 0.01 =
250Ω. NLX FanC
Signal Input

Figure 8. Typical 12V VDD Application Circuit

November 2006 13 M9999-112206

Micrel, Inc. MIC502

Package Information

0.026 (0.65)
MAX) PIN 1

0.157 (3.99) DIMENSIONS:

0.150 (3.81) INCHES (MM)

0.020 (0.51)
0.013 (0.33)
0.050 (1.27)
TYP 0.0098 (0.249) 45
0.010 (0.25)
0.0040 (0.102) 0.007 (0.18)

0.197 (5.0) 0–8 0.050 (1.27)

0.064 (1.63) 0.189 (4.8) SEATING 0.016 (0.40)
0.045 (1.14) PLANE
0.244 (6.20)
0.228 (5.79)
8-Pin SOIC (M)

PIN 1

DIMENSIONS:
INCH (MM)

0.380 (9.65) 0.255 (6.48)

0.370 (9.40) 0.245 (6.22)
0.135 (3.43)
0.125 (3.18) 0.300 (7.62)

0.013 (0.330)
0.010 (0.254)

0.018 (0.57) 0.130 (3.30) 0.380 (9.65)

0.320 (8.13)
0.100 (2.54) 0.0375 (0.952)
8-Pin Plastic DIP (N)

November 2006 14 M9999-112206

 Micrel, Inc. MIC502

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.

© 2003 Micrel, Incorporated.

November 2006 15 M9999-112206