Structural Design Style

VHDL provides means to represent digital systems (circuits) at 3 different levels of abstractions,
namely
- Dataflow
- Behavioral or Algorithmic
- Structural

We already considered the first 2 styles.

A structural design style is often referred to as a hierarchal design approach. It textually specifies
how the building blocks of the system referred to as components, are interconnected without
worrying about how these components work.

In this topic, we will discuss structural design style and then illustrate this style with examples
using both
- Positional Port Mapping and
- Named or Nominal Port Mapping

Principle
The design is split (partitioned) into smaller easy to design and verify blocks and then connect
them structurally to create a top-file design

IN1 Comp_1 Comp_2 OUT1

IN2

IN3 ● OUT2
Comp_3 Comp_4
IN4 OUT3

Comp_5 OUT4
IN5

Components range from basic gates to complex subsystems of large digital systems
Implementation Using Structural Modeling
There are two major steps
1. Partition design into components and annotate the system (all inputs, internal signals and
outputs should be clearly labeled (named)).
2. Convert it to VHDL
Syntax of a structural design
VHDL provides a formal way to do this
• Declare a list of components being used
• Declare signals which define the nets that interconnect components
• Component instantiations using Port Map.

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It should be noted that components and signals are declared within the architecture declaration
part before the BEGIN statement of the architecture.
The top level file consists of
1. Library declaration and Packages
2. Entity declaration
3. Architecture
o Components declarations
o Internal signals declarations
Begin
o Components instantiations and connections
o [VHDL statements]
End architecture

Component Declaration
Before components can be instantiated, they need to be declared in the architecture declaration
section.
Component declaration is similar to entity declaration with the reserved word ENTITY replaced
by COMPONENT

Syntax
COMPONENT component_name [is]
Port (input and output definitions);
End COMPONENT [component_name];

A component is declared ONCE and can be used (instantiated) any number of times.
Component Instantiation and Interconnections
The use of components is referred in VHDL to as instantiation and their interconnection as port
mapping.
The command PORT MAP is used to show how the input and output pins are connected to the
component.
Syntax component instantiation
Instance_name: component_name PORT MAP (port_association_list);
Example
G1: Gate_OR2 PORT MAP (a, b, w);
The component instantiation is a concurrent statement.
The statement has 3-key parts (name, component_name, port_map)

Prefaced with a label: identifier (names the part)
A unique label that identifies a particular component in the circuit

Followed by the component name

Followed by keyword ‘port map’

Followed by signal map list

PORT MAP
The PORT MAP describes how signals (actual signals) in the architecture are to be connected to
the ports (formal signals) of the component
VHDL allows 2 connectivity styles when instantiating components
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 • Positional Port Mapping (Association)
• Named (Nominal) Port Mapping (Association)

1. Positional Port Mapping

In this technique, the formal signal names (component ports) of the component are not explicitly
listed. Instead, the actual signals must be placed exactly in the same order as they are listed in the
component declarations. Each signal name is separated by a comma.

This approach requires less text to describe but can lead to misconnections due to mismatches in
the order of the signals being connected

Syntax for Positional Port Mapping

Instance_name: component_name PORT MAP (actual_sig1, actual_sig2, ….);

2. Named Port Mapping

In named port mapping, the name of each port of the component (formal name) is explicitly
specified. It is then followed by a => (finger symbol, pronounced “connected to”) and then the
actual signal, that is, the signal that is to be connected to.
Syntax for Named Port Mapping
Instance_name: component_name PORT MAP (formal_sig => actual_sig1,
formal_sig => actual_sig, ….);
With the named port mapping, the port connections can be listed in any order since the details of
the connection are explicitly specified
This technique is less prone to errors. It has the advantage of acting as a remainder of which port
each signal is being connected to. In addition, it gives a VHDL analyzer an extra opportunity for
checking the consistency of the design.
In port mappings based on the named association, the port names (formal) of a component are
written on the left of the => operator.

Association is “component_port_name => connect_port”

Associations can appear in any order
The two styles may be used together as long as the association is not then made ambiguous.
Example
As an example, let’s consider a 1-bit full adder, as shown below in Figure 1.
Here, we have three types of components AND_2, XOR_2 and OR_2.
The internal signals are labelled t1, t2, and t3.
The VHDL structural description of the Full-Adder circuit is shown below.

●
●

Figure 1 Internal circuit a 1-bit Full Adder

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Library ieee;
Use ieee.std_logic_1164.all;
entity Full_Adder is
port (A, B, Cin: in std_logic;
Sum, Cout : out std_logic);
end Full_Adder;
architecture STRUCTURE of Full_Adder is
-- Declaration of components and local signals
-- There are three types of components to be declared.
component AND_2 Component
port (x1, x2 : in std_logic; Y : out std_logic); Declarations
end component;
component OR_2
port (x1, x2 : in std_logic; Y : out std_logic);
end component;
component XOR_2
port (x1, x2 : in std_logic; Y : out std_logic);
end component;

signal t1, t2, t3 : std_logic; Internal Signal

begin Declaration
-- Define the component connections (instantiation of components)
G1: XOR_2 port map (a, b, t1);
G2: AND_2 port map (a, b, t2);
G3: XOR_2 port map (Cin, t1, Sum);
G4: AND_2 port map (Cin, t1, t3);
G5 : OR_2 port map (t2, t3, Cout) ;
end STRUCTURE;

Next, we need to define each component, i.e., write the VHDL code of each component.
Where should we write the VHDL code of each component? There are several locations where
these codes can be written
1. In a PACKAGE (best)
2. Within the top-file (after architecture)
3. Each component in a separate VHDL file and all files should be saved in the current
folder (WORK Library).

In examples 1 and 2 below (pages 5-7), all VHDL codes are written in the top-file.

Advantages of Structural Design Style

This design style is best suited for large and complex digital systems.
• Each component can be designed and tested in isolation before being incorporated into
the high level(s) of the design
• Uses divide-and-conquer design approach (reduces design complexity)
• It is a good practice to collect useful components together into reusable library (Package)
so they can be used elsewhere in the same design or later on in other designs, thus saving
the designer time
• Components are technology independent and so can be reused in a wide variety of
different projects

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Structural_Examples
Example 1
●
Structural VHDL code of
circuit of Figure 1. ●
●

Figure 1

1. Using Positional Port Mapping

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2. Using Nominal Port Mapping

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Example 2 Structural VHDL code of circuit of Figure 2.

G1 ●
●

● ●

Figure 2