Scribd
Upload
19 views3 pages

VHDL Mac

The document contains VHDL code for a MAC unit that multiplies two 8-bit inputs and outputs a 17-bit result. It includes the entity, architecture, and testbench for the MAC unit.

Uploaded by

Ramya M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
19 views3 pages

VHDL Mac

The document contains VHDL code for a MAC unit that multiplies two 8-bit inputs and outputs a 17-bit result. It includes the entity, architecture, and testbench for the MAC unit.

Uploaded by

Ramya M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

VHDL Code for MAC Unit :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MACvhdl is
port(A,B :in std_logic_vector(7 downto 0);
int :in std_logic_vector(7 downto 0);
output :out std_logic_vector(16 downto 0));
end MACvhdl;

architecture Behavioral of MACvhdl is


signal out1:std_logic_vector(16 downto 0);
begin
process (A,B)
begin
output <=x"0";
for int in 0 to 7 loop
B[int] <=x”1”;
out1 <= out1 + (a<<int);
end if;
end loop;
end process;
end Behavioral;

Test Bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_MACvhdl IS
END tb_MACvhdl;
ARCHITECTURE behavior OF tb_MACvhdl IS

COMPONENT MACvhdl
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
out : OUT std_logic_vector(16 downto 0)
);
END COMPONENT;

--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');

--Outputs
signal out : std_logic_vector(16 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: MACvhdl PORT MAP (
A => A,
B => B,
out => out
);

stim_proc: process
begin
A<= 8'b00000000;
B<= 8'b00000000;
wait for 100 ns;
A<= 8'b00101100;
B<= 8'b00010011;
wait for 200 ns;
wait;
end process;
END;

You might also like