EUA2310

15-W Stereo Class-D Audio Power

Amplifier with Speaker Protection
DESCRIPTION FEATURES
The EUA2310 is a high efficiency, 2 channel bridged-tied
Wide Supply Voltage: 8V to 26V
load (BTL), class-D audio power amplifier. Operating from
Unique Modulation Scheme Reduces EMI Emission
a 16V power supply, EUA2310 is capable of delivering
15-W/ch into an 8-Ω Load From a 16-V Supply
15W/ channel of continuous output power to a 8Ω load
10-W/ch into an 8-Ω Load From a 13-V Supply
with 10% THD+N. The EUA2310 features a differential
30W into a 4-Ω Mono Load From a 16-V Supply
input architecture offering improved noise immunity over a
87% Efficient Class-D Operation Eliminates
single-ended (SE) input amplifier. Amplifier gain is Need for Heat Sinks
internally configured and can be selected to 20, 26, 32 or
Four Selectable, Gain Settings
36dB utilizing the G0 and G1 gain select pins. Advanced
Differential Inputs
EMI suppression technology enables the use of
Speaker Protection Circuitry
inexpensive ferrite bead at the outputs while meeting EMC
Auto Gain Control
requirements.
Thermal and Short-Circuit Protection
The speaker protection circuitry is integrated into
28-pin TSSOP Package with Thermal Pad
EUA2310 to limit the amount of current through the
RoHS compliant and 100% lead(Pb)-free
speaker. Meanwhile, the AGC detects output signal clip Halogen-Free
due to the over level input signal and suppresses it

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automatically. The EUA2310 also features short-circuit and
thermal protection preventing the device from being APPLICATIONS

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damaged during a fault condition. The EUA2310 is

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available in thermally efficient 28-pin TSSOP package.
Televisions

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Typical Application Circuit
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Figure1. Simplified Application Schematic

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EUA2310

Pin Configurations
Package Type Pin Configurations

TSSOP-28 (EP)

Pin Description

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PIN TSSOP-28(EP) I/O/P DESCRIPTION
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs

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SD 1 I
enabled). TTL logic levels with compliance to AVCC.

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Open drain output used to display short circuit or dc detect fault status.
FAULT 2 O
Voltage compliant to AVCC.
LINP 3 I
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Positive audio input for left channel.
LINN 4 I
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Negative audio input for left channel.
GAIN0 5 I
四 ofGain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I
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Gain select most significant bit. TTL logic levels with compliance to AVCC.

.
AVCC 7 P

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AGND

GVDD
8

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P

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Analog signal ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 4.5V. Also should be
used as supply for PLIMIT function.
Power limit level adjust. Connect a resistor divider from GVDD to GND to
PLIMIT 10 I
set power limit. Connect directly to GVDD for no power limit.
RINN 11 I Negative audio input for right channel.
RINP 12 I Positive audio input for right channel.
NC 13 P Not connected
PBTL 14 I Parallel BTL mode switch
Power supply for right channel H-bridge. Right channel and left channel
PVCCR 15,16 P
power supply inputs are connect internally.
BSPR 17 I Bootstrap I/O for right channel, positive high-side FET.
OUTPR 18 O Class-D H-bridge positive output for right channel.
PGND 19 Power ground for the H-bridges.
OUTNR 20 O Class-D H-bridge negative output for right channel.
BSNR 21 I Bootstrap I/O for right channel, negative high-side FET.
BSNL 22 I Bootstrap I/O for left channel, negative high-side FET.
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EUA2310
Pin Description (Continued)
PIN TSSOP-28(EP) I/O DESCRIPTION
OUTNL 23 O Class-D H-bridge negative output for left channel.
PGND 24 Power ground for the H-bridges.
OUTPL 25 O Class-D H-bridge positive output for left channel.
BSPL 26 I Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel
PVCCL 27,28 P
power supply inputs are connect internally.

Ordering Information
Order Number Package Type Marking Operating Temperature Range

xxxxx
EUA2310XIR1 TSSOP-28 (EP) -40 °C to +85°C
EUA2310

EUA2310 □ □ □ □

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Lead Free Code

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1: Lead Free, Halogen Free

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Packing
R: Tape & Reel

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Operating temperature range
I: Industry Standard

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Package Type

.
X:TSSOP (EP)

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EUA2310
Absolute Maximum Ratings
▓ Supply Voltage, AVCC,PVCC, ------------------------------------------------------------------------- -0.3 V to 30V
▓ Input Voltage, SD ,GAIN0,GAIN1,PBTL, FAULT ----------------------------------------- -0.3 V to VCC +0.3V
▓ Input Voltage, PLIMIT ---------------------------------------------------------------------- -0.3 V to GVDD +0.3V
▓ Input Voltage, RINN,RINP,LINN,LINP ------------------------------------------------------------- -0.3 V to 6.3V
▓ Thermal Resistance θJA (TSSOP-28_EP) ---------------------------------------------------------------- 34°C /W
▓ Free-air Temperature Range, TA --------------------------------------------------------------------- -40°C to +85°C
▓ Junction Temperature Range, TJ -------------------------------------------------------------------- -40°C to +150°C
▓ Storage Temperature Rang, Tstg ------------------------------------------------------------------- -65°C to +150°C
▓ Lead Temperature ------------------------------------------------------------------------------------------ 260°C
▓ Load Resistance, RLOAD ---------------------------------------------------------------------------------- 3.2Ω Minimum
▓ ESD Susceptibility (HBM) ------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions

Min. Max. Unit
Supply voltage, VCC PVCC,AVCC 8 26 V
High-level input voltage, VIH SD ,GAIN0,GAIN1,PBTL 2 V

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Low-level input voltage, VIL SD ,GAIN0,GAIN1,PBTL 0.8 V

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High-level input current, IIH SD ,GAIN0,GAIN1,PBTL,VI=2V,VCC=18V 50 µA

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Low-level input current, IIL SD ,GAIN0,GAIN1,PBTL,VI=0.8V,VCC=18V 5 µA

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Low-level output voltage, VOL FAULT , RPULL-UP=100k, VCC=26V 0.8 V
Oscillator frequency, fOSC 230 330 kHz
Operating free-air temperature, TA
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DC Characteristics TA = +25°C ,VCC=24V, RL=8Ω (Unless otherwise noted)

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Symbol Parameter Conditions Unit
Min. Typ. Max.
Class-D output offset voltage
VOS VI= 0V, Gain = 36dB 5 50 mV
(measured differentially)
ICC Quiescent supply current SD =2V, no load, PVCC=24V 65 mA

ICC(SD) Quiescent supply current in shutdown µA

SD =0.8V, no load, PVCC=24V 250 400
mode
VCC=12V, High Side 240
rDS(on) Drain-source on-state resistance mΩ
IO=500mA, TJ=25°C Low Side 240
GAIN0=0.8V 19 20 21
GAIN1=0.8V dB
GAIN0=2V 25 26 27
G Gain
GAIN0=0.8V 31 32 33
GAIN1=2V dB
GAIN0=2V 35 36 37
tON Turn-on time SD =2V 28 ms
tOFF Turn-off time SD =0.8V 28 ms
GVDD Gate Drive Supply IGVDD=100µA 4.2 4.5 4.8 V
tDCDET DC Detect time V(RINN)=5V, VRINP=0V 420 ms

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EUA2310
DC Characteristics TA = +25°C ,VCC=12V, RL=8Ω (Unless otherwise noted)
Symbol Parameter Conditions EUA2310 Unit
Min. Typ. Max.
Class-D output offset voltage
VOS VI= 0V,Gain =36dB 5 50 mV
(measured differentially)
ICC Quiescent supply current SD =2V, no load, PVCC=12V 45 mA
Quiescent supply current in shutdown µA
ICC(SD) SD =0.8V, no load, PVCC=12V 200 1000
mode
VCC=12V, High Side 240
rDS(on) Drain-source on-state resistance mΩ
IO=500mA, TJ=25°C Low Side 240
GAIN0=0.8V 19 20 21
GAIN1=0.8V dB
GAIN0=2V 25 26 27
G Gain
GAIN0=0.8V 31 32 33
GAIN1=2V dB
GAIN0=2V 35 36 37
tON Turn-on time SD =2V 28 ms
tOFF Turn-off time SD =0.8V 28 ms
GVDD Gate Drive Supply IGVDD=2mA 4.2 4.5 4.8 V

VO Output voltage maximum under

技 mV(PLIMIT)=1.3V, VI=1Vrms 6.75 7.90 8.75 V

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PLIMIT control

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AC Characteristics TA = +25°C ,VCC=24V, RL=8Ω (Unless otherwise noted)

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Symbol Parameter Conditions Unit
Min. Typ. Max.

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200mVPP ripple at 1kHz,
KSVR Power supply ripple rejection -60 dB

.
Gain= 20dB, Inputs ac-coupled to AGND
PO Continuous output power

w w THD+N=10%, f=1kHz, VCC=16V 15 W

Vn Output integrated noise

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THD+N Total harmonic distortion +noise VCC=16V, f=1kHz, Po=7.5W( half-power)

20Hz to 22kHz, A-weighted filter,

Gain=20dB
0.2
200
%
µV
-74 dBV
Crosstalk VO=1Vrms, Gain=20dB, f=1kHz -100 dB
Maximum output at THD+N< 1%,
SNR Signal-to-noise ratio 90 dB
f=1kHz,Gain=20dB, A-weighted
fOSC Oscillator frequency 230 280 330 kHz
Thermal trip point 150 °C
Thermal hysteresis 30 °C

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EUA2310
AC Characteristics TA = +25°C ,VCC=12V, RL=8Ω (Unless otherwise noted)
Symbol Parameter Conditions EUA2310 Unit
Min. Typ. Max.
200mVPP ripple from 20Hz ~1kHz,
KSVR Power supply ripple rejection -60 dB
Gain= 20dB, Inputs ac-coupled to AGND
PO Continuous output power THD+N=10%, f=1kHz, VCC=13V 10 W
THD+N Total harmonic distortion +noise RL=8Ω, f=1kHz, Po=5W( half-power) 0.2 %

20Hz to 22kHz, A-weighted filter, 200 µV

Vn Output integrated noise
Gain=20dB -74 dBV
Crosstalk PO=1W, Gain=20dB, f=1kHz -100 dB
Maximum output at THD+N< 1%,
SNR Signal-to-noise ratio 90 dB
f=1kHz,Gain=20dB, A-weighted
fOSC Oscillator frequency 230 280 330 kHz
Thermal trip point 150 °C
Thermal hysteresis 30 °C

Block Diagram

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Figure2.

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EUA2310
Typical Characteristics

Figure3. Figure4.

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Figure5.
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Figure7. Figure8.

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EUA2310

Figure9. Figure10.

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Figure11.
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Figure13. Figure14.

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EUA2310

Figure15. Figure16.

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Figure17. Figure18.

Figure19. Figure20.

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EUA2310

Figure21. Figure22.

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Figure23.
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Figure25. Figure26.

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EUA2310

Figure27. Figure28.

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Figure29. Figure30.

Figure31. Figure32.

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EUA2310

Figure33. Figure34.

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Figure35. Figure36.

Figure37. EMI Test and FCC Limits

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EUA2310
Application Information
Differential Input
The differential input stage of the amplifier cancels any common-mode noise that appears on both input lines of the audio
channel. To use the EUA2310 with a differential source, connect the positive signal of the audio source to the INP pin and
the negative signal from the audio source to the INN pin (Figure 38).

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Figure 38. Differential Input

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Single-Ended Input
When using an audio source with a single-ended “out”, it is important to connect the RINN and LINN pins to the GND of

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the audio source with coupling capacitors. (Figure 39).

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Figure 39. Single Ended Input

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EUA2310
Application Information (continued)

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Figure 40. 4Ω/30W PBTL Output

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EUA2310
2
 RL  
 
  R + 2 R  × VP 
Gain Selection 
  L S  
The gain of the EUA2310 is set by two input terminals, POUT = ------------------ (1)
GAIN0 and GAIN1. 2R L
The gains listed in Table 1 are realized by changing the For unclipped power
taps on the input resistors and feedback resistors inside Where:
the amplifier. This causes the input impedance (ZI) to be RS is the total series resistance including RDS(on), and any
dependent on the gain setting. The actual gain settings are resistance in the output filter.
controlled by ratios of resistors, so the gain variation from RL is the load resistance.
part-to-part is small. However, the input impedance from VP is the peak amplitude of the output, VIN is the input
part-to-part at the same gain may shift by ±20% due to amplitude.
shifts in the actual resistance of the input resistors.
For design purposes, the input network should be  6 × VPLIMIT If 0.6 × VPLIMIT < VIN < 2.4 × VPLIMIT
VP = 
designed assuming an input impedance of 40 kΩ, which is
 2.5 × VIN If VIN > 2.4 × VPLIMIT
the absolute minimum input impedance of the EUA2310.
At the lower gain settings, the input impedance could
increase as high as 120 kΩ. POUT (10%THD) = 1.25 × POUT (unclipped)
Table.2 PLIMIT Typical Operation
Table.1 Gain Setting
Output Voltage
AMPLIFIER INPUT PLIMIT Output
Test Conditions() Amplitude
GAIN1 GAIN0 GAIN (dB) IMPEDANCE (kΩ) Voltage Power (W)
(VP-P)
TYP TYP PVCC=24V, VIN=1Vrms,
0 0 20 100 4.5 31.7 36

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RL=8Ω, Gain=26dB
0 1 26 50 PVCC=24V, VIN=1Vrms,

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1 0 32 50 1.6 16.16 32
RL=8Ω, Gain=26dB
1 1 36 50

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PVCC=24V, VIN=1Vrms,
1.31 11.26 26.9
RL=8Ω, Gain=26dB
SD Operation
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1.01 7.246 21.6

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RL=8Ω, Gain=26dB
Connect SD to a logic high for normal operation. Pulling
PVCC=24V, VIN=1Vrms,
SD low causes the outputs to mute and the amplifier to

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0.102 4.129 16.37
RL=8Ω, Gain=26dB
enter a low-current state. Never leave SD unconnected,

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PVCC=24V, VIN=1Vrms,
because amplifier operation would be unpredictable. 4.5 12.53 28.4

.
RL=8Ω, Gain=20dB
For the best power-off pop performance, place the

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PVCC=24V, VIN=1Vrms,

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amplifier in the shutdown prior to removing the power 1.4 11.46 27.2

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RL=8Ω, Gain=20dB
supply voltage.
PVCC=24V, VIN=1Vrms,
1.024 7.399 21.9
PLIMIT RL=8Ω, Gain=20dB
The voltage at pin 10 can be used to limit the power to PVCC=24V, VIN=1Vrms,
0.1 1.071 8.3
levels below that which is possible based on the supply RL=8Ω, Gain=20dB
rail. Add a resistor divider from GVDD to ground to set PVCC=12V, VIN=1Vrms,
4.5 8.648 20.28
the voltage at the PLIMIT pin. An external reference may RL=8Ω, Gain=20dB
also be used if tighter tolerance is required. Also add a PVCC=12V, VIN=1Vrms,
0.73 4.029 16.47
1µF capacitor from pin 10 to ground. Auto Gain Control RL=8Ω, Gain=20dB
function is included to limit the output peak-to-peak PVCC=12V, VIN=1Vrms,
0.1 1.078 8.34
voltage, by adjusting the gain of the amplifier. The gain RL=8Ω, Gain=20dB
changes depending on the amplitude, the PLIMIT level, Auto Gain Control Function
and the attack and release time. The gain changes
constantly as the audio signal increases and/or decreases The AGC works by detecting the audio input envelope.
to suppress the clipped output signal. The output voltage The gain changes depending on the amplitude, the power
can be used to calculate the maximum output power for a supply level, and the attack and release time. The gain
given maximum input voltage and speaker impedance. changes constantly as the audio signal increases and/or
decreases to suppress the clipped output signal. The
maximum attenuation is -12dB . The attack time is 1.5Sec
and the released time is 1.5Sec per step.

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EUA2310
GVDD Supply thermal set point, the device enters into the shutdown
The GVDD Supply is used to power the gates of the state and the outputs are disabled. This is not a latched
output full bridge transistors. It can also be used to supply fault. The thermal fault is cleared once the temperature of
the PLIMIT voltage divider circuit. Add a 1µF capacitor the die is reduced by 30oC. The device begins normal
to ground at this pin. operation at this point with no external system interaction.

DC Detect Input Resistance

EUA2310 has circuitry which will protect the speakers Changing the gain setting can vary the input resistance of
from DC current which might occur due to defective the amplifier from its smallest value, 50 kΩ ±20%, to the
capacitors on the input or shorts on the printed circuit largest value, 100 kΩ ±20%. As a result, if a single
board at the inputs. A DC detect fault will be reported on capacitor is used in the input high-pass filter, the -3 dB or
the FAULT pin as a low state. The DC Detect fault will cutoff frequency may change when changing gain steps.
also cause the amplifier to shutdown by changing the state
of the outputs to Hi-Z. To clear the DC Detect it is
necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential
duty-cycle of either channel exceeds 20% (for example,
+60%, -40%) for more than 420 msec at the same polarity. The -3dB frequency can be calculated using Equation 2.
This feature protects the speaker from large DC currents Use the ZI values given in Table 1.
or AC currents less than 2Hz. To avoid nuisance faults
due to the DC detect circuit, hold the SD pin low at 1
power-up until the signals at the inputs are stable. Also, f = ---------------- (2)
2 πZ C

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take care to match the impedance seen at the positive and i i
negative inputs to avoid nuisance DC detect faults. Input Capacitor, CI
PBTL Select
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EUA2310 offers the feature of parallel BTL operation required to allow the amplifier to bias the input signal to
the proper dc level for optimum operation. In this case, CI

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with two outputs of each channel connected directly. If
the PBTL pin (pin 14) is tied high, the positive and and the input impedance of the amplifier (ZI) form a

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negative outputs of each channel (left and right) are high-pass filter with the corner frequency determined in
Equation 3.

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synchronized and in phase. To operate in this PBTL
(mono) mode, apply the input signal to the RIGHT input

g
and place the speaker between the LEFT and RIGHT

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outputs. Connect the positive and negative output together

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for best efficiency. For an example of the PBTL

INFORMATION section. w
connection, see the schematic in the APPLICATION

For normal BTL operation, connect the PBTL pin to local

ground.
Short-Circuit Protection and Automatic Recovery 1
f =
Feature c 2 πZ C -----------------(3)
i i
The EUA2310 has short-circuit protection circuitry on the
outputs that prevents damage to the device during The value of CI is important, as it directly affects the bass
output-to-output shorts, output-to-GND shorts, and (low-frequency) performance of the circuit. Consider the
output-to-VCC shorts. When a short circuit is detected on example where ZI is 50 kΩ and the specification calls for
the outputs, the part disables the output drive. A latched a flat bass response down to 20 Hz. Equation 3 is
fault flag is resulted. The EUA2310 can automatic recover reconfigured as Equation 4.
for normal operation if short was removed. If the short 1
was not removed, the protection circuitry again activates. C = -----------------(4)
i 2 πZ f
i c
Thermal Protection
Thermal protection on the EUA2310 prevents damage to In this example, CI is 0.16µF; so, one would likely choose
the device when the internal die temperature exceeds a value of 0.22µF as this value is commonly used. If the
150oC. There is a 10oC tolerance on this trip point from gain is known and is constant, use ZI from Table 1 to
device to device. Once the die temperature exceeds the calculate CI.

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EUA2310
Power Supply Decoupling, CS Output Filter
The EUA2310 is a high-performance CMOS audio Most applications require a ferrite bead filter. The ferrite
amplifier that requires adequate power supply decoupling filter reduces EMI around 1 MHz and higher (FCC and
to ensure that the output total harmonic distortion (THD) CE only test radiated emissions greater than 30 MHz).
is as low as possible. Power supply decoupling also When selecting a ferrite bead, choose one with high
prevents oscillations for long lead lengths between the impedance at high frequencies, but low impedance at low
amplifier and the speaker. The optimum decoupling is frequencies.
achieved by using two capacitors of different types that Use an LC output filter if there are low frequency (<1
target different types of noise on the power supply leads. MHz) EMI-sensitive circuits and/or there are long wires
For higher frequency transients, spikes, or digital hash on from the amplifier to the speaker.
the line, a good low equivalent-series-resistance (ESR) When both an LC filter and a ferrite bead filter are used,
ceramic capacitor, typically 0.1µF to 1µF placed as close the LC filter should be placed as close as possible to the
as possible to the device VCC lead works best. For IC followed by the ferrite bead filter.
filtering lower frequency noise signals, a larger aluminum
electrolytic capacitor of 220µF or greater placed near the
audio power amplifier is recommended. The 220µF
capacitor also serves as local storage capacitor for
supplying current during large signal transients on the
amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220µF or larger capacitor
should be placed on each PVCC terminal. A 10µF
capacitor on the AVCC terminal is adequate.
BSN and BSP Capacitors Figure41.
The full H-bridge output stages use only NMOS
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transistors, that require bootstrap capacitors for the high
side of each output to turn on correctly. A 220nF~1uF

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ceramic capacitor, rated for at least 25V, must be

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connected from each output to its corresponding bootstrap
input. (See application circuit diagram in Figure 38,39.)

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The bootstrap capacitors connected between the BSxx

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pins and corresponding output function as a floating

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power supply for the high-side N-channel power
Figure42.

.
MOSFET gate drive circuitry. During each high-side

w
switching cycle, the bootstrap capacitors hold the

w
w
gate-to-source voltage high enough to keep the high-side
MOSFETs turned on.
Using Low-ESR Capacitors
Use capacitors with an ESR less than 100mΩ for
optimum performance. Low-ESR ceramic capacitors
minimize the output resistance. For best performance over
the extended temperature range, select X7R capacitors.
Figure43.

DS2310 Ver1.0 Feb. 2012 17

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EUA2310
Package Information
TSSOP-28 (EP)

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科 co
通 h.
恒 ec
海 ot
四 of
.g
w w
MILLIMETERS INCHES

w
SYMBOLS MIN. MAX. MIN. MAX.
A - 1.20 - 0.047
A1 0.00 0.15 0.000 0.006
b 0.19 0.30 0.007 0.012
E1 4.40 0.173
D 9.60 9.80 0.378 0.386
D1 2.80 6.30 0.110 0.248
E 6.20 6.60 0.244 0.260
E2 2.10 3.30 0.083 0.130
e 0.65 0.026
L 0.45 0.75 0.018 0.030

DS2310 Ver1.0 Feb. 2012 18