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Digital System Design

The document discusses digital system design and provides VHDL code examples for modeling a 4-to-1 multiplexer and 1-to-4 demultiplexer using different styles. It includes code for implementing a 4-to-1 multiplexer and 1-to-4 demultiplexer using data flow, structural, and behavioral modeling styles in VHDL. The aim is to write VHDL code for a 4-to-1 multiplexer and 1-to-4 demultiplexer using various modeling styles.

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Gourav Vashist
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88 views10 pages

Digital System Design

The document discusses digital system design and provides VHDL code examples for modeling a 4-to-1 multiplexer and 1-to-4 demultiplexer using different styles. It includes code for implementing a 4-to-1 multiplexer and 1-to-4 demultiplexer using data flow, structural, and behavioral modeling styles in VHDL. The aim is to write VHDL code for a 4-to-1 multiplexer and 1-to-4 demultiplexer using various modeling styles.

Uploaded by

Gourav Vashist
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as ZIP, PDF, TXT or read online on Scribd
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DIGITAL SYSTEM DESIGN

Practical Examination(2020)
EE-330-F

Name: Gourav Vashist


Roll No: 5445663
Branch: CSE 6th SEM
Date : 26 september,2020
MULTIPLEXER

❖ Multiplexer is a combinational circuit that has maximum of


2n data inputs, ‘n’ selection lines and single output line. One of
these data inputs will be connected to the output based on the
values of selection lines.

❖ Since there are ‘n’ selection lines, there will be 2n possible


combinations of zeros and ones. So, each combination will
select only one data input.
DEMULTIPLEXER
• De-Multiplexer is a combinational circuit that performs the
reverse operation of Multiplexer. It has single input, ‘n’ selection
lines and maximum of 2n outputs. The input will be connected to
one of these outputs based on the values of selection lines.
•

• Since there are ‘n’ selection lines, there will be 2n possible


combinations of zeros and ones. So, each combination can
select only one output.
AIM: Write VHDL code for 4:1 Mux and 1:4 De-Mux using various
styles of modelling.

• 4:1MUX (Data flow style modelling)


library ieee ;
use ieee.std_logic_1164.all ;
entity mux4 is
port(d0,d1,d2,d3,s0,s1 : in bit ;
y : out bit) ;
end mux4;
architecture dataflow of mux4 is
begin
y <= ((d0 and (not s0) and (not s1)) or (d1 and s1 and (not s0)) or
(d2 and (not s1) and s0) or (d3 and s0 and s1));
end dataflow ;
❖ Structural modeling of 4:1 mux

library ieee;
use ieee.std_logic_1164.all;
entity MUX4_1 is
port ( Sel0,Sel1 : in std_logic;
A, B, C, D : in std_logic;
Y : out std_logic );
end MUX4_1;

architecture structural of MUX4_1 is


component inv
port (pin : in std_logic;
pout :out std_logic);
end component;

component and3
port (a0,a1,a2: in std_logic;
aout:out std_logic);
end component;
component or4
port (r0,r1,r2,r3:in std_logic;
rout:out std_logic);
end component;

signal selbar0,selbar1,t1,t2,t3,t4: std_logic;


begin
INV0: inv port map (Sel0, selbar1);
INV1: inv port map (Sel1, selbar1);
A1: and3 port map (A, selbar0, selbar1, t1);
A2: and3 port map (B, Sel0, selbar1, t2);
A3: and3 port map (C, selbar0, Sel1, t2);
A4: and3 port map (D, Sel0, Sel1, t4);
O1: or4 port map (t1, t2, t3, t4, Y);
end structural;
4:1MUX (Behavioral style modelling)
library ieee;
use ieee.std_logic_1164.all;
entity MUX4_1 is
port ( Sel : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic );
end MUX4_1;
architecture behavior of MUX4_1 is
begin
process (Sel, A, B, C, D)
begin
if (Sel = "00") then
Y<= A;
elsif (Sel = "01") then
Y<= B;
elsif (Sel = "10") then
Y<= C;
else
Y<= D;
end if;
end process;
end behavior;
• 1:4 DE-MUX (Data flow style modelling)
Code:
library ieee ;
use ieee.std_logic_1164.all ;
entity demux4 is
port ( Y : in std_logic;
SEL : in std_logic_vector (1 downto 0) ;
D : out std_logic_vector (3 downto 0) ) ;
end demux4 ;
architecture dataflow of demux4 is
begin
D(0) <= (not SEL(0)) and (not SEL(1)) ;
D(1) <= SEL(0) and (not SEL(1)) ;
D(2) <= (not SEL(0)) and SEL(1) ;
D(3) <= SEL(0) and SEL(1) ;
end dataflow ;
❖ Structural modeling of 1:4 Demux

library IEEE;
use IEEE.std_logic_1164.all;

entity bejoy_1x4 is
port(s1,s2,data_in : in std_logic;
d1,d2,d3,d4 : out std_logic);
end bejoy_1x4;

architecture arc of bejoy_1x4 is

component dmux
port(sx1,sx2,d : in std_logic;
z1,z2 : out std_logic);
end component;

begin
dmux1 : dmux port map(s1, s2, data_in, d1, d2);
dmux2 : dmux port map(not s1, s2, data_in, d3, d4);
end arc;
1:4 DEMUX (Behavioral style modelling)
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEMUX_SOURCE is
Port ( I : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end DEMUX_SOURCE;
architecture Behavioral of DEMUX_SOURCE is
begin
process (I, S)
begin
if (S <= "00") then
Y(0) <= I ;
elsif (S <= "01") then
Y(1) <= I ;
elsif (S <= "10") then
Y(2) <= I ;
else
Y(3) <= I ;
end if;
end process; end Behavioral;
Thank You

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