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Cadence Interview Product Validation Role

The document outlines the technical rounds for an interview process for a Product Validation Engineer position at Cadence, including questions asked in each round related to Verilog, SystemVerilog, Linux, UVM methodology, protocols, simulation concepts, and the HR round. The technical rounds cover topics such as blocking vs non-blocking, delay types, UVM phases and components, scoreboarding, race conditions, clocking blocks, sequences versus sequencers, and verification approaches. The HR round asks questions about the candidate's location, reasons for applying to Cadence, willingness to relocate, how they learned of the opening, and salary expectations.

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Sanjay Sanju Yadav
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1K views3 pages

Cadence Interview Product Validation Role

The document outlines the technical rounds for an interview process for a Product Validation Engineer position at Cadence, including questions asked in each round related to Verilog, SystemVerilog, Linux, UVM methodology, protocols, simulation concepts, and the HR round. The technical rounds cover topics such as blocking vs non-blocking, delay types, UVM phases and components, scoreboarding, race conditions, clocking blocks, sequences versus sequencers, and verification approaches. The HR round asks questions about the candidate's location, reasons for applying to Cadence, willingness to relocate, how they learned of the opening, and salary expectations.

Uploaded by

Sanjay Sanju Yadav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CADENCE : Product_validation_Engineer_1 (March_2020_Noida)

Verilog SV Linux UVM Others


Technical round -1
1.Blocking vs Non 1.Modport 1.head command 1.factory? Why you choose our
blocking 2.clocking blocks 2. ‘O’ command ? 2.’uvm utils macros company ?
2.Delay types 3.logic vs reg 3. replace command 3.component vs object What we(Cadence) do ?
3.Function vs task 4.packages 4.chomp 4.uvm_config_db vs
4.final vs initial block 5.virtual interfaces 5.chop resourse_db Protocols:
5.always@ vs 6.queue vs mailboxes 5.phases 1.wheather gates used in
always_comb 7.why queues are not used 6.how to start phases AHB-APB
instead of mailbox 7.which are top down and 2.Protocol details
8.scope resolution/use bottom up explanation
9.inout in modport? 8.uvm_analyis port? 3.Master to slave
9.user defined phases in UVM / communication
how to use it 4.Burst types?

Technical round - 2
1. Inter delays vs 1. Scoreboard 1. Is it necessary to create 1. Introduce ur self
intra delay 2. Packages components with factory 2. Scripting language?
:examples ? 3. If we declares same 3. VHDL?
function name in 4. UVM?
packages and module 5. 9 balls , 1 less weight
is it feasible puzzle
4. Race condition : 6. 3 bulbs , 3 switches
example puzzle
5. Monitor? 7. (a+b)^2
6. Why came to SV? 8. (a+b)^3
7. Features of SV 9. (a+b+c)^3 …..how do u
8. Class ? slove?
9. Oop concept ?
10. $monitor vs $ display ?
11. Abstract class : need :
why
Technical round - 3
1. Clocking Blocks ? 1. Sequence_item vs 1. 38*9
2. Race condition: avoid Sequence vs sequencer vs 2. 38*99
3. Function vs task Driver
4. Logic vs reg 2. Virtual_sequencer
5. Logic vs wire 3. How to drive value from
6. Can logic wire use test case
together 4. Agents in UVM
7. Can logic used for
internal variables
8. Logic vs bit
9. Modport
10. Config_db
11. Can ref is used in
module
12. Packages
13. Ref is used for
14. Monitor
Technical round : 4
1. Task vs function which 1. Self-introduction
you preferred to use 2. Verification Approach
3. Contributions and what
you done during
training course
4. After completion of
course till now what
you are doing
5. Are Written coverages
for FSM ?
HR_Round
1. Where do you stay ?
2. Why cadence?
3. Are u willing to relocate
4. How u came to know about this opening
5. Salary expectations

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