» Degree Examination, CBCS - June / July 2018 ARM Microcontroller and Embedded Systems Max. Marks: 80 FIVE full questions, selecting ONE full question from each module. Juswer any Module - 1 | m explain the architecture of ARM cortex m3 microcontroller (10 Marks) Ans. — : : oS | | { | f | 7 | 1 3 4 | ‘ ; len t | iL | Ui <1 | Private | Fhe conex m3 is a 32 bit microprocessor, It has a 32 bit data path, a 32 bit register bank and 32 bit memory interfaces. The processor has a hardward architecture, which ‘means that it has a separate instruction bus and data bus) This allows instructions and data accesses to take place at the same time and as a result of this the performance of the increases because data accesses do not affect the instruction pipeline. This feature results in multiple bus interfaces on cortex m3, cach with optimized usage and the ability to be used simultaneously. However the instruction and data buses share the same memory space. For complex applications that require more memory system features the cortex m3 processor has.an optimal memory protection unit and it in possible to use an external cache if its required. Both little Indian and big Indian Memory system are supported. The cortex m3 includes a number of fixed interngl Sunstar Exam Scanner 1 a. Scanned with CamScannerane Microconerolier andE Sytem, VE Senv (EC/TC) de debugging compere euing compen ms and features stl (06a \ . Explas sy General porpose exists ha RO RIO. RI RID RID (MSP) RIS (PSP) 5, RIS, (Stack polniy in banked rex m3 contains 2 stack pointers (R13). They are banked so that only one in les is called the return address in store RIS Program counter The PC Explain the operations modes and privilege levels available in ARM cortex MS wil a neat transition diagram, (06 Maris) 2 Sunstar Exam Seantet Tread mode wel for acing he oo Sn ued mse 01> crags PS 2 nay? cyl rye MRS 10 PRI MASK : nd 1 7 0 CONTROL sos in ARM cortex (06 Marks) arm corte, Scanned with CamScannerVE Sen (Corre) _ aml Microcontroller and Embedded, sy Treesrcalvac opin rman were option ith ie - ‘yan Sb Pan nrepicr wsanetin stra bY 8 PUSH ering 8 cee eet ee ror panne Swed a SOT SR oe steamer ce Site ico en ery ‘tore (PUSH there ube resem ea FOP an 8 ef oo Ron RR R2=2 bere! oe FSI > re Roo sc a : ~~ isnt tonack a USI (Ray se Rack acing (HO and ce ctge OPK sete RS a xc wisn og FOP) teste KI an SP ed OPURD etre sn SP ay Module -2 ‘issn, 6 i ae svete PSR ager wa sia gC Css [ager enéne USNR RR i ROR. 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Jiy 2018 find R3= Ox00001111 * {)RSBAV RS, RY, A010 ADD R8,R9,R3 {ii) BIC.W R6, RS, F006 {is) ORR RS, RO (08 Marks) ‘the contents of the Assume RS = 0300000088, RI = 0x00000006 RB=0><00000088, R9=0:<00000006 R3=0 0000111 ARSBWREROOXIO Scanned with CamScanner R8=0 00001107 )Bicw R6,R8,#0%06 ivJORRRSRI RS=RSIRI RS=0< 00001107 Module 3, ian architecture (08 Maris) case Tp Greater numberof instructions 2) Generally no instruction pipe linings feature FNon orthogonal instruction st 4) Operations ae performed on registers ememory depending onthe instucton Formed on reais 4) Operation Fe ad only the memory oP and storeVI Sem (EC/TC) ARM Microcontroller and Embedded syn, | ges -JunetIWy 2018 3) Limited vo interface WO interface al pe comme commun prot ‘its also known as dal om ‘hele oF gem “a sger byte3 byte 2b) Base address +0 020000 (base address) A 0x 20001 (BA +1) 0x20002 (BA+3) 0520003 (BA#3) ‘Base address +1 Base address +2 Base address +3 dian : Big endian atthe lowest address an teger byte 3 byte 2 yle | byted wi Scanned with CamScanner Base Address +0 [Byie3, 0x 20000 (BA) BA+I Byte2 0520001 (BA#+1) BAY Byte = | 0x20002(BA+2) BASS Byted 032003 (BA+3) ) 2C bus Gi) INDA (ii) Optocouper (08 Marks) b. What are the features of the follo (iv) 1 aire interface Ans. i) Ie bus ‘The inter Wire Device (EEPROM) developed by Phillips semi conductors 12C was to provider an easy way of cont x system and the peripheral chips clock SCL and ser ses af mec wel in Ee ten an mee (08 Marks) ssused in embeded spt tory (ROM) Read write memory / random a desig ae oe55 memory Infrared (IrDA) is serial half duplex i communication between devices itis in use from the ok with it IDA supports poi Sanstar Exam ScatterViSomCEC/TC) _ ARM Microcontroller andl Embedded sy, The rom en oe erg ey oe Smell Wan ge seen ert es tceret ven sie Power o het ‘Wispenly inom acton oles ey net Base HON (HNO) aes ROM a ORNL vie py, FROM mabe ye othe ecolog Fer storing ats, ot WOM Une mael ROM mena ee HH REAE ea, yg EEIWOM OTP ant fl nd wo development prose. EPROM sy the arption yearn he eating gt of on FE. TBEPROM S Aste me ides he tnrntion contin in she ‘memory cane ied ying lel sia he esters 3) Real write memory RAM. EPROM RAM SHAM oe) [Laveen Bandas omy wag myocyte secoceate tiem lien Bota eta Se RA se da eam of ene made up of fipflop static RAM is the fistest form of TAM available SRAM is. {Stipa het wie nwering al reece ee ‘opens mci oon ak recog regen on Rea sad 1 conta t read ymanie RAM (DRAM) : Dyas RAM sores hain the form of cha | ‘ume oof MOS tar ees The atatages of DRAM ae igh dt) {Jo ont compare o SRAM The drains i that sac the 5 Sore a share it gets lek off wit me an poet this hey He ed eof tn do pret thts , Explta the following crests an mi Reset ert. ame ‘Ans. () Brawn out protectin cca prevens te ee evens the proceso / sonra fom users Program execution beavis when the supply vote othe proses! cowl bee sytem s()Brown-ont prose aa ‘Sanshar Easn Sz tA ee ee ihaeal may Some es gether oem sieclcbretesal science reece Teena” ara ae soet aelentoe ‘irene tte ao ny ot dw a vee ee Teste 7 ‘he i * Ttve too ent Modute-4 et ey anergy oe Sol a rayon Simacuua is measure of how much 9 you can ely wpan the proper Rey pce ae to u Ean See Scanned with CamScanneroperational aspects are gf gory a easily one ea te inthe iment, ta (0 prototype and market fa product The Dataflow graph (DFG ‘4 data flow graph. The in DFG nota Tenibedded hardware esting ens he desired manner, where as frm W expected Way. ich is closely related to biology. Evolvabiliy translates the data processi : ined by data, model in represened using block arrows. represents inputs data and an outward arrow from the process represents produ (08 Marks) is a data di ee ow lets have a look atthe plementation ofa DFG. Suppose one ofthe functions Novo application conzins the comp imsutrol Dataflow Graph ment x=a+ band y=X-€. Control node aq a b ‘ Dataflow node Datafow node control DFG models sed foe modeling ap CDFG models consis both dat oper ts dts ow Graph as element and condition as deision Feta low nodes Letushaveafok theimplementation Jon making process. The CDFG model for he seme the decision making “embedded mavare des ses appreactes for embedded poets funtion tobe performed, eae sr aces a el yb sdf een ON Ea pct! based rare de THE come lo knwn spt oop oe Ba, Ans, coro ie ap et ad eked for applic fal and where the response tine is N0t ei al procedural progranmming where te code esited ria atte tp ofthe program codes 1 Surater Exam Scanner 2 canned with CamScanner ae1 4 first and the tasks just bel is true procedural one. The firmware execution flow non parameters and perform initial is memory, registers ete. ang fies task and execute it the second task ‘on Cop of it, example of GPOS used ‘windows embedded 8.1 which offers devices like handhelds, point of sale Ten acteristics of a embedded system. of a embedded system are as follows, 1) Application and domain specific 2) Reactive and Real Time 3) Operates in harsh environments buted size and weight 6) Power concerns 1) Application and domain specific: Ifyou closely observe find that each embedded system is designed to perf functions and they are developed in such a manner to do the inten« (08 Marks) wy embedded system, na set of defined sensors or input devices in realtime and t it reacts in a designed ms desired level. 3) Operates i should be deployed in controlled env embedded system deployed may be a dusty one or area subject to vibrations and shock, acs June Iuly 2044. Distributed : The tam er system many “tbl means that embedded systems may be apart bedded conto bedded systems may’ be @ ted embedded system from a 3 Product aesthetics i oduct aethtas choose a product 6) Power concerns: important factor that needs tobe hea ans embeed system shoul be designed in isipation by the system, Module-s utrenly held by another held by the ist process, Fombiad oecurrenee ofthese four conditions sted combedded system design and of IDE environment for naa 15 Sanchar Exam Seater Scanned with CamScannerVI Sem CEC/TC) A illustrated in the fi (PC) or host, which acts asthe heat ofthe ted based on the t7 hey are s tallable In embedded system development context IDE stands for for developing and debugging is a software package which bunt Cross performs cross + in the process of converting a source code writen in by processor / controller widerstandable machine code ‘software tool used for simulating the various conditions for checking lator 15 hardware des OR 10. a, Three processes with process IDs P1, P2, P3 with est 5, is respectively enters operation are involved. (08 Marks) Ans. p.[p.[, [P, 1s 24 SIT lime for PI = 14ms time =(P2+ P44 P34 PI)/4 = (04347414)/4 ins Suastar Exam Seater y cs June Tuly 2018 oe ua ma um Around Timer P2 "Seu “Turm Arouind Time for Pa Sing =(5-2)42 19342 i around time =(P2-+ P4+P3.4PI)/4 Lamsee b. Mention the sequence of operations embedding the Semare with 2 mer and draw the interfacing * (08 Marks) Ans. PG. for embedding the firmware with # programmer ie to the specified port of PC ¥y on the PC and ensure proper connectivity is meer ig the look pi into the open socket as per Ul - 17 Sanchar Exam Seanier - P r Scanned with CamScanner