UNIVERSITY OF ZIMBABWE

2020 May - June Examinations

2021 May -June Test 1

Faculty: SCIENCE

Department: COMPUTER SCIENCE

Paper Code and Title: HCT222 Computer Architecture and

Organization

Duration: 2 Hours

Examiner: Mr M. Munyaradzi

Authorized Material: Calculator

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Question 1 [25 marks]
Assume an arbitrary number system having a radix of 5 and 0, 1, 2, L and M as its independent
digits.
Determine:

(a) the decimal equivalent of (12ML.L1); [4 marks]

(b) the total number of possible four-digit combinations in this arbitrary number
system. [4 marks]

(c) Find the binary equivalent of (17F.F6)16 and the hex equivalent of

(1011001110.011011101)2. [4 marks]

(d) Find the octal equivalent of (2F.C4)16 and the hex equivalent of (762.013)8

[3 marks]

(e) In a number system, what decides

(i) the place value or weight of a given digit and [3 marks]

(ii) the maximum numbers representable with a given number of digits? [3 marks]

(f) Using 8-bit 2s complement notation,

perform the calculation 1710 – 2210 [4 marks]

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Question 2 [25 marks]
a) To process an instruction, a CPU goes through a cycle that has three main stages.
Name and describe each stage in this cycle [6 marks]

b) Four computer terms and eight descriptions are shown in the boxes below. Briefly
explain why you would link each computer term to the descriptions that you suggest.
[6 marks]

Computer Term Description

i. Data can be read but not altered

i. Arithmetic and logic unit (ALU) ii. Carries out operations like addition and
multiplication

iii. Stores bootstrap loader and BIOS

ii. Control unit
iv. Fetches each instruction in turn

v. Carries out operations such as AND,

iii. Random access memory (RAM) OR, NOT

vi. Stores part of the operating system

currently in use
iv. Read only memory (ROM)
vii. Stores data currently in use

viii. Manages execution of each instruction

c) One of the key features of von Nuemann computer architecture is the use of buses.
Provide a brief description for each of the buses.
[6 marks]

d) The seven stages in a von Neumann fetch-execute cycle are shown in the table below.
Place each stage in the correct sequence and also give a brief explanation on the
incrementation of the program counter with respect to the seven stages [7 marks]

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 Stage Sequence number
the instruction is then copied from the memory location contained
in the MAR and is placed in the MDR

the instruction is finally decoded and is the executed

the PC contains the address of the next instruction to be fetched

the entire instruction is then copied from the MDR and placed in
the CIR

the address contained in the PC is copied to the MAR via the

address bus

the address part of the instruction, if any, is placed in the MAR

the value in the PC is then incremented so that it points to the next

instruction to be fetched

Question 3 [25 marks]

a) Consider three different processors PI, P2, and P3 executing the same instruction set with
the clock rates and CPIs given in the following table.

i. Which processor has the highest performance [2 marks]

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 ii. If the processors each execute a program in 10 seconds, find the number of cycles find
the number of instructions. [3 marks]

iii. We are trying to reduce the time by 30% but this leads to an increase of 20% in the CPI.
What clock rate should we have to get this time reduction? [3 marks]

b) For problems below, use the information in the following table.

i. Find the IPC (instructions per cycle) for each processor. [2 marks]

ii. Find the clock rate for P2 that reduces its execution time to that of PI. [2 marks]

iii. Find the number of instructions for P2 that reduces its execution time to that of P3.
[3 marks]

c) The following table shows the number of instructions for a program.

i. Assuming that arithmetic instructions take 1 cycle, load and store 5 cycles and branch 2
cycles, what is the execution time of the program in a 2 GHz processor?
[3 marks]
ii. Find the CPI for the program. [3 marks]

iii. If the number of load instructions can be reduced by one-half, what is the speed-up and
the CPI? [4 marks]

Question 4 [25 marks]

a) Describe pipelining, different pipelining hazards and how are they can be eliminated
[3,3,2 marks]
b) Briefly describe cache coherency and how is it eliminated [5 marks]

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 c) Cache performance can be improved in a number of ways, briefly
describe how [5 marks]
d) Explain the difference between hardwired control and micro programmed control.
e) The following four cache designs C1 through C4, are proposed for the Beta. All use LRU
replacement where applicable (e.g. within each set of a set associative cache).
Cache C1 C2 C3 C4
Total Data 8K 4K 8K 16K
Words
Total Lines 8K 4K 4K 8K
Associativity Fully 2-way S.A Direct Mapped Fully
Block size, 1 1 2 2
words/line

i. Which cache would you expect to take the most chip area (hence cost)? [2 marks]
ii. Which cache is likely to perform worst in a benchmark involving repeated cycling
through an array of 6K integers? Explain. [2 marks]
iii. It is observed that one of the caches performs very poorly in a particular benchmark
which repeatedly copies one 1000-word array to another. Moving one of the arrays seems
to cure the problem. Which cache is most likely to exhibit this behaviour? Explain.
[3 marks]

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