UM0116 User Manual: STR7 Family Flash Programming
UM0116 User Manual: STR7 Family Flash Programming
User manual
Introduction
This reference manual describes how to program the Flash memory of an STR7
microcontroller.
The STR7 embedded Flash memory can be programmed using In-Circuit Programming or
In-Application programming.
The In-Circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG protocol to load the user application into the microcontroller.
ICP offers quick and efficient design iterations and eliminates unnecessary package
handling or socketing of devices.
In contrast to the ICP method, In-Application Programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART...) to
download the data to be programmed in memory. IAP allows you to re-program the Flash
memory while the application is executing. Nevertheless, part of the application has to have
been previously programmed in one of the Flash banks using ICP.
The MCUs supported by this reference manual are the STR71x, STR73x and STR75x.
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
FPEC (FLASH Program/Erase controller): The write operations to the 2 banks are managed
by an embedded FPEC.
IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of
a microcontroller while the user program is running.
ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a
microcontroller using JTAG protocol while the device is mounted on the user application
board.
JTAG (Joint Test Action Group): The debug interface of the ARM7TDMI core is based on the
Joint Test Action Group (JTAG) protocol.
Contents
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UM0116 Contents
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Flash module organization UM0116
The on-chip Flash is divided in 2 banks that can be read and modified independently one
from the other: one bank can be read while another bank is being modified.
Table 1 shows the Flash Module Organization, while Table 2 shows the Control Register
interface, with the registers that can be addressed by the CPU.
FLASH_CR1-0 Flash Control Registers 1-0 0x10 0000 - 0x10 0007 2 x 32-bit
FLASH_DR1-0 Flash Data Registers 1-0 0x10 0008 - 0x10 000F 2 x 32-bit
FLASH_AR Flash Address Register 0x10 0010 - 0x10 0013 32-bit
FLASH_ER Flash Error Register 0x10 0014 - 0x10 0017 32-bit
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UM0116 Flash module organization
The Flash program memory is organized in 32-bit wide memory cells which can be used for
storing both code and data constants. The flash module is located at a specific base
address in the memory map of each STR7 Microcontroller type. For the base address,
please refer to the related STR7 Microcontroller Reference Manual.
SystemMemory is a sector used to boot the device in SystemMemory Boot Mode. The area
is reserved for use by STMicroelectronics. It is programmed by ST when the device is
manufactured and protected against spurious write/erase operations.
Bank 1 contains 16 Kbytes of Data Memory: it is divided into 2 sectors (8 Kbytes each). You
can program application data in this area.
You can Program Bank 0 and Bank 1 independently, i.e. you can read from one bank while
writing to the other.
The write operations of the two banks are managed by an embedded Flash Program/Erase
Controller (FPEC). The high voltage needed for Program/Erase operations is internally
generated.
The Flash memory can be protected against different types of unwanted access
(read/write/erase). There are two types of protection:
● Sector Write Protection
● Flash DEBUG/READOUT Protection
Refer to Section 3 for more details.
During a Flash write operation any attempt to read the bank under modification will output
invalid data. This means that the Flash bank is not fetchable when a write operation is
active.
Note: The write operation commands must be executed from another bank or another memory
(internal RAM or external memory).
You can program Flash memory using In-Circuit Programming and In-Application
programming.
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Read/program the STR7 embedded Flash UM0116
2.1 Introduction
This section describes how to read or to program the STR7 embedded Flash.
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UM0116 Read/program the STR7 embedded Flash
Once the write operation is started, the Flash controller checks the validity of the operation
(see Section 2.3.7 on page 9). When validity has been verified, it sets the BSY bits in
FLASH_CR0 while processing the operation. The Flash controller releases the BSY bits
when the operation is completed.
The Flash controller can only manage one write operation at a time. For example, it is not
possible to program a word while erasing a sector even if the word belongs to a different
sector. During a write operation to a user bank, any access to the bank is forbidden and will
return undefined data.
This means that code or data fetches cannot be made while a write operation on the bank is
being performed.
To bypass this limitation, for long operations like a sector erase, a suspend mechanism
enables to temporary stop it to perform higher priority tasks. After the high priority tasks
complete, the previous operation can be completed.
The bits in the FLASH_CR0 register allow you to monitor the Flash controller status and to
check if a write operation is on going.
An interrupt request can be generated at the end of each write operation if the INTM bit in
the FLASH_CR0 register is set.
It is recommended to read the Flash Error Register (FLASH_ER), at the end of a write
operation, to check that the operation was completed successfully.
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Read/program the STR7 embedded Flash UM0116
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UM0116 Read/program the STR7 embedded Flash
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Read/program the STR7 embedded Flash UM0116
Table 4. Abbreviations
read/write (rw) Software can read and write to these bits.
read-only (r) Software can only read these bits.
Software can read as well as clear this bit by writing ‘0’. Writing ‘1’ has
read/clear (rc_w0)
no effect on the bit value.
Software can read as well as set this bit. Writing ‘0’ has no effect on
read/set (rs)
the bit value.
reserved (Res.) Reserved bit, must be kept at reset value.
WMS SUSP WPG DWPG SER Res. Res. SPR Res. SMBM2) INTM INTP Reserved
rs rw rw rw rw rw rc_w0 rw rc_w0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3) 1)
PWD Reserved LOCK Res. BSYA1 BSYA0 Res.
rw r r r
1) 2) 3)
Not available in STR73x. Available only in STR73x. Not available in STR75x.
The Flash Control Register 0 (FLASH_CR0) is used to enable and to monitor all the write
operations for the Flash controller.
Note: If two or more operation selection bits (WPG, DWPG or SER) are set at the same time, they
will be ignored and the current operation will be cancelled.
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UM0116 Read/program the STR7 embedded Flash
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Read/program the STR7 embedded Flash UM0116
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UM0116 Read/program the STR7 embedded Flash
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Read/program the STR7 embedded Flash UM0116
rs rs rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rw rw rw rw rw rw rw rw
1)
Not available in STR73x.
The Flash Control Register 1 (FLASH_CR1) is used to specify the Sectors or the Banks to
be erased, or during any write operation started with the WMS bit to monitor the status of
each sector and each bank of the module.
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UM0116 Read/program the STR7 embedded Flash
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
The Flash Address Register (FLASH_AR) and the Flash Data Registers (FLASH_DR1-0)
must be written by software, prior to starting a programming operation, to specify the target
address and the data to be programmed in Flash.
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Read/program the STR7 embedded Flash UM0116
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Reserved
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved WPF RESER SEQER Res. Res. 10ER PGER ERER ERR
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UM0116 Read/program the STR7 embedded Flash
Note: Double Word Program is always performed on the Double Word aligned on a even Word: bit
ADD2 of FLASH_AR is ignored.
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Read/program the STR7 embedded Flash UM0116
Note: Original setup of Select Operation bits in FLASH_CR0 must be restored before the
operation resume, otherwise the operation is aborted and bit RESER of FLASH_ER is set.
Note: Before resuming a suspended erase, FLASH_CR1 must be read to check if the Erase is
already completed (FLASH_CR1=0x00000000 if Erase is completed).
Example: Word Program of data 0x5555AAAA at address 0x05554 in the Flash Module.
FLASH_CR0 |= 0x20000000; /*Set WPG in FLASH_CR0*/
FLASH_AR = 0x00005554; /*Load Add in FLASH_AR*/
FLASH_DR0 = 0x5555AAAA; /*Load Data in FLASH_DR0*/
FLASH_CR0 |= 0x80000000; /*Operation start*/
Once the Program operation is finished, the Erase operation can be resumed in the
following way:
FLASH_CR0 |= 0x08000000; /*Set SER in FLASH_CR0*/
FLASH_CR0 |= 0x80000000; /*Operation resume*/
Note: Note that during the Program Operation in Erase suspend, bit SER and SUSP are low.
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UM0116 Flash memory protection
Two kind of protections are available: sector Write protection to prevent unwanted writes and
DEBUG/READOUT Protection to avoid software piracy. They are described in the following
subsections.
The protection bits are stored in non-volatile Flash cells that are read once at reset and
stored in 3 volatile registers:
● FLASH_NVWPAR used to store the write protection bits for each sector of the Flash
Module
● FLASH_NVAPR1-0 used to store the DEBUG/READOUT protection bit.
The first time you program FLASH_NVWPAR or FLASH_NVAPR0 both the non-volatile and
volatile part of the register are written. At any later stage, any write to these registers will
affect only the volatile part, which will be restored with the content of the corresponding non-
volatile part at the next reset event.
The content of the non-volatile part of the register FLASH_NVAPR1 is also copied at every
reset event into the corresponding volatile register. In this case however any write will
always update both the volatile and the non-volatile parts.
Note: Before being configured by the reset process, all the available protections are forced active
during reset.
The protection registers are not directly accessible for writing. They can be programmed
using a set protection operation and writing them as a normal write operation.
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Flash memory protection UM0116
ensure that the software does not provide a way for a hacker to download the Flash
memory content.
● In Embedded SRAM Boot Mode (STR75x): the embedded Flash is automatically
disabled and thus it is not possible to download its content (it is also not possible to
execute it).
● In Exernal Memory Boot Mode
– In the STR71x, it is not possible to use EMI boot mode when DEBUG protection is
enabled.
– In the STR75x, it is possible to use SMI boot mode when READOUT protection is
enabled, but the embedded Flash is automatically disabled and its content cannot
be downloaded or executed.
● In SystemMemory Boot Mode (STR73x/STR75x), then the program executed from
SystemMemory ensures that it is not possible to output the embedded Flash memory
contents.
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UM0116 Flash memory protection
Reserved W1P[1:0]1)
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved W0P[7:0]
rw
1)
Not available in STR73x.
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Flash memory protection UM0116
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBUG READ
Reserved
1) OUT2)
rw rw
1)
Not available in STR75x.
2)
Not available in STR71x and STR73x.
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UM0116 Flash memory protection
PEN[15:0]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDS[15:0]
rw
The FLASH_NVAPR1 register is organized as 16 pairs of bits (PENx - PDSx). The delivery
value of The FLASH_NVAPR1 register is 0xFFFFFFFF. The first time you disable the
DEBUG/READOUT protection you must program to PDS0 ‘0’. To re-enable the protection
you must program to bit PEN0 ‘0’: this is possible only if PDS0 has been already
programmed to ‘0’. This cycle of disabling/re-enabling the protection can be repeated with
the next PDS1/PEN1 pair of bits and so on. PDS1 can be programmed to ‘0’ only if PEN0
has been already programmed to ‘0’, PEN1 can be programmed to ‘0’ if and only if PDS1
has been already programmed to ‘0’. The programming to ‘0’ of the bits of the
FLASH_NVAPR1 register must therefore follow the PDS0-PEN0-PDS1-PEN1-PDS2-PEN2-
...-PEN15 sequence, obtaining up to 16 unprotection/protection cycles.
Note: At any reset event the non-volatile part of FLASH_NVAPR1 register is copied into its volatile
part. Unlike with the FLASH_NVAPR0 and FLASH_NVWPAR register, any write will always
update both the volatile and the non-volatile parts: i.e. no temporary unprotection is possible
with FLASH_NVAPR1 register.
Note: All the STR73x Flash protection registers (FLASH_NVWPAR, FLASH_NVAPR0 and
FLASH_NVAPR1) are write only in User boot modes and Read/Write when booting from
SystemMemory mode.
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Flash memory protection UM0116
Note: You can disable and re-enable the DEBUG/READOUT Protection permanently (as shown in
examples 5 and 6) a maximum of 16 times.
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UM0116 Flash register map
Addr. Regis
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
ter 9 8 7 6 5 4 3 2 1 0
Offset Name
DWPG
SMBM
SUSP
LOCK
BSY1
BSY0
INTM
WMS
WPG
PWD
INTP
SER
SPR
Res.
Res.
Res.
0x10 FLASH
Res. Reserved Reserved
0000 _CR0
B1F1
B1F0
0x10 FLASH
B1S
B0S
Reserved Reserved Reserved B0F(7:0)
0004 _CR1
0x10 FLASH
DIN(31:0)
0008 _DR0
0x10 FLASH
DIN(31:0)
000C _DR1
0x10 FLASH
ADD(31:0)
0010 _AR
SEQER
RESER
PGER
ERER
10ER
WPF
ERR
Res.
Res.
0x10 FLASH
Reserved
0014 _ER
FLASH
W1P1
W1P0
0x10
_NVW Reserved Reserved W0P(7:0)
DFB0
PAR
READOUT
DEBUG
FLASH
0x10
_NVAP Reserved
DFB8
R0
FLASH
0x10
_NVAP PEN(15:0) PDS(15:0)
DFBC
R1
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Revision history UM0116
5 Revision history
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UM0116
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