Lec 24 Design of Hack Computer
Lec 24 Design of Hack Computer
Memory
data
@R1
a CHIP Xor { program
And Memory
output
ALU
D=M
IN a, b;
Not notb aAndNotb
OUT out; instruction
register
instruction instruction @temp
PARTS:
data
load M=D
Or out on
Not nota
Not(in=a, out=nota); Memory
address
fetch
input
notaAndb Not(in=b, out=notb);
mux
And And(a=nota, b=b, out=w1); data
fetch /
execute
instruction
b And(a=a, b=notb, out=w2); address address bit
control bus 0 00 00 00 00 0 00 00 01
Or(a=w1, b=w2, out=out);
} address bus
1 11 11 10 00 0 01 00 00
address bus (data flows not shown, to minimize clutter)
0 00 00 00 00 0 01 00 00
Nand to Tetris / www.nand2tetris.org / Chapter 5 / Copyright © Noam Nisan and Shimon Schocken Slide 25
ulator
1 11 00 01 10 0 00 10 00
nput pins (e.g. a and b)
Lecture # 24
tb, notaAndb)
Design of Hack Computer
ight © Noam Nisan and Shimon Schocken Slide 33
global main
SECTION .data
msg: db "Learning is fun with Arif", 0Ah, 0h
len_msg: equ $ - msg 0: b8 01 00 00 00
SECTION .text 5: bf 01 00 00 00
main:
#include<stdio.h> mov rax,1 a: 48 be 00 00 00 00 00
#include<stdlib.h> mov rdi,1 11: 00 00 00
int main(){ mov rsi,msg 14: ba 1b 00 00 00
mov rdx,len_msg
printf("Learning is fun with Arif\n"); syscall
19: 0f 05
exit(0); mov rax,60 1b: b8 3c 00 00 00
} mov rdi,0 20: bf 00 00 00 00
syscall 25: 0f 05
instruction ALU
data
memory memory
address of data in
next
instruction D register
A register
PC
reset
outM
From data memory inM 16
16 writeM To Data Memory
ALU 1
addressM
From instruction memory instruction 15
16
CU
restarting reset
D register
15 PC To Instruction Memory
signal 1 A register
PC
Inputs: Outputs:
• Data Value • Data Value
• Instruction • Write to Memory? (yes/no)
• Reset Bit • Memory Address
• Address of next instruction
Instructor: Muhammad Arif Butt, Ph.D. 5
Chip Parts of Hack CPU and their Control
ALU Output ALU Output
instr[4]
instr[6..11]
loadAReg
D register
inM Mux16
M input
Write M
C
A register output zr, ng
instr[12] Address M
Memory address output
Reset
Reset bit
load
PC
Program counter output
PC
D register
inM Mux16
M input
Write M
C
A register output zr, ng
Address M
Memory address output
Reset
Reset bit
PC
Program counter output
PC
D register
Instrution
Mux16 A register Complete
ALU
Specification Out M
loadAReg
D register
y Code Format:
Mux16
Instrution
C-Instruction
A register Out M
ALU
dest= comp ;jump
111 a cccccc ddd jjj instr[15]
inM Mux16
M input
c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 Write M
C
A register output zr, ng
instr[12] Address M
Memory address output
Reset
Reset bit
loadAReg
D register
y Code Format:
Mux16
Instrution
C-Instruction
A register Out M
ALU
dest= comp ;jump
111 a cccccc ddd jjj instr[15]
inM Mux16
M input
c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 Write M
C
A register output zr, ng
instr[12] Address M
Memory address output
Reset
Reset bit
c5 c6 d1 d2 d3 loadAReg
j1 j2 j3
D register
dest d1 d2 d3 effect: the value is stored in:
null
Instrution 0 0Mux16
0 The valueA register
is not stored Out M
M 0 0 1 RAM[A] ALU
111 Da cccccc 0ddd jjj
1 D register
0 instr[15]
MD 0 1 1 RAM[A] and D register Mux16
inM
A 1 0 0 A register
M input
Reset
Reset bit
jump j1 j2 j3 effect: load
null 0 0 0 no jump PC
Program counter output
JGT 0 0 1 if out > 0 jump
PC
JEQ 0 1 0 if out = 0 jump
JGE 0 1 1 if out ≥ 0 jump
JLT 1 0 0 if out < 0 jump load = f(jump bits, zr/ng bits)
JNE 1 0 1 if out ≠ 0 jump if (load == 1)
JLE 1 1 0 if out ≤ 0 jump
JMP 1 1 1 Unconditional jump PC = A
Instructor: MuhammadifArif 11
to jump to ROM[17], D-1Butt,
==Ph.D.
0
Control Input of ALU Chip
ALU Output ALU Output
instr[4]
instr[6..11]
loadAReg
D register
Complete Specification
Mux16
Instrution
A register of C-Instruction ALU
Out M
inM Mux16
1 11 a c1 c2 c3
M input
c4 c5 c6 d1 d2 d3 j1 j2 j3
Write M
comp c1 c2 c3 c4 c5 c6 dest d1 d2 d3
A register output
effect: the value is stored in: zr, ng
C
0 1 0 1 0 1 0 null 0 0 0 The value is not stored
1 1 1 1 1 1 1 M 0 0 1 RAM[A]instr[12] Address M
Memory address output
-1 1 1 1 0 1 0 D 0 1 0 D register
Reset
D 0 0 1
Reset bit
1 0 0 MD 0 1 1 RAM[A] and D register
A M 1 1 0 0 0 0 A 1 0 0 A register load
!D 0 0 1 1 0 1 AM 1 0 1 A register and RAM[A]
!A !M 1 1 0 0 0 1 AD 1 1 0 A register and D register
-D 0 0 1 1 1 1 AMD 1 1 1 A register, RAM[A], and D register PC
Program counter output
-A -M 1 1 0 0 1 1
D+1 0 1 1 1 1 1 jump j1 j2 j3 effect:PC
A+1 M+1 1 1 0 1 1 1 null 0 0 0 no jump
D-1 0 0 1 1 1 0
JGT 0 0 1 if out > 0 jump
A-1 M-1 1 1 0 0 1 0
D+A D+M 0 0 0 0 1 0 JEQ 0 1 0 if out = 0 jump
D-A D-M 0 1 0 0 1 1 JGE 0 1 1 if out ≥ 0 jump
A-D M-D 0 0 0 1 1 1 JLT 1 0 0 if out < 0 jump
D&A D&M 0 0 0 0 0 0 JNE 1 0 1 if out ≠ 0 jump
D|A D|M 0 1 0 1 0 1 JLE 1 1 0 if out ≤ 0 jump
a==0 a==1 JMP 1 1 1 Unconditional jump
PARTS:
// Chip implementation code on next slide
✔
instruction data out
instruction ALU
data
memory memory
address of data in
next
instruction D register
A register
PC
reset
in
RAM
16 (16K)
out
16,383
16,384 Screen 16
address (8K
24,575 memory
15 map)
24,576 Keyboard
Memory Load
0 16K-Register/words RAM
in
in RAM Implementation tips:
• Memory of 16K registers, each 16 bit-wide. Out holds the value stored at the
(16K) 16
memory location specified by address. If load==1, out then the in value is loaded
16 RAM
into the memory location specified16by address (the loaded value will be emitted
out to out from the next time step onward)
address
16
• Feed the 16 bit i n value to all the registers, simultaneously
16,383 16 • Use DMux8Way chip to select one of the eight registers specified by address
Screen 15• Use Mux8Way16 chip to select the 16 bit contents of register specified by
address 16,384 address on 16 bit out output
(8K
15 memory RAM16K.hdl
24,575 map)
CHIP RAM16K {
24,576 Keyboard
IN in[16], load, address[14];
OUT out[16];
PARTS:
DMux4Way(in=load, sel=address[12..13], a=load0, b=load1, c=load2, d=load3);
in
in 0 RAM 16 out
Screen
16
(16K) 16
16,383 address
16,384 Screen out
(8K 15
memory 16
address 24,575 map)
24,576
15
Keyboard Screen Built in Chip
Screen.hdl
CHIP Screen {
IN in[16], // what to write
load, // write-enable bit
address[13]; // where to read/write
OUT out[16]; // Screen value at the given address
BUILTIN Screen;
CLOCKED in, load;
}
Memory
0
in 0 RAM
16
in (16K) RAM built-in
16,383 chip
16,384 (16K)
out
16 Screen
(8K out
memory 16
16,383 16
address 24,575 map)
16,384 Screen
address
24,576
15 Keyboard (8K memory
15 24,575
map) Key Board Built in Chip
KeyBoard.hdl
24,576 Keyboard
CHIP Keyboard {
Nand to Tetris / www.nand2tetris.org / Chapter 5 / Copyright © Noam Nisan and Shimon Schocken
20
Instructor: Muhammad Arif Butt, Ph.D.
Memory Chip Implementation
Memory.hdl
CHIP Memory {
IN in[16], load,
/** The complete address[15];
address space of the Hack computer's data memory, including RAM and memory-
OUT mapped I/O. Facilitates read and write operations, as follows:
out[16];
PARTS: Read: out(t) = Mem[address(t)](t)
DMux(in=load, sel=address[14], a=loadRam, b=loadScreen);
Write: if load(t) then Mem[address(t)](t+1) = in(t)
RAM16K(in=in, address=address[0..13], load=loadRam, out=outRam);
In words: the chip always
Screen(in=in, outputs the value stored at the memory
address=address[0..12], location specified by address.
load=loadScreen, out=outScreen);
Keyboard(out=outKeyboard);
If load==1, the in value is loaded into the register specified by address. This value becomes available
through the out output from the
Mux4Way16(a=outRam, next time stepc=outScreen,
b=outRam, onward. d=outKeyboard, sel=address[13..14],
out=out);
The memory access rules are as follows:
} Only the top 16K+8K+1 words of the address space are used.
0x0000-0x5FFF: accessing an address in this range results in accessing the RAM. 21
Instructor: Muhammad Arif Butt, Ph.D.
0x4000-0x5FFF: accessing an address in this range results in accessing the Screen.
The Hack Computer
✔ ✔
instruction data out
instruction ALU
data
memory memory
address of data in
next
instruction D register
A register
PC
reset
Hack Program
0000000000001101
1110101001010101 instruction data out
0000000000000001 Instruction data
1110101001101011 load memory CPU
0000001100110101 memory
1110010111011111 ROM32K
*
* Address data in
*
1111001001100111
reset
Hack Program
0000000000001101
1110101001010101 Instruction instruction data out data
0000000000000001
memory CPU memory
1110101001101011 load
0000001100110101 ROM32K
1110010111011111
*
* Address data in
*
1111001001100111
reset
Hack Computer
reset
reset
✔ inM ✔
instruction ✔ writeM
reset
CHIP Computer {
IN reset;
PARTS:
ROM32K(address=pc, out=instruction);
CPU(inM=memoryOut, instruction=instruction, reset=reset, outM=outM,
writeM=writeM, addressM=addressM, pc=pc);
Memory(in=outM, load=writeM, address=addressM, out=memoryOut);
}
Demo
Hack Computer Chip
add.asm, swap.asm,
rect.asm