International Journal of Advanced Information Science and Technology (IJAIST) ISSN: 2319:2682

Vol.4, No.9, September 2015 DOI:10.15693/ijaist/2015.v4i9.60-64

Design and Analysis of Charge Pump for

PLL Applications using 70nm Technology
DEEPSHIKHA MITTAL1 VIRENDRA VERMA2
M.TECH Scholar Assistant Professor
Dept. of Electronics & Communication Dept. of Electronics & Communication
Sanghvi Inst. Of Management & science Sanghvi Inst. Of Management &science
Indore,IndiaIndore,India

Abstract—This paper presents a CMOS Charge Pump a phase frequency detector (PFD), a CP, a passive loop
using 70nm technology that operates at 0.7V. The filter (LF), and a voltage controlled oscillator (VCO). In
proposed circuit has simple symmetric structure and a PLL the phase difference between the reference signal
provides more stable operation deals with different (often from a crystal oscillator) and the output signal is
approaches to design a high speed CMOS charge pump translated into two signals – UP and DN. The output of
circuit for PLL application. A charge pump is a kind of
the PFDis fed to a charge pump circuit to get a constant
DC to DC converter that uses capacitors as energy storage
elements to create either a higher or lower voltage power current at the output. The charge pump output is passed
source. Its frequency range is 500MHz to 1GHz.Charge through a low pass filter to generate the control voltage
pump is one of the important parts of PLL which converts for the VCO circuit. Figure1 show block diagram of
the phase or frequency difference information into a PLL [3].
voltage, used to tune the VCO.

Keywords—charge pump, PFD, loop filter, phase-locked

loops (PLL).

I.INTRODUCTION

A charge pump IC converts, and optionally regulates,

voltages using switching technology and capacitive-
energy storage elements. Charge pumps offer high-
efficiency and compact solutions for applications with
generally low-output current requirements. Charge Figure 1: Phase Locked Loop
pump maintain constant output with a varying voltage
input. A charge pump based Phase lock loops (PLL) are
widely used as a clock generator in a variety of Hence there are five functional blocks in a PLL circuit
applications including microprocessor, wireless such as phase frequency detector (PFD), Charge Pump,
receivers, and disk drive electronics [3]. As technology loop filter, voltage controlled oscillator (VCO) and
changes, our demands are also increases, high speed, frequency divider.
portable and low power consumption communication In this paper explain Charge Pump circuit and also
system has become increasingly day by day. These taken result of many research worker.
systems require high-precision local clock generator
(local oscillator) and difficulty is deal with the help of II.OVERVIEW OF BASIC CHARGE PUMP
PLL circuit design. Due to the irreplaceable advantages,
this technology is most widely in CMOS charge pump A charge pump is a three position electronic switch
phase lock loop (CPLL). CPLL is a very simple and which is controlled by the three states of PFD. Current
efficient method of designing PLL having low jitter and sources I1 and I2 are identical. Two outputs of PFD QA
low power, zero static phase error and high speed [14]. and QB are given to the X and Y inputs of charge pump
The charge pump circuit is the heart of PLL. The (CP) respectively. Capacitor Cp serves the purpose of
charge pump (CP) based PLL is the most popular loop filter. Figure 2 shows the combined architecture
architecture. The CP-PLL derives its name from the of the charge pump and loop filter [6].
fact that the phase detector (PD) output is a current If QA=QB=0, then S1 and S2 are off and Vout (or
source as opposed to a voltage source and "pumps" Vcont) remains constant. If QA is high and QB is low,
current into and out of the loop-filter. This form of PLL then I1 (UP current) charges Cp. Conversely if QA is
is popular because it is adaptable to integration in low and QB is high, then I2 (DOWN current) discharges
microcircuit devices. This type of the CPLL consists of

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International Journal of Advanced Information Science and Technology (IJAIST) ISSN: 2319:2682
Vol.4, No.9, September 2015 DOI:10.15693/ijaist/2015.v4i9.60-64

Cp. Hence, if suppose, A leads B, then QA continues to When they are both ON, they operate in the saturation
produce pulses and Vout rises steadily. region. So to carry same currents, P5 and N1 have to be
perfectly matched.

Figure 3: Propose Charge Pump

IV. PROPOSED PFD

Figure 2: PFD-CP-Loop Filter Combination
The PFD circuit is used to find the difference in phase
and frequency between the two input signals reference
III. PROPOSED CHARGE PUMP DESIGN frequency and input frequency which is feedback from
the output of the VCO. The PFD generates two output
signals UP and DOWN that switches the output current
There are number of charge pump circuits were of the pump. PFD circuit generally implemented using
designed to reduce jump phenomenon and current D flip-flops (DFFs). The output of the PFD depends
mismatch. The proposed circuit is low voltage and upon both phase and frequency of the input signals.
increases the performance of the charge Initially both the signals will be low. When one of the
pump.Improved charge pump circuit is shown in figure PFD input rises the corresponding output becomes high.
3. The simulationswaveforms are shown in fig. the
First when the signal UP is at a high logical level diagram of PFD are shown below in fig.4 (a) which is
transistor P1 is off, and the current IUP is steered to implementing on Tanner Tool.
transistor P2. Since the power supply is 0.7V, when
transistor P2 is ON, transistor P4 will not have enough
voltage headroom between its gate and source to be
ON.Since transistors P2 and P3 form a current mirror, a
current IUP will be pushed into the capacitor C, raising
the voltage VC. Now when the signal UP is at logical
zero transistor P1 and P4 turn ON. The current steered
in P2 and therefore P3 negligible. The voltage at the
capacitor should, ideally remain stable. P5 and N1 are
used to pre-discharge to the gate of P3. When the UP
signal is switched from 0 to 1, the charging time of P3
is relatively long, which result in delaying open speed
of P3. So to overcome this problem, P5 and N1 are
taken advantage at the gate of P3. Then the voltage at
the gate of P3 is rapidly pulled down once the UP
signal switches from 0 to 1 opening P3 in a much
shorter time. In other hand DN=1 pull-down network is
ON and the capacitor CP will be discharged.

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International Journal of Advanced Information Science and Technology (IJAIST) ISSN: 2319:2682
Vol.4, No.9, September 2015 DOI:10.15693/ijaist/2015.v4i9.60-64

Figure 5: Pumping Up the Output Voltage

Figure 4(a): PFD using DFF

UP and DOWN signals generated by the PFD are shown in

fig 4(b). PFD is simulate using tanner tool, and the supply
voltage is 0.7V.

Figure 6: UP current when charging the capacitor

Figure 4(b): Up and Down Signals

V. SIMULATION RESULTS Figure 7: Pumping Down the Voltage

The proposed charge pump was designed using 70nm

CMOS technology. All results are reported are with a
0.7V power supply. Simulations were done using
Tanner tool. The pull UP current I1 and pull down
current I2are both set to 70µA.the operating frequency
is 500MHz.

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International Journal of Advanced Information Science and Technology (IJAIST) ISSN: 2319:2682
Vol.4, No.9, September 2015 DOI:10.15693/ijaist/2015.v4i9.60-64

[4] V. Lule, V. Nasre, “Area professional 0.18um CMOS Phase

Frequency Detector for high speed PLL”. InternationalJ.
ofScientific and Research, Vol. 2, February 2012.

[5]S.B. Rashmi, Siva S. Yellampalli, “Deign of Phase

FrequencyDetector and Charge Pump for high Frequency
PLL”.International J. of Soft Computing And Engineering, Vol. 2
May2012.

[6] B. Razvi, Design of ANALOG CMOS Integrated, Mc Graw-

Hill, 2001.

[7] Woogeun Rhee, “Design of High-Performance CMOS Charge

Pumps in Phase-Locked Loops”, IEEE International
Symposiumon Circuits andSystems, ISCAS‟99. vol. 2, 30 May-2
June 1999,pp.545-548.
Figure 8: Down Current When Discharging the Capacitor
[8] Yuan Sun, Liter Siek, andPengyu Song, “Design of a
HighPerformance Charge Pump Circuit for Low Voltage
PhaseLocked Loops”, IEEE2007 International Symposium on
Table I Integrated Circuits (ISIC-2007), pp. 270- 274.
PERFORMANCE SUMMARY
[9] Xue Hong, Li Zhiqun, Wang Zhigong, et al., “Charge Pump
Design for PLL Synthesizer”, Chinese Journal Of
Semiconductor, vol. 28, NO.12, Dec. 2007, pp. 116-120.
Parameter Results
Technology 70nm [10] Jae-Shin Lee, Min-Sun Keel, Shin-Il Lim, et al, „„Charge
PumpWith perfect current matching Characteristics in Phase
Locked Loops‟‟, Electronics Letters, Vol.36, No.23 9
Power supply 0.7V Nov.2000, pp. 1907-1908.

Frequency 500MHz to 1000MHz [11]Li Zhiqun et al, „„Design of a high performance CMOSCharge
Pump for phase-locked loop Synthesizer”, Chinese Journal of
Power 0.41mW Semiconductors, vol. 32, NO.7, July 2011, pp, 116-120.
consumption
Output voltage 200mv to 500mv [12]Aniruddha c. kailuke et al, “design and Implementation of low
Power Dickson charge Pump in 0.18um CMOS
process”,international Journal of scientific & engineering
Up and down 70µA research, vol. 4, August 2013.
Current
[13] S. Chen, Z. Li, “An improved high speed charge Pump in 90nm
CMOS technology”, IEEE journal of Solid state in 2011.

VI. CONCLUSION [14] Zhiqum Li et al, “A Novel CMOS Charge Pump with High
Performance for Phase-Locked Loops Synthesizer”,
IEEEjournal, 25-28 Sept. in 2011.
We are presented a new charge pump circuit, optimized
for very low voltage PLL applications. The circuit was [15] Crawford James A, “Frequency Synthesizer
designed using 70nm technology. It operates from a DesignHandbook”[M]. Boston London Artech House 1994.
lower power supply voltage 0.7V, compared to recently
[16]Ganesh Kumar Balachandran, Phillip E. Allen, “Switched
reported designs. Simulation results showed that the Current Circuits in Digital CMOS Technology with Low
circuit is suitable for high frequency operation Charge Injection Errors” [J]. IEEE Journal of Solid-
(500MHz to 1GHz) with lower power consumption StateCircuits, 2002, 37(10), pp.1271-1281.
0.41mW).This circuit is implementing using Tanner
[17]Yuan Sun, Liter Siek, Pengyu Song, “Design of
Tool. HighPerformance Charge Pump Circuit for Low Voltage Phase-
locked Loops”. IEEE International Symposium on Integrated
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Authors Profile
[2] C. Cao, Y. Ding, Kenneth K. O., “A 50-Ghz Phase Locked
LoopIn 0.13um CMOS”.IEEE Journal of Solid- State Circuits, Miss Deepshikha Mittalreceived
Vol. 42, no. 8, August-2007. the B.E. degree in Electronics and
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[3]Huili Xu1, Zhiqun Li, “Design of a Low Power Charge Pump
Circuit for Phase-locked Loops”. IEEE J. In 2012. from Priyatam Institute of

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International Journal of Advanced Information Science and Technology (IJAIST) ISSN: 2319:2682
Vol.4, No.9, September 2015 DOI:10.15693/ijaist/2015.v4i9.60-64

Technology and Management, Indore, Distt. Indore,

RGPV Bhopal University, India, in 2008. Currently doing
M.Tech. in Electronics and communication engineering
from Sanghvi Institute of management & Science,
Indore, RGPV Bhopal University, India.

Mr. Virendra K. Verma received

the B.E. degree in Electronics and
communication engineering from
the Jawaharlal Institute of
Technology, Borawan, Distt.
Khargone, RGPV Bhopal University,
India, in 2001. M.Tech. Degree in
Micro-electronics and VLSI design from SGSITS Indore,
RGPV Bhopal University, Pursuing PhD from RGPV
Bhopal University. He is currently working as Asst.
Professor in department of Electronics &
communication engineering at Sanghvi Institute of
management & Science, Indore. His research interest
includes VLSI Design.

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