Computer Architecture & Organization Unit 4
Computer Architecture & Organization Unit 4
Computer Architecture & Organization Unit 4
Memory Hierarchy:
The total memory capacity of a computer can be visualized by hierarchy of components. The memory hierarchy
system consists of all storage devices contained in a computer system from the slow Auxiliary Memory to fast
Main Memory and to smaller Cache memory.
Auxiliary Memory:-
Auxiliary memory access time is generally 1000 times that of the main memory, hence it is at the bottom of the
hierarchy.
Main Memory:-
The main memory occupies the central position because it is equipped to communicate directly with the CPU
and with auxiliary memory devices through Input/output processor (I/O). When the program not residing in main
Each memory is a collection of numerous memory locations. To access data from any memory, first it must be
located and then the data is read from the memory location. Following are the methods to access information
from memory locations:
1. Random Access: Main memories are random access memories, in which each memory location has a
unique address. Using this unique address any memory location can be reached in the same amount of
time in any order.
2. Sequential Access: This methods allows memory access in a sequence or in order.
3. Direct Access: In this mode, information is stored in tracks, with each track having a separate read/write
head.
Main Memory:-
The memory unit that communicates directly within the CPU, Auxillary memory and Cache memory, is called
main memory. It is the central storage unit of the computer system. It is a large and fast memory used to store
2. ROM: Read Only Memory, is non-volatile and is more like a permanent storage for information. It also
stores the bootstrap loader program, to load and start the operating system when computer is turned
on.
Types of ROM
a) PROM(ProgrammableROM)
b) EPROM(Erasable PROM)and
c) EEPROM(Electrically ErasablePROM)
Auxiliary Memory:-
Devices that provide backup storage are called auxiliary memory. For example: Magnetic disks and tapes are
commonly used auxiliary devices. Other devices used as auxiliary memory are magnetic drums, magnetic bubble
memory and optical disks. It is not directly accessible to the CPU, and is accessed using the Input/Output
channels.
Cache Memory:-
The data or contents of the main memory that are used again and again by CPU, are stored in the cache memory
so that we can easily access that data in shorter time. Whenever the CPU needs to access memory, it first checks
the cache memory. If the data is not found in cache memory then the CPU moves onto the main memory. It also
transfers block of recent data into the cache and keeps on deleting the old data in cache to accomodate the new
one.
Hit Ratio
The performance of cache memory is measured in terms of a quantity called hit ratio. When the CPU refers to
memory and finds the word in cache it is said to produce a hit. If the word is not found in cache, it is in main
memory then it counts as a miss. The ratio of the number of hits to the total CPU references to memory is called
hit ratio.
The n data input lines provide the information to be stored in memory, and the n data output lines supply the
information coming out of particular word chosen among the 2kavailable inside the memory. The two control
inputs specify the direction of transfer desired.
The memory unit will then take the bits presently available in the input data lines and store them in the specified
1. Apply the binary address of the desired word into the addresslines.
2. Activate the read input.
The memory unit will then take the bits from the word that has been selected by the address and apply them into
the output data lines. The content of the selected word does not change after reading.
RAM interfaces:-
Data RAM:-
The data RAM shown below is organized as 8 ways 256-bit wide contiguous memories. It supports the following
accesses:
The NS bit takes the value of 1 for NS data, and 0 for secure data.
Note:-You require a 21-bit wide memory to support the parity option.
Cache lookup:-
The tag RAM format:
Each line is marked as secure or NS depending on the value of the AWPROT[1] or ARPROT[1] value on the
original transaction. The security setting of the access, AWPROT[1] or ARPROT[1], is used for Cache Lookup
and compared with the NS attribute in the Tag. The tag RAM contains a field to hold the NS attribute bit
corresponding for each cache line. This is required so that the NS attribute bit for all cache ways is compared to
generate the cache hit.
Note
The cache is not automatically flushed when the processor changes security state.
If an access is performed, and has an AWPROT[1]/ARPROT[1] value of 1'b1, then the NS attribute
must be HIGH. Cache lookups are performed on lines marked as NS, the NS cache line attribute = 1,
according to Physical Address(PA).
If any access is performed in secure state, and the transaction has an AWPROT[1]/ARPROT[1] value of
1'b0), then the NS attribute must be LOW. Cache lookups are performed on lines marked as secure (NS
cachelineattribute=0)accordingtoPA.AsecureaccessonlyhitsontagswithasecureNSattribute.
RAM sizes:-
The below table shows the different sizes of RAM.
L2 cache size Data RAM Tag RAM Dirty RAM
128KB 1 × (256 + 32) × (ways × 512) Ways × (20 + 1) × 512 1 × (2 × ways) × 512
256KB 1 × (256 + 32) × (ways × 1024) Ways × (19 + 1) × 1,024 1 × (2 × ways) × 1,024
512KB 1 × (256 + 32) × (ways × 2048) Ways × (18 + 1) × 2,048 1 × (2 × ways) × 2,048
1MB 1 × (256 + 32) × (ways × 4096) Ways × (17 + 1) × 4,096 1 × (2 × ways) × 4,096
2MB 1 × (256 + 32) × (ways × 8192) Ways × (16 + 1) × 8,192 1x (2 × ways) × 8,192
Optical Memories:
Optical memories are used for large, storage of data. These devices provide the option of variety of data storage.
These can save up to 20 GB of information. The data or information is read or written using a laser beam. Due to
its low cost and high data storage capacity these memories are being freely used. Apart from low cost these
memories have long life. But the problem is that of low access time.
Advantages of CD ROM:
1. Storage capacity is high.
2. Data storage cost per bit is reasonable.
3. Easy to carry.
4. Can store variety of data.
Disadvantages of CD ROM:-
WORM or Write Once Read Many or CD-R or CD-Record able are a kind of optical device which provides the
user the liberty to write once on the CD R. The user can write on the disk using the CD R disk drive unit. But this
data or information cannot be overwritten or changed. CD R does not allow re-writing though reading can be
done many times.
Advantages of WORM:-
1. Storage capacity is high.
2. Can be recorded once.
3. Reliable.
4. Runs longer.
5. Access time is good.
Disadvantages or limitations of WORM:-
1. Can be written only once.
Erasable Optical Disks are also called CD RW or CD rewritable. It gives the user the liberty of erasing data
already written by burning the microscopic point on the disk surface. The disk can be reused.
Advantages of CD RW:-
Storage capacity is very high.
1. Reliability is high.
2. Runs longer.
3. Easy to rewrite.
Limitations of CD RW:-
Access time is high.
DVD or Digital Versatile Disk is another form of optical storage. These are higher in capacity than the CDs. Pre-
recorded DVDs are mass-produced using molding machines that physically stamp data onto the DVD. Such disks
are known as DVD-ROM, because data can only be read and not written nor erased. DVD Rs are the blank record
able DVDs which can be recorded once using optical disk recording technologies by using DVD recorders and
then function as a DVD-ROM. DVD-ROM. Re writable DVDs DVD-RAM can be recorded.
Multilevel memories:
Memory Hierarchy
Three key characteristics increase for a memory hierarchy. They are the access time, the storage capacity and the
cost. The memory hierarchy is illustrated in figure 9.1.
Memory Performance
Goal of the memory hierarchy. Try to match the processor speed with the rate of information transfer
from the lowest element in the hierarchy.
The memory hierarchy speed up the memory performance.
The memory hierarchy works because of locality of reference.
– Memory references made by the processor, for both instructions and data, tend to cluster together
+ Instruction loops, subroutines
+ Data arrays, tables
– Keep these clusters in high speed memory to reduce the average delay in accessing data
– Over time, the clusters being referenced will change -- memory management must deal with this
Performance of a two level memory
Cache memory:-
A cache memory is a fast random access memory where the computer hardware stores copies of information
currently used by programs (data and instructions), loaded from the main memory. The cache has a significantly
shorter access time than the main memory due to the applied faster but more expensive implementation
technology. The cache has a limited volume that also results from the properties of the applied technology. If
information fetched to the cache memory is used again, the access time to it will be much shorter than in the case
if this information were stored in the main memory and the program will execute faster.
Time efficiency of using cache memories results from the locality of access to data that is observed during
program execution.
We observe here time and space locality:
Due to these localities, the information loaded to the cache memory is used several times and the execution time
of programs is much reduced. Cache can be implemented as a multi-level memory. Contemporary computers
usually have two levels of caches. In older computer models, a cache memory was installed outside a processor
(in separate integrated circuits than the processor itself). The access to it was organized over the processor
external system bus. In today's computers, the first level of the cache memory is installed in the same integrated
circuit as the processor. It significantly speeds up processor's co-operation with the cache. Some microprocessors
have the second level of cache memory placed also in the processor's integrated circuit. The volume of the first
level cache memory is from several thousands to several tens of thousands of bytes. The second level cache
memory has volume of several hundred thousand bytes. A cache memory is maintained by a special processor
subsystem called cache controller. If there is a cache memory in a computer system, then at each access to a
main memory address in order to fetch data or instructions, processor hardware sends the address first to the
cache memory. The cache control unit checks if the requested information resides in the cache. If so, we have a
"hit" and the requested information is fetched from the cache. The actions concerned with a read with a hit are
shown in the figure below.
When accessing data stored under a virtual address, the virtual address has to be converted into a physical
memory address by the use of address translation. Before translation, the virtual memory system checks if the
segment or the page, which contains the requested word or byte, resides in the main memory. It is done by tests
of page or segments descriptors in respective tables residing in the main memory. If the test result is negative, a
physical address sub-space in the main memory is assigned to the requested page or segment and next it is loaded
into this address sub-space from the auxiliary store. Next, the virtual memory system up-dates the page or
segment descriptions in the descriptor tables and opens access to the requested word or byte for the processor
instruction, which has emitted the virtual address.
The virtual memory control system is implemented today as partially hardware and software system. Accessing
descriptor tables and virtual to physical address translation is done by computer hardware. Fetching missing
pages or segments and up-dating their descriptors is done by the operating system, which, however, is strongly
supported by special memory management hardware. This hardware usually constitutes a special functional unit
for virtual memory management and special functional blocks designed to perform calculations concerned with
virtual address translation.
Memory allocation:-
Memory is the processes by which information is encoded, stored and retrieved. Encoding allow information that
is from the outside world to reach our senses in the forms of chemical and physical stimuli. Memory allocation is
a process by which computer programs and services are assigned with physical or virtual memory space. Memory
allocation is the process of reserving a partial or complete portion of computer memory for the execution of
programs and processes. Memory allocation is achieved through a process known as memory management.
Memory allocation is primarily a computer hardware operation but is managed through operating system and
software applications. Memory allocation process is quite similar in physical and virtual memory management.
First Fit
In this algorithm, searching is started either at the beginning of the memory or where the previous first search
ended.
Best fit
In this algorithm, all free memory blocks are searched and smallest free memory block which is large enough to
accommodate desired block K is used to allocate K.
Non preemptive allocation can’t make efficient use of memory in all situation. Due scattered memory blocks
larger free memory blocks may not be available. Much more efficient us of the available memory space is
possible if the occupied space can be re allocated to make room for incoming blocks by a method called as
Compaction.
Associative Memory:-
A memory unit accessed by content is called associative memory or content addressable memory(CAM) or
associative storage or associative array. Memory is capable of finding empty unused location to store the word.
To search particular data in memory, data is read from certain address and compared if the match is not found
content of the next address is accessed and compared. This goes on until required data is found. The number of
access depend on the location of data and efficiency of searching algorithm.
Hardware Organization
Associative Memory is organized in such a way.
Match Logic:-
Let us include key register. If Kj=0 then there is no need to compare Aj and Fij.
1. Only when Kj=1, comparison isneeded.
2. This achieved by ORing each term withKj.
Write operations:-
If the entire memory is loaded with new information at once prior to search operation then writing can be done by
addressing each location in sequence. Tag register contain as many bits as there are words in memory. It contain
1 for active word and 0 for inactive word. If the word is to be inserted, tag register is scanned until 0 is found and
word is written at that position and bit is change to1.
Advantages:-
This is suitable for parallel searches. It is also used where search time needs to be short.
1. Associative memory is often used to speed up databases, in neural networks and in the page tables
used by the virtual memory of modern computers.
2. CAM-design challenge is to reduce power consumption associated with the large amount
of parallel active circuitry, without sacrificing speed or memory density.
Disadvantages:-
1. An associative memory is more expensive than a random access memory because each cell must have an
extra storage capability as well as logic circuits for matching its content with an external argument.
2. Usually associative memories are used in applications where the search time is very critical and must be
very short.