Unit-1

By: Namata Singh

The computers can be classified into various categories as given below:

 Micro Computer
 Laptop Computer
 Work Station
 Super Computer
 Main Frame
 Hand Held
 Multi core

Micro Computer: A personal computer; designed to meet the computer needs of an

individual. Provides access to a wide variety of computing applications, such as word
processing, photo editing, e-mail, and internet.

Laptop Computer: A portable, compact computer that can run on power supply or a battery
unit. All components are integrated as one compact unit. It is generally more expensive than a
comparable desktop. It is also called a Notebook.

Work Station: Powerful desktop computer designed for specialized tasks. Generally used for
tasks that requires a lot of processing speed. Can also be an ordinary personal computer
attached to a LAN (local area network).

Super Computer: A computer that is considered to be fastest in the world. Used to execute
tasks that would take lot of time for other computers. For Ex: Modeling weather systems,
genome sequence, etc (Refer site: http://www.top500.org/)

Main Frame: Large expensive computer capable of simultaneously processing data for
hundreds or thousands of users. Used to store, manage, and process large amounts of data that
need to be reliable, secure, and centralized.

Hand Held: It is also called a PDA (Personal Digital Assistant). A computer that fits into a
pocket, runs on batteries, and is used while holding the unit in your hand. Typically used as
an appointment book, address book, calculator and notepad.

Multi Core: Have Multiple Cores – parallel computing platforms. Many Cores or computing
elements in a single chip. Typical Examples: Sony Play station, Core 2 Duo, i3, i7 etc.

GENERATION OF COMPUTERS
Development of technologies used to fabricate the processors, memories and I/O units of
the computers has been divided into various generations as given below:
 First generation
 Second generation
 Third generation
 Fourth generation
 Beyond the fourth generation

By: Namata Singh

First generation:
1946 to 1955: Computers of this generation used Vacuum Tubes. The computes were built using
stored program concept. Ex: ENIAC, EDSAC, IBM 701.
Computers of this age typically used about ten thousand vacuum tubes. They were bulky in
size had slow operating speed, short life time and limited programming facilities.

Second generation:
1955 to 1965: Computers of this generation used the germanium transistors as the active
switching electronic device. Ex: IBM 7000, B5000, IBM 1401. Comparatively smaller in
size About ten times faster operating speed as compared to first generation vacuum tube
based computers. Consumed less power, had fairly good reliability. Availability of large
memory was an added advantage.

Third generation:
1965 to 1975: The computers of this generation used the Integrated Circuits as the active
electronic components. Ex: IBM system 360, PDP minicomputer etc. They were still smaller
in size. They had powerful CPUs with the capacity of executing 1 million instructions per
second (MIPS). Used to consume very less power consumption.

Fourth generation:
1976 to 1990: The computers of this generation used the LSI chips like microprocessor as
their active electronic element. HCL horizen III, and WIPRO‟S Uniplus+ HCL‟s Busybee
PC etc.
They used high speed microprocessor as CPU. They were more user friendly and highly reliable
systems. They had large storage capacity disk memories.

Beyond Fourth Generation:

1990 onwards: Specialized and dedicated VLSI chips are used to control specific functions
of these computers. Modern Desktop PC‟s, Laptops or Notebook Computers.

By: Namata Singh

Functional Unit

A computer in its simplest form comprises five functional units namely input unit, output unit
memory unit, arithmetic & logic unit and control unit. Figure 2 depicts the functional units of
a computer system.

Figure 2: Basic functional units of a computer

Let us discuss about each of them in brief:

1. Input Unit: Computer accepts encoded information through input unit. The
standard input device is a keyboard. Whenever a key is pressed, keyboard
controller sends the code to CPU/Memory.

Examples include Mouse, Joystick, Tracker ball, Light pen, Digitizer, Scanner etc.

2. Memory Unit: Memory unit stores the program instructions (Code), data
and results of computations etc. Memory unit is classified as:

 Primary /Main Memory

 Secondary /Auxiliary Memory

By: Namata Singh

 Primary memory is a semiconductor memory that provides access at high speed.
Run time program instructions and operands are stored in the main memory. Main
memory is classified again as ROM and RAM. ROM holds system programs and
firmware routines such as BIOS, POST, I/O Drivers that are essential to manage the
hardware of a computer. RAM is termed as Read/Write memory or user memory that
holds run time program instruction and data. While primary storage is essential, it is
volatile in nature and expensive. Additional requirement of memory could be supplied
as auxiliary memory at cheaper cost. Secondary memories are non volatile in nature.

3. Arithmetic and logic unit: ALU consist of necessary logic circuits like adder,
comparator etc., to perform operations of addition, multiplication, comparison of two
numbers etc.

4. Output Unit: Computer after computation returns the computed results, error
messages, etc. via output unit. The standard output device is a video monitor,
LCD/TFT monitor. Other output devices are printers, plotters etc.

5. Control Unit: Control unit co-ordinates activities of all units by issuing control
signals. Control signals issued by control unit govern the data transfers and then
appropriate operations take place. Control unit interprets or decides the
operation/action to be performed.

The operations of a computer can be summarized as follows:

1. A set of instructions called a program reside in the main memory of computer.

2. The CPU fetches those instructions sequentially one-by-one from the main memory,
decodes them and performs the specified operation on associated data operands in
ALU.

3. Processed data and results will be displayed on an output unit.

4. All activities pertaining to processing and data movement inside the computer
machine are governed by control unit.

• A bus is a communication pathway connecting two or more devices

• Usually broadcast (all components see signal)
• Often grouped
o A number of channels in one bus
o e.g. 32 bit data bus is 32 separate single bit channels
• Power lines may not be shown
• There are a number of possible interconnection systems
• Single and multiple BUS structures are most common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)
• Lots of devices on one bus leads to:
o Propagation delays
o Long data paths mean that co-ordination of bus use can adversely affect
performance
o If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to overcome these problems
By: Namata Singh
 Fig: Bus Interconnection Scheme

o Carries data
 Remember that there is no difference between “data” and “instruction” at
this level
o Width is a key determinant of performance
 8, 16, 32, 64 bit
• Address Bus
o Identify the source or destination of data
o e.g. CPU needs to read an instruction (data) from a given location in memory
o Bus width determines maximum memory capacity of system
 e.g. 8080 has 16 bit address bus giving 64k address space
• Control Bus
o Control and timing information
 Memory read
 Memory write
 I/O read
 I/O write
 Transfer ACK
 Bus request
 Bus grant
 Interrupt request
 Interrupt ACK
 Clock
 Reset

Multiple Bus Hierarchies

 A great number of devices on a bus will cause performance to suffer

o Propagation delay - the time it takes for devices to coordinate the use of the bus
o The bus may become a bottleneck as the aggregate data transfer demand approaches
the capacity of the bus (in available transfer cycles/second)
 Traditional Hierarchical Bus Architecture
o Use of a cache structure insulates CPU from frequent accesses to main memory
o Main memory can be moved off local bus to a system bus
o Expansion bus interface
 buffers data transfers between system bus and I/O controllers on expansion bus
 insulates memory-to-processor traffic from I/O traffic

By: Namata Singh

Traditional Hierarchical Bus Architecture Example

 High-performance Hierarchical Bus Architecture

o Traditional hierarchical bus breaks down as higher and higher performance is
seen in the I/O devices
o Incorporates a high-speed bus
 specifically designed to support high-capacity I/O devices
 brings high-demand devices into closer integration with the processor and at
the same time is independent of the processor
 Changes in processor architecture do not affect the high-speed bus, and vice
versa
o Sometimes known as a mezzanine architecture

By: Namata Singh

High-performance Hierarchical Bus Architecture Example

Elements of Bus Design

• Bus Types
o Dedicated
 Separate data & address lines
o Multiplexed
 Shared lines
 Address valid or data valid control line
 Advantage - fewer lines
 Disadvantages
o More complex control
o Ultimate performance
• Bus Arbitration
o More than one module controlling the bus
 e.g. CPU and DMA controller
o Only one module may control bus at one time
o Arbitration may be centralised or distributed
• Centralised Arbitration
o Single hardware device controlling bus access
 Bus Controller
 Arbiter
o May be part of CPU or separate
• Distributed Arbitration

By: Namata Singh

 o Each module may claim the bus
o Control logic on all modules

• Timing
o Co-ordination of events on bus
o Synchronous
 Events determined by clock signals
 Control Bus includes clock line
 A single 1-0 is a bus cycle
 All devices can read clock line
 Usually sync on leading edge
 Usually a single cycle for an event
• Bus Width
o Address: Width of address bus has an impact on system capacity i.e. wider bus
means greater the range of locations that can be transferred.
o Data: width of data bus has an impact on system performance i.e. wider bus
means number of bits transferred at one time.
• Data Transfer Type
o Read
o Write
o Read-modify-write
o Read-after-write
o Block

1.8 PCI
 PCI is a popular high bandwidth, processor independent bus that can function as mezzanine
or peripheral bus.
 PCI delivers better system performance for high speed I/O subsystems (graphic display
adapters, network interface controllers, disk controllers etc.)
 PCI is designed to support a variety of microprocessor based configurations including both
single and multiple processor system.
 It makes use of synchronous timing and centralised arbitration scheme.
 PCI may be configured as a 32 or 64-bit bus.
 Current Standard
o up to 64 data lines at 33Mhz
o requires few chips to implement
o supports other buses attached to PCI bus
o public domain, initially developed by Intel to support Pentium-based systems
o supports a variety of microprocessor-based configurations, including multiple
processors
o uses synchronous timing and centralized arbitration

By: Namata Singh

Typical Desktop System

Note: Bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the
processor’s I/O capability.

Typical Server System

Note: In a multiprocessor system, one or more PCI configurations may be connected by bridges
to the processor’s system bus.

PCI Bus Lines

• Systems lines
o Including clock and reset
• Address & Data
o 32 time mux lines for address/data
o Interrupt & validate lines
• Interface Control
• Arbitration
o Not shared
o Direct connection to PCI bus arbiter

By: Namata Singh

 • Error lines
• Interrupt lines
o Not shared
• Cache support
• 64-bit Bus Extension
o Additional 32 lines
o Time multiplexed
o 2 lines to enable devices to agree to use 64-bit transfer
• JTAG/Boundary Scan
o For testing procedures

PCI Commands
• Transaction between initiator (master) and target
• Master claims bus
• Determine type of transaction
o e.g. I/O read/write
• Address phase
• One or more data phases

PCI Enhancements: AGP

 AGP – Advanced Graphics Port
o Called a port, not a bus because it only connects 2 devices

Introduction of General Register based CPU Organization

When we are using multiple general-purpose registers, instead of a single accumulator register, in
the CPU Organization then this type of organization is known as General register-based CPU
Organization. In this type of organization, the computer uses two or three address fields in their
instruction format. Each address field may specify a general register or a memory word. If many
CPU registers are available for heavily used variables and intermediate results, we can avoid
memory references much of the time, thus vastly increasing program execution speed, and
reducing program size.

For example:

MULT R1, R2, R3

This is an instruction of an arithmetic multiplication written in assembly language. It uses three

address fields R1, R2, and R3. The meaning of this instruction is:

R1 <-- R2 * R3

This instruction also can be written using only two address fields as:

MULT R1, R2
By: Namata Singh
In this instruction, the destination register is the same as one of the source registers. This means
the operation

R1 <-- R1 * R2

The use of large number of registers results in short program with limited instructions.

Some examples of General register based CPU Organization are IBM 360 and PDP- 11.

The advantages of General register based CPU organization –

Efficiency of CPU increases as there are a large number of registers are used in this organization.
Less memory space is used to store the program since the instructions are written in compact
way.

The disadvantages of General register based CPU organization –

Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to be more
intelligent in this aspect.
Since large number of registers are used, thus extra cost is required in this organization.

General register CPU organisation of two type:

1) Register-memory reference architecture (CPU with less register) –

In this organisation Source 1 is always required in register, source 2 can be present either in
register or in memory.Here two address instruction formats is the compatible instruction format.
2) Register-register reference architecture (CPU with more register) –
In this organisation ALU operations are performed only on a register data. So operands are
required in the register. After manipulation result is also placed in register.Here three address
instruction formats is the compatible instruction format.

Introduction of Stack based CPU Organization

The computers which use Stack-based CPU Organization are based on a data structure called
stack. The
stack is a list of data words. It uses Last In First Out (LIFO) access method which is the most
popular access
method in most of the CPU. A register is used to store the address of the topmost element of the
stack
which is known as Stack pointer (SP). In this organisation, ALU operations are performed on stack
data. It
means both the operands are always required on the stack. After manipulation, the result is
placed in the
stack.

By: Namata Singh

The main two operations that are performed on the operators of the stack are Push and
Pop. These two
operations are performed from one end only.

1) Push –
This operation results in inserting one operand at the top of the stack and it decrease the
stack pointer
register. The format of the PUSH instruction is:
PUSH
It inserts the data word at specified address to the top of the stack. It can be implemented
as:

//decrement SP by 1
SP <-- SP - 1

//store the content of specified memory address

//into SP; i.e, at top of stack
SP <-- (memory address)

2) Pop –
This operation results in deleting one operand from the top of the stack and it increase the
stack pointer
register. The format of the POP instruction is:

POP
It deletes the data word at the top of the stack to the specified address. It can be
implemented as:

//transfer the content of SP (i.e, at top most data)

//into specified memory location
(memory address) <-- SP

//increment SP by 1
SP <-- SP + 1
Operation type instruction does not need the address field in this CPU organization. This is
because the
operation is performed on the two operands that are on the top of the stack. For example:
SUB

This instruction contains the opcode only with no address field. It pops the two top data
from the stack,
subtracting the data, and pushing the result into the stack at the top.

PDP-11, Intel’s 8085 and HP 3000 are some of the examples of the stack organized
computers.

By: Namata Singh

The advantages of Stack based CPU organization –

Efficient computation of complex arithmetic expressions.

Execution of instructions is fast because operand data are stored in consecutive memory
locations.
Length of instruction is short as they do not have address
field.

The disadvantages of Stack based CPU organization –

The size of the program increases.

By: Namata Singh

 ADDRESSING MODES

Each instruction of a computer specifies an operation on certain

data. There are various ways of specifying address of the data to
be operated on. These different ways of specifying data are called
the addressing modes. The most common addressing modes are:

 Immediate addressing mode: This is the simplest

form of addressing. Here, the operand is given in the
instruction itself. This mode is used to define a
constant or set initial value of variables. The
advantage of this mode is that no memory reference
other than instruction fetch is required to obtain
operand. The disadvantage is that the size of the
number is limited to the size of the address field,
which is small compared to word length in most
instruction sets.

 Direct addressing mode: In direct addressing mode,

effective address of the operand is given in the

By: Namata Singh

address field of the instruction. It requires one memory
reference to read the operand from the given location
and provides only a limited address space. Length of
the address field is usually less than the word length.

 Indirect addressing mode: In Indirect addressing

mode, the address field of the instruction refers to the
address of a word in memory, which in turn contains
the full length address of the operand. The advantage
of this mode is that for the word length of N, an
address space of 2N can be addressed. The
disadvantage is that instruction execution requires
three or more memory references is required to fetch
the operand.

 Register addressing mode: Register addressing

mode is similar to direct addressing. The only
difference is that the address field of the instruction
refers to a register rather than a memory location. So,
only 3 or 4 bits are used as address field to reference
8 to 16 general purpose registers. The advantages of
register addressing are small address field is needed
in the instruction and no time-consuming memory
references are need. The disadvantage of register
addressing is that the address space is very limited.

 Register indirect addressing mode: This mode is

similar to indirect addressing. The address field of the
instruction refers to a register. The register contains
the effective address of the operand. This mode uses
one memory reference to obtain the operand. The
address space is limited to the width of the registers
available to store the effective address. The
advantage of this mode is large address space and
disadvantage is one extra memory reference is
needed.

 Displacement addressing mode: The displacement

addressing modes is combination of the direct
addressing and register indirect addressing. In
displacement addressing, the instruction have two
address fields, one will have the memory location
address and another will have displacement value to
be added to get the effective address. There are 3
types of addressing mode in displacement addressing
mode. They are :

Relative addressing- Here next instruction address

is added to the address field to produce the
effective address of the operand. Thus the effective
address is a displacement relative to the address of
the instruction. Here, address field is assumed as
2’s complement number.

By: Namata Singh

Base register addressing- Here the referenced
register contains a main memory address and
address field contains a displacement from that
address.

Indexing addressing- Here, the address field

references a main memory address, and the
reference register contains a positive displacement
from that address.

The advantage of this mode is flexibility in addressing

and disadvantage is complexity.

 Stack addressing mode: Stack is a linear array of

locations referred to as last-in first out queue. The
stack is a reserved block of location, appended or
deleted only at the top of the stack. Stack pointer is a
register which stores the address of top of stack
location. This mode of addressing is also known as
implicit addressing. Here the effective address is the
top of the stack, so no memory reference which is the
advantage. It’s disadvantage is limited applicability.

By: Namata Singh