PowerArtistUserGuide Academic

PowerArtist 1
2
User Guide 3
Software Release 2011.1.3
© 2011 Apache Design, Inc.

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© 2011 Apache Design, Inc.

PowerArtist™ User Guide
Table of Contents
CHAPTER 1 Installing and Setting Up PowerArtist

Introduction ................................................................................................................. 1
Supported Operating Systems .................................................................................... 1
Installing the Software................................................................................................. 1
Distribution Tree.......................................................................................................... 2
PowerArtist Licensing.................................................................................................. 3
Installing Licenses and FLEXlm ....................................................................... 3
Understanding License File Entries.................................................................. 3
Support for Multiple License Servers ............................................................... 4
Product vs. Feature Licenses........................................................................... 4
Waiting for a Feature License .......................................................................... 4
Resolving Feature Checkout Problems ............................................................ 4
Setting the UNIX Environment Variable for PowerArtist ............................................. 5
CHAPTER 2 Using the PowerArtist Shell

Introduction ................................................................................................................. 7
Understanding the ptshell Command Options ............................................................ 7
Invoking the GUI from the ptshell ..................................................................... 9
Reverting to the Legacy Shell ........................................................................ 10
ptshell Features......................................................................................................... 10
Customizing Your PowerArtist Environment Using Initialization (INI) Files .... 11
Sample Initialization File................................................................................. 12
Understanding Log Files and Key Files.......................................................... 12
Understanding the Link Between Commands and the PowerCanvas ...................... 13
CHAPTER 3 PowerArtist Tutorial Part 1: Power Analysis

Introduction ............................................................................................................... 15
Tutorial Organization ...................................................................................... 16
Copying the PowerArtist Tutorial Files ...................................................................... 17
Contents of the Top-Level Tutorial Directory.................................................. 17
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CONTENTS PowerArtist™ User Guide iv
Contents of the Analysis Directory ................................................................. 17

Understanding Command File Set-Up Methods ....................................................... 18
Running an RTL Full-Chip Power Analysis Using Command Files........................... 19
Examining the Contents of the Tcl Command Files ....................................... 20
Running the Tcl Scripts .................................................................................. 26
Viewing Power Analysis Results in the PowerCanvas.............................................. 31
Manipulating Your Design in the Schematic................................................... 32
Viewing Clock Trees....................................................................................... 33
Waveform Cross-Probing ............................................................................... 37
Running Full-Chip Analysis Using the PowerCanvas Wizards ................................. 38
Performing Design Inferencing Using the HDL Inferencing Wizard ............... 38
Running Vector Analysis Using the Vector Wizard ........................................ 42
Running the Average Power Wizard .............................................................. 45
Running the Time-Based Power Wizard ........................................................ 49
Running an RTL Block-Level Power Analysis........................................................... 53
Basic Flow for Running the Block-Level Tutorial............................................ 53
Using the Command Files .............................................................................. 54
Viewing the Block-Level Power Results in the PowerCanvas ........................ 59
Running the Block-Level Tutorial Using the Power Canvas Wizards ............. 59
Running Power Analysis with Clock Gating .............................................................. 60
Using the PowerCanvas Wizards ................................................................... 60
Running a Power Analysis with a Mixed-Vt Cell Library ........................................... 61
Running Power Analysis with Voltage Islands .......................................................... 64
Running a Power Analysis with Power Gating .......................................................... 66
Running the Full-Chip Gate-Level Power Analysis Tutorial ...................................... 69
Understanding Power Analysis Results in the Text-Based Power Report ................ 71
Internal Power Consumption .......................................................................... 71
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CONTENTS PowerArtist™ User Guide v
Pad Power Consumption................................................................................ 73

Clock Power Consumption ............................................................................. 74
Clock Domain Power Consumption................................................................ 77
Inferred Buffer Tree Power............................................................................. 78
Area................................................................................................................ 79
Net Frequencies ............................................................................................. 79
Power Consumption by Model/Gate Type...................................................... 79
Summary................................................................................................................... 80
CHAPTER 4 PowerArtist Tutorial Part II: Power Reduction

Introduction ............................................................................................................... 81
About PowerBots............................................................................................ 82
Tutorial Organization ...................................................................................... 82
Copying the PowerArtist Tutorial Files ...................................................................... 83
Contents of the Top-Level Tutorial Directory.................................................. 83
Running the Reduction Tutorial Using Command Files ............................................ 84
Setting Important Environment Variables.................................................................. 85
Basic Flow for Running the Reduction Tutorial ......................................................... 85
Using the Command Files......................................................................................... 86
Reviewing Reduction Results in the PowerCanvas .................................................. 93
Examining Simple Power Reductions ............................................................ 95
Examining Advanced Power Reduction Results .......................................... 107
Examining Power Linter Reduction Results ................................................. 116
Running the Reduction Tutorial Using the PowerCanvas Wizards ......................... 119
Using the HDL Inferencing Wizard ............................................................... 119
Using the Power Reduction Wizard.............................................................. 119
Using the RTL Rewrite Wizard .................................................................... 124
Reviewing the Output Reports ................................................................................ 127
Reviewing the Power Reduction Report....................................................... 127
Reviewing the Power Reduction Clock Gating Report ................................. 131
CHAPTER 5 Using the PowerCanvas

Introduction ............................................................................................................. 135
Chapter Organization ................................................................................... 135
Overview of the PowerCanvas Initial View.............................................................. 136
The PowerCanvas Menus ............................................................................ 137
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CONTENTS PowerArtist™ User Guide vi
Using the Edit Menu ..................................................................................... 138

Using the Tools Menu .................................................................................. 138
Using the View Menu ................................................................................... 138
Using the Help Menu.................................................................................... 139
PowerCanvas Dialogs............................................................................................. 141
Using the Find Dialog ................................................................................... 141
Using the Properties Dialog.......................................................................... 144
Using the Smart Source Browser ................................................................. 147
Using the Hierarchy Browser .................................................................................. 148
Column Header Definitions for the Power Table .......................................... 149
Controlling the Hierarchy Browser From the Design Menu .......................... 149
Using the Schematic Display .................................................................................. 152
Controlling the Schematic from the Schematic Menu .................................. 152
Using the Mouse to Zoom In and Out on the Schematic.............................. 155
Expanding the Schematic by Double Clicking Ports .................................... 155
Basic Clock Tree Manipulation ..................................................................... 157
Using the Simple Reduction Dialog......................................................................... 159
Column Header Definitions for the Simple Reductions Dialog ..................... 159
Column Header Right-Click Pop-Up Menu................................................... 161
Simple Reduction Dialog Data Filters........................................................... 162
The View Menu ............................................................................................ 163
The Detail Menu ........................................................................................... 164
Using the Simple Sorting and Filtering Features .......................................... 165
Using the Advanced Sorting and Filtering Features..................................... 165
Using the Linter Reductions Dialog......................................................................... 168
Column Header Definitions for the Linter Reductions Dialog ....................... 168
Using the Prism Dialog............................................................................................ 170
Categories of Implementation of Suggested Modifications .......................... 172
Definitions for the Bit Counters in the Prism Dialog ..................................... 173
Column Header Definitions for the Prism Dialog .......................................... 173
Filtering Prism Dialog Data........................................................................... 175
Using the Normal vs. Optimal Views ............................................................ 177
Using the Waveform Viewer.................................................................................... 180
Supported Waveform Sources ..................................................................... 180
Finding and Displaying Waveforms from an FSDB File ............................... 180
Manipulating the Waveform Display............................................................. 184
Displaying Waveforms from a PTCL File ..................................................... 184
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CONTENTS PowerArtist™ User Guide vii
Displaying Waveforms from an HSPICE or Spectre Simulation................... 185

Using the Waveform Viewer Options Menu ................................................. 185
Adding Notes to a Plot.................................................................................. 189
Comparing Waveforms in the Same Plot ..................................................... 189
Opening Tabs in a Separate Window........................................................... 189
CHAPTER 6 Getting Your Design into PowerArtist

Introduction ............................................................................................................. 191
Command-Line Flow for Verilog.............................................................................. 192
Command-Line Flow for VHDL ............................................................................... 192
Command-Line Flow for Mixed-Language Designs ................................................ 194
VHDL Designs with One or More Verilog Modules ...................................... 194
Verilog Designs with One or More VHDL Modules ...................................... 194
Case Sensitivity............................................................................................ 195
Compiling Mixed-Language Designs in a Single Run .................................. 196
Creating Your Map Files ......................................................................................... 197
The synonym Statement .............................................................................. 197
Running the wwvmkr Utility ..................................................................................... 198
Contents of the ptSourceFiles.tcl File........................................................... 198
Metacomment Processing....................................................................................... 199
Creating Custom VHDL Packages.......................................................................... 200
Technique 1: Modifying Your Installation ..................................................... 200
Technique 2: Multiple Compile Scripts ......................................................... 200
Defining Libraries for Command-Line Use .............................................................. 202
HDL Advanced Topics ............................................................................................ 202
Using Power Macros .................................................................................... 202
Overriding Parameter Settings for Top-Level VHDL or Verilog Modules ..... 204
Controlling Array Inferencing ........................................................................ 205
CHAPTER 7 Preparing for Power Analysis

Introduction ............................................................................................................. 209
Estimating Net Capacitances .................................................................................. 210
Back-Annotating Capacitance Using SPEF ................................................. 211
Using Back-Annotated Load Capacitances for Primary Outputs.................. 213
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CONTENTS PowerArtist™ User Guide viii
Specifying Default Output Load Capacitance Using a Command Option .... 213
Using Back-Annotated Wiring Capacitances for Local Nets ........................ 213
Specifying Wire Load Models....................................................................... 213
Using Apache Default Wire Load Models for Capacitance Analysis ............ 216
Using PACE Technology Files During Power Analysis (Beta) ................................ 217
Using Clock Distribution Network Models .................................................... 217
Understanding Priorities and Precedence When Using PACE Models ........ 218
Using the SetClockGatingStyle Command................................................... 218
Additional Guidelines for Using PACE Models............................................. 219
Understanding Output File Changes due to PACE Models.......................... 219
Estimating Pin Capacitance .................................................................................... 220
Handling Voltages in Liberty Format ....................................................................... 221
Handling Designs with Multiple Libraries ................................................................ 221
Handling Designs with Multiple Power Supplies ..................................................... 223
Creating a Virtual Supply.............................................................................. 223
Assigning a Virtual Supply to a Hierarchical Instance .................................. 223
Liberty Power Supply Support...................................................................... 224
Running RTL Mixed-Vt Power Analysis .................................................................. 225
Critical Liberty Leakage Attributes................................................................ 225
Categorizing Cells for Multiple Vts ............................................................... 226
Default Cell Selection for Mixed-Vt Analysis ................................................ 227
Sample Mixed-Vt Flow and Tcl File .............................................................. 227
Understanding Mixed-Vt Analysis Results in the Report File ....................... 228
Setting up Clock Power Analysis ............................................................................ 229
Commands for Clock Power Analysis .......................................................... 229
How Clock Power Analysis Works ............................................................... 230
Controlling Forward Clock Tracing ............................................................... 231
Setting up Clock Gating for Power Analysis............................................................ 233
Clock Gating Flow for Power Analysis ......................................................... 233
Performing Enhanced Clock Gating ............................................................. 234
Library Modeling of Integrated Clock Cells................................................... 235
Setting up Clock Gating for Power Reduction......................................................... 235
Clock Gating Flow for Power Reduction....................................................... 235
Clock Gating Algorithm................................................................................. 236
Hierarchical Clock Gating............................................................................. 238
Inferring Buffer Trees for Nets with High Fanout .......................................... 238
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CONTENTS PowerArtist™ User Guide ix
CHAPTER 8 Analyzing Simulation Activity

Introduction ............................................................................................................. 239
Defining Different Groups at Each Design Phase ................................................... 240
Understanding the Design Flow with Vector Analysis ............................................. 241
Creating Analysis Graphs ....................................................................................... 241
Determining the Type of Vector Analysis to Run.......................................... 241
Running Vector Analysis Using Command Files .......................................... 242
CHAPTER 9 Analyzing Simulation-Based Average Power

Introduction ............................................................................................................. 245
Overall Design Flow ..................................................................................... 245
Running a Power Analysis in Full Simulation Mode ................................................ 246
Controlling Your Average Power Analysis.................................................... 246
Sample CalculatePower Specification for Full Simulation Mode .................. 248
Running Analysis with Incomplete Simulation Data ................................................ 248
Performing Gate-Level Average Power Analysis .................................................... 249
Analyzing Large Gate-Level Designs ........................................................... 249
Running Modal Analysis.......................................................................................... 249
Understanding the Basics of the Detailed Power Report ........................................ 252
Available Power Report Formats.................................................................. 253
Controlling the Contents of the Power Report......................................................... 253
Analyzing Average Power Using a SAIF File .......................................................... 265
Flow Details.................................................................................................. 265
Understanding Power Value Fluctuations Between SAIF and Other Formats ...
266
Analyzing Average Power Using Partial Stimulus Files .......................................... 266
Name Mapping Flow .................................................................................... 267
Advanced Flows ........................................................................................... 269
Re-Using a Stimulus File from a Previous Run ....................................................... 269
CHAPTER 10 Analyzing Time-Based Power

Introduction ............................................................................................................. 271
Overall Design Flow ..................................................................................... 271
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CONTENTS PowerArtist™ User Guide x
Understanding the Inputs for a Time-Based Power Analysis.................................. 272

Controlling Your Time-Based Power Analysis ........................................................ 272
Required Options for all Time-Based Analyses............................................ 272
Additional Arguments Required for Gate-Level Only ................................... 273
Additional Arguments Required for RTL and Mixed Analysis Only .............. 273
Setting Timing Windows for Time-Based Power Analysis............................ 274
Running the Analysis .............................................................................................. 275
Understanding and Reviewing Outputs and Results of the Time-Based Analysis .. 276
Contents of the ASCII Report File ................................................................ 276
Generating and Viewing Waveforms............................................................ 277
Measuring the Distance Between Two Data Points ..................................... 278
Using Results .......................................................................................................... 281
Using Peak Power or Current Information in CoolTime ............................... 281
Monitoring Flop Clock Activity ................................................................................. 281
Sample Flop Clock Activity Graphs .............................................................. 283
CHAPTER 11 Analyzing Vectorless Average Power

Flow Overview......................................................................................................... 287
Creating the VAF File.............................................................................................. 287
Setting the Frequency and Duty Cycle for Clock Nets ................................. 287
Setting the Frequency for Primary Inputs ..................................................... 288
Setting the Frequency for Ports of a Specific Type ...................................... 288
Setting the Duty Cycle of Critical Control Signals that are Not Primary Inputs ..
288
Setting the Activity and Duty Cycle for Busses Driven by Tri-Stated Signals.....
289
Setting the Frequency and Duty Cycle on Leaf-Level Instances.................. 289
Setting the Frequency for Memories ............................................................ 289
Handling Blackbox Instances ....................................................................... 289
Understanding Common Warning Messages ......................................................... 290
Example 1: Mixing Commands or Using SetInstanceStimulus Commands................290
Example 2: Two Net Names that Resolve to the Same Net .......................................290
Example 3: Conflicting Value Setting for the Same Object (Net/Port) ........................291
Example 4: Conflicts Caused by Wild Cards...............................................................291
CHAPTER 12 Examining and Implementing Power Reduction Opportunities

Introduction ............................................................................................................. 293
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CONTENTS PowerArtist™ User Guide xi
Recommended Flow for Implementing Power Reductions ..................................... 294

Controlling Clock Domains During Reduction .............................................. 295
Performing Power Reduction Analysis.................................................................... 297
Viewing Reduction Results ..................................................................................... 297
PowerBot Overview................................................................................................. 298
Running PowerArtist Clock PowerBots ........................................................ 299
Generating Synthesis Constraints................................................................ 300
Power Reduction PowerBots .................................................................................. 305
Low-Activity Non-Enabled Register.............................................................................305
Datapath Operator Isolation ........................................................................................307
Local Explicit Clock Enable .........................................................................................309
Split Memory Words....................................................................................................314
Gate Memory Clock ....................................................................................................322
Prism ...........................................................................................................................324
Observability Don't Care .............................................................................................331
Power Linter PowerBots.......................................................................................... 335
Memory Power Linter ..................................................................................................336
MUX Power Linter .......................................................................................................337
Register Power Linter..................................................................................................344
Clock Enable Condition Linter.....................................................................................345
Rewriting Your RTL................................................................................................. 347
Inputs............................................................................................................ 347
Flow for Rewriting the RTL ........................................................................... 347
RewriteRTL Debug Switches ....................................................................... 349
Directory Organization.................................................................................. 349
Controlling the Format of Rewritten Code .................................................... 350
Form of the Code Modifications for LNR ...................................................... 350
LNR Gate-Level Simulation.......................................................................... 355
Form of the Code Modifications for GMC ..................................................... 355
Form of Code Modifications for Prism .......................................................... 358
General Form of Modifications for Different Code Types ............................. 362
Formal Verification of Rewritten Code.......................................................... 367
Errors, Warnings and Notes Generated by the Rewrite Process ................. 370
Running Hierarchical Rewrite.................................................................................. 372
Understanding the Hierarchical Rewrite Methodology ................................. 372
CHAPTER 13 Performing Functional Verification of RTL Changes

Introduction ............................................................................................................. 377
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CONTENTS PowerArtist™ User Guide xii
Using Standard Verification Tools by Defining ADS_PA_FV .................................. 377

Generating a Rule File to use in the nCompare Utility (Beta) ................................. 378
Performing Functional Simulation ................................................................ 382
CHAPTER 14 Analyzing the Effects of Power Gating with Proprietary Commands

Introduction ............................................................................................................. 383
Required Inputs for Power Gating........................................................................... 384
Defining Libraries ......................................................................................... 385
Creating Source Files.............................................................................................. 386
Special Option to the Elaborate Command............................................................. 387
Setting up Your Command File for Power Gating ................................................... 387
Defining Library Associations ....................................................................... 387
Defining Virtual Supplies .............................................................................. 388
Defining Power Domains.............................................................................. 388
Defining Retention Cell Mapping .................................................................. 388
Sample Command File for a Power Gating Flow ......................................... 388
Performing Simulation-Based Power Analysis with Power Gating.......................... 389
Performing Vectorless Power Analysis with Power Gating ..................................... 389
Creating a Vectorless Activity File ................................................................ 390
Understanding the Output Reports for Power Gating Analysis ............................... 390
Sample Report for Simulation-Based Analysis............................................. 390
Sample Report for Vectorless Analysis ........................................................ 392
CHAPTER 15 Using Standard File Formats

Introduction ............................................................................................................. 395
Using a CPF Input Flow (Beta) ............................................................................... 396
CPF Input Use Model ................................................................................... 396
Supported CPF 1.1 Commands ................................................................... 397
Sample CPF Input ........................................................................................ 398
Sample PowerArtist Report Section for the CPF Flow ................................. 399
Using a CPF Output Flow (Beta)............................................................................. 403
Mapping PowerArtist Tcl Commands to Generated CPF Commands ......... 404
Quick Reference Checklist for CPF Output Flow ......................................... 408
Sample Input and Output for a CPF Flow .................................................... 409
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CONTENTS PowerArtist™ User Guide xiii
Using a UPF Input Flow (Beta) ............................................................................... 412

UPF Input Use Model ................................................................................... 412
Supported UPF Commands and Options ..................................................... 413
Sample UPF Input ........................................................................................ 414
Sample PowerArtist Report Section for the UPF Flow ................................. 414
Using an SDC Input Flow........................................................................................ 416
Using ReadSDC Output with a PowerArtist Command File ......................... 416
Mapping SDC commands to PowerArtist Tcl Commands ............................ 417
Sample SDC Input File ................................................................................ 418
Sample Output Files..................................................................................... 418
CHAPTER 16 Acquiring Simulation Data

Introduction ............................................................................................................. 421
Using an FSDB Approach ....................................................................................... 422
Improving FSDB Performance ..................................................................... 422
Improving FSDB Capacity ............................................................................ 423
Generating a VCDe File from an FSDB File................................................. 424
Using the Standard VCD Approach ........................................................................ 424
Writing a VCD File from a Verilog Simulator ................................................ 425
Writing a VCD File from ModelSim............................................................... 425
Writing a VCD File from the Cadence NC-Sim Simulator ............................ 425
Creating a Named Pipe to Manually Compress VCD Files .......................... 425
Using an IAF Approach ........................................................................................... 426
Acquiring Simulation Data in Palladium Flows ........................................................ 427
Troubleshooting Tips............................................................................................... 429
Missing 'timescale in Verilog ........................................................................ 429
Zero Length activities.iaf File........................................................................ 429
Problems with ModelSim .............................................................................. 429
Zero Delay Simulation .................................................................................. 430
CHAPTER 17 Generating Etcl Files for CoolTime

Introduction ............................................................................................................. 433
Generating an Activity-Based Etcl File .................................................................... 434
Performing a Vector Analysis ....................................................................... 434
Analyzing the Waveform .............................................................................. 435
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CONTENTS PowerArtist™ User Guide xiv
Controlling the Precision of the Data in the Etcl File .................................... 435
Generating the Etcl File................................................................................ 435
Using a Name Mapped Flow ........................................................................ 436
Generating a Power-Based Etcl File ....................................................................... 438
Automatically Selecting the Highest Activity Clock Cycle............................. 438
Manually Selecting Single or Multiple Clock Cycles of Interest .................... 439
CHAPTER 18 Writing OpenAccess Database Applications

Introduction ............................................................................................................. 441
Introduction to OADB Programming........................................................................ 442
PowerArtist Netlist Properties ................................................................................. 443
Instance Properties ...................................................................................... 443
Net Properties .............................................................................................. 444
Pin Properties............................................................................................... 445
Module Properties ........................................................................................ 445
Hierarchical Instance Properties .................................................................. 446
Writing a Native OpenAccess Application............................................................... 447
Contents of the Documentation Package ..................................................... 447
Basic Requirements for a Native OpenAccess Tcl Application .................... 448
Flow for Writing a Native Tcl Application ...................................................... 448
Using a Script ............................................................................................... 449
Using the PowerArtist API to Write an OpenAccess Application ............................ 451
Getting Started ............................................................................................. 451
Using the Design Navigation Utilities ........................................................... 453
Using the Netlist Traversal Utilities............................................................... 454
Using the Design Query Utilities................................................................... 455
Using the Analysis Reporting Utilities........................................................... 456
Using the Reduction Reporting Utilities ........................................................ 456
Using the Power Database Mapping Utilities ............................................... 457
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1
Chapter 1
Installing and Setting Up PowerArtist 1
Introduction
This chapter provides instructions to enable you to install the software and have
access to the PowerArtist application. You will need to perform the following three
steps:
1. Install the software on one of the supported operating systems.
2. Install and point to the appropriate licenses.
3. Set a critical environment variable to point to the installation directory.
Supported Operating Systems

PowerArtist is supported on the following operating systems/platforms:
 64-bit Solaris version 10
 32-bit Red Hat Enterprise Linux (RHEL) 4.0 and 5.0
 64-bit: RHEL 4 and 5 on Opteron and Xeon; Suse 9 and 10 on Xeon
If you have a relatively large design you should use a 64-bit platform. If you are not
able to synthesize your design on a 32-bit Linux system, you should strongly
consider using a 64-bit machine for your power analysis and reduction runs.
Installing the Software

To install the software on any supported OS, perform the following steps:
1. Decide where you want to put the distribution and change your working directory
to that directory. The subdirectory sequence/version/PowerTheater will be created
within your current working directory.
2. Uncompress and extract the software distribution by typing the following
command. Note that the name of the zipped tar file is platform-dependent.
gunzip -c PowerTheaterversion.platform.tar.gz | tar xf -
Apache Design, Inc.

CHAPTER 1 — Installing and Setting Up PowerArtist PowerArtist™ User Guide 2
Distribution Tree
Note that you can install multiple platform distributions in the same directory, as
further discussed in the following section.
Distribution Tree
The Apache PowerArtist distribution is organized so that executables for multiple
platforms can be installed in the same location. For example, you could install the
Linux version in the same directory as the Solaris version, with no duplication of
data. Therefore, platform-specific files are kept under directories with the following
platform-specific names:
 linux—for 32-bit Linux, RHEL 4 and RHEL 5
 linux-x86_64—for 64-bit Linux for Opteron, RHEL 4, RHEL 5 and SUSE 9 and 10
 sunsol64—for 64-bit SunSol OS 10
Note, however, that the PATH environment variable must include the
$POWERTHEATER_ROOT/bin directory. It need not have any platform-specific
path elements, because a platform-independent script will invoke the correct
excutable.
The PowerArtist distribution consists of the following directories:
 bin—contains the executables. Set your PATH to include this directory.
 doc—contains the PDF documentation and the release notes.
 examples—contains some user examples as well as some examples oriented
toward library developers.
 lbin—contains administrative programs that you will not want in your PATH. This
includes the FLEXlm administration utilities and the PowerArtist license server.
 lib—contains library files needed by the power tools.
 misc—contains the source to the wwvmkr VHDL makefile program.
 pthdl_src—contains VHDL source files for the IEEE, STD, Synopsys and Vital
libraries for the HDL analyzer, pthdl (run by the Elaborate command).
 scripts—contains
 sfl_lib—contains the SFL model file (sfl_lib.dat) and generic technology library
information.
 tutorial—contains files for running both command-line and GUI-based tutorials in
PowerArtist.
 vhdl_src—contains VHDL source files for the IEEE, STD, Synopsys and Vital
libraries for the legacy VHDL analyzer, wwvhdl.
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PowerArtist Licensing
This section includes the procedure for installing licenses and provides information
on various licensing topics, including troubleshooting tips. Note that the software
version number (for example, 2011.1) used in the following examples will change
with every software release. Furthermore, these examples assume that you installed
the PowerArtist distribution tar kit in the /pkg directory.
Installing Licenses and FLEXlm

Use the following process to install licenses and FLEXlm® from Flexera:
1. Obtain a license file (license.dat) from Apache Design.
2. Install the license.dat file.
If you have other FLEXlm-licensed software, you may want to append the
license.dat file to your existing license.dat file. If you do not, then simply install it
into the /pkg/sequence/version/PowerTheater/lib/ directory.
3. Set the LM_LICENSE_FILE environment variable to point to the installed
license.dat file, for example:
setenv LM_LICENSE_FILE /pkg/sequence/2011.1/PowerTheater/lib/license.dat
4. If you have a demo license, the installation is complete.
You have a demo license if the string “DEMO” appears in the license.dat file.
5. Edit the license.dat file to specify the full pathname to the vendor daemon.
Replace the path specified in the DAEMON line with the following:
/pkg/sequence/2011.1/PowerTheater/lbin/apacheda
6. Start the license server by running the following command:
/pkg/sequence/2011.1/PowerTheater/lbin/lmgrd \
-c /pkg/sequence/2011.1/PowerTheater/lib/license.dat \
-l /pkg/sequence/2011.1/PowerTheater/lbin/lmgrd.log
Note that any user can do this—you don’t have to be “root”.

The -c option specifies the name of the license file.
The -l option specifies the name of the log file.
Understanding License File Entries

A typical license file entry looks like this:
FEATURE sptPowerGating apacheda 2012.10 15-feb-2012 20 \

START=27-apr-2011 SIGN="0320 733C 1702 CC6B A286 A8B0 DB8A \
9839 82CC 4E33 7903 E64F 0A34 744F 8A17 929D BB22 FDE2 C415 \
C3BF 8BFC"
Apache Design, Inc.

The first number, 2012.10, is the last supported build date for programs using this
feature. In this case, all programs built on or before October, 2012 will be allowed to
check out this feature. This is often referred to as the “maintenance end date”,
indicating that no new software built after this date will run with this license feature.
The second date, 15-feb-2012, is the last day this feature can be checked out. In this
case, no programs will be allowed to check out this feature after February 15, 2012.
This is often referred to as the expiration date.
Support for Multiple License Servers

PowerArtist supports multiple FLEXlm license servers. See the FLEXlm
documentation for details on how to set up multiple license servers.
Product vs. Feature Licenses

PowerArtist licenses are categorized into product licenses and feature licenses.
Product licenses “own” feature licenses. This means that you can perform power
analysis steps in parallel only if you have multiple product licenses.
Waiting for a Feature License

If you do not have a required feature license available to you immediately, you can
instruct the software to wait for a license to become available. This feature is
controlled by the -wait_for_license option to most of the Tcl commands. For example:
Elaborate -wait_for_license true
will wait for the license that controls elaboration to become available rather than
exiting when one is not immediately accessible.
On the product level, the ptshell also has an option to wait for a product license (such
as an SOC or an -artist license, for example:
ptshell -SOC -wait
waits for the SOC product license to become available rather than exiting
immediately with a message indicating that a license is not available.
Resolving Feature Checkout Problems

If you get random license checkout problems, change your license file’s port number
to something else in case there is a conflict with another vendor’s daemon.
Example
SERVER hostname 000f1f64dc32 7788
In this example, 7788 is the port number.
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Setting the UNIX Environment Variable for PowerArtist

To configure PowerArtist for your use, you (and all other users) need to set the
POWERTHEATER_ROOT environment variable to the proper installation directory.
On the UNIX command line, set up your environment by typing the following:
setenv POWERTHEATER_ROOT /your_path/version/PowerTheater
set path =($POWERTHEATER_ROOT/bin $path)
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7
Chapter 2
Using the PowerArtist Shell 2
Introduction
The PowerArtist shell (ptshell) is a fully functional Tcl shell, from which all other
PowerArtist commands must be invoked. You can use any standard Tcl command
inside of this shell. When you start up the shell, you will be informed as to which
product you are running, and then receive a ptshell prompt. Once you get the
prompt, you can run any of the PowerArtist commands.
Understanding the ptshell Command Options

This command launches the PowerArtist Tcl shell (ptshell). You can source Tcl scripts
or type a sequence of commands from within the ptshell. Use the “exit” command to
close the ptshell.
Syntax
ptshell [-artist | -SOC] [-cmd tcl_command] | [-tcl tcl_file]

[-wait]
Options
-artist
Consumes a license at the PowerArtist level. You will get a ptshell prompt with this
option.
-SOC
Consumes a license at the SOC level. You will get a ptshell prompt with this
option. This is the default. If you have no sptSOC license and you have specified
neither the -artist or -SOC options, ptshell will attempt to consume an sptArtist
license.
-cmd tcl_command
Executes the specified Tcl command and then exits with the result.
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CHAPTER 2 — Using the PowerArtist Shell PowerArtist™ User Guide 8
-tcl tcl_file
Sources a file containing Tcl commands and then exits with the result. These
commands may also include PowerArtist commands.
-wait
Waits for the appropriate product license to become available rather than exiting
immediately with a message indicating that a license is not available.
Example 1
ptshell
This command invokes the PowerArtist shell. At the resulting ptshell prompt, you
may type any Tcl command or PowerArtist command. This does not specify a license
level so -SOC is assumed. Therefore, you will be able to execute all PowerArtist-PT
commands. You will not, for example, be able to perform a power reduction analysis.
Example 2
ptshell -artist
This command invokes the PowerArtist shell. The -artist option allows you to run all
PowerArtist features (including power reduction analysis and RTL rewrite).
Example 3
ptshell -artist -tcl run_Elaborate.tcl

This consumes licenses at the Power Artist level and then runs the Tcl script
Elaborate.tcl. A sample Elaborate.tcl file might be:
source ptSourceFiles.tcl
Elaborate -scenario_file my.scn \
-top top \
-synlib_files {mylib.lib}
When the Elaborate command completes, the ptshell will be exited.
Example 4
ptshell -artist
ptshell % source Elaborate.tcl
This series of commands does the same thing as the command in example 3. except
that you will remain in the ptshell when the Elaborate script is complete. that it does
not exit the ptshell.
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Example 5
ptshell
ptshell % source ptSourceFiles.tcl
ptshell % Elaborate -scenario_file my.scn -top top -synlib_files
{mylib.lib}
ptshell % exit
When you type ptshell followed by a carriage return, you get a ptshell prompt, which
defaults to “ptshell %”. You can type a sequence of commands at this point.
Example 6
ptshell
ptshell % help command
As in example 5, when you type ptshell followed by a carriage return, you get a
ptshell prompt. You can then type “help command” at the ptshell prompt to print a list
of commands that you can use in a PowerArtist command file/Tcl script.
Example 7
ptshell -cmd "CalculatePower -help" > cphelp

This prints help information for the CalculatePower command. It is first sent to stdout
which is then re-directed to a file named “cphelp”. Whenever you want to run a Tcl
command from the ptshell, you must enclose the command in quotes as shown here;
otherwise you will get an error.
Invoking the GUI from the ptshell

You can invoke the PowerCanvas GUI from ptshell using the PowerCanvas
command:
ptshell % PowerCanvas
You can optionally use the -pdb option to specify the power database to load:
ptshell % PowerCanvas -pdb top.pdb
You can also bring up the GUI from the UNIX command line as shown in the
following examples.
Example 8
PowerArtist-PT
This is the recommended way to invoke the PowerArtist-PT PowerCanvas if you
want (or have) only the analysis capabilities of the PowerCanvas GUI.
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ptshell Features
Example 9
PowerArtist
This is the recommended way to invoke the PowerArtist PowerCanvas with full
analysis and reduction capabilities.
Reverting to the Legacy Shell

If you want to use the legacy ptshell, you need to specify the PT_DISABLE_APSH
environment variable:
setenv PT_DISABLE_APSH 1
This setting reverts to the legacy ptshell.
ptshell Features
The ptshell is a fully functional Tcl shell from which you can invoke any standard Tcl
command. In addition, ptshell supports a set of TCSH-like features for command
editing, file completion, and more. The ptshell has the following features:
 Command-line help for command file commands.
— You can type “help command_name” such as “help CalculatePower”. You can
specify a partial command name with standard glob-style wild cards such as
“help Calc*” or “help *db*”.
— You can type “command_name -help” such as “Elaborate -help” in the ptshell to
get a list of options for the Elaborate command.
— You can generate an alphabetical list of all accepted PowerArtist Tcl commands
(or pt_set variables) by typing “help command” (or “help variable”) at the ptshell
prompt.
 An auto-generated history file—As each PowerArtist command is executed, it is
echoed into a ptshell.history file in your current working directory. This allows you
to run Tcl programs that execute commands that are then captured in the history
file. You can then source this file (using the Tcl source command) to re-run the
exact sequence of commands.
 Command/file name completion with the Tab key—the shell will expand a
command to the next unique character and provide a list of all possible
commands/file names to complete the entry.
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ptshell Features
 Command-line editing—use the left and right arrows, control characters and
escape sequences to edit the current command on the command line. The
following table lists the keystroke combinations and their associated actions.
Key/Key Combination Action
Ctrl-a Goes to the beginning of the line
Ctrl-b Moves back one character
Ctrl-d Deletes current character
Ctrl-e Goes to end of the line
Ctrl-f Moves forward one character
Ctrl-k Yanks and deletes until the end of the line
Ctrl-n Gets the next command from history
Ctrl-p Gets the previous command from history
Ctrl-y Pastes the yanked buffer
Esc-b Moves back one word
Esc-f Moves forward one word
Left arrow key Moves back one character
Right arrow key Moves forward one character
Up arrow key Gets the previous command from history
Down arrow key Gets the next command from history
 Recalling commands from history—use the up and down arrows to scroll through
commands that were previously executed in the current session. By default, 20
commands are saved in history. Use “history keep 50” to increase the history size
to 50.
 An initialization file (.ini) file that allows you to customize your ptshell run (see the
next section for details).
Customizing Your PowerArtist Environment Using Initialization

(INI) Files
You can use .ini files to customize your ptshell setting at multiple levels. You can use
this file to change the default names of the log file and the key file (see,
Understanding Log Files and Key Files for details). You can also specify a custom
ptshell prompt. You can place the .ini files in different locations to customize at
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ptshell Features
different levels. The shell sources the .ini files in the following order (the last one
taking precedence over previously read files):
1. $POWERTHEATER_ROOT/ptshell.ini (default .ini file)
This default .ini file is read first. Further .ini files (if present) will modify the settings
in this file.
2. $HOME/ptshell.ini file, if present, is read next.
You can use this .ini file to customize the shell for you as a user.
3. $PWD/ptshell.ini file, if present, is read next.
You can use this .ini file to customize the shell for a particular run.
4. The file pointed to by the $PTSHELL_INI variable, if present, is read last.
You will typically use this .ini file to customize the shell for a particular project.
Sample Initialization File

The following sample initialization (.ini) file includes ptsh_* variables that you can use
to customize your PowerArtist shell.
#++++++++++++++++++++++++++++++++++++
# Sample Initialization File
#++++++++++++++++++++++++++++++++++++
set ptshLogFile my_ptshell.log
set ptshKeyFile my_ptshell.key
set ptshPrompt “my_ptshell %”
#++++++++++++++++++++++++++++++++++++
Understanding Log Files and Key Files

When you run ptshell, you will always get a .key file and a .log file that capture
session information in different ways:
 ptshell.log
This file captures all tool outputs for your current session. This includes
commands run, output generated (including the content of each of the individual
command_name.log files), the contents of any sourced files, etc. You can change
the name of this file using the ptshLogFile Tcl variable in your .ini file.
 ptshell.key
This file captures commands executed from the ptshell. You can source this key
file to re-run the exact sequence of commands from the recorded session. You
can change the name of this file using the ptshKeyFile Tcl variable.
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Understanding the Link Between Commands and the PowerCanvas

You can invoke the PowerCanvas, which is the PowerArtist graphical user interface,
by specifying different commands to ptshell (see examples 3-5). As you will see in
later chapters, the PowerCanvas contains the following major blocks of functionality:
 Wizards that guide you through a process to perform major tasks such as HDL
elaboration, vector analysis, power calculation or power reduction. They help you
set up the various task options and then execute one or more of the key
PowerArtist commands.
 Features that help you diagnose power bugs in your design and understand the
output of various automated reduction algorithms.
In this way, the PowerArtist commands are closely linked to the PowerCanvas
wizards.
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15
Chapter 3
PowerArtist Tutorial Part 1: Power

Analysis 3
Introduction
This tutorial shows you how to run both average and time-based power analysis
using a batch flow and a PowerCanvas flow. It includes the following types of
analyses: full-chip, block-level, clock gating, mixed-vt, voltage_islands, power gating
and gate-level full chip. Running power analysis is a simple three-step process, as
shown by the following graphic:
Verilog/VHDL Power-Characterized
Source Libraries
Three easy steps:

Elaborate
1. Compile Design
Simulation
2. Run Vector Analysis GenerateActivityWaveforms
Activity
3. Run Power Analysis CalculatePower

Choose your analysis mode average time-based
Power Database
(OADB) Power Reports
PowerCanvas
The main steps in this power analysis flow are controlled by the following commands:
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CHAPTER 3 — PowerArtist Tutorial Part 1: Power Analysis PowerArtist™ User Guide 16
Introduction
 Elaborate—creates the scenario file for Verilog, VHDL and mixed-language

designs.
 GenerateActivityWaveforms—analyzes the activity file and produces waveform
files representing the activity in your design.
 CalculatePower -analysis_type average—performs an average power analysis.
 CalculatePower -analysis_type time_based—performs a time-based power
analysis.
There are three goals to the tutorial:
 To introduce you to the PowerArtist command file setup.
 To introduce you to the PowerCanvas GUI.
 To present sample power-aware design flows for different types of analysis.
 To guide you through interpreting the results.
Note that this tutorial does not cover power reduction. To run the power reduction
tutorial, see the PowerArtist Tutorial Part II: Power Reduction.
Tutorial Organization
The following topics are covered in this tutorial:
 Copying the PowerArtist Tutorial Files
 Understanding Command File Set-Up Methods
 Running an RTL Full-Chip Power Analysis Using Command Files
 Viewing Power Analysis Results in the PowerCanvas
 Running Full-Chip Analysis Using the PowerCanvas Wizards
 Running an RTL Block-Level Power Analysis
 Running Power Analysis with Clock Gating
 Running a Power Analysis with a Mixed-Vt Cell Library
 Running Power Analysis with Voltage Islands
 Running a Power Analysis with Power Gating
 Running the Full-Chip Gate-Level Power Analysis Tutorial
 Understanding Power Analysis Results in the Text-Based Power Report
 Summary
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Copying the PowerArtist Tutorial Files
Copying the PowerArtist Tutorial Files

There are two tutorials in the /tutorial directory. It is recommended that you copy the
entire contents of the tutorial directory to a local run directory:
cp -r $POWERTHEATER_ROOT/tutorial .
The analysis design is a mixed-language RTL design of a 64-bit PCI controller. The
bulk of the design is captured in Verilog with one file, representing the fifo controller,
captured in VHDL.
Contents of the Top-Level Tutorial Directory

The following table lists the contents of the entire tutorial directory:
Directory Name Description
analysis Contains the analysis tutorial files. These tutorials

teach you how to perform HDL inferencing, vector
analysis and average and time-based power analysis
at both the RTL and gate levels of abstraction.
libraries Contains all of the technology libraries required to run

the tutorials.
settings/ This file illustrates how you can establish site-wide tool
global_setting.tcl settings that are shared among users. These settings
are leveraged in all the tutorials.
reduction Contains the reduction tutorial files. This tutorial

teaches you how to perform an RTL power reduction
analysis. This tutorial is not described in this chapter.
For instructions on running the reduction tutorial, see
PowerArtist Tutorial Part II: Power Reduction.
For the analysis tutorials, you will need all but the /reduction directory.
Contents of the Analysis Directory

The analysis directory contains a number of sub-directories that each run a different
type of analysis tutorial as shown in the following table.
full_chip Runs a full-chip RTL tutorial that shows how to run all
of the critical analyses in PowerArtist. You will be
running simulation-based analyses here.
block Runs a tutorial on a sub-block of the full-chip design in

the full_chip directory. You will be performing a
vectorless analysis here.
clock_gating Shows you how to run clock gating analysis using the
full_chip design.
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Understanding Command File Set-Up Methods
mixed_vt Shows you how to run analysis using mixed VT using

the full_chip design.
voltage_islands Shows you how to run multiple voltage-domain

analysis using the full-chip design.
power_gating Shows you how to run power gating analysis using the
full-chip design.
full_chip_gate Shows you how to run a gate-level analysis on the full-

chip design, which has been synthesized to gates.
It is recommended that you run these tutorials in the order they are listed in this
table. In addition to the tutorial sub-directories, there is also a design_data directory
that contains design data that is used by all of the analysis tutorials. It includes both
gate and RTL source files and simulation data.
Understanding Command File Set-Up Methods

Before starting this tutorial, it’s important that you understand the ways in which you
can set up your Tcl command files. It is recommended that you specify the command
file commands with command-line options that determine the inputs for the
commands, the type of analysis they run and the output files generated.
Recommended Method Sample Script
# Elaborate Design
Elaborate -top top -elaborate_write_power_db true -blast_regfile all
This script runs the Elaborate with the -top, -elaborate_write_power_db and -
blast_regfile options specified. Alternatively, you could specify these command
options as standalone pt_set variables. You would then specify the command without
options. The following command file excerpt uses this set-up method. You would
specify these variables before the command to which they apply.
Alternative Method Sample Script
# Elaborate Design
pt_set top top
pt_set elaborate_write_power_db true
pt_set blast_regfile all
...
Elaborate
In this sample file, each of the pt_set variables specified before the Elaborate
command determine how the command will run. The Elaborate command is then
called last. Using this method, you can specify one pt_set variable that affects
multiple commands.
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Running an RTL Full-Chip Power Analysis Using Command Files
Note that the pt_set variable names are the same as the command options but
without the preceding dash (-), therefore, “-blast_regfile” becomes “pt_set
blast_regfile”. For a complete list of pt_set variables, see Alphabetical List of pt_set
Variables in the PowerArtist Reference Manual.

To begin the full-chip tutorial, change directories to your local full_chip tutorial
directory, for example:
cd tutorial/analysis/full_chip
The following table lists the files in this directory.
File Name Description
README Provides the basic flow for running this tutorial.
ptshell.ini Initialization file specific to the full-chip tutorial.

This file sets the ptshell prompt and specifies the
names of the .log and .key files for this tutorial.
command.tcl files Tcl scripts meant to be sourced from within the

ptshell that perform various tasks related to power
analysis (for example, design elaboration, vector
analysis, average power analysis, etc.) These are
identical to the operations you perform using the
interactive wizards.
ptSourceFiles.tcl Contains a list of VHDL libraries and VHDL files in

your design in the order in which they must be
analyzed and elaborated. It consists of AddLibrary
and CompileFile commands.
For details on this file, see ptSourceFiles.tcl File
Format.
project_settings.tcl Sources a global Tcl file containing site-wide tool

settings and the libraries.tcl file containing library
information. Using a single file like this to source
other files will save time and reduce keystrokes.
This file is also specified in the HDL Inferencing
wizard.
power_aware.tcl Contains the power-aware commands required to

run the tutorial. This file contains all of the
commands that constrain the power analysis of
the design. Constraints can include:
-voltage and power domains
-mixed VT
-clock gating
-the libraries to be used for each sub-block of the
design
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analysis_wizard.tcl This file is used by the power analysis wizards to

source the project_setting.tcl file and the
power_aware.tcl file.
clock.tcl Contains commands that define the clocks in the

design.
txrx.vc Verilog startup file for the full chip that tells the
HDL elaborator which Verilog files must be loaded
for your design.
libraries.tcl Contains commands that define your Liberty

libraries.
/.ads_power_config This hidden directory contains a persistent

representation of what you enter in the
PowerCanvas wizards. The next time you invoke
the same wizards, all of the data you previously
entered will be pre-loaded in the forms. This
allows you to rapidly perform similar operations.
run_Elaborate.tcl Run scripts to invoke from the Unix shell. As an

run_VectorAnalsys.tcl alternative method, you could run the tutorial by
run_CalculateAveragePower.tcl typing the following commands at the Unix
prompt:
run_CalculateTimeBasedPower.tcl
ptshell -tcl run_Elaborate.tcl
ptshell -tcl run_VectorAnalsys.tcl
ptshell -tcl run_CalculateAveragePower.tcl
ptshell -tcl run_CalculateTimeBasedPower.tcl
Examining the Contents of the Tcl Command Files

1. Open the ptshell.ini file. This file contains shell initialization settings for the full-
chip tutorial.
set ptshKeyFile full_chip.key

set ptshLogFile full_chip.log
set ptshPrompt "full_chip_ptshell %"
As you run the tutorial, PowerArtist generates a key file and log file (both with a
“full_chip_” prefix) in your run directory. These files are useful for debugging or
recreating a previous run. For more information on these files, see Understanding
Log Files and Key Files. In addition, the ptshell prompt for this tutorial will have an
“full_chip_” prefix. Note that this .ini file overrides the default .ini file that comes
with the tarkit. For more information on the initialization file, see Customizing Your
PowerArtist Environment Using Initialization (INI) Files.
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2. Open the project_settings.tcl file. This file is shown here:
# Obtain global site-wide settings

source ../../settings/global_settings.tcl
# Specify the technology libraries

source libraries.tcl
This file obtains site-wide tool settings (from the global_setting.tcl file) and reads-
in library information (from the libraries.tcl file). The libraries.tcl file contains a
series of ReadLibrary commands. Creating this type of file saves you time and
requires fewer keystrokes.
3. Open the power_aware.tcl file. This file contains different setting depending on the
type of analysis you are running. For the full-chip tutorial, this file contains clock
gating commands and MonitorInstances commands. An excerpt from this file is
shown here:
##############################################
# Clock Gating Commands
SetClockNet -name top.clk -mode infer -gate_clock yes

SetClockNet -name top.pci_clk -mode infer
SetClockNet -name top.tck -mode infer
SetClockGatingStyle -clock_cell_attribute latch_posedge_precontrol
SetClockBuffer -type root -name SEQCLKBUFX4MTH -library hvt -fanout 2
SetClockBuffer -type branch -name SEQCLKBUFX8MTH -library hvt -fanout 2
SetClockBuffer -type leaf -name SEQCLKBUFX8MTH -library hvt -fanout 60
##############################################
# Instances to monitor in the design
MonitorInstances -name top.core1.t1 -all 1

MonitorInstances -name top.core1.r1 -all 1
4. Make special note of the following information in this Tcl file:

— The SetClockNet command defines the three clocks in the design and specifies
that clock gating be performed (-gate_clock yes) for the clock named “top.clk”.
For top.pci_clk it specifies “-mode infer” tells PowerArtist to infer to the clock
tree in this design. This is essential to achieve accurate full-chip RTL Power
Analysis.
— The SetClockGatingStyle command specifies the value of the
clock_gating_integrated_cell attribute, which in this case
latch_posedge_precontrol. During the clock inferencing step of any power
analysis, PowerArtist searches for this attribute to determine candidate clock
gating cells.
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— The SetClockBuffer commands specify three types of clock buffers: root,

branch and leaf. when you want to infer a clock tree. These are required when
you want to infer a clock tree.
— The MonitorInstances command tells PowerArtist to generate the power report
that lists all of the children instances for top.core1.t1 and top.core1.t2.
5. Open the Elaborate.tcl file. This script compiles and elaborates the design using
the Elaborate command. It generates a scenario file which is a binary
representation of the elaborated design. This file is shown here:
# Elaborate the design

set design top
# Read in the design

Elaborate \
-elaborate_write_power_db true \
-elaborate_log ElaborateBatch.log \
-power_db_name $design.Batch.pdb \
-scenario_file $design.Batch.scn \
-top $design \
-verilog_2001 true \
-verilog_startup_file txrx.vc
6. Make special note of the following information in this command file:

— The “set design top” is a simple standard Tcl variable that sets the top module
to “top”. This defined “design” variable is used in the rest of the script.
— Since the full-chip design is a mixed design that has some Verilog and some
VHDL, this script sources the ptSourceFiles.tcl and specifies the -
verilog_startup_file option to the Elaborate command.
— The -elaborate_write_power_db option writes out a power database (.pdb) file.
When Elaborate runs, it creates this power database.
This power database is an OpenAccess™ database (OADB) that contains a
hierarchical netlist representing your design as well as power analysis and
reduction values. PowerArtist uses this database to generate hierarchical tree
and schematic displays of your design, and to store power analysis and
reduction information. You are able to write your own applications that access
the netlist and power-related information. For more information, see Writing
OpenAccess Database Applications.
— The resulting scenario file, as specified with the -scenario_file option, will be
named top.Batch.scn (since $design is set to “top”).
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7. Open the GenerateActivityWaveforms.tcl file. The commands and variables in this

file run full-chip vector analysis:
# Perform Vector Analysis
# Define the vector groups for the design
DefineGroup top { top }

DefineGroup core { top.core1 }
DefineGroup pci { top.core1.p1 }
DefineGroup rxchan { top.core1.r1 }
DefineGroup txchan { top.core1.t1 }
set design top
GenerateActivityWaveforms \
-activity_file ../design_data/rtl_sim/activities.vcd \
-activity_waveform_group_list { top core pci rxchan txchan } \
-activity_waveform_graph_type frequency_per_interval \
-activity_waveform_interval_size 15160ps \
-activity_waveform_number_of_intervals 400 \
-activity_waveform_start_time 6071580ps \
-fsdb_output_file top_activity.fsdb \
-log GenerateActivityWaveformBatch.log \
-scenario_file top.Batch.scn \
-top_instance txrx_tst.top1

— Simulation data in the form of a VCD file is supplied as the activities.vcd file.
Full-chip vector analysis requires some form of simulation data. You can use
any one of three approaches to acquire simulation data: the Intermediate
Activity File (IAF) approach, the standard VCD approach, and the FSDB
approach. In the IAF approach, special-purpose code provided by Apache is
linked into your simulator to create the .iaf file when your simulation is run. In
the standard VCD approach, no special code is linked but standard VCD
commands used with your simulator are used to produce the VCD file. In the
FSDB approach, you generate an FSDB file using the Verdi™ product from
SpringSoft to obtain activity information from your simulator of choice. FSDB
files are excellent ways to store your activity data because they represent the
information in a more compressed manner than other formats. See Chapter 16,
Acquiring Simulation Data for detailed information on how to create the
simulation activity files.
— The DefineGroup command defines groups (top, core, pci, rxchan and txchan).
These groups will have separate waveforms in the resulting FSDB file that
captures the average activity of all the nets local to those instances as a
function of time.
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— The GenerateActivityWaveforms command performs the vector analysis. In this

case, it sets the interval size to 15160ps, the number of intervals to 400 and
begins the analysis at 6071580ps. The -activity_waveform_group_list option
specifies the five groups created earlier by the DefineGroup command.
9. Open the CalculateAveragePower.tcl file (as shown below). The settings in this file
run the full-chip average power analysis.
#Calculate the power of the design
set design top

CalculatePower -analysis_type average \
-average_report_file $design.AverageBatch.rpt \
-average_report_options agip \
-average_write_power_db true \
-compress_gaf true \
-default_output_load 3.9e-11 \
-detailed_vertical_report true \
-finish_time 12135580ps \
-gaf_file $design.AverageBatch.gaf \
-calculate_log CalculatePowerAverageBatch.log \
-mode_file txrx.mode \
-power_db_name $design.AverageBatch.pdb \
-save_clock_trees_netlist true \
-start_time 6071580ps \
-top_instance txrx_tst.top1 \
-use_scan_flops true \
-vertical_report_instances $design \
-wireload_library hvt
— The CalculatePower command is set to run average analysis (-analysis_type
average). All of the -average* options are specific to this type of analysis.
— Simulation data is provided by the activities.vcd file.
The quality of the simulation data provided to PowerArtist is a major factor in the
quality of the power analysis. Accurate power analysis for typical usage of a
design requires typical simulation data. The CalculatePower command analyzes
the simulation results and generates compressed summary data in the
top.AverageBatch.gaf file. This file will then be used for power analysis in this
run and subsequent runs of CalculatePower to save time from having to re-
analyze the VCD file each time you run the software.
— It will generate a detailed vertical report of analysis results.
— It will run a modal (-mode_file) analysis using the txrx.mode file. The design in
this tutorial has different modes of operation and it useful to know the power
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consumed in each mode. Typical modes of operation for chips are standby,
sleep, receive, transmit, interrupt, etc. By getting a good understanding of the
modal power of your chip, you can gain a better understanding of the battery
needs for your applications. For details on the format of the mode file, see
Mode File Format.
— The log file that this analysis generates will be named
CalculatePowerAverageBatch.log.
— The -save_clock_trees_netlist true option generates power database
schematics for the clock tree in the design. Without this setting, you will not be
able to view your clock tree in the PowerCanvas.
— The power database that this analysis generates will be named
top.AverageBatch.pdb. This is the file you will load into the PowerCanvas.
— The analysis looks for wire load models in the Liberty library with the logical
library name hvt.
— Scan flops will be used to perform analysis (this is the default behavior).
11. Open the CalculateTimeBasedPower.tcl file (as shown below). The settings in this
file run the full-chip time-based power analysis. Many of these options are
identical to those required to perform the average power calculation.
# Calculate the power of the design

set design top
CalculatePower -analysis_type time_based \
-active_edge positive \
-fsdb_output_file $design.TimeBasedBatch.fsdb \
-calculate_log CalculateTimeBasedPowerBatch.log \
-num_clock_cycles 400 \
-power_db_name $design.TimeBasedBatch.pdb \
-reference_clock top.clk \
-time_based_report_file $design.TimeBasedBatch.rpt \
-time_based_write_power_db true \
— The CalculatePower command is set to run a time-based analysis (-
analysis_type time_based). All of the -time_based* options apply to this type of
analysis.
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— The simulation time from 6071580ps to 12135580ps will be broken up into

intervals of 400 clock cycle blocks. Each 400 cycle block will result in an
average power estimation therefore generating a power-over-time waveform.
This waveform is saved in the top.TimeBasedBatch.fsdb file which you can
view in the Apache Waveform Viewer.
CalculateTimeBasedPowerBatch.log.
top.TimeBasedBatch.pdb. This is the file you will load into the PowerCanvas.
Running the Tcl Scripts

Use the following steps to run the command file flow for the full-chip tutorial:
1. Type “ptshell” to start the PowerArtist shell. The prompt for this tutorial will be:
full_chip_ptshell %
As soon as the ptshell starts, you will see the following additional files in your run
directory:
— full_chip.key—Records keystrokes run as part of this tutorial. You can re-run a
session by sourcing this file.
— full_chip.log—Records log information (inputs and outputs) for this tutorial.
capturing the output of standard out.
2. From the ptshell prompt, source the project_setting.tcl script to setup project-
specific parameters and read your libraries.
full_chip_ptshell % source project_settings.tcl
Note: You can take advantage of the command completion feature of the ptshell.
For example, you can simply type “source p” followed by the Tab key and to see a
list of files that match. Type additional characters followed by Tab until the
ambiguity is resolved. Using this feature will save you time and cut down the
number of keystrokes required to run the command-line tutorial.
3. Source the Elaborate.tcl script to compile the design and create a PowerArtist
scenario file:
full_chip_ptshell % source Elaborate.tcl
The ptshell can do limited checking on the correctness of the data. It can verify
that files are readable. However, the arguments are not completely checked until
the actual application gets spawned. As an example, if you specify a CompileFile
command, the actual source file is not parsed until the Elaborate command is
executed.
When the script is finished, you will see the following files in your run directory:
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— ElaborateBatch.log—This file captures log information for the Elaborate

command. If you get any unexpected results, you can look through this file to
make sure that the settings listed are those that you expected to be set.
— top.Batch.scn—This is a binary representation of the full-chip design. This
scenario file is called later by the analysis scripts.
— top.Batch.pdb—At this point in the flow, this PDB file contains the design
hierarchy. You can use the PowerCanvas to explore this hierarchy at this point.
The power analysis run will add to this file.
4. Exit the ptshell:
full_chip_ptshell % exit
5. View and analyze the elaborated design in the PowerCanvas.
a. Invoke the PowerCanvas using either of the following commands:
% 1PowerArtist-PT -pdb top.Batch.pdb
or
% PowerArtist -pdb top.Batch.pdb
The hierarchy browser (at the top level) and the collapsed schematic of the
elaborated design appears.
Figure 1 Display of top.Batch.pdb File (Elaborated Design)
1. If you are a returning PowerTheater user and you do not have a PowerArtist license, you
will need to invoke the PowerCanvas GUI using the PowerArtist-PT command. Note that it
does not have the full functionality of the PowerArtist license.
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b. Click the top(top) instance in the left-hand pane of the hierarchy browser. Click
the + symbols next to the nested hierarchical instances to display their
instances in the right-hand pane called the power table.
6. When you are finished examining the elaborated design, exit the PowerCanvas
(select File > Exit).
7. Restart the ptshell:
% ptshell
8. Source the project_settings.tcl file again.
You must reload this file whenever you restart the ptshell in this tutorial flow.
9. Source the GenerateActivityWaveforms.tcl script to run vector analysis:
full_chip_ptshell % source GenerateActivityWaveforms.tcl
Vector Analysis shows how the activity varies over time for selected blocks in your
design. Vector Analysis should be done before power analysis to ensure that the
testbench has exercised the design as expected and can be used to identify a
suitable time window to perform power analysis. Note that additional details are
available in Analyzing Simulation Activity.
When the script is finished, you will see the following filed in your run directory:
— GenerateActivityWaveformBatch.log—This file captures log information for the
GenerateActivityWaveforms command that controls vector analysis. If you get
any unexpected results, you can look through this file to make sure that the
settings listed are those that you expected to be set.
— top_activity.fsdb—This is the FSDB file containing waveforms for the specified
groups.
10. Exit the ptshell and restart the PowerCanvas GUI.
11. Display the resulting waveforms from the vector analysis:
a. From the PowerCanvas main menu, select Tools > Waveform Viewer.
The Add Waveform Source menu appears.
b. Select top_activity.fsdb from the Files list on the right and click OK.
c. In the Waveform Name field, type an * to find all waveforms and click the
Search button.
d. Select all of the waveform names, select “Place waveforms in: One plot” and
click the Add waveform to plot area button.
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The resulting waveforms show the average activity over time for the specified
groups.
Figure 2 Vector Analysis Waveforms for Each Specified Group
Notice that the rxchan module (colored blue) has very little activity in the first
half of the simulation then turns on. The inverse happens with the txchan
instance (colored orange). This clearly indicates that the pci controller starts out
transmitting packets of information and switches to receive packets. The
average net activity in the controllers when the controller is either transmitting or
receiving is about 9 MHz and less than 1 MHz when the chip is not in that mode
of operation.
 Use the cursor to highlight an individual graph. Hover on the graph legend to
minimize all but the selected graph. Hover on the graph itself to increase the
thickness of the line.
 Move the cursor over a data point on a graph to display the coordinates.
 Hold down the middle mouse button and drag a red rectangle to zoom in to an
area of interest.
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 Right-click and hold anywhere on the waveform to display a pop-up menu. Use
this menu to manipulate the waveform display. For details on all options
available, see Using the Waveform Viewer Options Menu.
 Click the Tips tab at any point to see more tips on using the viewer.
12. Exit the PowerCanvas GUI and restart the ptshell.
14. Source the power_aware.tcl file to read in the power constraints for this tutorial:
full_chip_ptshell % source power_aware.tcl
15. Source the CalculateAveragePower.tcl script to run average power analysis:
full_chip_ptshell % source CalculateAveragePower.tcl
When the script is finished, you will see the following filed in your run directory:
— CalculatePowerAverageBatch.log—This file captures log information for the
CalculatePower average run.
— top.AverageBatch.pdb—This power database now includes average power
analysis data.
— top.AverageBatch.rpt—This is the a text-based power report. For small
designs, you may find this format useful; for larger designs, you will want to use
the PowerCanvas to review the results.
16. Exit the ptshell.
17. Review and analyze the results of the average power analysis in the
PowerCanvas. For details see, Viewing Power Analysis Results in the
PowerCanvas.
18. Restart the ptshell.
full_chip_ptshell % source power_aware.tcl
21. Source the CalculateTimeBasedPower.tcl script to run time-based power analysis:
full_chip_ptshell % source CalculateTimeBasedPower.tcl
When the script is finished, you will see the following files in your run directory:
— CalculatePowerTimeBasedBatch.log—This file captures log information for the
CalculatePower time-based run.
— top.TimeBasedBatch.pdb—This power database now includes time-based
power analysis data.
— top.TimeBasedBatch.rpt—This is the a text-based power report for the time-
based run.
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Viewing Power Analysis Results in the PowerCanvas

23. Review and analyze the results of the time-based power analysis in the
PowerCanvas.

Once you have run any power analysis (average or time-based) you can view those
results in the PowerCanvas.
1. Load the power database named top.AverageBatch.pdb that was created by the
CalculateAveragePower.tcl script.
By default, the hierarchy browser is not colored.
2. To see the power results in the hierarchy browser, select Design
> Hierarchy >
Colorize by > Power. You can also color the power table by selecting Design >
Hierarchy > Colorize by > Power. The hierarchy browser now shows the design
colored for power as shown in the following figure:
Figure 3 Display of top.AverageBatch.pdb (Average Power Analysis Results)
The colorizing follows a thermal spectrum. The more power consumed, the hotter
the color (red indicating the most power consumed). The less power consumed,
the cooler the tab. Select this tab and select the data you want to view from the
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list; then click the Add waveforms to plot area button to display the waveform in
the View tab.
Manipulating Your Design in the Schematic

This section gives you a basic understanding of how to probe your design/results
using the schematic view. Once you have a basic understanding, you can
experiment with your own design.
1. From the hierarchy browser, click on t1/txchan then right click and select Show in
Schematic.
The t1 instance will display in the schematic.
2. Use your +/- key to zoom or do a press-drag-release to zoom in around t1, as
shown in the following figure.
phic
w rG a
Ne
N eed
Figure 4 Schematic Display of Module Selected in the Hierarchy
3. Notice the dynamic information display just above the schematic. This display
changes as you move your cursor over the elements in the schematic. This
display includes information such as instance name, cell name, parent, static/
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dynamic/total power, clock gating status, and optimization status. From this figure,
you can see that instance t1 consumes a total of 10.63 mW of power.
4. Do a shift-double click on the border of t1 which will then show a detailed view of
its schematic.
5. Do a shift-double click again to return to a view that only shows the primary ports.
If you zoom-in, you will notice that the port stubs for single-bit pins are thinner
than the port stubs for bus ports.
6. Double-click the bus port stub for din[63:0].
7. Click the wire coming from this port that is on the outside of the instance boundary
and select Schematic > Properties. or right-click and select Properties.
8. To see all of the nets, click the + sign next to the txdin pin name.
The Properties dialog will appear as shown in the following figure.
Figure 5 Properties Dialog for Net txdin
This dialog displays the frequency, capacitance source, transition time, average
activity, etc. for each net in the bus. Once you have opened this dialog, you can
click on different areas in the schematic and the dialog will update accordingly.
You can use this dialog to view net information for both single-bit ports and bus
ports. Furthermore, you can add tabs to this dialog to display other pins, nets, or
instances. For complete details on how to use the Properties dialog, see Using the
Properties Dialog.
Viewing Clock Trees

The PowerCanvas allows you to view both the clock tree for the entire design or for a
specific portion of the design. You can start with the full clock tree and zoom-in to
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tree segments or you can start with the clock tree for a specific register and build the
clock tree up from there. However, to be able to view clock trees you must save them
while performing a CalculatePower or ReducePower command. Do this by specifying
the “-save_clock_trees_netlist true” option as shown in the tutorial Tcl scripts.
If you want to see the clock tree for the entire design, you must first display a wire in
the schematic that corresponds to the actual clock net. You will select the wire and
then select a menu item that will generate the full clock tree corresponding to that
highlighted wire. In the tutorial design, there are three clock nets: top.clk, top.pci_clk
and top.tclk.
You can use the following process to generate the full clock net for top.clk.
1. Erase the schematic by doing a right-click and selecting Collapse Full Schematic.
This goes back to the view with only the primary inputs displayed.
2. From the Tree display, select core1/clogic.
3. Right-click and select Show in Schematic.
4. Double-click the clk pin for core1.
This brings up a vendor gate named sclk1 (SEQPIC), which in this case is a pad
cell.
5. Select/highlight the wire that goes to that pad cell.
6. Right mouse click on that wire and select Pin > Show Clock Tree as shown in the
following figure.
Figure 6 Displaying the Clock Tree for the Entire Design
This may take a few seconds. The entire clock tree will be displayed.
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7. You can now zoom in to see specific segments.
Displaying the Clock Tree for a Specific Register

If you want to see the clock tree associated with a specific register, you need to first
display the register in the schematic. You can then select the clock pin and select a
menu item to generate the clock tree. The clock tree that is displayed will be the
entire tree traced from the clock pin back up to the root buffer including any trace
instances or inferred integrated clock gating cells.
You can use the following process to display the clock tree for a single register:
1. Erase the schematic by doing a right-click and selecting Collapse Full Schematic.
This goes back to the view with only the primary inputs displayed.
2. Ensure that Design > Power Table > Hide Registers is not checked.
3. In the hierarchy, expand core1/clogic.
4. Select r1(rxchan) / s1(rxfsm) in the hierarchy view.
5. In the power table, scroll down to the register listing and select instance name
CurSt (the first listed register) and select Show in Schematic from the pop-up
menu.
Register core1.r1.s1.CurSt[0] displays in the schematic as shown in the following
figure:
Figure 7 Zoomed-in Schematic Display of Register core1.r1.s1.CurSt
6. Click the clock[0] pin/stub and select Pin > Show Clock Tree from the pop-up
menu.
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7. The clock tree for that register will be displayed in a separate window as shown
here:
Figure 8 Clock Tree for Register core1.r1.s1.CurSt[0]
Once you have the clock tree for this register displayed, you can build up the clock
tree by double clicking the red wires/nets.
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8. Double click the red net segment going into the input of SEQCLKBUFX8MTH
buffer. You will see additional connections to the clock tree for register
core1.r1.s1.CurSt[0] as shown in the following figure:
Figure 9 Additional Connections to the Clock Tree for Register core1.r1.s1.CurSt[0]
Waveform Cross-Probing
To perform waveform cross-probing from the schematic, first make sure that the
waveform viewer is visible by selecting Tools > Waveform Viewer. Then load the
FSDB or VCD file that contains the simulation data you want to see. When you select
a pin, port or net in the schematic, PowerArtist searches the simulation data you
loaded into the Waveform Viewer for data that matches the selected object’s name.
The matches are shown in the Search field. Simply select the waveforms you want to
view and click the Add waveforms to plot area button. For more details, see Using
the Waveform Viewer.
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Running Full-Chip Analysis Using the PowerCanvas Wizards

This section shows you how to elaborate your design, run vector analysis and a full-
chip power analysis using the PowerCanvas wizards. The main goal of all the
wizards is to introduce new users to the PowerArtist analysis tools. Specifically, the
wizards are designed to do the following:
 Guide the you through the steps required to perform a power analysis or reduction
run.
 Show you the critical options that are required to perform even the most basic
analysis. You can specify many additional options if you use the Tcl command file
flow as described earlier in this tutorial.
 Show you how commands and command options are generated from the user
interface and put into task-specific files in the .ads_power_config directory. You
can then build your own run scripts based on these output files.
 As you become more experienced, you will likely migrate to running more of your
analyses using the Tcl command files.
Note that each wizard corresponds to a PowerArtist Tcl command. For example, the
HDL Inferencing wizard corresponds to the Elaborate command. The power analysis
wizards both call the CalculatePower command. Therefore, the input fields
correspond to the equivalent command options. For example, the “Top instance
name” field, corresponds to the CalculatePower -top_instance option. When you are
finished running the wizard, you can look at the files in the ./.ads_power_config
directory to see the exact settings that you made in the wizards. These files are
hidden so you are not tempted to edit them. Do not edit them.
Performing Design Inferencing Using the HDL Inferencing Wizard

The first step in any PowerArtist run is to inference the design. You can use the
following process to run the HDL Inferencing wizard.
1. Invoke the PowerCanvas using either of the following commands:
% PowerArtist-PT
or
% PowerArtist
2. From the menu bar, select Tools > HDL Inferencing.
The HDL Inferencing wizard appears as shown in Figure 10.
In this full-chip tutorial, the design has both Verilog and VHDL and so both are
checked. If you have a design that is a pure Verilog design, you would check the
Verilog box and uncheck the VHDL box.
3. Verify that the txrx.vc simulation startup file is specified as the Verilog Command
File. Note that if you click the right-most icon, a file selector is displayed. You can
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then open the txrx.vc file. For additional information about this file, see Verilog
Startup File Format in the PowerArtist Reference manual.
4. To edit a specified input file, use the following process:
a. Click the icon to the right of the file specification. You will get an Xterm with
the editor of your choice editing the file. You can use the $EDITOR environment
variable to set the editor in advance.
b. If the input field is empty, a file browser will pop-up allowing you to choose or
enter a file name for saving the edited file.
c. Close the file browser. You get an Xterm with your file open in the editor of your
choice.
d. When you are done editing the file, simply close the editor.
Current step is
highlighted
Unvisited steps are

preceded by yellow
dot. A step that fails
has a red dot.
Uncheck for a pure

Verilog design.
Click to edit file
A bank of four buttons (Previous, Next, Finish and

Cancel) appear at the bottom of each screen. Any button
not applicable to the current screen is grayed out.
Figure 10 HDL Inferencing Wizard Language Setup Screen
5. Click Next.
The Top level setup screen appears. Note that you can also select the step
directly from the list of steps on the left side of the window.
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6. Verify that the top-level module has been set to “top”. The top-level parameters
are used if you have Verilog defparam or VHDL generic override values you want
to put in. To add a parameter, click the Add button and then type the name of the
parameter and the value. To delete a parameter, select the parameter and value
(Ctrl-click to select multiple parameters) then click the Delete button. This is not
needed for this design.
7. Click Next.
The Library setup screen appears.
Use this screen to specify the Liberty libraries (this tutorial does not use them).
8. Click Next.
The Blackboxes screen appears.
9. Click Next.
The Analysis options screen appears.
Figure 11 HDL Inferencing Wizard Analysis Options Screen
All of the fields on this screen are populated for this tutorial. Note that since this is
an RT-level design, the “Gate level design” box is not checked.
10. Notice that there is a startup script specified for this tutorial called
project_settings.tcl. You can create any Tcl script and apply it here to inferencing.
The script can contain any number of command file Tcl commands.
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11. Verify that the resulting scenario file name is set to top.scn.
12. Verify that the Power database field is set to top.pdb.
13. Click Next.
The Run the inferencing command screen appears.
14. Click the Run button to start the inferencing.
As the inferencing is running, you will see that an analysis report is printed
interactively into the large text field. Error and warning messages are printed here.
When the inferencing is complete, you will see the Done screen.
Figure 12 HDL Inferencing Wizard Log
Notice the summary table of error and warning messages.

15. Click the Next button to see a Summary of error and warning messages.
16. Click the Finish button to close the wizard.
This will bring you back to the main display where you will see a tree display of
your the tutorial design hierarchy. You can double-click on the modules to display
any children. By default, inferred instances are not displayed. To display them,
select Tree > Display Inferred Instances.
17. In your working directory, cd to the .ads_power_config sub-directory.
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18. Locate the HDLInferencing file (use the “vi” editor to see the contents).
This file was generated by the HDL Inferencing wizard and contains all of the
commands/options/variables settings that you just ran in the tutorial. You can use
this file to generate your own Tcl command file to run future batch analyses.
Running Vector Analysis Using the Vector Wizard

You can use the Vector Analysis wizard to perform vector analysis in the
PowerCanvas. To do so, use the following process:
1. From the PowerCanvas main menu, choose Tools > Vector Analysis.
This brings up the Define instance groups screen.
Figure 13 Vector Analysis Define Instance Groups Screen
You can use this screen to define groups of instances for vector analysis. It works
the same way as the DefineGroup command used in the command-based flow.
For the tutorial, there are five defined groups, all of which are checked to be
included in the analysis.
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2. Note the following navigation tips for this screen:

— To see the instances included in a particular group, click the + icon to the left of
the group name.
— To exclude an instance group from the current analysis without deleting it,
simply uncheck the appropriate Report box.
— If you want to create a new group, you would use the following process:
a.Click the New Group button.
b.Type in the name for the new group where it says <Group>.
c.Select an instance from the Design Hierarchy box. Click the + sign next to the
top module name to move down the hierarchy and select an instance. The
groups automatically include all hierarchical instances underneath the
instances you indicate. The design hierarchy displayed supports the top 3
levels of your design.
d.Click the icon to include the selected instance in the new (highlighted)
group If you want to edit the group name, double click the group name in the
Groups column.
3. Maintain the current group settings and click Next.
This brings up the Analysis options Screen.
Figure 14 Vector Analysis Wizard Analysis Options Screen
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In this step, you specify input/output options and analysis options for the current
run.
4. Make note of the following input settings:
— The startup script called project_settings is specified. This Tcl file sources
another global settings Tcl file. You can specify any Tcl commands or variables
you want to apply on a site-wide or project-wide basis.
— The top instance name is the hierarchical path to the top level of the design in
the VCD file. In this case, the top instance is txrx_tst.top1.
— The VCD file used in this tutorial is ./design_data/rtl_sim/activities.vcd.
5. Make note of the following output settings:
— This vector analysis will generate an FSDB output file (top_activity.fsdb).
— It will create a file called xstates.log which contains X state net names.
6. Click Next.
This brings up the Analysis type Screen.
Figure 15 Vector Analysis Wizard Analysis Type Screen
This is where you select the type of vector analysis to run—clock-based or time-
based. This tutorial runs a time-based analysis and so the clock-based is grayed-
out.
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7. Verify the following input settings:

— Time based is selected.
— Start Time: 6071580ps. This defines the simulation time step that forms the
starting point for the analysis.
— Interval size: 15160ps. This is the length of the interval in time steps.
— Number of intervals: 400
— Allowed time for X states: 10ns
8. Click Next and then Run to start the vector analysis.
9. When the analysis completes, click the Finish button to close the vector analysis
screen.
Running the Average Power Wizard

You can use the Average Power Analysis wizard to run an average power analysis.
To do so, use the following process:
1. From PowerCanvas main menu bar, select Tools > Average Power Analysis.
The Average Power Analysis wizard appears as shown below:
Figure 16 Average Power Analysis Wizard Select Design Activity Screen
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This screen indicates that this is a simulation-based analysis. You could also
perform a vectorless analysis or one that uses an existing GAF file or a SAIF file
as input. For more information on using SAIF, see Analyzing Average Power
Using a SAIF File.
2. Click the Next button.
The Set Global Activity File Creation Options screen appears as shown in Figure
17. This is the screen where you specify input files and other options that affect
the generation of a GAF file.
Figure 17 Average Power Analysis Wizard Set Global Activity Creation Options Screen

— Top Instance Name: txrx_tst.top1
— Simulation data (FSDB/VCD): ../design_data/rtl_sim/activities.vcd
— Start Time: 6071580ps
— Finish Time: 12135580ps
— Allowed time for X states: 10ns
— Output Compressed GAF box is checked, this option enables compressed GAF
as output.
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— Global Activity File (GAF): top.gaf

— File containing X state net names: xstates.log
The Power Analysis Options screen appears as shown in Figure 18.
Figure 18 Average Power Analysis Wizard Set Power Estimation Options Screen
5. Verify the following analysis option settings:

— Startup script: project_settings.tcl
— Clock definition file: clock.tcl
This file contains clock definition information supplied with the SetClockNet,
SetClockGatingStyle and SetClockBuffer commands.
Note: This average power wizard tutorial is the only one that specifies a clock
definition file. In all of the other tutorials (command line or wizard-based), the
clock definition commands are embedded in the power_aware.tcl file.
— Default output load capacitance: 39.00pF
— Wire load library: hvt
6. Verify the following Output options settings:
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— Report file name: top.Average.rpt

— Power database name: top.pdb.
7. Click the Advanced Options tab.
This tab includes advanced settings on handling negative power numbers,
separating internal load power, including register clock pin power in clock power
and skipping net capacitance estimation. None of these options are used in this
tutorial.
8. Click Next to bring up the Run screen and then click the Run button to perform the
analysis.
As the analysis runs, you will see log information on the screen.
9. When the analysis completes, you will see a Summary table at the end of the log
file window.
Figure 19 Average Power Analysis Wizard Log File and Summary Table
10. Click the Finish button.

This closes the wizard and brings you back to the main window.
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Running the Time-Based Power Wizard

You can use the Time Based Power Analysis wizard to run time-based analysis. To
do so, use the following process:
1. From the PowerCanvas main menu, choose Tools > Time Based Power Analysis.
The Time Based Analysis wizard appears as shown:
Figure 20 Time Based Power Analysis Wizard Design Activity Options Screen

— Top Instance Name: txrx_tst.top1
— Simulation data (FSDB/VCD): ../design_data/rtl_sim/activities.vcd
— Activity Start Time: 6071580ps
— Activity Finish Time: 12135580ps
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The Power Analysis Options screen appears as shown in Figure 21.
Figure 21 Time Based Power Analysis Wizard Power Analysis Options Screen
This is the screen where you specify the parameters for the time-based analysis.
4. Verify the following analysis option settings:
— Startup script: analysis_wizard.tcl
There is a significant difference between this tutorial and the average power
tutorial. The time-based tutorial uses the analysis_wizard.tcl file. This file
sources the power_aware.tcl (which contains the clock file commands) and the
project_setting.tcl file.
— Clock definition file: blank
The clock file field is in the wizard to remind you of the importance of clock
power to an accurate power analysis. The clock-related commands are no
different from other power-aware commands and, therefore, can be included in
the startup script file, as they are here.
— Default output load capacitance: 39.00
— SPEF: blank
— Wire load library: hvt
— Reference clock: top.clk
— Active edge: Positive
— Cycles per interval: 20
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The Output Options screen appears as shown in Figure 22.
Figure 22 Time Based Power Analysis Wizard Output Options Screen
6. Verify the following output option settings:

— Report file name: top.TimeBased.rpt
— Power over time output file: top.fsdb.
— Power database name: top.pdb
7. Click Next to bring up the Run screen and then click the Run button to perform the
analysis.
As the analysis runs, you will see log information on the screen.
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8. When the analysis completes, you will see a Summary table at the end of the log
file window.
Figure 23 Time Based Power Wizard Log File and Summary Table
9. Click the Finish button.

This closes the wizard and brings you back to the main window.
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Running an RTL Block-Level Power Analysis

This tutorial will show you how to run a vectorless average power analysis using
PowerArtist Tcl command files. If you haven’t already done so, copy the contents of
the entire tutorial directory to a local directory.
For this tutorial, you will need the following block directory (in addition to the top-level
/settings directory). The following table lists the contents of the /block directory.
README Provides the basic flow for running this tutorial.
ptshell.ini Initialization file specific to the block-level tutorial. This

file sets the ptshell prompt and specifies the names of
the .log and .key files for this tutorial.
power_aware.tcl Sources the technology libraries and specifies clock

information using the SetClockNet command.
project_settings.tcl Sources a global Tcl file containing site-wide tool

settings and the libraries.tcl file containing library
information. Using a single file like this to source other
files will save time and reduce keystrokes. This file is
also specified in the HDL Inferencing wizard.
Elaborate.tcl Runs the elaboration step to create a scenario file and

a power database.
CalculatePower.tcl Runs block-level average power analysis.
rxchan.vc Verilog startup file, for the rxchan block, that tells the
Verilog compiler which Verilog files must be loaded for
your design.
rxchan.vaf Vectorless activity file for the block.
run_Elaborate.tcl Run scripts to invoke from the Unix shell. As an

run_CalculatePower.tcl alternative method, you could run the tutorial by typing
the following commands at the Unix prompt:
ptshell -tcl run_Elaborate.tcl
ptshell -tcl run_CalculatePower.tcl
Basic Flow for Running the Block-Level Tutorial

The basic flow for this tutorial is as follows:
1. Type “ptshell” to start the ptshell. The prompt for this tutorial will be:
block_ptshell %
block_ptshell % source project_settings.tcl
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3. Source the Elaborate.tcl script to compile the design and create a PowerArtist
scenario file and a power database:
block_ptshell % source Elaborate.tcl
4. Source the power_aware.tcl file to read power constraints:
block_ptshell % source power_aware.tcl
5. Source the CalculatePower.tcl file to run vectorless average power analysis:
block_ptshell % source CalculatePower.tcl
6. View the results in the PowerCanvas using the following command:
PowerArtist-PT
For details on this process see, Viewing Power Analysis Results in the
PowerCanvas.
Using the Command Files

This section describes each of the .tcl files for the block-level tutorial in detail and
provides detailed steps for running these scripts.
1. Open the ptshell.ini file. This file contains shell initialization settings for the full-
chip tutorial.
set ptshKeyFile block.key

set ptshLogFile block.log
set ptshPrompt "block_ptshell %”
As you run the tutorial, PowerArtist generates a key file and log file (both with a
“block_” prefix) in your run directory. These files are useful for debugging or
recreating a previous run. For more information on these files, see Understanding
Log Files and Key Files. In addition, the ptshell prompt for this tutorial will have a
“block_” prefix. Note that this .ini file overrides the default .ini file that comes with
the tarkit. For more information on the initialization file, see Customizing Your
PowerArtist Environment Using Initialization (INI) Files.
2. Open the project_settings.tcl file. This file is shown here:
# Obtain global site-wide settings

source ../../settings/global_settings.tcl
# Specify the technology libraries

source libraries.tcl
This file obtains site-wide tool settings (from the global_setting.tcl file) and reads-
in library information (from the libraries.tcl file). The libraries.tcl file contains a
series of ReadLibrary commands. Creating this type of file saves you time and
requires fewer keystrokes.
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3. Open the power_aware.tcl file. This file contains clock gating commands, as
shown here:
##############################################
SetClockNet -name rxchan.clk -mode infer

SetClockNet -name rxchan.pci_clk -mode infer

4. Open the Elaborate.tcl file. The commands in this file compile your design and
perform inferencing.
# Elaborate the design

set design rxchan
Elaborate \
-elaborate_write_power_db true \
-elaborate_log ElaborateBatch.log \
-top $design \
-verilog_startup_file rxchan.vc
Much of this script is the same as that for the full-chip tutorial with the following
differences:
— The design variable is set to “rxchan” to represent the block.
— This block is pure Verilog and therefore has only the verilog startup file
specified—rxchan.vc.
— The resulting scenario file name will be rxchan.Batch.scn.
— The resulting power database will be named rxchan.Batch.pdb.
5. Open the CalculatePower.tcl file. The variables and commands in this file run an
average power analysis on the block-level design.
# Calculate the power of the design

set design rxchan
-average_report_file $design.Batch.rpt \
-calulate_log CalculatePowerBatch.log \
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-vectorless_input_file $design.vaf \

— The CalculatePower command is set to run an average analysis (-
analysis_type average). All of the -average* options apply to this type of
analysis.
CalculatePowerBatch.log.
rxchan.Batch.pdb. This is the file you will load into the PowerCanvas.
— The -save_clock_trees_netlist true option generates power database
schematics for the clock tree in the design. Without this setting, you will not be
able to view your clock tree in the PowerCanvas.
— The vectorless activity file will be called rxchan.vaf and will look like the
following:
# Clocks:
#
# Name Frequency (Hz) Duty Cycle (Default: 0.5)
#
SetNetStimulus -net rxchan.clk -frequency 6.6e+07
SetNetStimulus -net rxchan.pci_clk -frequency 6.6e+07
# Primary IOs:
#
#
SetNetStimulus -net {rxchan.din[0]} -frequency 1.40451e+07
SetNetStimulus -net {rxchan.din[1]} -frequency 1.40451e+07
<snip>
# Other Nets:
#
#
SetNetStimulus -net {rxchan.wr_addr[0]} -frequency 1.75861e+07
SetNetStimulus -net {rxchan.wr_addr[1]} -frequency 8.5564e+06
<snip>
# Memories:
#
# Name Avg. Frequency(Hz) of Local Nets
#
SetInstanceStimulus -instance rxchan.dpmem.m0.m1 -frequency 2.76e+07
SetInstanceStimulus -instance rxchan.dpmem.m0.m2 -frequency 2.76e+07
<snip>
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This is a portion of the .vaf file. You should be very careful setting the clocks,
primary IO’s, critical signals, such as enable signals, and your memories. The
commands you will be using most often are the SetNetStimulus (for most nets)
and SetPortStimulus or SetInstanceStimulus for memories in your design.
1. Type “ptshell” to start up the PowerArtist shell. The prompt for this tutorial will be:
block_ptshell %
As soon as the ptshell starts, you will see the following additional files in your run
directory:
— block.key—Records keystrokes run as part of this tutorial. You can re-run a
session by sourcing this file.
— block.log—Records log information (inputs and outputs) for this tutorial.
capturing the output of standard out.
3. Source the Elaborate script to compile the design and create a PowerArtist
scenario file and a power database for the elaborated design:
block_ptshell % source Elaborate.tcl
When the script is finished, you will see the following additional files in your run
directory:
— ElaborateBatch.log—This file captures log information for the Elaborate
command. If you get any unexpected results, you can look through this file to
make sure that the settings listed are those that you expected to be set.
— rxchan.Batch.scn—The scenario file for the block-level design. The scenario
file is a binary representation of your design.
— rxchan.Batch.pdb—At this point in the flow, this PDB file contains the design
hierarchy. You can use the PowerCanvas to explore the design hierarchy at this
point. The power analysis run will add to this file.
4. Exit ptshell:
block_ptshell % exit
5. View and analyze the elaborated block-level design in the PowerCanvas.
a. Invoke the PowerCanvas using either of the following commands:
% PowerArtist-PT
or
% PowerArtist
b. From PowerCanvas main menu, select File > Load Design.
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From the file selection dialog, select the correct .pdb file (for example,
rxchan.Batch.pdb) and click OK.The hierarchy browser (at the top level) and
the collapsed schematic of the elaborated design appears.
Figure 24 Display of rxchan.Batch.pdb File (Elaborated Design)
c. Click the rxchan(rxchan) instance in the left-hand pane of the hierarchy browser.
d. Click the + symbols next to the nested hierarchical instances to display their
instances in the right-hand pane called the power table.
6. When you are finished examining the elaborated design, exit the PowerCanvas
(select File > Exit).
7. Type “ptshell” to restart the ptshell.
You must reload this file whenever you exit and restart the ptshell in this tutorial
flow.
9. Source the power_aware.tcl file to read power constraints for this tutorial:
block_ptshell % source power_aware.tcl
10. Source the CalculatePower.tcl file to run the block-level power analysis:
block_ptshell % source CalculatePower.tcl
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When the script is finished, you will see the following additional files in your run
directory:
— CalculatePowerBatch.log—A log file for the average power analysis run. It
includes all of the command option specifications, warnings and notes
generated by the analysis engine, CPU usage, etc. for the latest run.
— rxchan.Batch.pdb—A complete power database that includes the power
analysis results, in this case, for average power analysis.
— rxchan.Batch.rpt—The power report in text format.
12. Review the power analysis results in the PowerCanvas.
Viewing the Block-Level Power Results in the PowerCanvas

Once you have run any power analysis (average or time-based) you can view those
results in the PowerCanvas.
1. Bring up the PowerCanvas and load the power database named
rxchan.Batch.pdb which was created by the CalculatePower.tcl script.
% PowerArtist -pdb rxchan.Batch.pdb
The hierarchy tree now shows the design colored for power. The colorizing follows
a thermal spectrum. The more power consumed, the hotter the color (red
indicating the most power consumed). The less power consumed, the cooler the
color (blue indicating the least power consumed).
2. You can use the same steps outlined in Viewing Power Analysis Results in the
PowerCanvas section to review the block-level power results. Since this block
design is a small design, you can also review results in the text-based power
report, rxchan.Batch.rpt.
Running the Block-Level Tutorial Using the Power Canvas

Wizards
To run the block tutorial using the PowerCanvas wizards, you would use the same
process described in the Running Full-Chip Analysis Using the PowerCanvas
Wizards. You simply need to start from the /block directory. The wizard fields will be
pre-populated with the block-level data and input files.
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Running Power Analysis with Clock Gating
Running Power Analysis with Clock Gating

To achieve accurate full-chip RTL power analysis, the clock tree and clock gating that
will be added at the gate level must be taken into account. To provide this,
PowerArtist can infer a clock tree and consider the effect of clock gating. This helps
in early and accurate power estimates necessary for decisions that directly impact
chip cost—packaging, routing layers, heat sink etc. Clock gating is an important
power saving technique as clocks can consume 30-60% of the total chip power
consumption.
To access the clock gating tutorial files, change directories to the clock_gating
directory. The Tcl command files in this directory are similar to those in the full_chip
directory. The difference is in the content of the power_aware.tcl file. You can run the
clock gating analysis using either a command file flow or the PowerCanvas wizards.
The clock gating commands are identical to those used in the full-chip design.

Use the following process to run power analysis with clock gating:
1. Change directories to the clock_gating directory.
clock_gating_ptshell %
clock_gating_ptshell % source project_settings.tcl
4. Source the Elaborate.tcl command to compile the design to create a scenario file:
clock_gating_ptshell % source Elaborate.tcl
When the script is finished, you will see the scenario file (.scn), the power
database file (.pdb) and log files.
clock_gating_ptshell % source power_aware.tcl
6. Source the CalculateTimeBasedPower.tcl script to run time-based power analysis:
clock_gating_ptshell % source CalculateTimeBasedPower.tcl
When the script is finished, you will see several new files including an updated
power database (.pdb), the time-based log file and the power report file (.rpt).
Using the PowerCanvas Wizards

To run the clock gating tutorial using the PowerCanvas wizards, you would run the
same process as that described in the Running Full-Chip Analysis Using the
PowerCanvas Wizards. You simply need to start from the /clock_gating directory. The
wizard fields will be pre-populated with the correct data and analysis specifications.
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Running a Power Analysis with a Mixed-Vt Cell Library

PowerArtist allows you to estimate and explore leakage power savings with mixed-Vt
cells. A mixed-Vt approach may be optimal since low-Vt cells offer faster timing, but
have higher leakage while high-Vt cells have moderate timing with a lower leakage.
PowerArtist currently supports a percentage-based mixed-Vt analysis.
To access the mixed-vt tutorial files, change directories to the mixed_vt directory. The
Tcl command files in this directory are similar to those in the full_chip directory. The
difference is in the content of the power_aware.tcl file. You can run power analysis
using a mixed-Vt library using either a command file flow or the PowerCanvas
wizards.

Use the following process to run power analysis with a mixed-vt cell library:
1. Change directories to the mixed_vt directory and open the power_aware.tcl file.
An excerpt is shown here:
##############################################
# Mixed-VT Library Commands
SetLibrary -instance top -library {hvt RETENTION_EXAMPLE_LIB Memories}

SetLibrary -instance {top.core1.u1 top.core1.a1 top.core1.s1} -library {hvt lvt}
SetVoltageThreshold -group LOW_VT -pattern {*L}

SetVoltageThreshold -group HIGH_VT -pattern {*H}
##############################################
### Mixed Vt specific settings showing always on Virtual Supplies
SetVT -mode percentage -instance {top.core1.u1 top.core1.a1 top.core1.s1 } \

-vt_group {LOW_VT:30 HIGH_VT:70}
CreateVirtualSupply -supply Memories.vdd -virtual_supply MEMVDD -on 1

CreateVirtualSupply -supply hvt.vdd -virtual_supply HVTVDD -on 1
CreateVirtualSupply -supply lvt.vdd -virtual_supply LVTVDD -on 1
CreateVirtualSupply -supply VDDNW -virtual_supply RX_VDDNWS -on 1

CreateVirtualSupply -supply VDD -virtual_supply RX_VDDNWS -on 1
CreateVirtualSupply -supply VRET -virtual_supply RX_VRET -on 1
<snip>
CreateDomain -instance top.core1.r1 -virtual_supply {MEMVDD HVTVDD LVTVDD \

RX_VDDNWS RX_VRET}
CreateDomain -instance top.core1.t1 -virtual_supply {MEMVDD HVTVDD LVTVDD \
TX_VDDNWS TX_VRET}
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MapRetentionCell -instance {top.core1.r1} -attribute CK_LOW

MapRetentionCell -instance {top.core1.t1} -attribute CK_LOW -tag NoMap \
-notag true
##############################################

The commands shown here are required to incorporate a mixed-Vt library into a
design. It contains the SetLibrary and SetVt commands as well as several
iterations of the CreateVirtualSupply command to establish voltage domains.
These will be later leveraged as part of the power_gating tutorial. It also contains
the SetVoltageThreshold, defined here for two groups—LOW_VT and HIGH_VT.
For more explanation of the commands in this file see Sample Mixed-Vt Flow and
Tcl File.
mixed_vt_ptshell %
mixed_vt_ptshell % source project_settings.tcl
4. Source the Elaborate.tcl file to compile the design and create a PowerArtist
scenario file and a power database:
mixed_vt_ptshell % source Elaborate.tcl
mixed_vt_ptshell % source power_aware.tcl
6. Source the CalculatePower.tcl file to run average power analysis:
mixed_vt_ptshell % source CalculatePower.tcl
power database (.pdb), the CalculatePower.log file and the power report file (.rpt).
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7. View the results of this analysis by reviewing the top.Batch.rpt file. Locate the
“Mixed-VT cells distribution” section as shown below:
7. Mixed-VT Cells Distribution

==============================
Hier-Instance VT Group Specified Number of Cells

Name Name Percentage Selected
------------- -------- ---------- ---------------
top.core1.u1
HIGH_VT 70 145
LOW_VT 30 62
---------------
Total 207
top.core1.a1
HIGH_VT 70 58
LOW_VT 30 25
---------------
Total 83
top.core1.s1
HIGH_VT 70 579
LOW_VT 30 248
---------------
Total 827
For every hierarchical instance specified using the SetVT command (in the
power_aware.tcl file) this report includes the total number of default cells selected
for each of the specified VT groups. For example, 145 default cells selected for
instance top.core1.u1 were HIGH_VT cells while 62 were LOW_VT cells. For
additional information about this section of the report, see Understanding Mixed-Vt
Analysis Results in the Report File.

To run the mixed-vt tutorial using the PowerCanvas wizards, you would do exactly
the same process as that described in the Running the Average Power Wizard. The
only difference is the content of the power_aware.tcl file in that it contains command
required for running a mixed-vt analysis. You simply need to start from the /mixed_vt
directory. The wizard fields will be pre-populated with the correct data and analysis
specifications.
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Running Power Analysis with Voltage Islands

Voltage island techniques can be used to reduce the power on blocks that are not
timing critical. PowerArtist provides analysis algorithms that predict power savings
that could be achieved by assigning lower voltages for one or more blocks.
To access the required tutorial files, change directories to the voltage_islands
directory. The difference is in the content of the power_aware.tcl file. You can run the
power analysis using voltage islands using either a command file flow or the
PowerCanvas wizards.

Use the following process to run power analysis with voltage_islands:
1. Change directories to the voltage_islands directory and open the power_aware.tcl
file. An excerpt is shown here:
##############################################
SetLibrary -instance top.core1 -library {hvt Memories}
##############################################
# Voltage Domain Commands
CreateVirtualSupply -supply hvt.vdd -virtual_supply VDDRX -voltage 0.9

CreateVirtualSupply -supply hvt.vdd -virtual_supply VDDTX -voltage 0.8
CreateDomain -instance top.core1.r1 -virtual_supply VDDRX

CreateDomain -instance top.core1.t1 -virtual_supply VDDTX
##############################################

##############################################
# Instances to monitor in the design
MonitorInstances -name top.core1.t1 -all 1

MonitorInstances -name top.core1.r1 -all 1
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Notice the two CreateVirtualSupply and the CreateDomain command

specifications. These commands together create two domains (one for receiver
and one for the transmitter) that are given different voltage values.
voltage_islands_ptshell %
voltage_islands_ptshell % source project_settings.tcl
4. Source the Elaborate.tcl command to compile the design and create a PowerArtist
scenario file:
voltage_islands_ptshell % source Elaborate.tcl
voltage_islands_ptshell % source power_aware.tcl
6. Source the CalculatePower.tcl file to run average power analysis:
voltage_islands_ptshell % source CalculatePower.tcl
power database (.pdb), the log file (.log) and the power report file (.rpt).
7. You can now view the results of the analysis with voltage islands in the “Power
Domain Summary” section of the top.Batch.rpt report file in this directory.

To run the mixed-vt tutorial using the PowerCanvas wizards, you would do exactly
the same process as that described in the Running Full-Chip Analysis Using the
PowerCanvas Wizards. The only difference is the content of the power_aware.tcl file
in that it contains command required for running a power analysis with voltage
islands. You simply need to start from the /voltage_islands directory. The wizard
fields will be pre-populated with the correct data and analysis specifications.
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Running a Power Analysis with Power Gating

Power gating is a technique that saves leakage power by turning off supplies to
blocks that are inactive. You can use PowerArtist to accurately predict power savings
due to the implementation of power gating.
To access the power gating tutorial files, change directories to the power_gating
directory. The difference is in the content of the power_aware.tcl file. You can run
power analysis with power gating using either a command file flow or the
PowerCanvas wizards.

Use the following process to run power analysis with power gating:
1. Change directories to the power_gating directory and open the power_aware.tcl
file. This is the file that specifies the power gating commands. An excerpt is shown
here:.

##############################################
# Power Gating Commands
# Not partioning the design based on voltage islands.
CreateVirtualSupply -supply vdd -virtual_supply VDDRX -on top.rx_rq

CreateVirtualSupply -supply vdd -virtual_supply VDDTX -on top.tx_rq
CreateVirtualSupply -supply VDDNW -virtual_supply RX_VDDNWS -on top.rx_rq

CreateVirtualSupply -supply VDD -virtual_supply RX_VDDNWS -on top.rx_rq
CreateVirtualSupply -supply VRET -virtual_supply RX_VRET -on (!top.rx_rq)
CreateVirtualSupply -supply VDDNW -virtual_supply TX_VDDNWS -on top.tx_rq

CreateVirtualSupply -supply VDD -virtual_supply TX_VDDNWS -on top.tx_rq
CreateVirtualSupply -supply VRET -virtual_supply TX_VRET -on (!top.tx_rq)
CreateDomain -instance top.core1.r1 -virtual_supply {VDDRX RX_VDDNWS RX_VRET}

CreateDomain -instance top.core1.t1 -virtual_supply {VDDTX TX_VDDNWS TX_VRET}
MapRetentionCell -instance {top.core1.t1} -attribute CK_LOW -tag NoMap -notag true

<snip>
In addition to clock definitions, this power_aware.tcl file also defines power

domains for the power gating analysis using the CreateVirtualSupply and
CreateDomain commands. These commands are required implement power
gating in the design. Note that the SetLibrary here specifies a special retention cell
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library called RETENTION_EXAMPLE_LIB to ensure that registers are available

for the power domains.
power_gating_ptshell %
power_gating_ptshell % source project_settings.tcl
scenario file:
power_gating_ptshell % source Elaborate.tcl
power_gating_ptshell % source power_aware.tcl
6. Source the CalculateTimeBasedPower.tcl file to run time-based power analysis:
power_gating_ptshell % source CalculateTimeBasedPower.tcl
power database (.pdb), the time-based log file and the power report file (.rpt).
8. Review and analyze the results of the time-based power analysis in the
PowerCanvas.
9. You can see the impact of power gating by viewing the waveform. To do so,
perform the following steps:
a. Choose Tools > Waveform Viewer to open the graph in the Apache Waveform
Viewer.
b. From the Files list, select either the top.TimeBasedBatch.fsdb file (from the
command-line run) or the top.fsdb file (from the GUI run) and click the OK.
c. In the Waveform Name field, type an * to find all waveforms and click the
Search button.
d. Select only the receive (the pt0|top.core1.r1) and transmit (pt0|top.core1.t1)
waveform names, select “Place waveforms in: One plot” and click the Add
waveform to plot area button.
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The graph shows that the power of the receive channel is always zero in
transmit mode and vice-versa. PowerArtist has essentially cut-off leakage and
dynamic power for channels that are inactive in the appropriate modes.
Figure 25 Power Waveform of Receive and Transmit Blocks

To run the time-based power analysis with power gating using the PowerCanvas
wizards, you would run the same process as that described in the Running the Time-
Based Power Wizard. The only difference is the content of the power_aware.tcl file in
that it contains power gating commands. You simply need to start from the /
power_gating directory. The wizard fields will be pre-populated with the correct data
and analysis specifications.
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Running the Full-Chip Gate-Level Power Analysis Tutorial

You can run gate-level analysis on a fully synthesized netlist/placed and routed
design. This tutorial shows you how to perform different power analyses using a
sample gate-level design. This design is a synthesized version of the RTL design
you worked with in earlier sections of the tutorial; therefore, most of the inputs are
the same. This section highlights only those inputs that are different for this tutorial.
You can run either an average or a time-based power analysis to perform gate-level
power verification (with or without back-annotated parasitics). This time-based
analysis can be done for instantaneous power or current for different time steps.

Use the following process to run the gate-level tutorial:
1. Change directories to the full_chip_gate directory.
The Elaborate.tcl file is exactly the same as that used in the RTL full-chip tutorial.
Additionally, the VectorAnalysis.tcl, CalculateAveragePower.tcl and
CalculateTimeBasedPower.tcl files are nearly identical to those used in the full-
chip RTL tutorial. The only difference is that they specify a gate-level VCD that
comes from the design_data/gate_sim directory instead of the design_data/rtl_sim
directory.
full_chip_gate_ptshell %
full_chip_gate_ptshell % source project_settings.tcl
scenario file:
full_chip_gate_ptshell % source Elaborate.tcl
5. Source the GenerateActivityWaveforms.tcl command to perform vector analysis
on the gate-level design:
full_chip_gate_ptshell % source GenerateActivityWaveforms.tcl
Vector Analysis shows how the activity varies over time for selected blocks in your
design. When the script is finished, you will see
GenerateActivityWaveformBatch.log and the top_activity.fsdb in your directory.
You can load the FSDB file into the Apache Waveform View to see the resulting
waveforms.
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full_chip_gate_ptshell % source power_aware.tcl
7. Run either an average or time-based power analysis using the corresponding Tcl
script.
9. Review the results in the PowerCanvas or the text-based power report.

To run the gate-level tutorial using the PowerCanvas wizards, you would use the
same process as that described in the Running Full-Chip Analysis Using the
PowerCanvas Wizards. You simply need to start from the /full_chip_gate directory.
The wizard fields will be pre-populated with the correct data and analysis
specifications.
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Understanding Power Analysis Results in the Text-Based Power Report

In addition to reviewing the power analysis results in the PowerCanvas, you can also
review the results using the text-based power report (.rpt) file.
Both the average and time-based reports are divided into sections that each provide
valuable information about the power analysis of your design. At the top of the report
are the date and program version, along with values for numerous arguments and
parameters. This section describes a sample average power report from the full-chip
analysis tutorial.
The first headed section is an abstract of total power dissipation, divided into
components of internal power, pad power, clock power and inferred buffer power.
1. Total power consumption

==========================
Power(Watts)
Power contribution Static Dynamic Total
----- ------------ ------ ------- -----
Internal register power 4.36uW 705uW 710uW
Internal latch power 0W 0W 0W
Internal memory power 3.81mW 15.8mW 19.7mW
Other internal power 3.71uW 161uW 165uW
Total internal power 3.81mW 16.7mW 20.5mW
IP Core power 0W 0W 0W
Pad power 44.2mW 751mW 795mW
Clock power 144nW 440uW 440uW
Inferred Buffer power 139nW 4.9uW 5.04uW
Total power 48mW 768mW 816mW
Each of these categories is broken down into greater detail in the sections that
follow.
Internal Power Consumption

This section of the power report shows the details of the internal power consumption.
2. Internal power consumption

=============================
Note: (G) after either a register or 2-1 mux means this instance
is affected by clock gating.
Note: (F) after model name means power of this instance has been
forced by using SetPower command.
Note: (O) after model name means this instance has been
partially/fully optimized.
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Power(Watts)
Component Model Static Dynamic Total
--------- ----- ------ ------- -----
top user 3.81mW 16.7mW 20.5mW
#1942 connect 0W 0W 0W
#1943 connect 0W 0W 0W
#1944 auto 0W 0W 0W
core1 user 3.81mW 16.7mW 20.5mW
<snip>
Total internal power 3.81mW 16.7mW 20.5mW
For each module, this report provides several pieces of information:

 The hierarchical name of the HDL component.
 The Apache power model associated with the HDL object.
 The power consumed by that object. This is the key element provided by
PowerArtist.
Using the frequency values computed for the ports and the type of power model
associated with the object, PowerArtist can accurately estimate from the RTL the
power consumed by the object.
Among other options, PowerArtist reports let you separate static and dynamic power
estimates. The static power is generally independent of the frequency of the object,
although for some modules, such as memories, the static power could depend on the
value of control signals, such as chip select. For example, a ROM could consume a
certain amount of static power when active, and a smaller amount of power in
standby mode. PowerArtist computes the amount of time the ROM is in each mode,
and determines the static power based on these modes.
Logic Optimization
PowerArtist performs straightforward logic optimization to help increase accuracy.
This is becoming more important from a power analysis accuracy point of view
because more RTL code is either being generated from ESL synthesis tools or is
being designed for re-use. Both flows can result in unused registers in the design,
which can then result in unused combinational logic. The analysis tools locate
unused register bits and then trace logic to eliminate unused combinational logic.
They also optimize logic that generates constant outputs.
Optimization depends on analyzing the inferencing of a module at every instantiation;
therefore, optimization needs to happen when the power analyzers run. PowerArtist
may optimize registers only in certain instantiations—not all instantiations. In the
report, instances that have either been fully or partially optimized are marked with an
(O) after the model name. This is similar to how gated logic is marked with a (G) and
logic that has its power set by the SetPower command is marked with an (F).
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Pad Power Consumption

This section of the report shows the power consumed by each pad instantiated in
your design.
4. Pad power consumption

========================
Power(Watts)
Component Pad type Cap(F) Static Dynamic Total
--------- --- ---- ------ ------ ------- -----
top.sclk1 SEQPIC 281fF 154uW 866uW 1.02mW
top.sclk2 SEQPIC 59.4fF 154uW 874uW 1.03mW
top.sclk3 SEQPIC 22.1fF 154uW 0W 154uW
top.udi0 SEQPIC 132fF 154uW 0W 154uW
<snip>
Total pad power 44.2mW 751mW 795mW
For each I/O pad, several pieces of information are shown.

 The hierarchical name of the pad in the HDL design.
 The name of the pad model in the chosen technology for that pad.
 The power consumed by that pad.
 The load capacitance attached to the output of the pad
Power consumed by pads is often a significant fraction of total power and
PowerArtist uses specific models for each pad in a technology to accurately estimate
the power. Power is estimated using the PowerArtist-computed frequency value for
the output net, parameters of the pad, and a user-provided value for the off-chip
capacitance driven by the net if it is an output.
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Clock Power Consumption

This section of the text power report shows the power consumed by each clock net.
Details about clock gating prediction and clock tree inferencing are included in this
clock power report section
5. Clock power consumption

========================
top.clk Instantiated 5.5056nW 1.276mW 1.276mW
Net properties:
Area : 1.35e-10
Senses : 1
Frequency : 65.303MHz
Transition time : 0s
Fanout capacitance : wire 1.7675pF*;pins 45.1fF
Wire power : 1.257mW
Pin power : 32.073uW
Wireload models used:

not used, capacitance back annotated
Traced instances:
Library Clock Driven By Driven Net Driven Power (Watts) Traced
Model Level Net Number Numbers Loads Static Dynamic Total Instance
----- ----- ---------- ------- ----- ------ ------- ----- --------
BUFX20 1 0 38 1 146pW 69.1uW 69.1uW top.core1.I1
BUFX20 2 38 37 2 146pW 68.9uW 68.9uW top.core1.L2_I1
INVX12 3 37 36 1 146pW 160uW 160uW top.core1.L3_I1
INVX12 4 36 35 1 146pW 155uW 155uW
<snip>
Total power 5.54nW 232mW 2.32mW
Traced nets:
Net Frequency Transition Wire Pin Net Wire Net Pin Net
Number Time Cap Cap Power (W) Power (W)
------ --------- ---- --- --- --------- --------- ---
1 15.831MHz 0s 2.61fF* 0F 481nW 0W top.1
2 65.963MHz 0s 156fF* 70.03fF 52.2uW 23.4uW top.2
3 65.963MHz 0s 173fF* 55.98fF 57.9uW 18uW top.3
4 65.963MHz 0s 221fF* 31.63fF 74.1uW 10.6uW top.4
<snip>
Total 7.41pF 2.61pF 2.47mW 873uW
<snip>
For each clock net, the following information is provided:

 The hierarchical net name, the type of analysis, and the total power for the clock
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tree. The analysis type will be either Instantiated, which means that it was traced,
or Inferred meaning clock inferencing was done.
 Area occupied by the net.
 Clock senses.
 Frequency of the clock net.
 Transition Time.
 Fanout capacitance of the clock net (divided into contributions from wire and pin
capacitances).
 Power consumed as the net toggles (divided as wire and pin components).
 The wire load model applied to the net (the first entry is the net name, the second
entry is the wire load model applied to that net). If you assigned wire load models
to sub-nets of the clock tree, they would be listed here as well.
 Descriptions of the instances that were traced as part of the clock tree, which
includes the following:
— Library Model: the Liberty model name.
— Clock Level: the depth in the clock tree for this particular instance
— Driven Net Numbers: the net numbers from the “Traced nets” section that this
instance drives. Most instances will drive one net, but some instances may
drive multiple nets. The power portion is split into static/dynamic/total just like in
the Internal Power Consumption portion of this report.
— Driven by Net Number: the net number that was traced through to get to this
particular instance. Note that the “Driven by” net may have Index 0. This means
that this is the clock net you are either inferring or tracing.
— Driven Loads: the number of loads this particular instance is driving.
— Traced Instance: the full hierarchical instance name (listed last to
accommodate a long name).
Note that if the instance is a leaf buffer that is driving only clock pins, it is marked
with an (L) in the Clock Level column.
 Descriptions of each clock net in the design. This section lists every net in the
clock tree and contains the following fields:
— Net Number. this number allows you to figure out what instance drives this net
— Frequency: the toggling frequency of this net.
— Transition Time: the slew time either back-annotated or calculated by the slew
calculator, the back annotated slew values are annotated with an asterisk. The
power portion is split into Pin Power and Wire Power.
— Wire Capacitance: capacitance determine from a wire load model or a back-
annotated value. In the case of a back-annotated value, the number is
annotated with an asterisk to indicate that it was a user-specified value.
— Pin Cap: the total capacitance of the pins driven by this net.
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— Net Wire Power and Net Pin Power: the total power separated into pin and wire
amounts
— Net: the full hierarchical instance name for this net.
Controlling the Clock Tracing Order

The order in which clocks are traced does not impact power calculations, but it does
impact how the power is associated with a particular clock. The contents of the clock
power section in your power analysis reports depends completely on the order in
which clocks are traced. The order in which you specify your clock nets in the clock
file and if you specify the -frequency option to the SetClockNet command completely
control the order in which nets are traced in a predictable fashion.
Clocks specified with frequencies in the clock file are traced first during power
analysis, starting from the highest frequency clock down to the lowest frequency
clock. If two nets have equal frequencies, the net listed first in the clock file is traced
first. Clocks with no specified frequency are traced last, in the order they are listed in
the clock file.
Additional Information on Clock Gating

If you performed clock gating, as was done in the Running Power Analysis with
Clock Gating section, the following additional information is included in the clock
power report.
 All output nets of clock-gated registers are listed on their own line.
 For each clock-gating cell (ICGC), the cell type and enable signal and duty
percentage are listed.
 For each clock-gating cell (ICGC), the static, dynamic, and total power usage is
provided.
 A separate section called Clock Gating Summary at the end of the Clock power
consumption section of the report. This section reports information on instantiated
ICGCs. See the following sample:
Clock Gating Summary:

---------------------
Clock net: top.clk
Number of inferred clock gating cells: 10
Number of registers gated by inferred clock gating cells: 376
Number of instantiated clock gating cells: 0
Number of registers gated by instantiated clock gating cells: 0
Total number of gated registers: 376
Total number of ungated registers: 77
The counts are the total number of register bits—not the number of register
instances (where an entire register bank is one instance). The sum of “Number of
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gated registers” and “Number of registers gated by instantiated clock gating cells”
may not be equal to the “Total number of gated registers”. This is because a
register may have a block-level instantiated ICGC and have a local inferred ICGC
as well. The “Total number of gated registers” section includes registers that are
either gated by inferred or instantiated ICGCs or both. The “Total number of
ungated registers” section includes those registers that are not gated by either
inferred or instantiated ICGCs.
For more information on clock gating, see Setting up Clock Gating for Power
Analysis.
Clock Domain Power Consumption

If you specified the -trace_domain option to the SetClockNet command, you will see
two additions to the report. First, the “Total power consumption” section will have an
additional line such as the following example:
Clock domain (excluding clock tree) power 280uW 40.8mW 41.1mW
Also, there will be a new section called “Clock domain power consumption”. This
section records the power of all of the elements traced in the clock domain. This
includes the clock distribution network leading up to the clock inputs of flops as well
as the elements traced through the Q outputs of the flops. The format of this report is
identical to the existing “Clock Power Consumption” section. There is a new sub-
section at the top of the domain power section that provides an Instance Summary
that has a format similar to the “Total power consumption” section.
3. Clock domain power consumption

=================================
1. Clock Net: top.clk
Instance Summary:
================
Power(Watts)
Static Dynamic Total
------ ------- -----
Register power 0W 920.12uW 920.12uW
Latch power 0W 0W 0W
Memory power 0W 5.7726mW 5.7726mW
IP core power 0W 0W 0W
Pad power 0W 5.9882mW 5.9882mW
Clock power 0W 6.9694mW 6.9694mW
Other power 0W 223.31uW 223.31uW
Internal load power 0W 6.4999mW 6.4999mW
Total power 0W 26.374mW 26.374mW
Apache Design, Inc.

Traced instances:
Library Clock Driven By Driven Net Driven Power (Watts) Traced
Model Level Net Number Numbers Loads Static Dynamic Total Instance
----- ----- ---------- ------- ----- ------ ------- ----- --------
connect 21 717 716 0 0W 0W 0W top.core1.r1.dp
connect 22 716 715 0 0W 0W 0W top.core1.r1.dp
...
In the “Traced instances” section of the report, the sequential elements will all be at
clock level 1. The clock distribution network will still be traced as part of the clock
power section of the report.
Inferred Buffer Tree Power

This section describes the buffer inferencing that happens when a net exceeds the
number of fanouts specified by the SetHighFanoutNet command. Its organization is
identical to that of the equivalent clock buffer section. For each inferred buffer tree,
the following information is supplied:
 Name of the net with a fanout that exceeds the limit specified by the
SetHighFanoutNet command.
 The hierarchical instance being driven by the net.
 The frequency of the net toggles.
 The number of loads.
 A description of the fanout tree. This includes the cells that were used to build up
the buffer tree, the library the cells came from, the counts of the cells, fanout
limitations of the cells and the amount of power consumed by the cells. The
capacitance seen in the buffer tree is also supplied because that is what controls
the number of cells inferred.
6. Inferred buffer tree power

=============================
Total dynamic power = 4.9uW
Total static power = 139nW
Inferred Buffer Tree:

Net name : top.core1.t1.f1.WR_PTR[8]
Driver instance: top.core1.t1.f1.WRCNTR.#1180
Frequency : 82.5KHz
Number of Loads: 74
Leaf Driver :
Cell : SEQCLKBUFX8MTH
Library : hvt
Count : 2
Cell maximum fanout : 60
Buffer power: static 8.26nW; dynamic 86.3nW
Fanout capacitance: wire 740fF; pins 97.2fF
Apache Design, Inc.

Total capacitance : wire 740fF; pins 97.2fF

<snip>
Area
This section of the text power report shows the width and height, and number of
registers and gates for each component. This report is generated if you use the “-
average_report_options a” option to CalculatePower.
7. Area
=======
Component Width Height Regs Gates

--------- ----- ------ ---- -----
top 1.98K 1.98K 694 3070942
core1 1.98K 1.98K 694 3070942
a1 10.9 10.9 0 93
<snip>
Total Counts 694 3070908
Total Net Routing Area 346K
Total Area (Gates+Routing) 4.28M
Net Frequencies
This section of the text power report shows the type, glitch, and frequency for each
net. This report is generated if you use the “-average_report_options g” option to
CalculatePower.
Net Type Glitch Frequency

--- ---- ------ ---------
top.Pclk PI 0.00% 63.2MHz
top.Pnreset PI 0.00% 0Hz
top.Pcs PI 0.00% 0Hz
top.Prd PI 0.00% 0Hz
Power Consumption by Model/Gate Type

This section provides summary information for every type of instance in the design.
This report is generated if you use the -vertical_report_instances option to
CalculatePower. For inferred elements, the cell count equals the number of separate
instances in the design and not the total bit width for bundled elements like registers
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Summary
and muxes. For vendor_gates, the cell count is the number of gates of that type in
the design.
Power(Watts)
Component Model Cell Static Dynamic Total
Count
--------- ----- ------ ------- ------- -----
top 2083 305nW 396mW 396mW
Register Power 523 76.3nW 10.1mW 10.1mW
Latch Power 0 0W 0W 0W
Memory Power 20 0W 369mW 369mW
Other Power 1540 229nW 16.2mW 16.2mW
AND2X1 18 2.62nW 377nW 379nW

AND3X1 6 875pW 30.7nW 31.6nW
AND4X1 66 9.62nW 1.5uW 1.51uW
Summary
You can use PowerArtist power analysis at various stages of the design
implementation:
 While designing your RTL
Use PowerArtist concurrently with RTL simulation to analyze power and identify
hot spots. If the design consists of mixed RTL and gate-level models, use
PowerArtist and apply simulation data as it becomes available for individual
modules or subsystems to improve the analysis accuracy for those blocks.
 After synthesizing
Once you have used PowerArtist at the RT-level to decide among design
alternatives, you will begin to synthesize portions of your design. Since logic
synthesis can substantially restructure control logic to minimize area or meet
timing constraints, you might want to repeat power analysis using post-synthesis
information. This can be done on a mixed RTL and gate-level design or on a fully
synthesized gate-level netlist.
 After place and route
Use PowerArtist with back-annotated capacitance values in a gate-level simulation
to use parasitic information from layout in the analysis.
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Note: The following material is not available in this version
of the Power Artist User Guide:
o Chapter 4 - PowerArtist Tutorial Part II : Power Reduction
o Chapter 12 - Examining and Implementing Power Reduction

Opportunities
135
Chapter 5
Using the PowerCanvas 5
Introduction
This chapter provides an overview of how to use the PowerArtist graphical user
interface, called the PowerCanvas. It describes each of the menu items available
and how to use them. It does not take you through a process step-by-step. To
become familiar with how you should use the PowerCanvas, run either the
PowerArtist Tutorial Part 1: Power Analysis or the PowerArtist Tutorial Part II: Power
Reduction. You should refer to this chapter if there is a particular aspect of the
PowerCanvas that is not covered in the tutorial or you just want to know how one
particular menu item works.
For details on starting the PowerCanvas, see Using the PowerArtist Shell and
Running an RTL Full-Chip Power Analysis Using Command Files.
Chapter Organization
The following topics are covered in this chapter:
 Overview of the PowerCanvas Initial View
 Using the Hierarchy Browser
 Using the Schematic Display
 Using the Simple Reduction Dialog
 Using the Linter Reductions Dialog
 Using the Prism Dialog
 Using the Waveform Viewer
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CHAPTER 5 — Using the PowerCanvas PowerArtist™ User Guide 136
Overview of the PowerCanvas Initial View

When you first bring up the PowerCanvas, as described in PowerArtist Tutorial Part
1: Power Analysis, you will need to load your design by selecting File > Load Design
and selecting your .pdb file. Alternately, you could use the “-pdb file_name” option to
the PowerArtist command to automatically load the specified power database. Note
that if you are loading a large design that may take some time, PowerArtist displays
an hour glass busy indicator. When your design is loaded, the display will look like
the following figure:
Hierarchy
Information
Display
Schematic of
Fully Collapsed
Design
Power Table
Figure 53 Initial Power Canvas Display (Tutorial Design)
The Power Canvas has two main sections—the hierarchy browser and the
schematic display. You can use the Design menu items to change the look of the
hierarchy browser and the schematic menu to do the same for the schematic display.
For more information on the using the hierarchy browser, see Using the Hierarchy
Browser. For details on using the schematic display, see Using the Schematic
Display.
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The PowerCanvas Menus

A snapshot of the menus available with the PowerArtist GUI—PowerCanvas—is
shown in the following figure. Note that some menus are enabled only when certain
conditions exist (for example, the Design and Schematic menus are available only if
an inferenced design is loaded).
Figure 54 PowerCanvas Menus
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Using the Edit Menu

The Edit menu has just one item, Find, which brings up the Find dialog. For detailed
information on this dialog, see Using the Find Dialog.
Using the Tools Menu

The Tools menu is divided into three sections. The first section includes items related
to analysis: HDL Inferencing, Vector Analysis, Average Power Analysis, and Time-
Based Power Analysis. For details on using these features, see PowerArtist Tutorial
Part 1: Power Analysis. The second section applies to reduction and includes Power
Reduction Analysis and Rewrite RTL. Details on using these features see
PowerArtist Tutorial Part II: Power Reduction. The last section includes the
Waveform Viewer and Command window. For information on how to use the
waveform viewer, see Using the Waveform Viewer.
Using the View Menu

The View menu has seven menu items, five of which control the display of paned
windows: Schematic Legend, Hierarchy, Information and Schematic.
The last three items are used for viewing and manipulating power reduction analysis
results. They appear only after a power reduction analysis is complete and the power
database is loaded. These items are: Simple Power Reductions, Linter Power
Reductions and Advanced Power Reductions. For details on using these dialogs,
see Examining Simple Power Reductions, Examining Power Linter Reduction
Results and Examining Advanced Power Reduction Results in the reduction tutorial.
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Using the Help Menu

The Help menu provides links to release notes, documentation, shortcut bindings
and version information. If you select Help > Shortcut Bindings, PowerArtist
displays the following menu, which describes various hot keys and their operations.
Figure 55 Schematic Viewer Shortcuts
Keyboard/Mouse Key
Menu Item or Key Combination Function
Right Arrow Right Arrow key Pans to the right by half the window size
Left Arrow Left Arrow key Pans to the left by half the window size
Up Arrow Up Arrow key Pans up by half the window size
Down Arrow Down Arrow key Pans down by half the window size
- - key Zooms out by half the window size
+ Shift + = Zooms in by half the window size
0 0 key Zooms to fit the available window space
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Keyboard/Mouse Key
Menu Item or Key Combination Function
Stroke-SE-Btn1 Hold down left mouse Zooms in to area in selection box

button and drag in
south east direction
Stroke-SW-Btn1 Hold down left mouse Zoom fit; fits the current window size
button and drag in
south west direction
Stroke-NE-Btn1 Hold down left mouse Zooms out; zooms out proportional to the
button and drag in north length of the stroke. The longer the stroke,
east direction the further out the zoom. As you drag the
mouse, PowerCanvas displays the value of
the zoom factor.
Stroke-Btn2 Click and hold the Pan; moves around the design
middle mouse button
Shift-Stroke-Btn1 Hold down Shift key Drag selected instance; performs a move
and click left mouse
button and drag across This move is only operational for elements
screen that are not nested inside the body of
another instance.
Click-Btn1 Single-click left mouse Select; this focuses in the schematic window
button and selects any element that is under the
mouse cursor.
Shift-Click-Btn1 Hold down Shift key Append to selection; adds clicked elements
while clicking left to your current selection
mouse button
Double-Click-Btn1 Double-click left mouse Navigate; expands the connectivity for the
button clicked object to include additional
connections.
Clicking on a net will show additional pins for
the net. Clicking on a pin will show the net
for the pin.
Shift-Double- Hold down Shift key Shows the children of the clicked instance
Click-Btn1 while double-clicking
left mouse button
Delete Delete key Removes the selected net from the view
Ctrl-Delete Hold down the Control Removes the selected instance from the
key and press the view
Delete key
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PowerCanvas Dialogs
PowerCanvas Dialogs
The PowerCanvas provides different dialogs that allow you to manipulate your data
in a number of ways. You can search the power database and view and edit the
source lines for selected elements.
Using the Find Dialog

The Find dialog allows you to do a number of different searches on your power
database. Select Edit > Find from the PowerCanvas to bring up the Find dialog as
shown in Figure 56.
Figure 56 PowerCanvas Find Dialog
The Find dialog allows you to search the power database for information relating to
instances, pins or nets. You control your search choice using the “Search For” pull-
down menu. Once you have done this, you enter the search criteria, controlling how
many criteria must be met using the + (add another one to the list), - (delete the last
one from the list) and Clear (clear the entire list). The criteria depend on the object
you select. If you choose instances, you can then search by name, hierarchical
name, name, cell name, total power, dynamic power and static power. If you choose
pins, you can search by hierarchical name, name, type and capacitance. If you
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PowerCanvas Dialogs
choose nets, you can search by hierarchical name, name, average activity,
capacitance, duty cycle, and frequency.
For name-based searches, you do not need to use wild card characters. You can
simply type in any part of the name and the find dialog will return all names that
contain that string. You can then ask for either a match (==) or not a match (!=). Also,
the name-based entries are case-insensitive. When using this dialog, it’s important
that you understand the difference between a hierarchical name and a name. A
hierarchical name is the full hierarchical path name where levels of hierarchy are
separated by a dot (.). The name is the portion of the name after the last (right-most)
dot. Assume, for example, that you have the following strings in your design:
a.b.c
a.bc
abc
A name search of using “b” as the search string will return a.bc and abc. It will not
match a.b.c because in that case “c” is the name, which does not match the pattern
“b” (0 or more name elements followed by a “b” followed by 0 or more name
elements). However, a hierarchical name search using “b” returns all three because
a.b.c matches the given pattern.
When you are searching for numeric values, the values will all be floating point
numbers but will be displayed using scientific notation. You will use the standard
relational operators to control your search (<, <=, ==, >=, >). If you do not specify a
unit when searching for a numeric value, Watts is assumed. You can specify, W
(default) mW, uW, or nW.
Once you have defined your search criteria, you will then click the Search button to
perform the search. Notice that the search button changes to a Stop button while the
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PowerCanvas Dialogs
search is working. If you want to stop the search at any time, you can click Stop. The
following figure shows sample search criteria with results.
Figure 57 PowerArtist Find Dialog (Search with Multiple Criteria)
If the search goes on for more than several seconds you will see a progress meter in
the status bar that indicates the percentage completion of the search.
Note: The first time you search the Instance, Net, or Pin category you will see a
“busy indicator” because the Find dialog does not know how many items are in the
design. After the first search, you will get a progress meter that indicates the percent
of the search that has been completed.
This sample search, which uses the power database from the reduction tutorial, finds
all hierarchical names (including inferred instances) that begin with u (or U) and have
a dynamic power greater than 7e-04W (or .7mW). In this example, the search criteria
matched 64 elements. You can use the Previous and Next buttons to step through
the each element in the returned list. Notice the Selection box on the bottom left of
the dialog. This box allows you to view the source for each element, the schematic
entry, or the hierarchy browser entry. Moreover, you can zoom-in on or center the
element in the schematic display. Note that you must first make the selection in this
section before clicking on an element in the returned list. Once the selection is made,
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PowerCanvas Dialogs
for example, “Display in source” you can then double-click any element in the list to
see the corresponding source.
Corresponding
Source
Figure 58 Displaying Source for Element in Returned Search List
You can click on any column header in the table of returned elements to sort the
elements by either increasing or decreasing order according to that criteria. The first
time you select a header, you will get an arrow showing the direction of the sort. The
second time you select the header inverts the sort.
Using the Properties Dialog

You can bring up the Properties dialog from the Schematic top-level menu or from
the schematic pop-up menu on the schematic display. This dialog displays a number
of properties (power values, frequency, transition times, average, activity, duty cycle,
wire capacitance, etc.) for nets, pins or instances in the design. You can do the
following with this dialog:
 Select nets, pins or instances from the schematic or from the hierarchy browser.
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PowerCanvas Dialogs
 Add tabs to allow you to save data for items you have selected and then toggle
between them. There is no limit on the number of tabs you can create. You can
use the and icons to add or remove tabs, respectively. You can also right-click
on the dialog heading to open a pop-up menu of tab actions. This menu has three
items: New Tab, Close Tab and Close Other Tabs.
 Suppress (hide) any of the columns, by right-clicking a column header and
disabling/enabling the columns from the pop-up menu that appears. To reorder the
columns, click on and drag the headers.
 Cross-probe to the Apache Waveform Viewer. To do so, first open the Apache
Waveform Viewer (select Tools > Waveform Viewer). Then, right-click a net/pin
name and select Show Waveform from the pop-up menu. For full details, see the
Using the Waveform Viewer section.
 Hide or change columns by right-clicking any column header and making an
appropriate selection.
 Select multiple elements to display in the same tab. The following figure has three
tabs, one for each element type.
Adds a tab Deletes

selected tab
Drag column
Parent instance of headers to
the selected item change order
Collapses
this set of
instances
Expands subsequent
instance selections
to show all pins
Figure 59 Properties Dialog with Multiple Tabs and Instances Displayed
Notice the different icons in the tab headings for each element. The icon
represents a net instance. The icon represents a pin. The icon represents
an instance. You can display multiple nets, pins or instances (using Ctrl-select)
within a single tab. Note, however, that you cannot display different elements in
the same tab.
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PowerCanvas Dialogs
 Display the pins for any of the listed instances. To do so, right-click any row and
select Show Instance Pins from the pop-up menu. If the tab is already showing
pins when you right click a menu item, select Don't Show Instance Pins to view
only the information for the parent instances. If you check the Expand instances
to pins by default box, the pins will display whenever you select an instance.
 Display the upstream, downstream or exclusive cones of logic for an instance pin.
To do so, simply select the appropriate entry from the right-click pop-up menu.
The following figure shows how you would display the downstream cone of logic
for the Y output pin on instance udi18.
Downstream Cone of Logic
Selected Pin
Figure 60 Displaying the Downstream Cone of Logic for an Output Pin
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PowerCanvas Dialogs
Using the Smart Source Browser

To view the source for an element in the hierarchy display, click the element and then
select Design > Hierarchy > Show in Source or just Show in Source from the right-
click pop-up menu. You can perform a similar operation from the schematic display.
The Smart Source browser will appear as shown in the following figure.
Figure 61 Smart Source Browser
Much like the coloring of the hierarchy and power table, the SmartSource browser
color codes source lines according to the amount of power consumed by elements
inferred in that line. The color given to a line of code reflects the sum of all elements
inferred by that line. Once you select (click) a line, you can right-click to display the
pop-up menu shown in Figure 61. The three options have the following functions:
 Show in --> Hierarchy: Displays the selected instance in the hierarchy browser.
 Show in --> Schematic: Displays the schematic elements associated with the
selected line of source code.
 Show in --> Source: Brings up the source code of the selected line. If the line
represents a module instantiation and the definition of that module exists in a file,
an additional source code browser is displayed with the editor positioned at the
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Using the Hierarchy Browser
line where the module definition occurs. If the line represents inferred logic, then
there is no additional source to display and the request is ignored.
You then have the choice of editing the source code. If you select the Edit button,
the line you have selected comes up in the editor that you set the first time you
selected the Edit button. The editor is placed in a read only mode. When you are
done with the browser, click the Close button.
You can use the Search box at the bottom of the browser to search for occurrences
of the string in the current file. The left and right arrow keys search forward and
backward in the file. By default, it searches for any instance.

This section describes the ways in which you can manipulate your design data in the
hierarchy browser in the PowerCanvas. The Design menu controls the display of the
hierarchy browser. The hierarchy browser has two panes: the left-hand side is the
hierarchy and the right-hand side is the power table
Sorts
Instances/
Modules
Hierarchy
Symbol Key for the Hierarchy Browser Power Table

= Hierarchical instance
= Inferred instance
= Register
= Gates (includes I/O pads and memories)
Figure 62 Hierarchy Browser
You can use the button (which by default shows “Power”) at the top right of the
hierarchy view to sort the data. You can sort by Power, Power Density, Instance,
Module or Area.
The power table displays the inferred instances, registers and gates that are within
the hierarchical instance (module) that is highlighted in the hierarchy view in the left-
hand pane.
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Column Header Definitions for the Power Table

The power table display has the following columns:
 *Instance: This is the name of the instance inferred from the RTL.
 *Module/Cell: This is the name of the modules/cell in the design.
 Logic Stat: This is the total leakage power of the logic and inferred buffers.
 Logic Dyn: This is the total dynamic power of the logic (internal plus net power)
and inferred buffers.
 *Logic Total: This is the sum of the leakage and dynamic power of the logic. The
latter includes internal plus net power and inferred buffers.
 Clk Stat: This is the total leakage power of the clock tree enclosed by a
hierarchical instance.
 Clk Dyn: This is the total dynamic power of the clock tree enclosed by a
hierarchical instance.
 *Clk Total: This is the sum of the leakage and dynamic power of the clock tree
enclosed by a hierarchical instance.
 *Total Pwr: This is the sum of the logic and clock tree power.
 *Pwr Density: This is the total instance power divided by the instance area.
 *Area: This is the instance area.
 *Clk Gated: For registers, it identifies whether it is clock gated or not.
 *Optimized: Indicates whether the instance can be optimized away, for example, if
it has no fanout.
* indicates that this field is enabled/displayed by default.
Note on Logic Instance Values: If the instance power under Logic Stat, Logic Dyn
or Logic Total are zero, it may be because it forms part of a clock tree. If so, its
power will be included there.
Note Clock Instance Values: If a leaf instance power value under Clk Stat, Clk
Dyn or Clk Total is non-zero value, it’s because it forms part of a clock tree so its
logic power is included here.
Controlling the Hierarchy Browser From the Design Menu

The Design menu has two top-level menu items: Hierarchy and Power Table and is
broken down the in the following way.
 Hierarchy
For the highlighted module/instance, you can perform the following actions:
— Show in Source: Opens a Smart Source browser on the source file containing
the selected element. The browser will be positioned at the source line and
colorized for power based on the module/instance from which you cross-
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probed. For details on using the Smart Source browser, see Using the Smart
Source Browser.
— Show in Schematic: Displays the selected instance in the schematic. You can
then zoom-in to get a closer look. For more information see, Using the
Schematic Display.
— Show Properties: displays the selection in the Properties dialog. For more
information, see Using the Properties Dialog.
— Colorize by: Colors the hierarchy browser by the following:
 Nothing (the default). This adds no color.
 Power: Colorizes the modules in the hierarchy by the power results. The
higher the power consumption, the hotter the color.
 Clock Power: Colorizes the modules in the hierarchy by the clock power
results. The higher the power consumption, the hotter the color.
 Power Density: Colorizes the modules in the hierarchy by power density
(power/area) as a percentage of the largest power density.
You can also select these items from the pop-up menu when you right-click on a
module in the hierarchy.
 Power Table
For the selected instance, you can perform many of the same actions listed under
the Hierarchy sub-menu and the following actions that apply only to selections in
the power table (or apply differently to them):
— Show Downstream Cones: Displays the downstream cone of logic in the
schematic for the selected inferred instance in the power table.
— Show Upstream Cones: Displays the upstream cones of logic in the schematic
for the selected inferred instance in the power table. For upstream cones, you
have the following additional display choices:
 Ignore Select Cones/Show Select Cones
Ignores/shows cones of logic for upstream select signals for 2-1 muxes,
unencoded muxes and tri-states.
— Colorize by: Colors the power table by the following:
 Nothing (the default). This adds no color.
 Power: Colorizes for power as a percentage of the parent instance.
You can also choose to hide different elements in the power table by checking the
following options:
— Hide Gates
— Hide Inferred Instances
— Hide Registers
— Hide IO Pads
By default, all elements are displayed.
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You can also select these items from the pop-up menu when you right-click on the
power table.
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Using the Schematic Display

The schematic display allows you to browse through a schematic representation of
the loaded design. This section describes the ways in which you can manipulate the
schematic view of your design in the PowerCanvas.
Controlling the Schematic from the Schematic Menu

The top-level Schematic menu offers a variety of options you can use to manipulate
the schematic. This menu has the following options/sub-menus:
 Colorize By...
Colorizes the schematic by either Power, Activity or Connectivity.
— Power: Colorizes by the power results. The higher the power consumption, the
hotter the color.
— Activity: Colorized by the activity of a given net. The more activity, the hotter the
color.
— Connectivity: This is a special “power debug” mode that associates colors with
instances of the schematic when you are tracing cones of logic. This is
explained in more detail in Viewing the Upstream Cone of Logic from an Input
Pin of a Candidate Register.
 Properties...
Brings up the Properties dialog. This dialog displays information on pins, nets and
instances selected from the schematic. This is especially useful to see all
instances connected to a particular bus port. Multiple selections will show as many
of the selected items as possible, even if they have different parents. You can
save selection information by creating a tab. For more information on how to use
this dialog, see Using the Properties Dialog and Viewing Power Analysis Results
in the PowerCanvas.
 Redraw
Redraws the current schematic.
 Zoom In/Zoom Out/Zoom Out Full
Zooms in/out or zooms to fit the full screen.
 Instance
This menu has the following sub-menus:
— Show In Hierarchy
Highlights the selected instance in the hierarchy browser.
— Show Source
Displays the selected instance source in the Source Code Browser, For details,
see Using the Smart Source Browser.
— Expand Children
Displays the schematic of all the child instances of the selected instance.
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— Collapse Children
Replaces the schematic of the child instances of the selected instance with just
the block symbol representing the parent instance.
— Show Clock Trees
Displays the clock trees for the selected instance. For details, see Basic Clock
Tree Manipulation.
— Show Downstream Cones
Displays all downstream cones of logic for the given instance.
— Show Upstream Cones
Displays all upstream cones of logic for the selected instance.
Ignore/shows cones of logic for upstream select signals for 2-1 muxes,
unencoded muxes and tri-states.
— Show All Pins
Displays all pins of the selected instance.
— Remove Unexpanded Pins
Removes pins that have not been expanded from the schematic view. For
example, when PowerArtist traces an instance in the schematic it does not
show all of the pins of the instances so as to provide an uncluttered view. You
can display all pins by selecting Schematic > Instance > Show All Pins. You can
then do a trace from one of those pins or invoke the pin/net dialog. If you then
want to collapse the instance to reduce clutter you can select Schematic >
Instance > Remove Unexpanded Pins.
 Pin
This menu affects any pin selected in the schematic and has the following sub-
menus:
— Expand Drivers/Loads
Expands the drives/loads for the selected instance pin/port.
— Collapse Driver/Loads
Removes the drives/loads for the selected instance pin/port.
— Show Clock Tree
Displays the clock trees for the selected pin. For details, see Basic Clock Tree
Manipulation.
— Show Downstream Cone
When selected for an output pin of an instance, it generates a schematic of the
downstream cone of logic for that pin. It stops tracing at register boundaries or
primary IOs.
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— Show Upstream Cone

When selected for an input pin of an instance, it generates a schematic of the
upstream cone of logic for that pin. It stops tracing at register boundaries or
primary IOs. For an example using the reduction tutorial, see Viewing the
Upstream Cone of Logic from an Input Pin of a Candidate Register.
Ignores/shows cones of logic for upstream select signals.
— Show Exclusive Cone
When selected for an input or output pin of an instance, it generates a
schematic for the exclusive cone of logic for that pin.
Ignore/shows exclusive cones of logic for select signals.
 Expand Full Schematic
Generates a full hierarchical schematic for your entire design. Before you select
this command, consider the potential time this will take due to the size of the
schematic that it will generate. When you do select this, the following progress
meter will appear:
This will give you an idea of how long it will take to display the full design. If you
decide you no longer want to display the full schematic, simply click the stop
button.
 Collapse Full Schematic
Clears the schematic view and takes you back to the original schematic, which
consists of the primary inputs and outputs.
 Auto Hide Pins
When selected, this toggle suppresses the display of unconnected pins for any
subsequent schematic display. This feature is most useful when showing cones of
logic as it will not display any of the pins that are not associated with the cone.
 When Tracing
This menu has two sub-menus:
— Colorize Data Path
Colorizes the data path while performing tracing.
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— Colorize Select Path

Colorizes the path for select signals while tracing.
You can also select these items from the pop-up menu when you right-click on the
schematic.
Using the Mouse to Zoom In and Out on the Schematic

By pressing and holding the left mouse button and moving the mouse, you will get
different zoom operations. There are three supported directions:
 To the NorthEast (up and to the right): this zooms out by a factor that is
proportional to the angle as well as the length of the stroke. You will see an
annotation “zoom value” on the display.
 To the SouthEast (down and to the right): this does a window zoom where the first
point is the upper left bounding box point and the second point is the lower right
bounding box. You will see the annotation “zoom in” on the display.
 To the SouthWest (down and off to the left): this does a zoom fit. You will see the
annotation “zoom fit” on the display.
Expanding the Schematic by Double Clicking Ports

Suppose you have pin-pointed a hierarchical instance that consumes a lot of power
and you want to see the schematic for it. You can simply select that element in the
hierarchy browser, right-click and select Show in Schematic. This will display the
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schematic symbol body in the schematic with input ports listed on the left side and
output ports on the right hand side, as shown in the following figure.
Figure 63 Hierarchical Schematic Body
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Double clicking this element in the schematic while holding the shift key down
expands the body into its equivalent schematic. You can then do a Zoom Fit to see
the following figure.
Figure 64 Nested Schematic for a Hierarchical Block
If you have done a power analysis, you can quickly find the nets that have high
activity since they will be a non-blue color. Other elements are displayed in different
shades of the thermal spectrum indicating that some of their powers are higher than
others. If you want to see how a port of this module is connected to other modules,
simply double-click on the port.
Basic Clock Tree Manipulation

To display a clock tree, you must first define your clock trees using the SetClockNet
command. Second, you must set the -save_clock_trees_netlist option to
CalculatePower or ReducePower. Finally you must perform the power analysis (you
will not be able to display clock trees after elaboration). Once you have performed
these requisite steps, you can use the following process to display a clock tree:
1. From the schematic display, select and highlight one of three elements to display
a clock tree:
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— The clock pin of an inferred register

— The clock pin of an instantiated gate-level instance
— The clock net defined using the SetClockNet command
2. If you select a pin, right-click to bring up the pop-up menu and select Pin > Show
Clock Tree.
This creates a new schematic window of either the inferred clock tree for this
element or the traced clock tree. If you select a pin, you will get the cone of logic
that leads to that particular clock pin. If you select the clock net, you will see the
entire clock tree generated in a new clock schematic.
Note that you cannot use the standard “less” and “more” schematic techniques
previously described to see less or more of your clock tree. You can only traverse the
clock distribution network in this view; that is, you do not have access to enable pins
of integrated clock gating cells, for example. Figure 65 shows a clock tree for inferred
register core1.s1.rxwrd.clock[0].
Figure 65 Inferred Clock Tree
This register name is a concatenated list of scalars.
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Using the Simple Reduction Dialog

There are three separate dialogs for viewing power analysis results: Simple
Reductions, Linter Reductions and Prism. This section describes the Simple
Reduction dialog.
To view the results of the GMC, LNR, LEC, ODC, and DOI PowerBots, bring up the
Simple Reduction dialog by selecting View > Simple Power Reductions. The Simple
dialog will appear as shown in the following figure.
Figure 66 Simple Reductions Dialog
Column Header Definitions for the Simple Reductions Dialog

You can click on any column header in the Simple Reductions dialog to sort the data
by that column. The following list provides a high-level definition of each column:
 Module: The name of the modules containing the reductions.
 Reduction: The type of reductions discovered in the given module. The line
number of the RTL where the reduction has been found is also listed in this
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column. Also, the name of the variable/instance associated with the reduction is
listed in this column at the lowest level.
 Instance: The name of the instance inferred from the RTL.
 Total Power: The total of the logic and clock power of the RTL before any
reduction takes place.
 Logic Power: This is all of the power that is not clock power. This include
combinational logic, sequential logic (latches and register) and instantiated library
elements.
 Clock Power: The power not including logic power. This will be the power of your
clock distribution network including any inferred buffers, inferred integrated clock
gating cells and any traced elements in your clock network.
 Saved Total: The total of the logic and clock power saved after all reductions (or
the specific reduction) are applied.
 Saved Logic: The power of the RTL logic that is saved per module, reduction, etc.
 Saved Clock: The clock power that is saved after the reduction(s) are applied.
 Pcnt Saved: The total of the logic and clock power saved as a percentage of the
total top-level power.
 Ideal Saved Logic: The power of the RTL logic saved after the reductions are
applied but before subtracting the logic power required to implement the
reduction.
 Ideal Saved Clock: The clock power that is saved after the reductions are applied
but before subtracting the clock power required to implement the reduction.
 Area Ovrhd: The total area required to implement the reduction(s).
 CGE Imp: The clock gating efficiency (CGE) improvement percentage, which is
the CGE value after reduction minus the CGE before reduction. This value is
displayed for clock-based reductions only (that is, LEC, LNR and ODC in this
dialog). The CGE for each instance of a register is displayed (see the blue text)
and the “Line” row displays the average of all its children.
 Bits: The bit width of the register.
 AA: The AA (auto-accepted) column indicates whether or not the reduction was
automatically accepted for rewrite. If a reduction is not auto-accepted, you can
hover your mouse over the word “No” to see a tool tip that tells you why the
reduction was not auto-accepted. Note that you can also filter on what has been
automatically accepted. In the Simple Reductions dialog, the PowerBots that can
be auto-accepted are: GMC, LNR and ODC.
 Accept: Ticking this checkbox will cause reductions that can be automatically
rewritten to be scheduled (when Automatic is selected from the pull-down menu)
and will add the power saved by any accepted reduction to the power summary
table.
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 Rewrite: The word “Scheduled” appears in this column when a reduction

opportunity is accepted for “Automatic” rewrite.
Column Header Right-Click Pop-Up Menu

If you right-click on any of the column headers in the Simple Reductions dialog, you
will see a pop-up menu. This menu shows you which column headers are already
displayed [X] and which are not. You can turn the display of these columns off and
on using this menu. Additionally, the first three selections in this menu have the
following functions:
 Auto Size Column: Extends the selected column to allow you to see the entire
contents of the column for all displayed reductions. Note that a ... in any column
indicates that there is text that is not displayed. To see the text, you can auto-size
the column.
 Auto Size All Columns: Extends all displayed columns to their full width or the
maximum width set in the Column Width dialog for that column.
 Column Width: When you select this, you will see the following dialog:
Figure 67 Column Width Dialog
In the input field, enter a specific width (in characters) and click OK. The column
from which you invoked this dialog will adjust to the specified width.
If you specify a column width and check the “Set value as maximum auto-fit width”
box, the specified value becomes the maximum width to which the Auto Size
Column feature will expand. This is useful when instance names are very long
and the Auto Size Column selection would otherwise make the columns too wide.
Note that this maximum setting will persist in the PowerCanvas. If you want to
remove the maximum setting, specify a value of 0 and click OK.
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Simple Reduction Dialog Data Filters

You can use the “Match” filtering mechanism to filter the data in the Simple
Reductions dialog. The available filters are described in the following table.
Table 1 Simple Reductions Dialog Data Filters
Filters that compare against strings using contains/doesn't contain:
Module Name
Reduction Instance
Filters that compare against numbers using standard relational operators:
Mod Total Power Line Saved Clock
Red’n Total Power Mod Pcnt Saved
Line Total Power Red’n Pcnt Saved
Line Logic Power Line Pcnt Saved
Line Clock Power Line Ideal Svd Lgc
Mod Saved Total Line Ideal Svd Clk
Red’n Saved Total Line Area
Line Saved Total Bits
Line Saved Logic
Filters that compare against
Auto-Accepted Accepted
Filters that compare against Scheduled, Rewritten, Failed
Rewrite
The purpose of using these filters is to reduce the amount of data you are viewing at
any point in time. For example, if you want to display only those reductions that were
auto-accepted, you can filter on “Auto-Accepted is yes”:
1. Remove all filtering by clicking the cancel icon.
2. Select Reductions > Mark All Not Accepted
3. Filter on “Auto-Accepted is yes”.
4. Select Reductions > Mark All Accepted.
You can use this type of filtering to restore the auto-accepted state of the reductions
after manually accepting or rejecting reductions in the GUI and saving your changes.
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The View Menu

The Simple and Linter Reduction dialogs have five menu items across the top of the
dialog: File, View, Reductions, Detail and Help. The View menu allows you to expand
or collapse collections (groups) of reductions at one time. Using this menu, you can
do the following:
 Expand the view of selected items
 Expand the view of all items
 Collapse the view of selected items
 Collapse the view of all items
To expand/collapse selected items, you first need to select one or more items using
the Shift-click or Ctrl-click method. With the selected items highlighted in blue, you
can then click the View menu and expand/collapse the selections to your level of
choice (Reduction, Line Number or Instances). The following figure shows you how
you can expand multiple selections down to the line number.
Figure 68 Expanding Selected Items to the Line Number
The “All” in the View menu items refers to all of the items currently displayed in the
dialog (not all items in the database). If you previously filtered out some of the data,
that filtered data is not included in the “All” operation.
For example, if you want to accept all LNR reductions you can do the following:
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1. Filter out all reductions other than LNR. In the Match field, select “Reduction
contains” and enter LNR in the input field. Click the magnifying icon to filter the
data.
2. Use the Shift-click method to highlight all remaining lines in the dialog.
3. Click Reductions > Mark all Accepted.
4. Select Reductions > Set All Rewrite Actions > Automatic.
5. Click the Save button to schedule the reductions.
The Detail Menu

The Detail menu allows you to perform several different operations on an instance
selected in the Detail tab (not from the reduction list). This menu provides the same
options as the right-click menu that pops-up when you right click an instance name in
the reduction list. The Details menu has one additional item—Show Waveform. You
can also bring up these options by right-clicking on an net/instance in the Detail tab.
Figure 69 Right-Click Menu from Detail Tab
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Using the Simple Sorting and Filtering Features

PowerArtist provides some simple features for sorting and filtering your data. In the
simple mode, you can sort by simply clicking on any column header. If a column
header does not show an arrow to the right of the column name, you can’t sort by
that column.
Filters on one criteria Click to sort by this column
Figure 70 Simple Filtering Features
In the simple mode, you can see there is only one “Match” filter line. This allows you
to filter on one set of criteria at a time. For example, you filter out any reductions that
do not reduce total power by a given amount. For additional information and an
example, see Filtering Reduction Results in the reduction tutorial.
Using the Advanced Sorting and Filtering Features

In addition to the simple sorting and filtering features, PowerArtist provides more
advanced sorting and filtering features. To use the advanced sorting and filtering
feature, click the arrow icon on the far right of the Simple Reductions dialog.
This expands the dialog to display new “Sort by” buttons and provides the ability to
filter on multiple fields. For example, you can filter on “module” and whether power
savings are greater than a specified value, then sort your data first by bits and then
by module/reduction. To add another sort or filter field, simply click the icon. You
can add up to three sort fields and as many filters as you like.
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In the following figure, there are two sorting fields and two filtering fields.
Selects
Sorts by Saved Total descending or
and Accepted ascending Adds a sort option
Removes last sort option
Filters on Reduction
and Module
Figure 71 Sample Multi-Level Advanced Sorting and Filtering
It is important to note that sorting is hierarchical, that is, it is applied within levels.
Specifically, the sort feature is applied to the different levels in the following order:
1. Module level
2. Reduction level
3. Line level
4. Instance level
Given this sort order, if you sort on bits, you won’t necessarily get the instance with
the highest bits first.
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Sorting Total Power by Module and Reduction

The following examples show how a total power sort is applied at the different levels
of hierarchy in the simple reduction wizard. For example, when you sort by Total
Power (by clicking the up arrow in the Total Power header) PowerArtist sorts each of
the various levels—Module, Reduction, Line and Instance—as shown in the following
figures.
Descending Sort on
Module Total Power
Descending Sort on
Reduction Total Power
Descending Sort on
Line Total Power
Descending Sort on
Instance Total Power
Figure 72 Sorting Total Power Values at Different Hierarchical Levels
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Using the Linter Reductions Dialog

This section describes the Linter reductions dialog though many of the features
described herein are also available, in a slightly modified form, in the other reduction
dialogs.
To view the results of the Linter PowerBots, bring up the Linter Reductions dialog by
selecting View > Linter Power Reductions. The Linter Reductions dialog will appear
as shown in the following figure.
Figure 73 Linter Reductions Dialog
Similar to the Simple Reductions dialog, you can use the What’s This feature to get
information on each of the column headers. You can also use the Match sorting
feature to sort the data.
Column Header Definitions for the Linter Reductions Dialog

You can click on any column header in the Linter Reductions dialog to sort the data
by that column. The following list provides a high-level definition of each column:
 Module/Linter: The name of the module/linter containing the linter reduction.
 Instance: The name of the register instance inferred from the RTL.
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For details on how you can use the data in this dialog to evaluate MUX power
reduction opportunities, see Understanding the PowerCanvas Data for the MUX
Linter.
 Total Power: The total power, including wasted power.
 Wasted Power: The total wasted power of the RTL (per module, linter, line or
instance as applicable).
 Pcnt Wasted: The total wasted power of the RTL in all instances (per module,
linter or line) as a percentage of the total module power. For modules, it does not
include child modules.
 Bits: The bit width of the instance associated with the linter. Note that you will
need to expand to the line level to see this information.
 Cone Power: The total average power in the exclusive cones of all instances that
experience wasted toggles (per module, linter or line).
 Start Points: The maximum number of start points in the exclusive cones over all
instances that experience wasted toggles (per module, linter or line).
rewritten to be scheduled and for all reductions will cause the power saved to be
accumulated in the power summary table.
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Using the Prism Dialog

This section describes the Prism dialog though many of the features described
herein are also available, in a slightly modified form, in the other reduction dialogs.
To view the results of the Prism PowerBot, bring up the Prism dialog by selecting
View > Advanced Power Reductions > Prism.
The Prism dialog will appear as shown in the following figure.
Figure 74 Prism Dialog (Initial View)
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Click on each of the + signs at the beginning of each line to expand the results. You
can also click on a row that has a + sign and click the * key to expand that row.When
you do so, you will see that each line is color-coded, as shown in the following figure.
Figure 75 Prism Dialog (Expanded View)
The color key applied to the Prism results is as follows:

 White row: These are the gated registers that form the start of the potential
enable propagated chain.
 Green row: These are candidate registers that only have gated registers
upstream. Green rows fall into the easy category.
 Yellow row: These are candidate registers that have gated and/or candidate
registers upstream. These fall into the medium category. Yellow rows are
always under green rows.
 Red row: The register instance in this row has unresolved dependencies, that
is, the enable logic required to clock gate this register is partially known. This
may happen when:
— a register is driven by an ungated register in addition to being driven by a
white, green or yellow register.
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— a register is driven by a primary input in addition to being driven by a white,

green or yellow register.
— a register is driven by a macro (memory, etc.) in addition to being driven by a
white, green or yellow register.
— a register is driven by a delayed version of itself in a feedback loop in
addition to being driven by a white, green or yellow register.
The icons at the beginning of each line indicate the type of element in the register
chain. The icons are:
— A register gated in the RTL.
— A register for which an enable has been generated by XORing the inputs
and outputs. If the register width is greater than min_width, the enable will also
be used to gate it.
— A gated register with a strengthened enable.
— A single candidate register: This indicates that the chain is a simple
register.
— Two registers whose outputs drive another register. This indicates that this
register is one of at least two other registers that drive another register. This
means that two or more registers share a common register chain. By selecting
the + sign that precedes the icon, you can see the next element in the chain.
— Two stacked registers: This indicates the start of a common register chain.
Somewhere else in the display is a row that has as the icon. Rather than
searching for that, you can right-click this row and select Move Common Chain
Here.
Categories of Implementation of Suggested Modifications

The Prism results can be put into three different categories: easy, medium and hard
as described here:
 Easy—creating an enable for this register from the upstream gated registers is
easy. You would just OR the enables and delay by a register.
 Medium—creating an enable for these registers is not so easy since there is a
candidate upstream; however, a simple inspection of the schematic may
uncover an easy way to create one.
 Hard—creating an enable for these registers is probably not possible since
upstream of this register are ungateable registers, macros, primary inputs, etc.
However, by looking at the schematic, you may be able to easily identify an
enable. For example, the upstream ungateable register might be an
initialization flop that never changes state outside of reset.
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Definitions for the Bit Counters in the Prism Dialog

In the bottom right corner of all reduction dialogs, in the status bar, you will see a set
of four bit counters with the following definitions:
 V(iable)—the total number of easy or medium bits. Note that it might not be
possible to accept all of these because some might have red candidates upstream
which could block an enable.
 A(utomatic)—the total number of bits that have been accepted for automatic
rewrite.
 M(anual)—the total number of bits that have been accepted for manual rewrite.
 M(odules)—the number of Verilog modules or VHDL architectures that are
displayed in the dialog.
Column Header Definitions for the Prism Dialog

You can click on any column header in the Prism Dialog to sort the data by that
column. The following list provides a high-level definition of each column header that
appears by default and those that you can enable (by right-clicking any column
header).
The columns available by default are as follows:
 Register: For a gated register it is the name of the register where the enable
originates. For a candidate register it is the name of the register to which the
enable can be propagated.
 Instance: The name of the register instance inferred from the RTL.
 Module: The name of the module containing the register.
 Clock Net: The name of the clock driving the register.
 Reg Power: The power of the register before clock gating. The value in
parentheses is the total power, before clock gating, of all the registers in the chain
starting from the gated register.
 Saved Total: The total power (register + clock - penalty) saved by gating the clock
to the register. The value in parentheses is the total power (register + clock -
penalty) saved in the chain starting from the gated register if all of the registers in
the chain were clock gated. Note that there might not be any savings if the clock
gating percentage is too low, too few register bits are gated, or the logic required
to gate the clock, an ICGC, consumes too much power.
 Saved Reg: The register power saved by gating the clock to the register. The
value in parentheses is the total register power saved in the chain starting from
the gated register if all of the registers in the chain were clock gated. Note that
there might not be any savings if the clock gating percentage is too low or too few
register bits are gated. Check the online help for a more detailed explanation.
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 Saved Clock: The clock power saved by gating the clock to the register. The value
in parentheses is the total clock power saved in the chain starting from the gated
register if all of the registers in the chain were clock gated. Note that there might
not be any savings if the clock gating percentage is too low, too few register bits
are gated, or if the ICGC consumes too much power.
 Ideal Saved Reg: This is the total register power saved in the chain starting from
the gated register if all of the registers in the chain were clock gated, but before
subtracting the power in the enable propagation logic. For a candidate register,
this is the register power saved by gating the clock to the register, before
subtracting the power required to propagate the enable from the upstream
registers.
 Ideal Saved Clock: The total clock power saved in the chain starting from the
gated register if all of the registers in the chain were clock gated, but before
subtracting the power due to the ICGCs and additional clock buffers. For a
candidate it is the clock power saved by gating the clock to the register before
subtracting the power due to the ICGC and additional clock buffers. Note that
there might not be any savings if the clock gating percentage is too lower, too few
register bits are gated, or if the ICGC consumes too much power.
 Pcnt Gated: The percentage of the time the clock to the register was clock gated.
The value is (1 - duty cycle) of the feedback MUX select signal expressed as a
percentage. For a gated register, the duty cycle is calculated from the simulation
data. For a candidate register, the duty cycle is estimated by ORing the upstream
enables. Sources that cannot be gated are ignored.
 Area Ovrhd: The total area required to implement the reduction(s).
 CGE Imp: The CGE improvement percentage, which is the CGE value after
reduction minus the CGE before reduction. This value is displayed for all
candidate registers. The root registers may or may not have a CGE value. If the
root register has its enable strengthened or has a generated enable (these roots
will have blue/yellow or just yellow icons) then the CGE improvement is displayed
due to the strengthening or new gating. Note that if the register is a simple user-
gated register, no CGE value is displayed since PowerArtist does not attempt to
improve the CGE for these registers.
 Bits: The bit width of the register.
 Opt: Indicates (by yes or no) whether you can save more power by strengthening
the gated register enable. If there are “yes” values in this column, you can switch
to the Optimal view (if you are in the Normal view) to see the extra savings. To do
this, simply select View > Analysis > Optimal (this is the default).
 Gated Regs: The number of upstream gated registers from which an enable can
be propagated.
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 Candidates: The number of upstream candidate registers from which an enable

can potentially be propagated. A candidate that has a candidate upstream of it
becomes a “medium” gating opportunity.
 Ungateable: The number of ungateable sources upstream. You need to inspect
these sources to see if they will prevent you from clock gating the register.
Ungateable sources makes a candidate a “hard” gating opportunity.
 CDC: false means this register does not cross clock domains—it is in one clock
domain. True would mean that it is in more than one clock domain.
 Local Enable: The number of enables that are available in the same module as
the candidate register.
 Extrn Enable: The number of enables that need to be routed to the same module
as the candidate register from other modules.
 Feeds Back: Indicates whether the output from the candidate register feeds back
to its input via another register. This might prevent you from gating the clock to the
register.
rewritten to be scheduled (when Automatic is selected from the pull-down menu)
and will add the power saved by any accepted reduction to the power summary
table.
 Rewrite: The word “Scheduled” appears in this column when a reduction
opportunity is accepted for “Automatic” rewrite.
Filtering Prism Dialog Data

In addition to sorting by table column, you can use the “Match” filtering mechanism to
filter the data.These filters are described in the following table.
Table 2 Prism Dialog Data Filters
Filters that compare against strings using contains/doesn't contain:
Any Register Any Module
Any Instance Any Clock Net
Filters that compare against numbers using standard relational operators:
Any/Chain Reg Power Any/All Bits
Any/Chain Saved Total Any/All Gated Regs
Any/Chain Saved Reg Any/All Candidates
Any /Chain Saved Clock Any/All Ungateable
Any/Chain Ideal Reg Any/All Local Enable
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Table 2 Prism Dialog Data Filters
Any/Chain Ideal Clock Any/All Extrn Enable
Any Pcnt Gated Chain Area Ovrhd
Any Area Ovrhd
Filters that compare against yes/no:
Any Feeds Back All Accepted
Any Accepted All Feeds Back
Any/All CDC Chain Optimized
The purpose of using these filters is to reduce the amount of data you are viewing at
any point in time. Filters starting with “Any...” mean that if a condition matches any
register in a chain, the whole chain will be visible whereas filters starting with “All...”
require that all registers in a chain match the condition for the chain to be visible.
Filters starting with “Chain...” apply to the values associated with the first or gated
register in the chain which are rolled-up values for the entire chain. Your goal is to
reduce your power as much as possible with as little work as possible. There are
several approaches to this problem.
Focus on a Module
You know by reviewing the hierarchy display that one module consumes more power
than it should. You should then use the “Any Module” filter to examine that particular
module. If the module has multiple instantiations you will see data for all the
instantiations.
From the hierarchy browser again, you might realize that there is one particular
instantiation of the module that is consuming more power than the others. You can
then use the “Any Instance” filter to locate register chains involving that instance. As
an example, you could use “contains” top.core1 to focus on all the register chains
involving that module instance.
Focus on Clock Domains

You may be very concerned about the clock power for a particular clock. You had run
PowerArtist and noticed that one clock domain consumed more power than you
expected. Use the “Any Clock Net” filter with the full clock name to locate those
register chains that are in the desired clock domain.
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Focus on the Amount Saved

If you want to see the opportunities that provide the most savings choose Chain
Saved Total and look for a number greater than some value.
Another way of looking at opportunities is by bit width. Generally, the wider the
register bank, the greater the opportunity for power savings. Use the “Any Bits” filter
and specify a bit width size using the “greater than” operand.
Focus on Easiest First

Making a source code edit where you do not have to cross module boundaries is the
easiest alternative. This means that the enable signal you are missing is local to your
module. Choose All Local Enable “greater than” 0 and the displayed opportunities
will require edits to just one file.
You will also want to focus first on registers that have no ungateable elements in
their chain. This means that enables are all immediately available. Filtering on “All
Ungateable equals 0” is a good start because this will leave you with chains where
the registers can be gated using upstream registers but bear in minds that some of
these upstream registers might themselves be more difficult opportunities.
Focus on the More Difficult

Once you have done all the easy changes, and you still want to continue reducing
power, you should remove from your view all the opportunities you have accepted.
Filter on “Any Accepted No” to remove from view any chain with an accepted
opportunity. To focus on chains crossing module boundaries, filter on Any Extrn
Enable “greater than” 0.
Using the Normal vs. Optimal Views

Designs often contain ineffective enables, which result in a substantial amount of
wasted power. These enables are recognized by the CEC linter, which then
estimates the resulting wasted power in the particular register they are enabling.
These inefficient enables can also impact the quality of the Prism powerbot results.
This is because Prism replicates existing enables to use as the enables of candidate
registers later in the chain. If these replicated enables are recognized by CEC, you
may be wasting power in both the gated register and in every register downstream
that uses that enable. Therefore, by making that one enable more efficient, you will
save even more power in the entire chain.
The Prism dialog has two different views—Normal and Optimal. The Normal view
represents the power savings you would achieve given the simulation vectors used
to perform the reduction analysis. The Optimal view represents the power savings
you would achieve if your enable was “optimal”.
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By examining the difference between the Normal and Optimal savings values, you
will be able to see the impact that an inefficient enable has on multiple registers in
your design. You can toggle between the two views using the View > Analysis menu.
The status bar at the bottom right of the dialog shows the current mode as Analysis:
type where type is Normal or Optimal (default).
The Opt?. column in the Prism dialog mean “Optimizable?”. If its value is “yes” then
this chain has an inefficient enable which you can optimize to further reduce power. If
its value is “no” then this chain has the best enable possible given the simulation
vectors used to perform the reduction analysis. The dialog displays this field for the
root (gated) register because this is the enable signal that will be leveraged through
the chain. As with other dialog columns you may filter the data using this column’s
value. For example, if you want to see only Prism opportunities that have enables
that are inefficient and can be optimized, you would filter that data using “Chain
Optimized is yes”.
Note that when you change the view between Normal and Optimal, PowerArtist
recalculates all of the values in the dialog, including roll-up values, using the
appropriate data. It also updates the summary pane.
Using the Optimized Results to Improve the Power in your Design

You will be able to view the optimal results in the Prism dialog if you run a reduction
analysis with the Prism PowerBot using either the ReducePower command or the
PowerCanvas wizard. Use the following flow to generate and view optimal results:
1. Run the ReducePower command with the Prism PowerBot enabled and open the
Prism dialog in the PowerCanvas.
2. Ensure that the display is in the “Analysis: Optimal” mode by selecting View >
Analysis > Optimal.Verify that you are in the Optimal mode by checking the status
bar at the bottom right of the dialog.
3. Filter out the chains that need optimizing and chains with small bit width registers.
You can do this by applying the following filters:
a. “Chain Optimized is no”
b. “Any Bits greater than 2"
4. Accept all of the easy chains by selecting Reductions > Mark All Chains Accepted
> Just Easy Candidates.
5. Make a note of how much power is saved in the summary table.
6. To see just these chains set a single filter to “Any Accepted is yes”
7. Sort on Saved Total (by clicking the column header). You now have a list of
register chains with readily available efficient enables that can be easily
implemented.
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8. Repeat this process on chains that would benefit from more efficient enables. To
do this, first define the following two filters:
a. “Chain Optimized is yes”.
b. “Any Bit greater than 2"
9. Accept all the easy chains by selecting Reductions > Mark All Chains Accepted >
Just Easy Candidates.
10. Make a note of how much the total savings has increased in the summary table. If
this amount is substantial, then modify the previous filter to:
a. “Chain Optimized is yes”.
b. “Any Accepted is yes”
11. Sort on Saved Total (by clicking the column header). You now have a list of
register chains with inefficient enables that if implemented would provide extra
power savings.
12. If there are many chains of this sort it might be useful to see if it is worth the effort
to create better enables to achieve the extra savings. To do this toggle the display
to Normal by selecting View > Analysis > Normal. Make a note of how much the
total savings in the summary table decreases. Based on this decrease, you can
decide whether you want generate better enables or just use the existing enables.
13. At this point, you are now left with things that are potentially more difficult to
implement. Follow your previously established methodologies.
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Using the Waveform Viewer

This section focuses on how to use the Apache Waveform Viewer. You can use the
waveform viewer to view output from PowerArtist or from external sources. Note that
you can use the Tips tab at anytime to see some tips on performing common
functions using the waveform viewer.
Supported Waveform Sources

You can view waveforms from the following sources:
 From an FSDB file.
The waveform viewer supports all FSDB files that PowerArtist supports.
The waveform viewer supports ETCL and PTCL files as well.
 From an HSPICE (CSDF or PSF) or a Spectre PSF file.
For details, see Displaying Waveforms from an HSPICE or Spectre Simulation.
As a PowerArtist user, you will mostly be using FSDB files and potentially PTCL files.
There is very little reason to use PTCL files since PowerArtist has the capability of
generating power waveforms in the FSDB format. These will be much faster and take
less disk space than their .ptcl equivalents.
Finding and Displaying Waveforms from an FSDB File

Use the following process to view waveforms stored in an FSDB file.
1. From the main PowerCanvas window, select Tools > Waveform Viewer.
The Waveform Viewer appears as a separate window with th Add Waveform
Source window open.
2. From the Add Waveform Source window, select an FSDB file (or PTCL file). For
demonstration purposes, you can use the FSDB file in the PowerArtist tutorial.
Simply navigate to the $POWERTHEATER_ROOT/tutorial/analysis/design_data/
rtl_sim/directory and select the activities.fsdb file.
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3. Click the OK button.
Figure 76 Selecting an FSDB File with the Waveform Viewer
4. To locate a signal name to view as a waveform, you have three choices:

— Type in a search pattern in the Waveform Name entry field. The pattern is case-
insensitive and can contain the * wild card character.
— Cross-probe instances from the schematic or the Properties dialog.
When you select an instance in the schematic, the name will be transferred to
the Waveform Name field with two modifications. The syntax will be:
*.full_path_to_instance.*
The *. is added to the beginning of all cross-probed nets/instance. This is due to
the top-level hierarchy of the testbench that is reflected in the FSDB file. Adding
a .* wild card at the beginning of the name will match any top-level string that
begins the hierarchical net names (for example, testbench.top0.).
The .* is added to the end of the hierarchical name so that the waveform viewer
finds all of the nets defined in the selected instance. It will recursively match all
the nets defined by its children instances as well. Given the sample in Figure
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76, if you selected t1/txchan the following name is added to the Waveform
Name field in the Search tab:
*.core1.t1.*
— Cross-probe wires from the schematic or Properties dialog.
If you select a wire, the name of the associated net will appear in the Waveform
Name field as:
*.full_path_to_net
Since there is a single net associated with the wire, there is no need for the .* at
the end of the name. If you select a bus, the name generated will be:
*.full_path_to_bus[*]
If you select an inferred instance or net, then no cross-probing is done to the
waveform browser since there can be no possible match in the FSDB file.
5. Once the Waveform Name entry field is filled-in, click the Search button to perform
the search. Cross-probing performs an automatic search for you. The waveforms
that are found, using the selected waveform source, will be listed in the box below
the entry field.
The following figure shows the Search tab with a list of available waveforms.
Figure 77 Waveform Viewer with a List of Available Waveforms
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In this figure, the search pattern is *.clk which locates 30 waveforms. If your
search returns more than 100 matches, the browser displays the first 100 matches
and generates a warning that the remaining matches will not be displayed. The
Search History selector menu contains a log of all searches in the current session.
As you keep searching, this menu is updated, allowing you to quickly go back and
forth between different search results. This eliminates the need to re-invoke a
search for a given pattern. For any of the listed searches, the first number
indicates the waveform source for which the search was executed, followed by the
pattern that was entered, and finally the number of matches.
6. From the list of available waveforms, select the waveforms you would like to
display, and click the Add waveforms to plot area button. If you want to select all
of the listed waveforms, right-click on the list and select Select All.
If the external file size is large, it may take some time for the waveforms to appear.
Note that although the option appears available, you cannot place more than one
digital waveform in a single plot (it will not look right). Figure 78 shows three
waveforms in individual plots that were selected from the Properties dialog.
Waveform
name
Increases
legend width
Waveform
legend
Figure 78 Waveform Display with Three Plots

Figure 78 Waveform Display with Three Plots
7. Right click on any plot to bring up a menu of available operations. You can
manipulate the display using the Display Options manu. For easier viewing, the
plots in this figure were increased in width by 20% (Display Options > Increase
height of all plots by 20%). For more information on options, see Using the
Waveform Viewer Options Menu.
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Understanding the Waveform Name

There are four distinct elements in a waveform name:
 The first element indicates the type of waveform: u (unknown), p (power), s
(state), and v (voltage).
 The second element represents the domain: t (ime) or f (requency).
 The third element is the index number assigned to the source of the waveform.
This index is listed next to the source name on the Waveform Source drop-down
list. The 0 index is used for the first waveform source. This index is increased by 1
for each additional source.
 The fourth element—the element that follows the pipe—indicates the name of the
waveform as exists in the waveform source. The following figure breaks-down a
sample waveform name.
st0|txrx_tst.clk
Type of
waveform
Domain type Waveform name
Index of source as it exists in the source
Figure 79 Break-Down of a Waveform Name
In this figure, the waveform is a state waveform in the time domain for a waveform
called txrx_tst.clk in the first listed source (source index 0).
Manipulating the Waveform Display

To delete the waveform, double-click a waveform name.
To zoom-in on particular area of interest on a waveform, click the middle mouse
button and hold it down while dragging the mouse to form a rectangle around the
area of interest.
Displaying Waveforms from a PTCL File

The waveform viewer can display waveforms from a PTCL file. The analysis tutorial
generates a ptshell.ptcl file. If you have this file available to you, you can view this file
by adding it to the waveform source, as described in the previous section. Simply
delete out the “*fsdb” from the end of th Filter field entry and replace it with “*ptcl” to
see the available PTCL fies.
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Displaying Waveforms from an HSPICE or Spectre Simulation

The waveform viewer can display waveforms from an HSPICE or Spectre simulation.
For HSPICE, the simulation output can be in either CSDF or PSF format.
To generate the output in CSDF format, you must include the following setting in your
HSPICE simulation input file:
.options CSDF
Make sure that there isn’t another output format option specified after this CSDF
specification (for example, “.options POST”)—this would override the CSDF setting.
Since a CSDF file is an ASCII file, displaying waveforms from very large CSDF files
will be slow; however, you can speed up this process by using .PROBE v(XXX)
statements in your HSPICE simulation input file—to limit number of reported
waveforms.
To generate the output in PSF format, you must include the following setting in your
HSPICE simulation input file:
.options psf=2
Specifying ‘2’ creates an ASCII PSF file, which the waveform viewer supports. Note
that the waveform viewer does not support binary PSF files.
For Spectre, you need to set the following option:
psfascii
You can then load HSPICE or Spectre output files as you would for any source file.
Using the Waveform Viewer Options Menu

Once you have a waveform in the plot area, you can right-click anywhere on the plot
to bring up the options menu. You must continue to hold the right mouse button to
see the menu as shown below. Note that some menu items have single-character
shortcuts, as noted on the right side of the options menu.
This main menu allows you to:

 Take a snapshot
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To take a snapshot of the current waveform view, press the “s” key or right-click on
the plot and select Snapshot from the options menu. You have the choice of either
.png or .gif formats for the saved snapshot. The default format is .png due to it’s
small file size.
 Delete a plot, Delete all plots, and Delete other plots (other than the current plot).
Using the Navigation Sub-Menu

From the options menu, select Navigation. The following sub-menu appears.
Using this sub-menu, you can do the following:

 Select a Zoom Style (Zoom x only, y only or x & y (default)).
 Zoom-in, Zoom-out, and fit area
 Pan a waveform in different directions.
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Using the Measurement and Annotation Sub-Menu

From the options menu, select Measurement and Annotation. The following sub-
menu appears:
Using this sub-menu, you can also do the following:

 Mark a data point. Simply hover the cursor over any area on a waveform and
press the “m” key or select Mark data point from this menu.
 Delete all data point markers on plot or on all plots
 Add a note (for more information see Adding Notes to a Plot).
 Delete notes on a plot.
 Toggle the ruler feature (form more information on using the ruler, see Measuring
the Distance Between Two Data Points..
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Using the Display Options Sub-Menu

To make changes to the way the waveforms display, select Display Options from the
options menu. The following sub-menu appears:
Using this sub-menu, you can do the following:

 Increase/decrease height of one/all plots by 20 percent.
 Increase/decrease waveform thickness.
 Toggle grid, which displays/hides a grid on the plot.
 Toggle background color, which switches the background from black to white and
back again.
 Toggle x-axis linear vs. log (Beta), which allows you to look at the x-axis in linear
values vs. log scale (for example, ticks would be 1,2,3,4 vs 1,10,100,1000).
 Transform Y axis to decibel (Beta). This is useful for generating bode plots from
some analog signals.
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Adding Notes to a Plot

At some point, you may want to share a snapshot of a waveform, either through
email or as a slide in a presentation. To save a snapshot of a particular waveform,
You may want to explain a detail about the plot or highlight a particular area of
interest.
Use the following process add notes to a waveform and take a snapshot:
1. Bring up the desired waveform view.
2. Press the “n” key or right-click on the plot to bring up the note window.
Alternately, you can right-click on any waveform and select Measurements and
Annotation > Add a note.
3. Type in the note content and click OK.

The note will be added at the point where you originally clicked on the waveform.
Additional note manipulations available:
 To move a note to a different location, simply click and drag it.
 To edit the contents of a note, simply double-click it. Deleting all contents in a note
will delete the note.
 To delete a single note, double-click an existing note to bring up the note window
and click the Delete Note button. To delete all notes from a plot, select
Measurements and Annotation > Delete all notes on plot from the options menu.
Comparing Waveforms in the Same Plot

To put multiple waveforms in the same plot, you should select the Place in one plot
checkbox on the Find Waveforms tab before clicking the Add waveforms to plot area
button. If you already have individual plots, you can drag one waveform into the plot
of another. To do so, click anywhere on a waveform and drag it to the other plot.
Opening Tabs in a Separate Window

To open a tab in a separate window (also referred to as a tearing tab), click the ------
perforation the tab titles. This will open the tab in a separate window. Closing the
separate window will bring it back to its tab. This feature allows you to view the Find
Waveforms tab and View Waveforms tab side-by-side and see the waveform
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additions immediately as you click the Find button. This is more efficient than clicking
back and forth between tabs.
If you are a new user, you might want to tear the Tips tab for quick reference while
you are viewing the waveform tab. This is also useful for comparing time-domain
waveforms on the time domain tab against their frequency spectrum counterpart on
the frequency domain tab.
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191
Chapter 6
Getting Your Design into PowerArtist 6
Introduction
This chapter describes the command-line flow for creating a scenario file for Verilog,
VHDL and mixed-language designs. The designs may be RT level, gate level or
mixed RTL and gate. The one common command that you will be using is the
Elaborate command.
The scenario file is a binary representation of the hierarchical micro architectural
netlist for your design. This chapter includes simple command examples to help you
understand the flow. More complex examples of commands can be found in the
examples/command_files directory.
You can create your scenario file from the command line (or from the PowerCanvas).
For either approach, you must first make sure the PowerArtist design environment is
set up correctly, as described in Installing and Setting Up PowerArtist.
 Command-Line Flow for Verilog
 Command-Line Flow for VHDL
 Command-Line Flow for Mixed-Language Designs
 Creating Your Map Files
 Creating Custom VHDL Packages
 Defining Libraries for Command-Line Use
 HDL Advanced Topics
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CHAPTER 6 — Getting Your Design into PowerArtist PowerArtist™ User Guide 192
Command-Line Flow for Verilog
Command-Line Flow for Verilog

This section describes how to prepare Verilog design files in order to elaborate your
design using Verilog files directly from the UNIX command line.
1. Ensure that the design successfully compiles in your target simulator and ideally
functions the way you expect.
2. Run the Elaborate command to create a scenario file for your design.
Syntax
Elaborate -scenario_file scn_file -top top_module
-verilog_startup_file startup_file
where startup_file is the Verilog startup file, scn_file is the full scenario file name
and top_module represents the root of your design.
Example
Elaborate -scenario_file my.scn -top top
-verilog_startup_file startup.vc
To get a list of all options available, see the Elaborate command in the PowerArtist
Reference Manual.
3. At this point, the flow becomes language independent. You will use the
CalculatePower and ReducePower commands to analyze your simulation
information and either run a power analysis or perform a power reduction.
Note that you might want to create run scripts that run these commands for you
instead of entering them directly on the command line. For sample scripts, see
Command-Line Flow for VHDL

Use the following process to perform power analysis using the command line for
designs that include VHDL.
1. Ensure that the design successfully compiles in your target simulator and ideally
functions the way you expect.
2. Generate your list of VHDL files that need to be compiled into the appropriate
libraries. There are three ways to do this:
— Automatically generate it using your internal processes just like you probably
generate your simulation compile script.
— Translate an existing command file format, like that used for your simulator of
choice to the PowerArtist format.
— Run the map-file/makefile/ptCompileScript option.
The flow described next covers the map-file approach.
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Command-Line Flow for VHDL
a. Build a mapping file that describes the names of all of your VHDL libraries and
the files you want to compile into them. For more detail, see section Creating
Your Map Files.
b. Build “Makefiles” using the mapping file generated during step a by running the
wwvmkr utility. These Makefiles define rules that compile your VHDL design
units in the correct order to meet VHDL language requirements, where all
design units must be compiled before they can be referenced. For more detail,
see section Running the wwvmkr Utility.
c. Run the ptCompileScript utility. This utility executes “make” on all of your
makefiles created in step b, determines all of the libraries and files used in your
design, generates a file, ptSourceFiles.tcl, that contains a series of CompileFile
commands that compile each of your VHDL files into the correct library in the
correct order. See Contents of the ptSourceFiles.tcl File file for a sample of what
this file looks like.
3. Generate a scenario file using the Elaborate command to analyze, elaborate, and
infer your design.
Syntax
Elaborate -top top_module_name -scenario_file scenario_name
where ptSourceFiles.tcl is the file generated by ptCompileFileScript,
top_module_name is the VHDL top-module name and scenario_name is the full
scenario file name.
Example
Elaborate -top top -scenario_file my.scn
4. At this point, the flow becomes language independent. You will use the
CalculatePower and ReducePower commands to analyze your simulation
information and either run a power analysis or perform a power reduction.
Note that you might want to create run scripts that run these commands for you
instead of entering them directly on the command line. For sample scripts, see
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Command-Line Flow for Mixed-Language Designs

Whether you compile on the command line, using a script or from the PowerCanvas,
you need to ensure that your design files contain instantiations and declarations of
modules (or entities) from different languages. In PowerArtist, you compile mixed-
language design at one time, which allows you to leverage information from your
mixed-language simulation environments.
VHDL Designs with One or More Verilog Modules

Before you compile a VHDL design that instantiates one or more Verilog modules,
you must ensure that:
 The VHDL source files contain a component declaration and an instantiation for
each Verilog module. The component must have the same name as the
corresponding Verilog module. The component ports must have the same name,
ordering, size and direction as the ports of the corresponding Verilog module.
 For example, your VHDL source files could contain the following component
declaration for a Verilog module, LEAF:
-- component declaration for the verilog module LEAF

component LEAF
port( I1, I2 : in bit_vector(1 downto 0 );
OUTPUT : out bit_vector(1 downto 0 ));
end component;
 It would also contain an instantiation of LEAF:
-- component instantiation of LEAF

INST_LEAF : LEAF
port map(I1(1 downto 0), I2(1 downto 0), OUTPUT(1 downto 0));
 The Verilog source files must contain definitions of the modules. For example,
your Verilog source files could contain the following definition of LEAF:
module LEAF (I1, I2, OUTPUT );

input [1:0] I1, I2;
output [1:0] OUTPUT;
...
endmodule
Verilog Designs with One or More VHDL Modules

Before you compile a Verilog design that instantiates one or more VHDL modules,
you must ensure that:
 The Verilog source files contain instantiations of VHDL entities/architectures. For
the module type name in the instantiation, the user must escape the work library
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name followed by the entity name and optionally append the architecture name in
parentheses:
\work_lib_name.entity_name(arch_name)
 The following uses are also allowable as long as they are un-ambiguous and
represent legal VHDL references:
entity_name(arch_name)
entity_name
 The instance ports must have the same ordering, size and direction as ports of the
corresponding VHDL entity. For example, your Verilog source files could contain
the following instantiation for a VHDL module, LEAF:
module top_level(..., I1, I2, OUT);

...
input [1:0] I1, I2;
output [1:0] OUT;
...
// work is the VHDL work library, LEAF the entity name,
// and RTL is the corresponding architecture
\work.LEAF(RTL) inst(.I1(I1), .I2(I2), .OUTPUT(O1));
...
endmodule
The VHDL source files must contain definitions of the modules. For example, your
VHDL source files could contain the following definition of LEAF:
entity LEAF is
port( I1, I2 : in bit_vector(1 downto 0 );
OUTPUT : out bit_vector(1 downto 0 ));
end;
Case Sensitivity
Case sensitivity is critical when matching design names supplied in external files like
net names in SPEF files or clock files, or instance or module names in options such
as -top. By default, the scenario database is constructed to be case sensitive if the
design is entirely in Verilog, or case insensitive if the design is VHDL or combination
of VHDL and Verilog.
If you have a mixed-language design and you make it case sensitive, all VHDL
identifiers will be expected to be upper-case and Verilog identifiers will be kept as
they were in the Verilog source files. In a mixed design, you might want to make it
case sensitive if, for example, you happened to have two Verilog identifiers that
differed only in case and you want to search for them in an application such as
power reduction (ReducePower).
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Compiling Mixed-Language Designs in a Single Run

Using the Elaborate command, you can compile both Verilog and VHDL source into
a single scenario database file. With this method, PowerArtist searches first to match
Verilog instances with a Verilog module definition, and then a VHDL entity-
architecture pair. Likewise, PowerArtist will search first to match VHDL instances with
a VHDL entity-architecture pair (if no configuration is specified) and then with a
Verilog module.
Using a Command-Line Flow

The Elaborate command can read both a Verilog startup file (specified with the -
verilog_startup_file option) and a script to compile VHDL source files (specified with
the -compile_script option).
Example
Elaborate -top my_lib.my_design_unit -scenario_file my_chip.scn
-verilog_startup_file my_file.f -compile_script ptSourceFiles.tcl
Alternatively, you can specify Verilog files and VHDL files together using a series of
CompileFile commands in a script passed to Elaborate using the -compile_script
option.
Sample Script
CompileFile -type verilog -file my_verilog.v -2001 yes
CompileFile -type vhdl -library toplib -file my_top_vhdl.vhdl
AddLibrary STD
CompileFile –type vhdl –library STD -file standard.vhd
AddLibrary IEEE
CompileFile –type vhdl –library IEEE -file std_1164.vhd
AddLibrary WORK
CompileFile –type vhdl –library work -file mydesign.vhd
To see a complete syntax for the CompileFile command.
Using the PowerCanvas

If you are using the HDL Inferencing wizard in the PowerCanvas, on the Language
setup screen be sure to check both the Verilog and VHDL boxes for a mixed-
language design and continue as you would for any design. For details see,
Performing Design Inferencing Using the HDL Inferencing Wizard.
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Creating Your Map Files
Creating Your Map Files

Each file that you supply to the wwvmkr utility must include the following:
 The names of your VHDL logical libraries.
 The UNIX file location of the compiled VHDL libraries and file dependency data
used by your Makefiles.
 The VHDL file names to be compiled into your VHDL logical libraries.
Sample Mapfile Syntax
map LIB1 ./ww_lib1 \

/home/tmiller/unit1 -i {unit1a.vhdl unit1b.vhdl} \
/home/gramirez/stypes -i {type1.vhdl type2.vhdl}
This statement indicates the following:

 The keyword map indicates that a “map” statement is coming. Line continuations
are indicated by a trailing backslash (\).
 LIB1 is the logical name of a VHDL library.
 LIB1 is being compiled into physical library location ./ww_lib1.
 There are two UNIX directories that contain VHDL source to be compiled into
logical library LIB1: unit1 and stypes.
 For unit1, the files to be included (-i) from that directory are unit1a.vhdl and
unit1b.vhdl. For stypes, the files to be included from that directory are type1.vhdl
and type2.vhdl.
It is strongly recommended that you use the VHDL standard libraries supplied with
the PowerArtist distribution and not the libraries provided with your simulator when
running PowerArtist. Using the PowerArtist libraries ensures that the pragmas
needed by the VHDL compiler have been inserted in the libraries.
The synonym Statement

If you are using ModelSim as your simulator, you may need to supply one additional
map file statement. This simulator lets you create synonym libraries. Different logical
library names may point to the same physical location. The synonym statement
maps a new logical library name to a previously specified logical library name. For
example, once IEEE appears in a map statement, it can be followed with the
synonym statement:
synonym SYNOPSYS IEEE
Now SYNOPSYS and IEEE point to the same location. The order of the parameters
is new name then old name.
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Running the wwvmkr Utility
Running the wwvmkr Utility

The PowerArtist wwvmkr utility reads in a map file—created either by hand, an
automated process or by make_mti_mapfile—and builds makefiles that you use to
compile your design.
Example
wwvmkr -m mapfile -w work
This command builds the Makefiles in your local working directory, following VHDL
93 rules. The top-level logical library is work (this is case-insensitive). You will next
execute the ptCompileScript, which calls the script wwcompile generated by your
wwvmkr run.
Example
ptCompileScript
This will create a file called ptSourceFiles.tcl that you need to source before you
specify the Elaborate command.
Contents of the ptSourceFiles.tcl File

The ptSourceFils.tcl file is a Tcl file that contains the following sections:
 Definitions of all of the standard libraries and the source files that define them.
 AddLibrary commands that map logical library names to physical libraries. A
typical AddLibrary command would be:
AddLibrary WORK /system/u/demouser/work
 CompileFile commands, providing file names, libraries, and VHDL standards (87/
93) to apply when compiling. A typical CompileFile command would be:
CompileFile -file test.vhdl -library /system/u/demouser/work -87 yes
These commands are written so that they support the legacy flow of pre-compiled
libraries. CompileFile can simply skip the physical-to-logical mapping and accept a
logical library name:
CompileFile -file test.vhdl -library WORK -87 yes
Note that the library name in this case must match a logical library name
previously defined in an AddLibrary command.
For complete syntax, see ptSourceFiles.tcl File Format in the PowerArtist Reference
Manual.
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Metacomment Processing
Metacomment Processing
VHDL is a strongly typed language and, furthermore, since you can create many
different types, frequent use is made of functions and procedures to provide type
conversion and to overload arithmetic and Boolean operators for your defined types.
When Elaborate processes your design, it analyzes the VHDL into equivalent
hardware elements ranging from simple gates to more complex blocks such as
adders, memories etc. In many cases, sub-programs used to overload operators and
to perform type conversions etc., contain VHDL which has no practical hardware
implementation and if included in the elaboration process would impair the accuracy
of the power analysis.
For example, the conversion of a STD_LOGIC_VECTOR to an INTEGER has to be
performed with the CONV_INTEGER function to satisfy VHDL syntax and semantics,
but from a hardware point of view the two types have the same representation and
so the CONV_INTEGER function passes the STD_LOGIC_VECTOR argument bit
for bit through to the INTEGER return value. To accomplish this without interfering
with the VHDL simulation, use is made of special comments embedded in the VHDL
source code. These special comments are called metacomments and are often of
the form:
-- pragma keywords
For example, to pass a function argument of STD_LOGIC_VECTOR to an INTEGER

can be achieved by including the following metacomment in the declaration section
of CONV_INTEGER:
-- pragma BUILT_IN SYN_UNSIGNED_TO_INTEGER
When Elaborate encounters this metacomment, it passes the argument bit for bit to
the return value and bypasses the body of the function. You can tell Elaborate to
ignore a section of VHDL (for example, sections that might contain TEXTIO
statements) as follows:
-- pragma translate_off
.. some VHDL to ignore..
-- pragma translate_on
For your convenience, PowerArtist can handle the class of metacomments used by
Synopsys which are included in the packages they distribute. So if you use these
libraries you don’t need to be concerned about inserting your own metacomments to
ensure that the elaboration process infers appropriate hardware from your VHDL.
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Creating Custom VHDL Packages

PowerArtist supplies all the standard Synopsys and IEEE VHDL standard libraries as
part of its distribution. These are all located in the following directory:
$POWERTHEATER_ROOT/pthdl_src
You might need to substitute these standard definitions with ones supplied as part of
your company’s standards. If you need to do this, you will have to provide the
Elaborate command with the location of these new standard library files. There are
two techniques to make this happen. The first and recommended technique requires
you to modify the PowerArtist installation directory. The second requires you to
compile Elaborate with multiple compile_scripts.
Technique 1: Modifying Your Installation

In the pthdl_src directory, you will notice two files:
 stdlibs.87.map
 stdlibs.93.map
Normally, these files are automatically read by the wwvmkr command depending on
the language standard you are following: stdlibs.87.map for VHDL 87 designs or
stdlibs.93.map for VHDL 93 designs.
These map files have identical syntax to the ones that you use to define the file/
library matching for your own design. These map files define three standard libraries
by default: IEEE, STD and SYNOPSYS. If you want to add or delete a file from one
of these three standard libraries, just edit the appropriate map file line. For example,
if you are a Synopsys user you might want to add support for Cyclone to their
SYNOPSYS library for all VHDL 93 designs. In this case, you might want to modify
the file in the following way:
map SYNOPSYS ww_synopsys $r -i syn_attr.vhd \

/my-cyclone-directory-path -i cyclone.vhd
Then run wwvmkr and ptCompileScript just like you have done in the past.
Technique 2: Multiple Compile Scripts

1. Using the AddLibrary and CompileFile commands, compile the base packages for
your design into a script called, for example, myBaseFiles.tcl.
AddLibrary STD
CompileFile -library STD -file mydir/standard.vhd
AddLibrary IEEE
CompileFile -library IEEE -file mydir/std_logic_1164.vhd
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2. Create the compile script for the remainder of the design as follows:
wwvmkr ## creates make files for VHDL design

ptCompileScript -c ## sources make files, creates ptSourceFiles.tcl
The wwvmkr run would be identical to that used by someone using the
PowerArtist standard supplied libraries. When you run ptCompileScript with the -c
option, PowerArtist generates a ptSourceFiles.tcl file that does not contain any
information related to PowerArtist standard libraries. The -c suppresses this
output.
3. Source the compile scripts and run the Elaborate command:
Example
source myBaseFiles.tcl
Elaborate
Each of the sourced files must follow the format for a standard compile script. The
Elaborate command reads and processes the scripts in the listed order.
Consequently, due to VHDL semantic rules, any design unit you need defined
must appear before it is referenced. In short, your standard libraries must get
compiled before all other files and they must be in the correct order.
In the sample script in step 1, the standard.vhd file which is compiled into STD
must be compiled before std_logic_1164.vhd is compiled into IEEE. Since these
two files appear in myBaseFiles.tcl they are automatically compiled before the
files defined in ptSourceFiles.tcl.
Keep in mind that this is a standard Tcl file. You can use standard Tcl features to
locate your particular libraries using environment variables and Tcl variables. For
example, the myBaseFiles.tcl script could be re-written as:
global env
set path $env(VHDL_STD_DIR)

AddLibrary STD
CompileFile -library STD -file $path/standard.vhd
AddLibrary IEEE
CompileFile -library IEEE -file $path/std_logic_1164.vhd
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Defining Libraries for Command-Line Use
Defining Libraries for Command-Line Use

Technology-specific information is supplied using Liberty format library files. To
specify these Liberty libraries, you can use one of two methods: the -synlib_files
option or the ReadLibrary command.
You can use the -synlib_files option (available with several commands) to specify
your Liberty library files, for example:
Elaborate -synlib_files {mylibrary1.lib mylibrary2.lib}
-verilog_startup_file my.vc -scenario_file mychip.scn -top core
This example loads two libraries called mylibrary1.lib and mylibrary2.lib.
You can also use the ReadLibrary command to specify Liberty files, for example:
ReadLibrary mylibrary1.lib
If you specify such a large number of ReadLibrary commands that the command line
generated to perform an elaboration, power calculation, power reduction or rewrite
would exceed the Unix limits on command-line size, PowerArtist automatically
generates a file called ptshell.libs.opts that contains the Liberty library names. This
file then gets referenced using the -i option to various commands.
HDL Advanced Topics

This section provides information on several advanced HDL topics.
Using Power Macros

The PowerArtist elaborate process supports power macros. This allows you to
replace HDL models written for simulation with more synthesis-aware and power-
aware models without modifying your design source. This is useful for the following
situations:
 You are using DesignWare™, which contains many models that are not
synthesizable, and you want to create some models that more closely represent
what would be synthesized.
 Your designers have used simulation models in their design to improve simulation
performance and you wish to replace those models with versions that would
normally be synthesized.
Apache provides a default set of power macro models that contain definitions to
replace some of the simulation models from the base DesignWare™ library. The
Elaborate command looks for these macro models in a power macro directory. The
default location for this directory is
$POWERTHEATER_ROOT/pthdl_src/macros
You can provide a different directory name using the Elaborate -
macro_directories option. This directory must contain:
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HDL Advanced Topics
 A set of Verilog source files that contain module definitions.

 A mapping file, named MacroMap, that specifies the name of each module to be
replaced in the design and the name of the module with which to replace it. The
name of each Verilog file should be the same as the name of the module plus the
.v extension. The Verilog module must be port compatible with the module it is
replacing. This also works for VHDL designs following standard conventions that
ensure that a VHDL architecture can instantiate a component written in Verilog.
For example, the macro directory can contain a macro map file that includes the
following line:
originalAndGate myAndGate
In this example, the macro directory must also contain a Verilog file named
myAndGate.v, which contains the module definition for the module myAndGate. The
elaborate process will mark all occurrences of Verilog modules or VHDL entities of
originalAndGate. It compiles myAndGate.v and replaces instances of
originalAndGate with the model constructed from myAndGate. It also applies any
parameters or generic values to this new model. The scenario database that
Elaborate produces contains instances of myAndGate where originalAndGate had
previously occurred.
Apache has modeled the following components that can be mapped onto the base
DesignWare™ library:
 adder
 adder/subtracter
 decrementer
 incrementer
 subtracter
 absolute value
 simple multiplier
 2-6 stage pipelined multipliers
 wallace tree multiplier
 partial multiplier
If you use DesignWare™, you do not have to do anything to take advantage of this
feature. By default, PowerArtist automatically substitutes any modules it finds in the
macros subdirectory. If you have created your own power macros and cannot install
them into the macros subdirectory, then you must use the Elaborate
-macro_directories option to point to the directory containing the power macros. If
you use multiple directories, use a Tcl list to specify the directories, as shown in the
following example:
Elaborate -macro_directories {dir1 dir2 dir3 ...}
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HDL Advanced Topics
Overriding Parameter Settings for Top-Level VHDL or Verilog

Modules
The PowerArtist elaborate process includes an option you can use to assign a value
to a top-level VHDL or Verilog module. The -parameter_maps option allows you to
override parameter settings, including generics.
For example, suppose you have the following Verilog (or equivalent VHDL fragment:
module top(in,out);
parameter size=2;
input [size-1:0] in;
output [size:0] out;
assign out = in+1;
endmodule
You could override the size parameter by adding the -param_map option to your Tcl
command file:
Elaborate -param_map {size=4} ...
When PowerArtist elaborates the Verilog design, size would be set to 4. If you have
multiple parameters you want to override, you can specify a Tcl list of parameters.
For example:
Elaborate -param_map {p1=4 p2=5}
You can also use the -param_map option to set generics. Take, for example, the
following VHDL fragment:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS
GENERIC(SIZE : integer);
PORT ( AA, BB, TT : IN STD_LOGIC_VECTOR(SIZE-1 downto 0);
CC : OUT STD_LOGIC_VECTOR(SIZE-1 downto 0));
END TOP;
ARCHITECTURE A0 OF TOP IS
BEGIN
CC <= BB AND TT;
END A0;
Given this fragment, you could add the following lines to your Tcl command file to set
the SIZE parameter:
Elaborate -param_map {size=4}
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HDL Advanced Topics
Controlling Array Inferencing

When a two-dimensional array is modeled in Verilog RTL, the array may be inferred
in one of two ways: either as a single two-dimensional register file or latch file, or as
a collection of individual state devices (registers and latches) with read and write
address decoding logic. For large arrays, register or latch files provide the best
balance of analysis accuracy versus capacity and power analysis performance. For
small arrays, the PowerArtist power analyzers can better account for clock gating
and other synthesis effects when inferencing maps an array to individual state
devices.
The Elaborate command provides options that allow you to control array inferencing.
You can use these options to tell PowerArtist to “blast” arrays into a combination of
state devices and the supporting control logic rather than to infer a single register or
latch file.
If you make extensive use of arrays and you plan to clock gate the registers that will
ultimately be synthesized, then you should take advantage of these options to force
bit blasting to occur in as many places as possible. The following options all use the
name “regfile”. These options must also be used for instances that would ultimately
be inferred as a latch file. There is no separate -blast_latchfile option as an example.
The options for bit-blasting are:
-blast_regfile list | all
Specifies either a Tcl list of 2-D arrays to bit-blast or all (all arrays will be bit-
blasted).
-preserve_regfile list | all
Specifies either a Tcl list of 2-D arrays to be preserved or all (all arrays will be
preserved).
-min_regfile_bit_count int
Specifies a minimum bit count (words x length) of 2-D arrays to be preserved as
register files or latch files.
Default: 32
-min_regfile_word_count int
Specifies a minimum word count for 2-D arrays to be preserved as register files or
latch files.
Default: 8
-min_regfile_word_length int
Specifies a minimum word length for 2-D arrays to be preserved as register files or
latch files.
Default: 3
The format for 2-D arrays to be provided to either blast_regfile or preserve_regfile is:
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HDL Advanced Topics
module_name.array_name
If the 2D array is used in a named block, generate statement or other named scope
in your Verilog, you must include that scope value. In this case, the name is of the
form:
module_name.scope_name.array_name
Application of the Options

You need to specify these options to the Elaborate command. The options are
applied by PowerArtist in the following sequence:
1. Any two dimensional arrays named with -blast_regfile or -preserve_regfile are
marked to be blasted or preserved respectively.
2. If either “-blast_regfile” all or “-preserve_regfile all” is specified, then all remaining
arrays are blasted or preserved as directed.
3. Otherwise, for each array, the word length, word count, and total number of bits
(determined by word count times the word length) are compared with the
minimum limits for register files. You may set these limits using the -min_regfile_*
options. If any of these are lower than the specified or default limits, then the array
is marked to be blasted.
Examples
The following Verilog examples show how you would translate the names in your
Verilog to the names required in the bit blasting options. All of the examples show
how the array names would be used in the -preserve_regfile option.
Example 1: Simple use
module top(clk, wen, wadr, wdata, radr, rdata);
<snip> ....
always @(posedge clk)

begin
reg [5:0] myRam [15:0];
if (wen)
myRam[wadr] = wdata;
rdata = myRam[radr];
end
In this case, the array name would be:
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HDL Advanced Topics
Elaborate -preserve_regfile top.myRam
Example 2: Named begin block

<snip> ....

begin : myblock
reg [5:0] myRam [15:0];
if (wen)
end
In this case, the array name as specified with the -preserve_regfile option would be:
Elaborate -preserve_regfile top.myblock.myRam
Example 3: Nested named begin block

<snip> ....

begin : myblock
begin : mysubblock
reg [5:0] myRam [15:0];
if (wen)
end
end
Elaborate -preserve_regfile top.myblock.mysubblock.myRam
Example 4: Generate Statement

<snip> ....
genvar i;
generate
for(i = 0; i < 4; i = i+1)
begin : blk

begin : myblock
begin : mysubblock
reg [7:0] myRam [31:0];
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HDL Advanced Topics
if (wen)
myRam[wadr] = wdata[i*8+3:i*8];
rdata[i*8+3:i*8] = myRam[radr];
end // mysubblock
end // myblock
end // blk
endgenerate
Elaborate -preserve_regfile top.blk.myblock.mysubblock.myRam
Note that the scope name for the generate block must be specified without the
[index] for each genvar iteration. The option applies to all generated copies of the
block, so that all copies of “myRam” get preserved.
Notes, Warnings and Error Messages

With respect to register file and latch files, you will see two different Warning
messages in your Elaborate.log file. If blasting occurs, you will see Warning 12000.
An example is:
Warning 12000: design.v:12 3x4 memory myRam not recognized as dual-
port RAM. Will be bit-blasted.
If blasting does not occur, you will see Warning 2859. An example is:
Warning 2859: design.v:15 inferred regfile instance myblock:myRam
with data width of 6, address width 4.
The Elaborate command generates no Notes or Error messages specific to bit

blasting. Note that in some cases, the colon “:” separator is printed for named
scopes. The Elaborate regfile options require that scope names be specified using a
dot “.” separator only.
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209
Chapter 7
Preparing for Power Analysis 7
Introduction
This chapter describes the steps required before you can run power analysis or
reduction. It includes information on setting net capacitance, handling designs with
multiple power supplies and libraries and clock power specification.
 Estimating Net Capacitances
 Using PACE Technology Files During Power Analysis (Beta)
 Estimating Pin Capacitance
 Handling Voltages in Liberty Format
 Handling Designs with Multiple Power Supplies
 Running RTL Mixed-Vt Power Analysis
 Setting up Clock Power Analysis
 Setting up Clock Gating for Power Analysis
 Setting up Clock Gating for Power Reduction
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CHAPTER 7 — Preparing for Power Analysis PowerArtist™ User Guide 210
Estimating Net Capacitances

Accurately estimating dynamic power in your design requires good estimates of your
net capacitances; therefore, before you begin your power analysis, you need to
determine how you will provide net capacitance information to PowerArtist. You can
use any of the following methods:
 Back-annotate capacitances using SPEF. For details see, Back-Annotating
Capacitance Using SPEF.
 Back-annotate load capacitances for primary outputs using a PowerArtist
capacitance file. You can get output load information based on the package you
will use for your design. Capacitances files for this purpose should supply loads
representing output load capacitances. For details, see Using Back-Annotated
Load Capacitances for Primary Outputs.
 Specify a default output load capacitance value using the -default_output_load
option to CalculatePower. For details see, Specifying Default Output Load
Capacitance Using a Command Option.
 Back-annotate capacitances for local signal nets using a PowerArtist capacitance
file. RTL floorplanners may be able to generate signal capacitances. This format is
most often used for RTL and mixed RTL/gate designs. If you are back-annotating
signal capacitances, you can only choose one format. You cannot mix SPEF and
wiring capacitances files. For details see, Using Back-Annotated Wiring
Capacitances for Local Nets.
 Specify a Power Artist Calibrator and Estimator (PACE) technology file (using the -
power_tech_file option) to estimate net capacitance for RTL, mixed RTL/gate or
gate-level designs. PACE files are also used for clock distribution network
modeling. For details on how to use a PACE file see, Using PACE Technology
Files During Power Analysis (Beta).
 Allow PowerArtist to use wire load models to estimate signal capacitances. This
can be used for either RTL and mixed-RTL and gate or for pure gate-level netlists.
You can set the wire load models using Tcl commands. For details see, Specifying
Wire Load Models.
 Allow PowerArtist to use default wire load models. For details see, Using Apache
Default Wire Load Models for Capacitance Analysis.
All nets not explicitly listed in a net capacitance file have their capacitance, length,
and routing-area values estimated from capacitance models either available in your
technology libraries or supplied automatically by PowerArtist. If you want no net
capacitance estimation to be performed, then you must supply the “-
no_module_net_capacitances true” option to the CalculatePower and ReducePower
power commands.
If you are using one of the capacitance file formats to back-annotate capacitances
onto your nets, PowerArtist performs two different checks. First, it generates a
warning message for every net in your back annotation file that it can’t find in the
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scenario file. Second, it generates a warning message for every net in the scenario
file that was not back-annotated after all back annotation files have been processed.
Back-Annotating Capacitance Using SPEF

This method is most often used for gate-level designs that have been placed and
routed. Note that SPEF files can be gzipped. PowerArtist determines if a file is
gzipped by examining the first bytes of the file (not by the file extension).
Note that only simple, lumped RC SPEF is supported.
If you only have one SPEF file that covers the entire design, use the -spef_file option
with the CalculatePower command, as in the following example:
CalculatePower -scenario_file my_chip.scn -spef_file my_chip.spef
Otherwise, you will be using the hierarchical flow as described next.
Hierarchical SPEF Processing

You have the option of providing parasitic information using hierarchical SPEF files.
PowerArtist supports two different flows:
 You can specify the list of SPEF files using the SetSpefFiles command and the top
SPEF design name using the SetTopSpef command. The SPEF reader will then
determine the hierarchy by going through the instantiations in the SPEF files (by
looking at the “*DEFINE” statements), and then processing them.
 Alternatively, you can specify a hierarchy (hierarchical instance) in the design
along with the SPEF file associated with it, using the ReadParasitics command.
The two flows are mutually exclusive. The SPEF reader will generate an error if the
flows are mixed. To use the flow involving “*DEFINE” records, you will need to
specify two separate commands: SetSpefFiles and SetTopSpef.
SetSpefFiles {file_name(s)}
This command provides the SPEF reader with all the files that you want to process
(you can specify a single SPEF file). The SPEF reader performs a rapid “read” of
these files to determine their associated design names. These design names must
later be referenced in “*DEFINE” statements following the SPEF specification.
SetTopSpef top_design_name
This command tells the SPEF reader the name of the design that forms the root of
your SPEF hierarchy. Typically, this maps to the top-level design unit in your design
hierarchy. The design name is then used to find the top-level SPEF file, which is
read. As the SPEF reader encounters *DEFINE statements, the other SPEF files are
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located and read-in. This command is not required when you specify only one SPEF
file.
Sample SetSpefFiles and SetTopSpef Commands
SetSpefFiles { top.spef middle.spef bottom.spef }
SetTopSpef top
If you want to use a flow that follows SPEF back-annotation methodologies

established by industry standard timing analysis products, then you need to include
the ReadParasitics command in your PowerArtist command file (Tcl script).
ReadParasitics -path hierarchical_inst_name -file SPEF_file_name
This command associates a particular SPEF file with a specific hierarchical instance
in the design. The instance name must be fully rooted (that is, it must contain the top
module name). Also, in PowerArtist, periods (.) separate levels of hierarchy.
Sample ReadParasitics Commands
ReadParasitics -path mydesign -file ../spef/mydesign.spef
ReadParasitics -path mydesign.mymodule0 -file ../spef/mymodule.spef
ReadParasitics -path mydesign.myblock1 -file ../spef/myblock.spef
Do not use the SetSpefFiles or SetTopSpef commands if you are using the
ReadParasitics command.
Handling SPEF Comments

To ignore C-style comments, you can include the SetCCommentsIgnore command.
This command is identical to the -iscc option. This command indicates that C-style
comments should be ignored in the SPEF file.
A sample line that contains a C-style comment is:
*NAME_MAP
*1931 buffer/read_rc1/buf_rp_read/*suffix*/a
If you are ignoring C-style comments, the exact string is taken as the net name.
You need to be aware of the following points when using these new commands:
Important Notes
 Do not use the -spef -spef_file and any of the hierarchical SPEF commands
together this will cause an error.
 This reader does an incremental back-annotation. If a net already has parasitics
associated with it, the parasitics specified in the SPEF will be added to them.
 If a net specified in the SPEF file is not found in the design, a warning is reported.
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Using Back-Annotated Load Capacitances for Primary Outputs

You can specify load capacitances for any primary output of the design by specifying
the output pin name and capacitance for that pin. The format of the capacitance file
is provided in the Capacitance File Format section of the PowerArtist Reference
Manual. To specify a file containing load capacitances from the command line, use
the -load_file command option as shown in the following example:
CalculatePower -scenario_file my_chip.scn -load_file my_chip_lds.cap
Specifying Default Output Load Capacitance Using a Command

Option
You can specify default output load capacitance using the -default_output_load
option to CalculatePower.
CalcultePower -scenario_file my_chip.scn -default_output_load 3.9e-11
You should always specify output loads. This is especially true if you have pads
instantiated in your design. If you supply a default load value using the -
default_output_load option or have annotated your loads using the -load_file option,
then you will not get messages about your primary output nets. Primary input nets
will not be flagged as missing annotations since capacitances on primary inputs have
no impact on power consumption.
Using Back-Annotated Wiring Capacitances for Local Nets

You also have the option of specifying a capacitance file that include capacitances
for local nets including primary outputs. To specify a wiring capacitance file, use the
CalculatePower -capacitance_file option.
CalcultePower -scenario_file my_chip.scn -capacitance_file my_chip_wirecaps.cap
Specifying Wire Load Models

Using Apache Tcl commands, you can set the wire load mode and models for your
design that the analyzers will use for power analysis. You can specify wire load
models at the following levels:
 The design level
 On an instance by instance basis hierarchically
 On a net by net basis
The following sections provide an overview of the various commands and
precedence rules used to select the wire load models. You can specify these wire
load models using either the SetWireLoadMode, SetWireLoadModel,
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SetWireLoadSelectionTable and SetCapEstimation Tcl commands or the -

wireload_library command-line option to CalculatePower or ReducePower.
Using the Wire Load Model Tcl Commands

The following table provides a quick synopsis of the available wire load Tcl
commands and the objects to which they apply:
Applicable Design
Object Tcl Command Valid Assignment Values
Design SetWireLoadMode Top or Enclosed
Design, Hierarchical SetWireLoadModel wire_load model from library file

Module Instance or Net
Design or Hierarchical SetWireLoadSelectionTable selection table group from

Instance library file
Design or Hierarchical SetCapEstimation wire_load model from Apache

Instance default library file
For details on how to use these Tcl commands in the command file, see Estimating
Pin Capacitance.
Rules for Estimating Wire Capacitance

Capacitance annotation takes precedence over capacitance estimation methods.
This section discusses precedence rules for capacitance estimation only. The Liberty
semantics define a hierarchy of defaulting rules that must be applied to determine
how tools should estimate capacitance using wire_load models.
The software first has to determine and locate the library to be searched for wire load
models. The software determines the correct library to be search by applying the
following rules in the given order:
1. If a SetWireLoadModel command explicitly supplies a logical library name, use
that library as the default library.
2. If there is no explicit specification of a logical library name and you have specified
the -wireload_library option, use that library as the default library.
3. Otherwise, select as the default library the first library that contains wire_load
models in the technology library list.
Once you have identified the library to search, then the commands themselves have
a set of hierarchical rules. The rules are:
1. The wire_load mode dictates how wire_load models of children instances are
assigned. If the mode is “top” assign the wire_load of the parent instance if a
parent exists and no commands pertain to this instance.
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2. If a SetWireLoadModel command has been specified for a particular instance, use

that model.
3. If a SetWireLoadSelectionTable command has been specified, locate the
wire_load selection table in the library, determine the area of the design, then
locate the area range and then determine the wire_load model. If the area does
not fall into a range specified by the selection table, choose the closest matching
range and use that wire_load model.
4. If a SetCapEstimation command has been specified, locate the wire_load model
in the Apache default capacitance file.
5. If no SetWireLoadSelectionTable command has been specified, look for the
selection table specified by the default_wire_load_selection attribute in the default
library. If such an attribute has been supplied, use the same rules as for
SetWireLoadSelectionTable to determine the wire load model.
6. If the default library contains no default_wire_load_selection attribute but it does
contain selection tables then:
— start from the beginning of the library file.
— find the first selection table that has a range with area limits that meet the area
requirements.
— if no such selection table exists, find the selection table that has the closest
matching area range.
7. If the default library does not contain selection tables, then use the wire_load
model specified by the default_wire_load_model attribute.
8. At this point, nothing has matched. Assume that the “SetCapEstimation
-technology 90 -scale 1” command has been specified. Follow the
SetCapEstimation rules to locate the wire_load model.
As you can see, the defaulting rules ensure that the power analyzers will always
estimate capacitance for your design. When all else fails, you will get capacitance
estimated using the default 90 nm technology libraries that come with the
PowerArtist installation. This is discussed in the following section. If you want to
suppress capacitance estimation completely, use the “-
no_module_net_capacitances true” command option (to CalculatePower or
ReducePower).
The wire load mode has default rules as well.
1. Use the mode specified by the SetWireLoadMode command.
2. If no such command has been specified, then use the default_wire_load_mode in
the default library being searched for wire_load models.
3. If the default_wire_load_mode is not found, then the default “enclosed” is used.
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Note
The power analyzers do not estimate the wiring capacitance of a net with no fanout. For
example, a primary output has no fanout; the only pin on the net is the driver. Therefore,
the estimators do not compute a wiring capacitance for it.
Using Apache Default Wire Load Models for Capacitance Analysis

Steps 4 and 8 in the previous section describe the conditions under which
PowerArtist will use the default wire load library that comes with the PowerArtist
installation. This section describes the reasons why you might want to use this built-
in library and what it contains.
Some sub-90 nm technology libraries (and smaller) no longer contain wire load
model information. Some technologists believe that wire load models are no longer
effective at predicting capacitance to a high enough accuracy for them to be used for
timing closure. Therefore, some companies no longer include wire load models in
their Liberty files. However, wire load models still have a strong role to play in power
analysis, especially at high levels of design abstraction.
If you do not have wire load models defined in your libraries and want to have wire
capacitance taken into consideration during power analysis using PowerArtist, you
can use the default wire load library that comes with the PowerArtist installation. This
default library has models for various technology sizes. Apache generated these
models based on experiences with a variety of technology sizes. It is recommended
that you use these libraries rather than not consider capacitance at all.
You can find the library in $POWERTHEATER_ROOT/sfl_lib/generic/seqcap.lib.
The file contains wire_load_selection tables for 180, 150, 130, 90, 65, and 45nm
technologies. To use this library for capacitance estimation, you must specify the
SetCapEstimation command or have no wire_load model information in any of your
technology libraries.
Unlike all of your other Liberty files, you do not need to specify the location of this file
using the -synlib_files option. The analyzers automatically locate this library and
insert it at the end of the library search path. Therefore, it is always available for use.
This library is read-only, so you can not accidentally modify it. However, once you
install the software you can modify it to create a site-specific set of technology
defaults.
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Using PACE Technology Files During Power Analysis (Beta)
Note on Using this Beta Feature

Before trying this beta feature/flow, please contact your Apache Design support team for
assistance.
To specify a PACE technology file, you need to include the -power_tech_file command
line option to the CalculatePower command in your run script. A PACE model file will
contain both capacitance models and clock distribution network models. The capacitance
models improve capacitance estimation accuracy. Similarly, the PACE clock
distribution network models improve the modeling of distribution network topology and
improve power analysis accuracy. The models apply to a pure gate level power analysis,
mixed gate and RTL or pure RTL.
PACE models are generated by a CAD engineer using PowerArtist commands. For
details on this process, see Generating PACE Technology Files (Beta) in the PowerArtist
Library Developer Guide.
Using Clock Distribution Network Models

The clock distribution network PACE models are designed to replace the SetClockBuffer
and SetClockGatingStyle commands as much as possible. Since they are frequency
dependent, you must specify the -frequency option to the SetClockNet command when
you specify a PACE model. You may also have to specify SetAttribute commands to
enable/disable the “dont_use” attribute in your Liberty library to control which clock
buffers or ICGCs may be chosen as a result of the electrical parameters stored in the
PACE model. The following run script provides a good example:
SetClockNet -name clk1 -frequency 5e+08 -mode infer -clock_gate yes

SetClockNet -name clk2 -frequency 2e+08 -mode infer -clock_gate no
SetClockNet -name clk3 -frequency 1e+08 -mode infer -clock_gate yes
SetAttribute -cell CKENAIAX8 -library typical -name dont_use -value false

SetAttribute -cell BUFX16 -library typical -name dont_use -value true

-scenario_file top.scn \
-synlib_files synlib.lib \
-verilog_startup_file verilog_files.vc \
-power_tech_file power.tech \
-top top \
-default_transition_time 64e-12 \
-domain_frequency_cell_selection true
Note the following points about this run script that uses a PACE model:
 The SetClockNet -frequency option is specified for all clocks in the design.
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 The SetAttribute commands in this script make certain that cell CKENAIAX8 is
considered as an ICGC, while buffer BUFX16 is not considered at all. You may
also set the PT_PACE_CLK_DONT_USE environment variable to false to ignore
the dont_use attribute when determining ICGCs and buffers from your Liberty
libraries. The behavior is, when you specify:
setenv PT_PACE_CLK_DONT_USE false
the “dont_use : true” Liberty attributes is ignored. When you specify:
unsetenv PT_PACE_CLK_DONT_USE
the “dont_use : true” Liberty attribute is honored.
 The final line in this script is the CalculatePower specification that includes the
PACE model specification by the -power_tech_file option and other required
parameters. Note that you can also specify the -power_tech_file option to the
ReducePower command.
Understanding Priorities and Precedence When Using PACE

Models
When using a PACE model, you must recognize the following priorities:
 Manual back annotation methods take precedence over PACE models. This
includes SPEF files, wire capacitance files, output load files and default output
load capacitance.
 PACE models will take priority over any wire load model-based capacitance
estimation technique you have applied. This includes SetWireLoadModel, default
wire load library lookups in Liberty files and the seqcap.lib default wire load model.
Also, it is your responsibility to determine that the PACE model is applicable to your
design. At a minimum, you should ensure that the technology node is the same as
the one used to create the PACE model.
Using the SetClockGatingStyle Command

You can use the SetClockGatingStyle command if you want explicit control over two
parameters. First, you can specify the -min_bit_width constraint. This overrides any
such value determined by the PACE model. Second, you can specify the -structure
option, which has the following syntax:
-structure branch | leaf
This controls whether ICGCs directly fanout to registers (leaf) or whether ICGCs can
fanout to buffers that then drive registers (branch). You can use this option to
increase analysis accuracy if you understand what will happen during CTS and
optimization of your design. By default, the branch or leaf value will be determined
when the PACE model is created and then that value will be applied to your design.
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You will see the impact of the -structure option in two different note messages that
are printed to your log file during a power analysis:
NOTE 9937 Clock net <name> drives <int> enabled register bits.
These registers are being considered for clock gating.
<int> ICGCs (with fanout=<int>) will be used to clock
gate these.
NOTE 9944 Clock net <name> drives <int> enabled register bits.
<int> <branch|leaf> ICGCs (with fanout=<float>) were used to
clock gate <int> registers. <int> registers were left ungated.
All other parameters specified with the SetClockGatingStyle command are ignored
when using a PACE model.
Additional Guidelines for Using PACE Models

PACE models affect the way some other PowerArtist commands are applied during
power analysis. Keep the following guidelines in mind when writing scripts that use
PACE models:
 Do not use the SetClockBuffer command with a PACE model. This command is
ignored completely. You will see warning 9932 if SetClockBuffer is specified along
with a PACE model file when performing a power analysis:
WARNING 9932: All SetClockBuffer command(s) in clock file foo.clk are

being ignored. Since clock power estimation is performed
using PACE file (aka power_tech_file).
 Do not specify the SetCellDefaultFanout command as it will have no effect when

used with PACE models.
 Do not specify arc-based estimation (“pt_set arc_based_estimation true”) when
using PACE models—you need to use the default pin-based estimation.
Understanding Output File Changes due to PACE Models

In addition to PACE-related log file messages, you will see additions to the report
files due to using a PACE model. For example, if buffers were identified using a
PACE model, the report file will have PACE explicitly identified, as in the following
sample output:
PACE Inferred Buffer Tree:

Net name : top.clk_2_0
Driver instance: top.U_2_0
Frequency : 100MHz
Number of Loads: 16
PACE Root Driver :
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Estimating Pin Capacitance
Cell : BUFX12
Library : typical
Count : 1
Buffer power: static 1pW; dynamic 32.5uW
PACE Branch Driver :

Cell : BUFX12
Library : typical
Count : 2
Buffer power: static 2pW; dynamic 65uW
PACE Leaf Driver :

Cell : BUFX12
Library : typical
Count : 4
Buffer power: static 4pW; dynamic 130uW
Estimating Pin Capacitance

PowerArtist recognizes the following .lib attributes, which are used to calculate pin
capacitance.
rise_capacitance_range (Min_rise, Max_rise)
fall_capacitance_range (Min_fall, Max_fall)
When you specify the -interpret_pin_caps_as option to the CalculatePower/
ReducePower commands, PowerArtist uses the rise_capacitance_range and
fall_capacitance_range attributes to calculate pin capacitances. The -
interpret_pin_caps option accepts the following values: min, max and avg.
CalculatePower -scenario_file my_chip.scn -interpret_pin_caps min
The actual pin capacitance values are calculated in the following manner:
 min: pin capacitance = (Min_rise + Min_fall) / 2
 max: pin capacitance = (Max_rise + Max_fall) / 2
 avg: pin captaincies = (Min_rise + Max_rise + Min_fall + Max_fall) / 4
The value you select will determine the manner in which PowerArtist calculates pin
capacitance. PowerArtist calculates pin capacitance using the following algorithm:
1. If rise_capacitance_range and fall_capacitance_range are present then calculate
it using the min, max or avg algorithm
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Handling Voltages in Liberty Format
2. Otherwise use the value from the capacitance pin-level attribute

3. Otherwise use the rise_capacitance and fall_capacitance attribute values
4. Otherwise set the pin capacitance to 0
If the -interpret_pin_caps_as option is not specified, then PowerArtist calculates pin
capacitance using the following algorithm:
1. Use the value from the capacitance pin-level attribute if present
2. Otherwise use the rise_capacitance and fall_capacitance attribute values
3. Otherwise use the rise_capacitance_range and fall_capacitance_range attribute
values following the “avg” algorithm.
4. Otherwise set the pin capacitance to 0
In the PowerCanvas, you can control pin capacitance using the Rise/Fall
Capacitance Range Interpretation field in the Advanced Options tab of the “Power
analysis options” page of the Power Reduction wizard.
Handling Voltages in Liberty Format

Normally, the characterization voltage is taken from the nom_voltage or from the
default power_rail attribute within the power_supply group. The estimation voltage
generally comes from the voltage set in the default_operating_conditions.
If no nom_voltage or default power_rail values are supplied, the characterization
voltage will come from values within the default operating conditions. If no
default_operating_conditions are supplied, the estimation voltage comes from the
nom_voltage or the default power_rail attribute within the power_supply group.
To get the dynamic power, PowerArtist derates the dynamic energy number by the
square of the estimation voltage divided by square of the characterization voltage.
For details about characterization and estimation voltages, see Liberty Power Supply
Support.
Any voltage you supply using the -voltage option to ReducePower will become the
estimation voltage for the entire design. Using -voltage is an obsolete technique that
has been replaced with the CreateVirtualSupply command. If the estimation voltage
does not equal the characterization voltage, voltage derating occurs.
Handling Designs with Multiple Libraries

If you have a hierarchical design, a Liberty library for one portion of the hierarchy
might not be suitable for a different portion of the hierarchy. In general, you might
want to do this because you are designing with multiple voltage domains or power
domains. More specifically, you might want to do this because:
 You have different operating conditions that you want to specify for different
modules.
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Handling Designs with Multiple Libraries
 You have a different set of cells that you want to be considered for default cell
selection for RTL power analysis.
 You synthesized your design to gates and used different libraries for various
blocks in your design.
Choices like these impact the power analysis of your chip. In PowerArtist, you can
assign Liberty libraries to hierarchical instances with libraries further down in the
hierarchy, overriding those higher in the hierarchy. All children of the hierarchical
instance inherit the library of the parent unless you specifically assign them their own
power library. You will control these choices using the SetLibrary command.
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Handling Designs with Multiple Power Supplies

Many designs use more than one power supply (or voltage rail). Common examples
include:
 A design with two voltage islands: one supply for the core of the chip and the
other for the I/Os.
 A design that uses power gating. The supplies to the power domains will need to
be explicitly turned on and off due to the use of sleep signals to put various power
domains of your chip in a stand by mode.
This section describes the ways in which PowerArtist Analysis supports designs with
more than one power supply. In addition, this section describes the special support
requirements for designs that require more than one power library (common in
hierarchical designs).
PowerArtist provides general support for multiple power supplies by:
 Allowing you to define additional power supplies, which are referred to as virtual
supplies.
 Allowing you to set virtual power supplies on an instance by instance basis.
Note that any changes to the power supply configurations should be completed after
generating a scenario file and before running any of the Power Wizards (power
analysis).
Creating a Virtual Supply

Creating virtual supplies is most useful for power gating applications. In this
application, you can define one virtual supply per library supply rail, per power
domain. This manner of creating virtual supplies supports the specification of on/off
conditions for power gating applications. To create a virtual supply, you will use the
CreateVirtualSupply command.
For voltage domain applications, you will at a minimum need the SetLibrary
command. You might also use the CreateVirtualSupply command to create virtual
supplies with different voltages than those defined as the default operating condition
in the library. If you provide a voltage, it becomes the estimation voltage and then the
library’s characterization voltage will be derated using the new estimation voltage
value. That new voltage will then be used to compute new energy and power
numbers. This flow incorporates the standard PowerArtist derating technique.
Assigning a Virtual Supply to a Hierarchical Instance

If you have a mixed-voltage design, you might want to explore the effects of
changing your voltage values. If your design is organized so that an entire
hierarchical sub-section of your design is at the same voltage, you can set the
correct values using the CreateDomain command.
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Liberty Power Supply Support

For a library with nom_voltage and operating conditions, the characterization voltage
is considered as the nom_voltage and the estimation voltage is picked up from the
default operating conditions.
Similarly, if a library defines multiple supplies using the power supply attribute as
nom_voltage : 1;
power_supply() {
default_power_rail : VDDlow;
power_rail(VDDhigh, 1.32) ;
power_rail(VDDlow, 1.32) ;
power_rail(VSShigh, 0.00) ;
power_rail(VSSlow, 0.00) ;
}
operating_conditions("BEST"){
process : 0.70;
temperature : 110;
tree_type : balanced_tree;
power_rail(VDDhigh, 1.00) ;
power_rail(VDDlow, 1.00) ;
power_rail(VSShigh, 0.00) ;
power_rail(VSSlow, 0.00) ;
}
default_operating_conditions : "Best";
then by the fact that the default_operating_conditions have selected "Best", the
estimation voltages for the supplies are taken as:
VDDhigh - 1V
VDDlow - 1V
VSShigh - 0V
VSSlow - 0V
and the power numbers are derated accordingly, based on the supply voltages
defined in the power_supply construct. To get the dynamic power, PowerArtist
derates the dynamic energy number by the square of the estimation voltage divided
by square of the characterization voltage. Similarly, PowerArtist derates leakage
power by the estimation voltage divided by the characterization voltage.
The Liberty rail_connection attribute is used to specify the power rails to which a
cell is tied. Power for an instance of the cell will be derived from those power rails
only.
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Running RTL Mixed-Vt Power Analysis

Using cells characterized for different threshold voltages (Vt) is a critical way to
control leakage power in low-power designs. Many gate-level synthesis and physical
design tools have the ability to optimize your design to reduce your leakage power
by replacing regular threshold voltages cells with cells that have a higher threshold
voltage. This optimization is typically done to cells on paths that have positive timing
slack.
To perform this optimization you must either have multiple libraries characterized at a
single threshold level or libraries characterized for multiple thresholds. Some tools,
such as PowerCompiler™, suggest that you get superior optimization results using
libraries characterized for multiple thresholds. PowerArtist allows you to perform
power analysis that takes mixed-Vt libraries into consideration and supports both
library methodologies.
Critical Liberty Leakage Attributes

Synopsys’ Library Compiler™supports two attributes related to threshold voltage:
 At the library level:
default_threshold_voltage_group : "string" ;
 At the cell level:
threshold_voltage_group : "string" ;
Your libraries should be defined with these attributes; PowerArtist uses the supplied
strings to differentiate threshold voltages for mixed-VT power analysis.
One use of these attributes in a library could be:
default_threshold_voltage_group : "HVT" ;
For this example, assume that the library provider has established conventions
where HVT implies high threshold voltage devices and LVT implies low threshold
voltage devices. In this case, the following example implies that unless a particular
cell has a threshold_voltage_group that cell is a high Vt device. Another example for
a mult-Vt library would be to have multiple cells with different
threshold_voltage_group attributes:
cell (NAND2_HVT) {
threshold_voltage_group : "HVT";
...
}
cell (NAND2_LVT) {
threshold_voltage_group : "LVT";
...
}
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PowerArtist allows you to use Tcl commands to supply these attributes if they are
missing from your libraries using the SetVoltageThreshold command (see
Categorizing Cells for Multiple Vts next).
The SetVT command is used to assign different thresholds to hierarchical instances
in your design. The methodology is based on the assumption that most customers
have an idea of the typical spread between different Vt points in their modules. An
example command is:
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group {HVT:70 LVT:30}
In this example, all of the inferred elements that are children of top.block1 and
top.block2 will have their default cells chosen from the libraries that are to be used
for power analysis such that 70% of the default cells have a vt_group with the value
HVT and 30% have the value LVT. The standard PowerCompiler defaulting is used; if
the threshold_voltage_group is not found in a cell, then the
default_threshold_voltage_group value is used. Instances that are not children of
top.block1 and top.block2 will be assigned default cells without any consideration for
the threshold voltage attributes.
It is possible to assign the SetVT command hierarchically. For instance, if one of the
instances is top.block1.child1, this will override the percentage values set by the
top.block1 SetVT command.
Categorizing Cells for Multiple Vts

If your libraries do not categorize cells using Liberty threshold voltage attributes, you
need to categorize cells for different threshold voltages using PowerArtist’s
SetVoltageThreshold command.
SetVoltageThreshold -group LVT -pattern { *_TL1 *_TL2 }

SetVoltageThreshold -group HVT -pattern { *_TH }
Given these sample settings, any cell names matching *_TL1 or *_TL2 will have their
threshold_voltage_group value set to LVT. Additionally, any cell names matching
*_TH will have their threshold voltage string set to HVT. The wild cards supported are
the typical glob-style wild cards.
The SetVT example, in the previous section, assumes that the supplied libraries
categorize the cells based on the Liberty threshold voltage attributes. If they are not
categorized this way, you must use the SetVoltageThreshold command in addition to
the SetVT command.
SetVoltageThreshold -group LVT -pattern { *_TL }

SetVoltageThreshold -group HVT -pattern { *_TH }
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group {HVT:70 LVT:30}
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Given these settings, any cells from the supplied libraries that are available for
top.block1 and top.block2 and have names that match the pattern *_TL will be
treated as part of the LVT threshold voltage group. Cells that match the pattern *_TH
will be treated as part of the HVT threshold voltage group.
Default Cell Selection for Mixed-Vt Analysis

If you do not perform mixed-Vt analysis using the SetVT command, for each of the
default cells, PowerArtist automatically chooses three cells from your .libs that can
drive low, medium, and high loads.
With mixed-Vt analysis, PowerArtist selects three additional default cells for each cell
type for each threshold group. This happens even if you specify only one mixed-Vt
library. For example, suppose you have the following sequence of commands:
SetLibrary -instance top.block1 -library mixed-vt

SetVT -instance top.block1 -vt_group {HVT:50 REG:20 LVT:30}
Given these settings, for each of the default cells, PowerArtist searches for three
candidate cells for each of the three voltage groups in the library “mixed-vt”.
Sample Mixed-Vt Flow and Tcl File

To prepare for mixed-vt power analysis, first create a file called, for example,
mixed_vt.tcl.
# Mixed-Vt Lib and Threshold Settings#

SetLibrary -instance {top} -library {scmetro_cmos10lp_hvt_ff_1p1v_125c \
scmetro_cmos10lp_lvt_ff_1p32v_125c}
SetVoltageThreshold -group LOW_VT -pattern {*L}
SetVoltageThreshold -group HIGH_VT -pattern {*H}
##Mixed-Vt Specific Settings##

SetVT -mode percentage -instance {top} -vt_group {LOW_VT:30 HIGH_VT:70}
As an example of a complex Tcl file containing a variety of command file commands,

consider the following case. If you want to perform power gating with mixed Vt
analysis, combine the power gating related commands with the mixed-Vt commands.
For this example, you could simply append the following commands after the
commands in the previous section in the mixed_vt.tcl file.
############################################
# Power Gating Commands
# rx_rq and tx_rq are sleep signals
CreateVirtualSupply -supply VDDNW -virtual_supply RX_VDDNWS -on top.rx_rq
CreateVirtualSupply -supply VDD -virtual_supply RX_VDDNWS -on top.rx_rq
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CreateVirtualSupply -supply VRET -virtual_supply RX_VRET -on (!top.rx_rq)

CreateVirtualSupply -supply VDDNW -virtual_supply TX_VDDNWS -on top.tx_rq
CreateVirtualSupply -supply VDD -virtual_supply TX_VDDNWS -on top.tx_rq
CreateVirtualSupply -supply VRET -virtual_supply TX_VRET -on (!top.tx_rq)
Understanding Mixed-Vt Analysis Results in the Report File

PowerArtist will generate a section in the .rpt file when you run a power analysis or
reduction and specify the SetVT command. For every hierarchical instance specified
in the SetVT command, the report will include the total number of default cells
selected for each of the specified Vt values.
Sample Report Section for Mixed-Vt Analysis
Mixed-VT Cells Distribution

===========================
------------- -------- ----------- ---------------
top.block1
HVT 50 40
REG 30 24
LVT 20 16
---------------
Total 80
-----------------------------------------------------
top.block2
HVT 50 20
REG 30 12
LVT 20 8
---------------
Total 40
If a particular default cell type could not be found from all of the specified
threshold_groups in the SetVT command, then default cells of that type will be
chosen independent of those threshold_groups, from the libraries that are set on that
hierarchical instance. The total number of those default cells selected will be shown
in an additional row where “Other VTs” is specified under the “VT Group Name”
column. For example, suppose you specified the following SetVT command:
SetVT -mode percentage -instance {top.block1} -vt_group {HVT:90 LVT:10}
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Setting up Clock Power Analysis
Assume that a few default cells could not be found for threshold_groups HVT and
LVT, and therefore those cells are chosen from other VTs. In this case, the following
report would be generated.
Mixed Vt Analysis Report with Other VTs Section

------------- -------- ----------- ---------------
top.block1
HVT 90 110
LVT 10 13
Other VTs 0 7
---------------
Total 130

You can set-up PowerArtist to perform clock power analysis. Clock power has two
primary components:
 Power consumed by the clock buffer (internal cell power) driving the capacitive
load
 Power due to the capacitive load
The capacitive load has two primary components:
 Load due to the cumulative input capacitance of the inputs of all clock loads
 Capacitance due to the wiring on the clock line
Pclk = (Cfanout + Cwire)V2fclk
The Cfanout value is determined by analyzing the HDL code, coupled with input
capacitance information from the technology file. The wiring capacitance (Cwire) is
based on an estimate of the amount of wiring required to distribute the clock. Cwire
therefore depends on the fanout of the net and is calculated from a wire load model
in the specified libraries. You can either specify this wire load model for a clock net or
allow PowerArtist to do the selection based on standard wire model selection rules.
Commands for Clock Power Analysis

PowerArtist provides a set of commands you can use to specify the clock net in the
design and provide information on any clock buffers for which a clock tree is to be
inferred. To enable clock power analysis, you must include the appropriate
commands in your PowerArtist command file.
The two commands that you can use to define your clock net are: SetClockNet and
SetClockBuffer (optional). The SetClockNet command specifies a clock net in the
design and is required. The SetClockBuffer command specifies clock buffers for
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which you want PowerArtist to infer a clock tree1. If you set SetClockNet -mode
option to “trace” the SetClockBuffer command is optional; it is required for inferred
clock trees.
Sample Usage
Assume a scenario whereby you want to trace a clock named “tclk” which has
special circuitry beginning with instance chip_top.mux21-a that you do not want to
include in the power analysis. Also assume that the wire load model WL_05x5
should be applied to chip_top.tclk and all of the sub-nets that make up this traced
clock net. Given these parameters, you would specify the following SetClockNet
command in your command file:
SetClockNet -name chip_top.tclk -mode trace -stop_at_instance chip_top.mux21-a
Furthermore, if you want to infer a clock net, pciclock, you would also include a
section similar to the following:
SetClockNet -name chip_top.pciclock -mode infer

SetClockBuffer -type root -name clkr -library lib1 -fanout 12
SetClockBuffer -type branch -name clkb -library lib1 -fanout 10
SetClockBuffer -type leaf -name clkl -library lib1 -fanout 8
If you want to set a wire load model to be used for the clock net defined, you can
specify the SetNetProperty command for example:
SetNetProperty chip_top.tclk wireload_model WL05x5
How Clock Power Analysis Works

For clock power analysis on a net driving a large number of clock pins, PowerArtist
first determines pin load due to all clock pins on the net, as well as capacitance due
to wiring needed to drive all the clock pins.
If there is an instance driving the clock net, PowerArtist determines the maximum
fanout for the instance output or the maximum capacitive load that output can drive.
For a gate-level instance, this information is obtained from the max_fanout or
max_capacitance attributes for the cell output pin represented in Liberty format. If
these attributes are not specified in the library, then you can use the
SetCellDefaultFanout or the SetDefaultFanout command to specify the default
fanout.
For an RTL instance, PowerArtist searches the output of the default NAND cell for
max_fanout/max_capacitance information, which is then used on the instance
1. Tree is the only topology PowerArtist supports.
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output. To specify the default fanout for an RTL instance, you have to use the
SetCellDefaultFanout command on the default NAND cell.
Since the SetCellDefaultFanout command never overrides the value for max_fanout
in your library, if you are performing an RTL power analysis, you could do either of
the following:
 Find all cells that are two-input NANDs and using wild cards in one or more
commands, set the defaults for just NAND gates.
 Do a complete wild card specification on cells and libraries. For example:
SetCellDefaultFanout -cell * -library * -fanout value
If there are no drivers for the net (that is, the clock net is a primary input) clock
buffers are always inserted. Using the specified buffers and their fanouts,
PowerArtist synthesizes a clock tree using the following process:
1. It calculates the number of leaf-level buffers to be inserted based on the number
of clock pins on the net, and the specified fanout for the leaf buffer.
2. It checks the branch fanout to determine how many branch buffers are needed
and then inserts branch-level buffers to drive the leaf buffers.
Using this method, PowerArtist continues to insert branch buffers, level after level,
until a stage is reached in which a single root buffer can drive all of the next branch-
level buffers.
Example
If there are 100 pins on a primary clock net (no driver) and the leaf buffer fanout is 4,
then 25 leaf buffers are inserted at the leaf level. If the branch driver fanout is 10 and
they have to drive 25 leaf buffers, 3 branch buffers are inserted. One root driver is
then added to drive the three branch buffers.
The wiring capacitance from the root buffer to all leaf buffers is calculated using the
wire load model for the clock net on which the buffers are inserted.
Controlling Forward Clock Tracing

PowerArtist performs forward clock tracing to isolate an instantiated clock path in a
design and create a separate report showing the power consumed by the clock path.
PowerArtist starts tracing forward from a net specified with the SetClockNet
command in the clock nets file. Tracing stops when any of the following are
encountered:
 A clock pin of a sequential device
 A primary output of the design
 Blackboxes
You can also control when the tracing stops by specifying either the -
stop_at_instance or -stop_at_cell option for a given clock (for example,
chiptop.CLKIN).
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Stop at Instance Example

SetClockNet -name chiptop.CLKIN -mode infer -gate_clock yes
-stop_at_instance /
{ chiptop.corepinmux.coretop.pbustop.syscfg_if.SYSPLL }
Given this example, PowerArtist stop tracing the CLKIN net when it reaches the
specified instance.
If the cell type is PLL, you could use the following setting:
Stop at Cell Example

SetClockNet -name chiptop.CLKIN -mode infer -gate_clock yes
-stop_at_cell { PLL }
Tracing will continue through any instances specified with the TraceThruInstance or
TraceThruCell commands.
Supported Timing Arcs

The following combinational timing arcs are supported:
 combinational
 combinational_rise
 combinational_fall
 three_state_disable
 three_state_disable_rise
 three_state_disable_fall
 three_state_enable
 three_state_enable_rise
 three_state_enable_fall
The following sequential timing arcs are supported:
 rising_edge
 falling_edge
RTL Designs without Timing Arcs

Tracing for RTL designs whose libraries do not contain any timing arcs is affected by
the number of output pins on an instance: if there are three or more output pins,
clock tracing will stop at that point. The inferred model types: decoder, comparator,
adder, tri-state driver, unencoded_mux, regfile, latchfile, or multiplier will cause
tracing to stop. When tracing fails, buffers leading up to the failure point will not be
included in the clock report.
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Setting up Clock Gating for Power Analysis
Estimating Instantiated Clock Tree Capacitance

If you have back annotated capacitances for your clock nets, PowerArtist will use
those values; otherwise, it uses wire load models for all wires up to and including the
leaf buffers. A wire load model for a net in the clock tree is selected based on the
following rules:
1. If you supplied a wire load model for the clock net, that wire load model is used for
the clock net as well as all of the sub-nets in the clock tree. (Sub-nets are nets
between clock buffers in the clock tree.)
2. If you supplied a wire load model for any of the sub-nets, that wire load model is
used for estimating the capacitance of the sub-net.
3. If no wire load model was supplied, PowerArtist uses standard area-based wire
load model rules to determine the wire load model, as is done for any net in the
design, to determine the wire load model assigned to the net.
It then uses the heuristic algorithm to estimate the capacitances of wires between the
leaf buffers and the clock pins of sequential devices by inferring clock trees between
them if needed.

PowerArtist allows you to select the conditions under which clock gating should be
performed to conserve power. PowerArtist will take this information into consideration
and perform clock gating during power analysis. The power report generated at the
end of the analysis will include information on clock gating, specifying which registers
were gated and providing details about which clock gating cells were used along with
the resulting power numbers.
The key features of PowerArtist clock gating include:
 Clock gating is performed using integrated clock gating cells that are defined
using the methodology established by Synopsys™.
 You control which integrated clock cells get selected from the library, the clock
nets that will be gated, and the minimum bit width required for a register bank to
be clock gated.
 Generated reports that describe the clock gating performed by PowerArtist.
Clock Gating Flow for Power Analysis

The flow for performing clock gating with power analysis in PowerArtist is as follows:
1. Define your integrated clock cells in your Liberty (.lib) libraries.
2. Add a section to your PowerArtist Tcl command file that indicates your clock
gating decisions. For every net you want to gate, be sure to specify the -
gate_clock option to the SetClockNet command:
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SetClockNet -gate_clock yes ...

3. Run your PowerArtist command file to perform an average power analysis.
4. Review the generated report file (.rpt) to see the clock gating results.
See the Running Power Analysis with Clock Gating section in the tutorial for a
sample power analysis with clock gating.
Performing Enhanced Clock Gating

One of the constraints for register-based clock gating is the required minimum bit
width that register banks must satisfy before they will be clock gated. You set this
constraint using the -min_bit_width option to the SetClockGatingStyle command.
However, synthesis tools now are creating “weak” enables that extract common sub-
expressions from enable expressions that don’t meet the minimum bit width
constraint. For example, examine the following RTL:

if (en1 and en2)
out1 = in1;

if (en1 and en3)
out2 = in2;
Assuming the two register assignments involve a total of 3 bits, you could actually
insert an ICGC that has en1 as the enable signal. The output clock of the ICGC then
becomes the clock input to the two register banks that have feedback muxes with
en2 as one select line and and3 as the other. Assuming that en1 is not enabled
100% of the time, then the clock going to the registers is toggling less often, saving
power.
Just as synthesis tools have constraints controlling the use of weak enables, so does
PowerArtist. There are two options that control this—one to the SetClockNet
command and the other to the SetClockGatingStyle command.
 In the SetClockNet, specify the following option:
-enhanced_cg true | false
The default is false. If you set this to true, weak enables will be used when
possible. This option is valid only when you have also specified “-gate_clock yes”.
If you do not specify “-gate_clock yes” and you do specify “-enhanced_cg true”,
PowerArtist will generate the following message
1594: "Clock net XXX will not be clock gated...".
 In SetClockGatingStyle, you need to specify the following option:
-min_bit_width_ecg int
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Setting up Clock Gating for Power Reduction
The combined bit width of all register banks gated with this weak enable must be
greater than or equal to this value. The default is 2 * -min_bit_width constraint.
Changes to the Power Analysis Report and the Power Database

If enhanced clock gating is performed, you will see the following changes to the
Clock Power Consumption section in the power analysis report:
 There will be a new sub-section titled Integrated Clock Cell Power for Enhanced
Gating. The format of this section is identical to the existing section, but it will
contain information describing the enhanced clock gating performed.
 The Clock Gating Summary will have the following additional line:
Number of registers enhanced gated by inferred clock gating cells.
This represents the total number of register bits gated using weak enables.
In addition, in the power database (.pdb file) any registers that have had enhanced
clock gating will be marked the same as other clock gated registers.
Library Modeling of Integrated Clock Cells

PowerArtist’s clock gating feature takes advantage of the modeling methodology
Synopsys has already defined for integrated clock cells. PowerArtist identifies
integrated clock gating cells by looking for the clock_gating_integrated_cell attribute
in the .lib file. It is recommended that these cells also have a max_fanout attribute.
This attribute tells the algorithm how many loads the cell can drive.
PowerArtist searches all Liberty files specified using the -synlib_files option for
integrated clock gating cells. There is no special switch for specifying the libraries
containing clock gating cells.

Clock gating is performed entirely by the reduction engine controlled by the
ReducePower command. No other command is involved in the process. To perform
clock gating, PowerArtist must be told which nets need to be gated and the type of
clock gating cells to be used for the gating. The clock nets that are to be gated are
not limited to a particular module hierarchy. This is because PowerArtist is not limited
to synthesizing a portion of your design, but can process the entire chip as a whole.
Clock Gating Flow for Power Reduction

If you want PowerArtist to perform clock gating during power analysis, you must
perform the following steps:
1. Define your integrated clock cells in your power libraries.
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2. Include the following commands in your PowerArtist command file or on the

command line: SetClockNet and SetClockGatingStyle. The SetClockNet
command defines which clock nets should be gated among other things. The
SetClockGatingStyle command defines the attributes that control how clock gating
is performed.
3. Run the ReducePower command to perform power reduction.
Clock Gating Algorithm

During clock gating, PowerArtist performs the following steps, in the following order.
1. It reads in the libraries specified using the -synlib_files option.
2. It reads in the clock-related commands from your command file.
3. It searches the libraries for all cells containing the clock_gating_integrated_cell
attribute whose value matches that supplied by the -clock_cell_attribute option to
the SetClockGatingStyle command.
Note that if the library does not contain output maximum fanout information, you
can specify it using the SetCellDefaultFanout command in the clock nets file.
4. It identifies the elements that are suitable for clock gating. To be suitable:
— It must be an SFL type of register. Register files cannot be clock gated.
— The clock name must match that specified using the SetClockNet command (in
the clock nets file) or is traceable from such a clock.
— The d_in of the register must be the output of a 2-1 feedback mux and the
d_out of the register must be an input to the same mux.
— All registers sharing the same clock, enable and reset pins are gathered
together. If the number of bits is greater than or equal to the min_bit_width
value, they will be clock gated. However, if you specified a list of instances with
the -instance or -hierarchical options to the SetClockNet command, only those
instances will be gathered together and clock gated. For more information see,
Hierarchical Clock Gating.
5. It gates the selected registers using the following process:
— It first identifies the best fitting integrated clock gating cell (ICGC) to drive the
register bank. The ICGC depends on three attributes: 1) the -gating_cells and
-clock_cell_attribute options to the SetClockGatingStyle command, 2) the
max_fanout attribute in its cell description in your technology file and 3) the -
max_bit_width option in the SetClockGatingStyle command.
— If the -gating_cells or -clock_cell_attribute options are specified then the choice
of ICGC is limited to those specified in the option values. These options
establish the candidate ICGCs.
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— If the -max_bit_width option is not specified then it identifies the best fitting
candidate ICGC based on max_fanout to drive the total number of bits in the
register bank.
 If no ICGC is identified that can drive all the bits, PowerArtist will build a
fanout tree based on the clock buffers specified in the clock nets file. Then
the ICGC drives the fanout tree.
 The load on the net driving the ICGC is reduced by the number of bits in
the register bank. The load is then increased by one due to the added
ICGC.
— If the -max_bit_width option is specified, PowerArtist chooses an ICGC that
best fits the specified value.
 PowerArtist adds as many ICGCs in parallel that are required to drive the
register bank load.
 No buffer tree will ever get inferred in this case.
 The load on the net driving the ICGC is reduced by the number of bits in
the register bank. The load is then increased by the total number of ICGS
added.
— If your technology library uses max_capacitance rather than max_fanout for its
ICGCs, then the max_capacitance value gets translated into a max_fanout
value by dividing the max_capacitance value by the input_capacitance of the
default flip-flop clock pin.
6. It performs an RTL average power analysis:
a. It determines the duty cycle of the select pin on the 2-1 mux driving the bits as
the duty cycle of the enable pin on the integrated clock cell.
b. It uses the gate-level power model for the integrated clock cell to calculate the
power consumed by the integrated clock cell.
c. It calculates power for the register bits that have been clock gated. The clock
activity for these register bits is derated by the duty cycle for the enable pin in
the clock gating cell. Likewise, the power for the feedback mux bits is reduced
to zero, because these feedback components are eliminated from the circuit.
7. It generates clock gating information in the power report (activities.rpt). It uses this
information while performing various reductions. Clock tree and clock gating
information is displayed in the PowerCanvas main window just above the tree
display. If you display the clock tree, which comes up in a separate window, you
can move your cursor over the different elements in the clock tree and the
dynamic display in the main window will change as you move along. This will
provide information such as Activity, Duty Cycle, Frequency, Net Capacitance, etc.
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Hierarchical Clock Gating

This feature gives you control over where the integrated clock gating cells are to be
inferred. By default, PowerArtist attempts to clock gate the entire design at one time.
Any inferred register that shares the same clock net and enable signal controlling a
feedback mux will be clock gated using the same integrated clock gating cell. A
buffer tree then handles the potentially high fanout load.
However, if you are using a logic synthesis tool that performs clock gating and that
has a capacity limitation, clock gating for the entire design cannot be implemented at
one time. Instead, only the large blocks in the design that form the boundaries
beyond which integrated clock gating cells cannot be shared will be clock gated. You
can use the -hierarchical option to the SetClockNet command to overcome this
particular situation. Assume the following design.
top
b1 b2
In this design, if you want to synthesize and clock gate block b2 separately from the
remainder of the design, you would use the following command:
SetClockNet -name top.clk -hierarchical top.b2 -gate_clock yes
In addition, PowerArtist can perform clock gating on selective blocks in a design
using the -instance option to the SetClockNet command.
In the same design, if you only want to clock gate block b2 but not clock gate b1,
then use the following command:
SetClockNet -name top.clk -instance top.b2 -gate_clock yes
Both the -hierarchical and -instance options accept a Tcl set of instance names. At
this time, they cannot accept wild cards.
Inferring Buffer Trees for Nets with High Fanout

PowerArtist can infer buffer trees for nets with high fanout. To use this feature, you
will need to specify the SetHighFanoutNet and SetBuffer commands in the command
file. For SetHighFanountNet, PowerArtist will infer a buffer tree for any net with at
least the given number of fanounts. Use the SetBuffer command to specify the
buffers used when inferring a buffer tree for these high fanount nets.
If you do not use this feature, during inferencing, you could get a tremendous
capacitive load on a driving pin which would lead to the inferred element.
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239
Chapter 8
Analyzing Simulation Activity 8
Introduction
PowerArtist has the ability to perform flexible activity analysis on time slices as small
as a clock cycle. This is called vector analysis. Analyzing your simulation activity
before you perform a power analysis allows you to:
 Determine if your testbench exercises your design correctly. A testbench for
average power differs from a testbench for peak power.
 Potentially detect functional flaws that are difficult to see by looking at simple
waveforms. For example, if your design should be in an “idle mode” and yet you
see significant activity, this might signal a design error.
The primary method PowerArtist uses to achieve these goals is to provide you with a
graph of activity over time. PowerArtist calculates activity data using the following
equation:
(toggle_counts_of_all_nets/number_of_nets)
Activity =
number_of_clock_cycles
(toggle_counts_of_all_nets/number_of_nets)
=
(toggles_on_clock_signal/2)
You run each simulation once while collecting activity data. Each run provides a
graph for a specific slice of the simulation time, showing the activity for selected
portions of the design on the Y axis and time on the X axis. The portions of the
design are called groups.
Each group corresponds to one line waveform on the graph, and can consist of any
number of hierarchical instances of your design. The activity analysis includes the
children of the defined instance. It averages the activities of all nets in the design
below the top level (as defined in the group). While activity is only an indicator of
power, displaying the average activity for each of the top-level blocks highlights test
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CHAPTER 8 — Analyzing Simulation Activity PowerArtist™ User Guide 240
Defining Different Groups at Each Design Phase
suites that fail to access all blocks on the chip at once, resulting in artificially low
power results.
The term “activity” is used to describe the average activity of named nets in the
group. Named nets are nets that have been explicitly specified in a simulation and
appear in a simulation dump, which would include the boundary pins.
PowerArtist’s vector analysis tool has two modes of operation: simulation time-based
and system clock-based. In simulation time-based mode, the average activity of the
group is graphed over time. In system clock-based mode, the ratio of the average
frequency of the group to that of the clock is reported.
 Defining Different Groups at Each Design Phase
 Understanding the Design Flow with Vector Analysis
 Creating Analysis Graphs
Defining Different Groups at Each Design Phase

As described in the introduction, vector analysis allows you to define arbitrary groups
of hierarchical instances in the chip. PowerArtist computes the activity for each
group, and displays the groups as individual lines in a graph. During different design
phases, you might want to define different kinds of groups:
 System design: you may want to know the activity for all the memories on the
chip, for overall clock activity or for overall I/O pad activity.
 RTL design: you may want to define each top-level block as its own group. In this
way, the tool can display graphs of activity over time for each block. You can raise
the activity coverage of your RTL test suite by making sure that the simulation
patterns exercise all the blocks at once. You should also capture the activity of the
primary inputs of your chip. You can compare these against similar activity graphs
from your gate-level design to make sure you have the same testbench driving
both. This is a useful check if you are doing RTL-to-gate correlation studies or
comparisons.
 Gate-level design: define activities on the primary inputs of your chip. Verify that
the activity is the same at the gate level as what you had seen at the RT level.
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Understanding the Design Flow with Vector Analysis
Understanding the Design Flow with Vector Analysis

The vector analysis tool fits seamlessly into your existing RTL design flow, which
would consist of the following steps:
1. Simulate your design to create a simulation activity file in any of the supported
formats.
2. Elaborate the design to create a PowerArtist scenario file.
3. Perform vector analysis to create analysis graphs of activity over time for specific
groups of instances. For details see, Creating Analysis Graphs.
4. Use the Apache Waveform Viewer to display the activity graphs.
At this point, you may want to use the tool’s feedback to improve the simulation
test suite for better coverage of high-activity conditions. See Creating Analysis
Graphs for more information.
5. Once you have confidence that your testbenches exercise the design completely,
you can use additional tools to find power peaks and graph power over time.
See Analyzing Time-Based Power for additional information.
Creating Analysis Graphs

Before using the analysis tools, you should verify that your testbenches have good
power coverage. Often, testbenches are designed for functional verification or fault
coverage, and might not represent typical operation or worst-case power situations.
PowerArtist’s vector analysis tool can show you portions of the design where your
testbenches do not produce enough activity. You can tune your testbenches, by
adding tests or exercising more blocks in each test, so that your testbenches
adequately cover all situations. If you don’t, you risk overlooking real power
problems.
Before you begin to find low-activity modules, you should already have a PowerArtist
scenario file and a simulation file. See Acquiring Simulation Data for information on
how to capture your simulation data. Once you are ready, you can run vector
analysis using either a Tcl scripted flow with command files or using the
PowerCanvas Vector Analysis wizard. The command-based flow is documented
here. For information on using the wizard flow, see Running Vector Analysis Using
the Vector Wizard in the tutorial.
Determining the Type of Vector Analysis to Run

There are two different types of vector analysis: clock-cycle mode and time-based
mode. The type of analysis is determined by the value of the following option:
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-activity_waveform_graph_type activity_per_cycle |
frequency_per_interval
Choose activity_per_cycle for clock-cycle mode or frequency_per_interval for time-
based mode. When you perform a vector analysis, you should be aligning your
intervals so that the dominant clock edge of your choice is at the first interval start
time and that each interval is some multiple of your clock period. If you choose the
activity_per_cycle mode this happens automatically for you. If you choose the
frequency_per_interval mode, you have to choose the interval start time and the
interval size carefully. The benefit of the frequency_per_interval mode is that it offers
you more flexibility if you don’t want to align your intervals with a clock edge.
Running Vector Analysis Using Command Files

Use the following process to run vector analysis and create your analysis graphs
using a command file (Tcl script):
1. Specify the DefineGroup command to define groups of hierarchical instances in
the chip, for example:
DefineGroup top "top"
DefineGroup core "top.core1"
DefineGroup pci "top.core1.p1"
DefineGroup rxchan "top.core1.r1"
This example defines four groups named top, core, pci and rxchan that will have
activity graphs generated for their associated instances.
2. Specify the GenerateActivityWaveforms command to run the vector analysis. You
will use different command options depending on the type of vector analysis you
want to run.
— Apply the following syntax to run a clock-cycle based activity analysis:
GenerateActivityWaveforms -activity_file file_name
-scenario_file file_name -top_instance inst_name
-activity_waveform_clock_name clock_name
-activity_waveform_clock_edge (pos | neg | auto)
-activity_waveform_cycles_per_interval int
-activity_waveform_graph_type activity_per_cycle
-activity_waveform_group_list group_list
-activity_waveform_log file_name
-activity_waveform_number_of_intervals int | all
-activity_waveform_start_clock_cycle int
-ptcl_output_file | -fsdb_output_file
-use_rtl_sim_data true | false
— Apply the following syntax to run a time-based activity analysis:
GenerateActivityWaveforms -activity_file file_name
-scenario_file file_name -top_instance inst_name
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-activity_waveform_graph_type frequency_per_interval
-activity_waveform_group_list group_list
-activity_waveform_interval_size time
-activity_waveform_log file_name
-activity_waveform_number_of_intervals int
-activity_waveform_start_time time
-ptcl_output_file | -fsdb_output_file
-use_rtl_sim_data true | false
The following Tcl command file shows a typical set up for a time-based vector
analysis.
-activity_file activities.iaf \
-scenario_file txrx.scn \
-top_instance top_instance txrx_tst.top1 \
-activity_waveform_graph_type frequency_per_interval \
-activity_waveform_group_list {top core pci rxchan} \
-activity_waveform_start_time 100us \
-activity_waveform_interval_size 1ns \
-fsdb_output_file ${topModule}_vectors_full.fsdb \
-activity_waveform_log Waveform.activity_vw.log \
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3. View the resulting FSDB or PTCL file in a waveform viewer. You can use the
Apache Waveform Viewer (or the Verdi™ product from SpringSoft). A sample
waveform is shown here:
Figure 80 Sample Vector Analysis Waveforms for Five Specified Groups
Note that this is the same waveform generated by the full-chip analysis tutorial.
For details on this flow and to try a sample run, see Running an RTL Full-Chip
Power Analysis Using Command Files section in the analysis tutorial.
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245
Chapter 9
Analyzing Simulation-Based Average

Power 9
Introduction
You can run PowerArtist average power analysis on RTL, gate-level and mixed RTL
and gate designs. Before you run average power analysis, it is highly recommended
that you read Chapter 7, Preparing for Power Analysis, which describes prerequisite
steps you need to perform before you begin a power analysis. It is also highly
recommended that you run through PowerArtist Tutorial Part 1: Power Analysis to
learn how to run both a command-line flow and wizard-based flow (for beginners) for
average power analysis.
Overall Design Flow

You should implement the following high-level design flow to perform time-based
power analysis:
1. Simulate your design and generate simulation data in the FSDB, IAF, or VCD
formats.
2. Build a scenario file using the Elaborate command. For details, see Getting Your
Design into PowerArtist.
3. Run vector analysis using the GenerateActivityWaveforms command. For details,
see Analyzing Simulation Activity.
4. Run the CalculatePower -analysis_type average command. Details for this
process are documented in this chapter.
5. View the reports, in text format, created by the CalculatePower command or view
the results, in the PowerCanvas, that you created by saving the power database.
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CHAPTER 9 — Analyzing Simulation-Based Average Power PowerArtist™ User Guide 246
Running a Power Analysis in Full Simulation Mode
 Running a Power Analysis in Full Simulation Mode

 Running Analysis with Incomplete Simulation Data
 Performing Gate-Level Average Power Analysis
 Running Modal Analysis
 Understanding the Basics of the Detailed Power Report
 Controlling the Contents of the Power Report
 Analyzing Average Power Using a SAIF File

Running power analysis in full simulation mode is done entirely by the
CalculatePower command. This command first converts simulation activity data into
a global activity file (GAF) and then runs the power analysis.
Controlling Your Average Power Analysis

As with all PowerArtist programs, you control the operation of your power analysis by
specifying the appropriate commands in your PowerArtist command file. To perform
an average analysis in full simulation mode, you need to specify the CalculatePower
command with the required arguments:
 -activity_file your_simulation_file
This option specifies an input stimulus file generated due to a functional simulator
run. The file may be in FSDB, VCD or IAF (generated by Apache PLI routines)
format. You must specify either -activity_file or -vectorless_input_file for an
average power analysis. CalculatePower automatically determines the type of the
simulation activity file.
 -gaf_file your_gaf_file
Specifies the name for your generated GAF file.
 -scenario_file your_scenario_file
This option specifies the scenario file you generated using the Elaborate
command. For more information, see Getting Your Design into PowerArtist.
 -synlib_files {file_name1 file_name2 ...}
Adds the specified file or Tcl list of files to the list of Liberty technology files. You
can also use the ReadLibrary command to specify which Liberty libraries to read.
 -top_instance top_module_name
This option specifies the instance in the simulation hierarchy that corresponds to
the top-level instance in your scenario file. The -top_instance is specified as a
dotted name, for example, testbench.corelogic_0, no despite the simulator that
was used.
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It is also recommended that you specify some additional options to control your
analysis in different ways.
 To control the point in time with which to begin power analysis, you can use the
-start_time option.
 To stop the conversion of simulation data before the point when the simulation
stopped, specify the stop time with the -finish_time option. This option is also
needed if simulation time ended long after the last signal toggle occurred.
Otherwise, your average power number will be incorrect.
 By using -start_time and -finish_time, you can perform a variety of “what-if”
scenarios without having to re-create the simulation activity file.
 If you have a gate-level design, you will need to specify the -gate_level_netlist
option. For details, see Performing Gate-Level Average Power Analysis.
 If you have an IAF, VCD, or FSDB file that does not match your scenario file you
will want to run with the -mixed_sim_prob_estimation option. For details, see
Running Analysis with Incomplete Simulation Data. You will also need to specify
this option if you have a partial stimulus file. For details, see Analyzing Average
Power Using Partial Stimulus Files.
 To perform mode-dependent power analysis, specify the name of the mode file
with the -mode_file option. For details see, Running a Power Analysis in Full
Simulation Mode.
 Simulations of large designs could result in a significant number of signals never
leaving the X state. This is particularly true for gate-level designs. This could
severely compromise the accuracy of your results. The Transition Counting on
Nets section describes how you can control some of the effects for RTL designs.
X states in gate-level designs will most likely cause power to be underestimated
since power vectors modeled in your power library will not match transitions to
and from X states. The CalculatePower command generates a warning such as:
wwgaf: Warning 3344: wwgaf encountered 54102 signal(s) that were in
an X state for more than 10ns amount of time.
This means that an X state of duration greater than 10 ns occurred 54,102 times
during the simulation run. This could be one signal being in an X state 54102
times or 54102 signals 1 time.
Seeing this message with an unexpectedly large number of signals is an
indication that your test bench may not be sufficiently robust for performing power
analyses. The duration may be controlled by the -allowed_x_time option.
Note on Pin-Based Estimation for Gate-Level Instances

There are two techniques that PowerArtist can use for power estimation of gate-level
instances: pin-based and arc-based. By default, PowerArtist uses pin-based
estimation which does not do arc monitoring. Arc monitoring requires the ports of the
instances to be output into your simulation data file—not just the nets connected to
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Running Analysis with Incomplete Simulation Data
the ports of the instance. This method is somewhat faster and consumes less
memory than the arc-based method, at the cost of some accuracy. Arcs are still
monitored for the following instances:
— IO pads
— instantiated memories
— non-memory cells containing bus pins
— macro combinational cells with 11 or more pins
To enable arc monitoring for additional cells and instances when using this option,
use the MonitorArcs command. If you want PowerArtist to perform arc-based
estimation for all gate-level instances, you can specify the “-arc_based_estimation
true” option to CalculatePower.
Sample CalculatePower Specification for Full Simulation Mode

To run a power analysis in full simulation mode, you may want to use a
CalculatePower command such as the following:
set design top

-average_report_file $design.AverageBatch.rpt \
-average_report_options agip \
-compress_gaf true \
-detailed_vertical_report true \
-gaf_file $design.AverageBatch.gaf \
-calculate_log CalculatePowerAverageBatch.log \
-mode_file txrx.mode \
-power_db_name $design.AverageBatch.pdb \
-vertical_report_instances $design \
Running Analysis with Incomplete Simulation Data

If you have an IAF, VCD, or FSDB file that does not match your scenario file in some
way, for example, some instance in the scenario file may be missing in the design
you simulated because the source files have changed, you will need to run the
CalculatePower command with the -mixed_sim_prob_estimation option. When you
run with this option, only some of the nets have .gaf data associated with them, as
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Performing Gate-Level Average Power Analysis
opposed to full simulation mode in which all of the nets are assumed to have .gaf
data available.
Performing Gate-Level Average Power Analysis

If you have a pure gate-level design, you will need to use the “-gate_level_netlist
true” Elaborate option when you create a new scenario file. This option tells the tools
that the design is meant to be gate level. If during scenario file creation Elaborate
encounters RTL components, it will black box them and generate warning messages.
Analyzing Large Gate-Level Designs

If you are executing PowerArtist on the 32-bit Linux system, you are severely
constrained by the size of design you will be able to run. On some Linux systems,
this may be at best 2GB of memory and on others, it is certainly no more than 4GB.
Therefore, it is recommended that for any meaningful sized, gate-level designs, you
use 64-bit Linux or Solaris platforms exclusively.
Running Modal Analysis

Large designs often have several operational modes, such as standby, receiving,
and transmitting. The power consumption for these modes will typically vary as
different sections of the chip may be inactive, or even powered down, in each mode.
Entering data into a mode description file enables PowerArtist to perform accurate
RTL power analysis for each mode. You can print the mode analysis results or
PowerArtist can compute a weighted average. Note that mode analysis is available
at the RTL designs or mixed RTL and gate-level designs only. It is not available if
you have a full gate-level design that you have signaled to PowerArtist-X using the -
gate_level_netlist option.
A mode file contains design-specific information that the tools use to execute several
power analyses corresponding to different operational modes of the design, and
combine the results into one or more reports.
The format for a mode file meant for simulation-based power analysis is shown here.
$mode "boolean_expression"
$report file_name
$result file_name
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Table 3 Elements Within the Mode File
Element Description
$mode boolean_expression This required keyword assigns a name to the operational

mode you are defining. The boolean_expression can be a
single signal name or a combination of signals in the design.
The signal’s hierarchical name is, in this case, with respect
to the top most scope (or testbench scope) in the VCD—not
the design’s “top” name. You can use any of the standard
boolean operators.
$report file_name This optional keyword writes a report file for this mode to the
specified file name. You can write this file to any directory by
specifying a relative or absolute file path name; however,
the “~” symbol is not supported in file path name.
$result file_name This optional keyword writes a result file for this mode to the
specified file name.
A sample mode file might look like the following:
$mode top.counting_off
$report counting_off.rpt
$mode top.counting_on
$report counting_on.rpt
This file says the design is expected to be in one of two modes: counting_off or
counting_on.
The name of the mode must be the name of a signal such that when it is asserted
high, the system is assumed to be in this mode. In this case, the design is expected
to find two signals: top.counting_off and top.counting_on. The names of the signals
must be in the VCD file and be rooted at the topmost scope (or testbench scope) in
the VCD.
For this mode file, PowerArtist performs two analyses, one for each mode. The
results of the analyses are written to two separate files (counting_off.rpt and
counting_on.rpt).
A second sample mode file might be:
$mode top.sys_request&&top.interrupt
$report request-interrupt.rpt
$mode "top.sys_request&&(!top.interrupt)"
$report request-not_interrupt.rpt
$mode "(!top.sys_request)&&top.interrupt"
$report not_request-interrupt.rpt
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$mode "(!top.sys_request)&&(!top.interrupt)"
$report not_request-not_interrupt.rpt
In this example, there are four modes. While processing the simulation data file,
PowerArtist monitors sys_request and interrupt. When either of these two signals
changes state, PowerArtist evaluates the various boolean expressions, determines
which one is true and allocates the energy to that mode bucket.
There are two edge cases for this method of modal power. If the simulator enters a
mode in which none of the mode signals are in a logic 1 state, the simulation activity
for those simulation periods is ignored (that is, the activity will not contribute to the
power of any mode). If more than one of the mode signals are in the 1 state at the
same time, simulation determines that the system is in the mode that appears first in
the mode file (counting_off in the first sample mode file).
Using a mode file containing n different modes results in n+1 report files. One report
file is produced and named for each mode and one report file is produced for the
entire simulation. This mode file produces a report file named for each of the modes,
counting_off.rpt and counting_on.rpt and another report file representing the entire
simulation, which is named as defined by the CalculatePower command.
To obtain the total power consumed during the two modes, you cannot add the
power consumed by each mode. Instead, you must:
1. Convert each power to energy.
2. Add the two energy values together.
3. Convert to power.
This is equivalent to computing a weighted sum (weighted by the amount of time
spent in each mode) of the two powers.
For more information on mode files and additional samples, see Mode File Format in
the PowerArtist Reference Manual.
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Understanding the Basics of the Detailed Power Report
Understanding the Basics of the Detailed Power Report

The detailed power report is stored in an ASCII file (or as an HTML file if you request
that using the -html_report_title option). Although some of the sections in this report
are always included others are generated/formatted depending on the values you
specify to the -average_report_options argument to CalculatePower. Major sections
(often used) include the following:
 Header: includes:
— Date and time report file was generated.
— Version of PowerArtist used.
— Library file used for the power calculation.
— Assumed clock frequency.
— Voltage values for the power supplies used.
— Name of the activity file.
— Names of any capacitance files.
— How the power consumed in driving inter-module nets is reported.
— Design and simulation prefix.
 Total Power Consumption: summarizes the results of the analysis.
 Internal Power Consumption: lists the power consumed by each individual leaf
module in the design. The specific content of this section will depend, in part, on
the options you specify the CalculatePower -average_report_options argument.
For more information, see Controlling the Contents of the Power Report.
 Pad Power Consumption: lists the power consumed by each individual IO pad in
the design, along with the capacitive load “seen” by that pad.
 Clock Power Consumption: lists the following information:
— The hierarchical net name, the type of analysis, and the total power for the
clock tree. The analysis type will be either Instantiated, which means that it was
traced, or Inferred meaning clock inferencing was done.
— Area occupied by the net.
— Clock senses.
— Frequency of the clock net
— Transition time of the clock net
— Fanout capacitance of the clock net (divided into contributions from wire and
pin capacitances).
— Power consumed as the net toggles (divided as wire and pin components).
— The wire load model applied to the net (the first entry is the net name and the
second entry is the wire load model applied to that net). If you assigned wire
load models to sub-nets of the clock tree, they would be listed here as well.
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Controlling the Contents of the Power Report
— Descriptions of the instances and net that were traced as part of the clock tree.
— The clock tree inferencing that occurred including buffers and integrated clock
gating cells that were inferenced.
— The clock gating summary that provides statistics on the number of gated and
ungated registers and the number of integrated clock gating cells either
instantiated or inferenced in your design.
To better understand the content of this report and to see a sample, see the Clock
Domain Power Consumption section in the analysis tutorial.
 Total Power Per Supply: lists each power supply used in the design with the power
consumed from each supply. This section is generated when you specify the
option “-average_report_options V” to the CalculatePower command.
To create a report where the internal and pad power are divided into their static
and dynamic components, you can specify the option
“-average_report_options s” to the CalculatePower command.
Power per supply is also reported as static and dynamic components.
 Vertical Report: reports power by cell. You can generate/manipulate this section
by specifying the following CalculatePower options:
-vertical_report_instances [{inst1 inst2 inst3...}]
-detailed_veritcal_report true
-vertical_report_sort_mode alphabetical | power
Available Power Report Formats

The power report is available in plain text or HTML. Plain text is always available. To
generate an HTML report, specify the CalculatePower -average_html_report_title
option. You can display these reports in any web browser.

You can specify different report options to CalculatePower to control what is included
in and the format of the instance power report in the Internal Power Consumption
section in several ways. In addition, you can specify reporting options that generate
additional sections in the power report.
This section provides many different sample reports that vary based on the specified
report options.
 A typical design, with no report options specified, contains the following instance
power section1.

=============================
Component Model Power(Watts)
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--------- ----- ------------

wavtab.cnt.#0 adder_rip 67.3uW
wavtab.cnt.#1 register 225uW
wavtab.dff.#0 register 194uW
wavtab.div.#0 adder_rip 246uW
wavtab.div.#1 register 851uW
wavtab.rom rom 4.03mW
Total internal power 5.62mW
 If you specify -average_report_options ip, the non-leaf hierarchical elements are

shown using indenting to indicate levels of hierarchy, rather than repeating all the
non-leaf cell names.

--------- ----- ------------
wavtab user 5.62mW
cnt user 293uW
#0 adder_rip 67.3uW
#1 register 225uW
dff user 194uW
#0 register 194uW
div user 1.1mW
#0 adder_rip 246uW
#1 register 851uW
rom rom 4.03mW
 If you specify -average_report_options mp, the inferred elements whose names

contain # are not shown. This makes the report much shorter and also shows only
the instances you have actually created in your design. See the following
example.

--------- ----- ------------
wavtab user 5.62mW
wavtab.cnt user 293uW
wavtab.dff user 194uW
wavtab.div user 1.1mW
 Another way of reducing the size of the report is to use -

instance_power_threshold float option, which eliminates from the report any
instance consuming a small amount of power. Normally you might set this to 1
1. Note that the report samples that have just one Power(Watts) column were generated
using the “f” reporting option that combines the static and dynamic power values into
one.
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percent (-instance_power_threshold 1). For the example shown here, the

elimination threshold was set to 10 percent (-instance_power_threshold 10), a
very high value.

--------- ----- ------------
wavtab.div.#1 register 851uW
It is important to notice that in each case, the total power reported is the same.
The report options only change which modules are shown in the report, and do
not change the power computation.
 If you specify -average_report_options a, the area estimation section will be
included in the report.
6. Area
=======
Component Width Height Regs Gates

--------- ----- ------ ---- -----
top.core1.a1.#241 33.8um 33.8um 0 69
top.core1.a1.#242 30.5um 30.5um 0 56
top.core1.j1.#1923 10.8um 10.8um 2 7
...
Total Counts 697 6382

Total Net Routing Area 542p(m^2)
Total Area (Gates+Routing) 106n(m^2)
 If you specify -average_report_options N, PowerArtist creates an additional

section that reports net transition time information.
6. Transition time of nets
==========================
Transition time(Sec.)
Net Rise Fall
--- ---- ----
top.Pclk 1.070e-10 1.070e-10
top.clk 1.070e-10 1.070e-10
...
top.core1.s1.#843 1.070e-10 1.070e-10
top.core1.s1.#491 1.070e-10 1.070e-10
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 If you specify -average_report_options V, PowerArtist creates an additional

section that reports power dissipation per power supply as well as how the
estimation of library voltages is determined.
2. Total power per supply
=========================
Estimation Library Power(Watts)

Supply Voltage(V) Voltage(V) Static Dynamic Total
------ ---------- ---------- ------ ------- -----
clock_gating.vdd 1.45 1.45 41.5nW 83.9uW 84uW
Estimation Voltage Source = nom_voltage
Library Voltage Source = nom_voltage
DP512x32.WW_Vdd 2.5 2.5 0W 344mW 344mW

std_cell_lib.vdd 2.5 2.5 142uW 2.72mW 2.86mW

txrxios.Vdd 3.3 3.3 2.64uW 94.8mW 94.8mW

Total power 145uW 442mW 442mW
 If you specify -average_report_options e, scientific notation is used to report

power numbers, as shown in the following report.

=============================
Power(Watts)
--------- ----- ------ ------- -----
top.core1.a1.#241 decoder 1.93e-06 0.00e+00 1.93e-06
top.core1.a1.#242 mux21 1.76e-06 0.00e+00 1.76e-06
 If you specify -average_report_options P, PowerArtist creates an additional

section that reports pin transition time information.
6. Transition time of pins
==========================
Transition time(Sec.)
Pin Rise Fall
--- ---- ----
top.sclk1.inpad.PAD 1.040e-10 1.040e-10
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top.sclk1.inpad.C 1.040e-10 1.040e-10

top.core1.u1.#133.in[0] 1.070e-10 1.070e-10
top.core1.u1.#133.out[0] 1.070e-10 1.070e-10
 If you specify -average_report_options g, PowerArtist creates an additional

section that reports net frequency and RTL glitch information, as shown in the
following report.
6. Net frequencies
==================
Net Type Glitch Edge rate

--- ---- ------ ---------
decode.metgen_top.afifo8x17.#858 Int 0.00% 31.7MHz
decode.metgen_top.afifo8x17.re_cnter Sync 0.00% 18MHz
decode.i_ry[0] PI 0.00% 4.42MHz
Possible net types include: Int (internal), Sync (synchronous), and PI (primary
input).
 If you specify the -average_report_options t, PowerArtist prints combined static
and dynamic instance power. This is applicable to all sections in the report file.
=============================
--------- ----- ------------
top.core1.a1.#241 decoder 1.93uW
top.core1.dpmem.m2.m2 DP512x32 1.43mW
 If you specified the -average_report_options v, PowerArtist replaces the gate

name with vendor_gate in the report as shown in the following sample.
=============================
Power(Watts)
--------- ----- ------ ------- -----
top.core1.a1.#241 decoder 1.93uW 0W 1.93uW
top.core1.p1.#1918 register 7.33uW 821uW 828uW
top.core1.r1.dpmem.m1.m1 vendor_gate 0W 47.9mW 47.9mW
...
Apache Design, Inc.

 The following example of a vertical report includes entries for each model type
only if you request a vertical report by specifying the -vertical_report_instances
and -detailed_vertical_report options to CalculatePower:
Power dissipation by model/gate type:

=====================================
Cell
Component Model Count Power(Watts)
--------- ----- ---- -------------
top.core1 8 24mW
Register power 2 4mW
Latch power 0 0mW
Memory power 0 0mW
Other power 6 20mW
adder_pg 2 8mW
comparator 1 1mW
decoder 1 5mW
mux21 2 6mW
register 2 4mW
========================================================
top.core2 12 36mW
Register power ...
...
Note that vertical reports do not include instances that are reported as part of
clock tree power.
Also, it is the number of instances being reported and not the number of bits. You
might have 1 register instance in the design that is 64-bit wide. The cell count will
be 1 not 64. If you performed clock gating in your design, you can obtain the
number of register bits from the Clock Gating Summary as shown here:
Clock Gating Summary:

---------------------
Clock net: top.clk
Number of inferred clock gating cells: 10
Number of registers gated by inferred clock gating cells: 376
Number of registers enhanced gated by inferred clock gating cells: 0
Number of instantiated clock gating cells: 0
Number of registers gated by instantiated clock gating cells: 0
Total number of gated registers: 376
Total number of ungated registers: 77
Notice the line “Number of registers enhanced gated by inferred clock gating
cells”. This line appears if you request enhanced clock gating be performed (using
the “-enhanced_cg true” option to the SetClockNet command. For more
information on enhanced clock gating, see Performing Enhanced Clock Gating,
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 If you specify the -average_report_options u, PowerArtist excludes vendor gates

from power and area reports. Use this option to reduce the size of your gate-level
power report. If you don’t use this option, every standard cell instantiation in your
design will be reported, which could add up to millions of lines. An excerpt of a
report with and without -average_report_options u is shown below. Power
variations are highlighted in red.
Sample Report with -average_report_options u
=============================
Power(Watts)
--------- ----- ------ ------- -----
...
...
Sample Report without -average_report_options u

=============================
Power(Watts)
--------- ----- ------ ------- -----
...
...
top.core1.dpmem.m2.m1 DP512x32 0W 14.3mW 14.3mW
...
 If you specify -average_report_options c, PowerArtist moves power associated

with clock switched-cap for registers or latches into the clock report. Excerpts of a
report with and without -average_report_options c are shown below. Power
variations are highlighted in red. If you specify an uppercase “C” option, then you
will get the clock switched-cap power for memories and IP blocks in your report.
Sample Report With -average_report_options c
==========================
Power(Watts)
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 921uW 959uW
Internal latch power 3.53uW 0W 3.53uW
Internal memory power 0W 344mW 344mW
Other internal power 100uW 964uW 1.06mW
Apache Design, Inc.

Total internal power 142uW 346mW 346mW

Clock power 2.69uW 7.1mW 7.1mW
Inferred Buffer power 139nW 4.9uW 5.04uW

=============================
Power(Watts)
--------- ----- ------ ------- -----
...
top.core1.t1.s1.#970 register 496nW 318nW 814nW
...

==========================
Power(Watts)
Net Type Static Dynamic Total
--- ---- ------ ------- -----
...
top.clk Inferred 2.46uW 5.97mW 5.97mW
...
Sample Report Without -average_report_options c

==========================
Power(Watts)
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 1.76mW 1.8mW
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=============================
Power(Watts)
--------- ----- ------ ------- -----
...
top.core1.t1.s1.#970 register 496nW 31.1uW 31.6uW
...

==========================
Power(Watts)
Net Type Static Dynamic Total
--- ---- ------ ------- -----
...
top.clk Inferred 2.46uW 5.69mW 5.69mW
...
 If you specify -average_report_options 0, PowerArtist creates an additional

section that reports internal driver power (the power required to toggle the net).
Excerpts of reports with and without -average_report_options 0 are shown below.
Power variations are highlighted in red. Note with -average_report_options 0 that
the internal load power is not reported as internal power consumption.
Sample Report With -average_report_options 0
==========================
Power(Watts)
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 999uW 1.04mW
Other internal power 100uW 143uW 243uW
Internal load power 0W 1.62mW 1.62mW

=============================
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Power(Watts)
--------- ----- ------ ------- -----
top.core1.r1.a1.#1721 xor 55.1nW 61.7nW 117nW
top.core1.r1.a1.#1722 xor 55.1nW 61.7nW 117nW
...
6. Internal load power consumption

==================================
Power(Watts)
Net Estimator Cap(F) Static Dynamic Total
--- --------- ------ ------ ------- -----
top.rx_rq Point to point 71fF 0W 13.2nW 13.2nW
top.updout[0] Point to point 79.1fF 0W 6.94uW 6.94uW
top.core1.s1.#309 Point to point 6.9fF 0W 0W 0W
top.core1.s1.#310 Point to point 6.9fF 0W 0W 0W
Note: Point to Point = Wireload model estimation.

Exact = SPEF or Capacitance file input
Note that the -r 0 option filters out the following nets:

— Nets that are traced as part of a clock network defined in your clock file
— Nets that do not have any capacitance value attached to them
— Nets that do not have any drivers or are driven by a connect or connect_inv
instance
— Nets that are the output of IO pads
— Nets with no output pins (that is, primary inputs)
Sample Report Without -average_report_options 0

==========================
Power(Watts)
----- ------------ ------ ------- -----
Internal power
Internal register power 38.4uW 1.76mW 1.8mW
Apache Design, Inc.


=============================
Power(Watts)
--------- ----- ------ ------- -----
...
top.core1.r1.a1.#1721 xor 55.1nW 1.15uW 1.21uW
top.core1.r1.a1.#1722 xor 55.1nW 1.15uW 1.21uW
...
 If you specify the -average_report_options d (and you provided a power diff file),
the new delta on parents in the power diff is reported for each section.
5. Internal Power difference to abc.res

=======================================
Component This(W) Ref(W) Diff(W)

--------- ------- ------ -------
top.core1.a1.#241 1.93uW 1.93uW -1.27E-21W
top.core1.a1.#242 1.76uW 1.76uW -1.27E-21W
6. Pad Power difference to abc.res

==================================
Component Pad type Cap(F) This(W) Ref(W) Diff(W)

--------- --- ---- ------ ------- ------ -------
top.sclk1.inpad PDI 2.09pF 1.91mW 1.91mW 200pW
top.sclk2.inpad PDI 1.94pF 1.91mW 1.91mW -7.24uW
7. Clock Power difference to abc.res

====================================
Net Estimator Cap(F) This(W) Ref(W) Diff(W)

--------- --------- ------ ------- ------ -------
top.clk Point to point 742fF 533uW 533uW -207pW
top.pci_clk Point to point 594fF 425uW 427uW -1.62uW
 If you specify -average_report_options r (and you have provided a power diff file),
the relative percentage delta on parents in the power diff is reported for each
section.
5. Internal Power difference to abc.res
=======================================
Component This(W) Ref(W) Diff(%)

--------- ------- ------ -------
Apache Design, Inc.

top.core1.a1.#241 1.93uW 1.93uW +0.000%

top.core1.p1.#1917 3.53uW 3.53uW +0.000%
top.core1.p1.#1918 842uW 844uW -0.207%
6. Pad Power difference to abc.res

==================================
Component Pad type Cap(F) This(W) Ref(W) Diff(%)

--------- --- ---- ------ ------- ------ -------
top.sclk1.inpad PDI 2.09pF 1.91mW 1.91mW +0.000%
top.sclk2.inpad PDI 1.94pF 1.91mW 1.91mW -0.379%
7. Clock Power difference to abc.res

====================================
Net Estimator Cap(F) This(W) Ref(W) Diff(%)

--------- --------- ------ ------- ------ -------
top.clk Point to point 742fF 533uW 533uW +0.000%
top.pci_clk Point to point 594fF 425uW 427uW -0.379%
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Analyzing Average Power Using a SAIF File
Analyzing Average Power Using a SAIF File

PowerArtist can perform an RTL, mixed RTL and gate or pure gate-level average
power analysis using a SAIF file, instead of a VCD or FSDB activity file. SAIF is a
well-defined ASCII format defined as part of the IEEE 1801 standard. SAIF files
capture toggle information directly from simulators. Since a basic SAIF format
contains only toggle counts, rather than value change sections as supplied by VCD
or FSDB files, using SAIF files has the following benefits:
 Faster simulation time since far less data is created by a simulator
 Less disk space is required for simulation.
 The SAIF file is smaller than an equivalent VCD file and therefore takes less time
to read during power analysis.
Despite these benefits, there are some drawbacks to using this format. The most
important one being that you cannot analyze power over time. As noted previously,
toggle counts are captured but not specific signal transitions and the time steps at
which they occurred.
The second problem is that signal correlation is not possible, again because only
toggle counts are stored. Therefore, state-dependent static power and dynamic
power calculations require heuristics to determine which conditions get matched in
your technology library. This results in less accurate power numbers when compared
to a full arc power analysis. This may be especially true for large macros like
compiled memories that have many pins and may have relatively complex power
modeling.
There are two SAIF formats. The basic format captures signal toggle information and
duty cycles. The State-Dependent/Path-Dependent (SDPD) format captures
information equivalent to the PowerArtist arcs in the GAF file. PowerArtist supports
both of these formats. If you want the most accurate power analysis results you should
use the SDPD format. Support for the SDPD format is in beta. This will be especially
true for a gate-level analysis. However, be aware that the power arc matching now
done during the CalculatePower command will now be done during your simulation
run. This your simulation will be slower than if you generate the basic format.
Flow Details
PowerArtist supports the SAIF format for average power analysis only. To use a SAIF
file, you need to specify the -saif_file option to the CalculatePower command in
addition to all of the other options you normally use, for example:
CalculatePower -analysis_type average -saif_file design.saif ...
PowerArtist automatically detects when the given SAIF file uses the SDPD format
and so will perform arc-based estimation. For basic SAIF files, PowerArtist
automatically performs pin-based analysis for RTL designs (and most gate-level
designs).
Apache Design, Inc.

Analyzing Average Power Using Partial Stimulus Files
Understanding Power Value Fluctuations Between SAIF and

Other Formats
You should expect subtle differences in power numbers for instances in your design
if you compare a SAIF-based power analysis with an equivalent VCD or FSDB-
based analysis.
Duty cycle is defined as follows:
duty_cycle = T1 / (T1 + T0)
where T1 = the total time in which the signal remains in the 1 state
T0 = the total time in which the signal remains in the 0 state.
Any X or Z values generated during simulation need to be translated into duty cycle
information. The equations used in the SAIF flow are:
duty_cycle = (T1 + (TX / 2) + (TZ / 2)) / (T1 + T0 + TX + TZ)
TCnew = TCSAIF + IG
In this equation the following apply:
 T1, T0, TX and TZ are fields from a line in the SAIF file
 TX and TZ is the total time in which the signal remains in the X or Z state,
respectively.
 TCnew is the newly calculated toggle counts
 TCSAIF is the original toggle count in the SAIF file
 IG are the internal glitches

PowerArtist can perform an RTL, mixed RTL and gate or pure gate-level average
power analysis without requiring that every user net name be present in an FSDB,
IAF or VCD file with its associated toggle information. If a net is not present in the
stimulus file but it is in the design, PowerArtist algorithmically estimates the activity of
the net while performing an average power analysis. Once it has estimated activity
values for all nets in the design, it then performs the power calculation. Note that the
more nets that are “missing” from the stimulus file, the less accurate the power
analysis. PowerArtist’s activity analysis allows you to trade-off the simulation time
and stimulus file size with the accuracy of the power analysis.
There are three flows to consider:
 RTL design using a partial RTL stimulus file
 Mixed RTL and gate or complete gate-level design using a partial RTL stimulus
file (see Name Mapping Flow).
 Gate-level design using a partial gate-level stimulus file (remember to use the
“-mixed_sim_prob_estimation true” option setting).
Apache Design, Inc.

In flows one and three, nothing special is required. If you are following the Palladium
flow (see Acquiring Simulation Data in Palladium Flows) CalculatePower will check
to make sure that the nets tagged as being selected in the scenario file are present
in your stimulus file. If not, CalculatePower issues a warning message.
Name Mapping Flow

In the second flow, you need a synthesized portion of a design (or all of the design)
to perform an average power analysis using an RTL stimulus file. You may find that
simulating designs at the gate level is becoming more difficult, but you still want to
perform a power analysis. There is one very important step that must be done before
this type of analysis is possible—name mapping.
During gate-level synthesis, the RTL design hierarchy often becomes flattened and
the RTL nets that will be inferred as registers are transformed into gate-level
instances; therefore, you must map as many of your RTL net names as possible into
gate-level equivalent names. Every gate-level net that is successfully mapped will
have its activity determined by CalculatePower using its RTL toggles. This toggle
information will be written out to the GAF file by the CalculatePower command. RTL
nets in the design will be mapped automatically assuming that you have not changed
either your RTL design hierarchy or your RTL modules between simulating the
design and starting the CalculatePower run. The missing nets will have their activity
calculated during average power analysis as in flows 1 and 3.
Currently, PowerArtist will do this gate-level mapping automatically using a mapping
file generated by Conformal™ from Cadence. Suppose for example that your original
design that you simulated was an RTL design. You would like to perform a power
analysis on a fully synthesized gate-level design. The steps you will follow are:
1. Simulate your RTL design and create a stimulus file.
2. Synthesize your design to the gate level
3. Create a “do” file that runs Conformal in its “compare” mode.
Running Conformal in the compare mode versus its full equivalency check mode
has two notable benefits. First, you can perform the mapping on your full-chip
design. There is no need for a hierarchical equivalence checking methodology so
the mapping step is much simpler to perform. Second, the performance is
significantly better. During an equivalence checking run, one of the first steps is a
compare operation that does the name mapping. Verifying the actual equivalence
between your RTL and gate-level netlists is what takes the most time.
The following “do” script sample shows how a compare run is performed:
vpxmode
// preserve original RTL register names
set naming rule "%s_reg" -register -golden
// preserve hierarchical block names in RTL signal naming
set naming rule %s %L[%d].%s %s -instance
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set system mode lec

remodel -seq_constant -repeat
add compare point -all
// compare
usage
report unmapped point > DESIGN.lec.unmapped
report compare data -class abort > DESIGN.lec.abort
report compare data -class noneq > DESIGN.lec.noneq
report mapped points > mapfile.dat
diag -sum
diag -all > DESIGN.lec.diag
exit -f
The key points to note in this script are:

a. The “set naming rule” command is specified to preserve the original names of
the RTL signals in the conformal mapping report.
b. The “compare” line is commented out. This tells Conformal to perform name
mapping only, without equivalency checking.
c. The name mapping file PowerArtist needs is generated using the “report
mapped points” command. The file created in this case, mapfile.dat, is what
CalculatePower will process.
4. Create your gate-level scenario file then run CalculatePower in its name mapping
mode to generate a GAF file and perform an average power analysis.
a. Specify the SetNameMapFile command. The syntax of this command is:
SetNameMapFile -map_file conformal_do_file_name -format conformal
Use the output of the Conformal “do” file as your file name.
b. Specify CalculatePower using the “-use_rtl_sim_data true” option to indicate
that you want to run in name mapping mode. This option indicates that the
specified GAF file will be generated by a name-mapped run.
You can run this entirely from a command file such as the following:
Elaborate -top top \
-gate_level_netlist true
-scenario_file design.scn
-verilog_startup_file design.vc
SetNameMapFile -map_file mapFile.dat -format conformal \
-top_instance testbench.top1 \
-average_report_file design.rpt \
-scenario_file design.scn \
-activity_file ../designData/design_rtl.vcd \
-gaf_file activities.gaf \
-synlib_files ../designData/flop.lib \
-use_rtl_sim_data true \
-gate_level_netlist true \
Apache Design, Inc.

Re-Using a Stimulus File from a Previous Run
The critical points are highlighted in red. You need to set the use_rtl_sim_data
variable to true to force the name mapping mode to occur. Notice that both the
Elaborate and CalculatePower commands are run in the gate netlist flow (that is,
they both specify the “-gate_level_netlist true” option).
The -use_rtl_sim_data option has a side effect of turning on the
-mixed_sim_prob_estimation and the -pin_based_estimation options. Without
-mixed_sim_prob_estimation turned on, missing nets will be flagged as errors.
The -pin_based_estimation option indicates that many nets are missing from the
design, so a complete arc-based power analysis is not possible.
Advanced Flows
At this point in time, PowerArtist supports name mapping files created by Conformal.
If you have Formality™ from Synopsys or have the ability to create you own name
mapping files, please contact your Apache Application Engineer who can answer
questions about how to handle such a flow. In the future, Apache plans to support
Formality.

Stimulus file processing typically takes a significant amount of time for any design of
substantial size. If you want to do some what-if experiments without re-reading your
stimulus file, you have to indicate this to the CalculatePower command. By default,
during a simulation-based, average power analysis, your stimulus file gets re-read. If
you want to prevent that from happening and you want to re-use the existing GAF file
created by a previous run, you must specify the following option:
-use_existing_gaf true
Apache Design, Inc.

Apache Design, Inc.

271
Chapter 10
Analyzing Time-Based Power 10
Introduction
PowerArtist allows you to obtain power and current waveforms as a function of time
for RTL, gate-level or mixed RTL and gate designs.
Before you run time-based power analysis, it is highly recommended that you read
Chapter 7, Preparing for Power Analysis, which describes prerequisite steps you
need to perform before you begin any power analysis. In addition, if you are a new
user, it is recommended that you run the full-chip tutorial. For details see, Running an
RTL Full-Chip Power Analysis Using Command Files.
Overall Design Flow

You should implement the following high-level design flow to perform time-based
power analysis:
1. Simulate your design and generate simulation data in the FSDB, IAF, or VCD formats.
2. Build a scenario file using the Elaborate command. For details, see Getting Your
Design into PowerArtist.
3. Run vector analysis using the GenerateActivityWaveforms command. For details,
see Analyzing Simulation Activity.
4. Run the CalculatePower -analysis_type time_based command. Details for this
process are documented in this chapter.
5. View the reports, in text format, created by the CalculatePower command or view
the results, in the PowerCanvas, that you created by saving the power database.
 Understanding the Inputs for a Time-Based Power Analysis
 Controlling Your Time-Based Power Analysis
 Understanding and Reviewing Outputs and Results of the Time-Based Analysis
 Monitoring Flop Clock Activity
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CHAPTER 10 — Analyzing Time-Based Power PowerArtist™ User Guide 272
Understanding the Inputs for a Time-Based Power Analysis
Understanding the Inputs for a Time-Based Power Analysis

To perform time-based power analysis you will need the following inputs:
 The CalculatePower -analysis_type time_based command with various other
options required for a time-based analysis. For complete syntax, see Syntax for
Time-Based Power Analysis.
 A scenario file representing the design generated by the Elaborate command. For
details, see Getting Your Design into PowerArtist.
 Libraries in Liberty format.
 Simulation traces stored in either FSDB, IAF or VCD formats.
 You can use any of the power-aware Tcl commands to control your power
analysis. Such commands include the SetClockGatingStyle and SetClockNet.
These commands and their functions are described in this chapter.
 Further, you may want to use the MonitorInstances and MonitorToggleInstances
commands to monitor various design elements. This chapter describes how you
would use these commands in your time-based power analysis.
Controlling Your Time-Based Power Analysis

As with all PowerArtist programs, you control the operation of your power analysis by
specifying the appropriate commands in your PowerArtist command file or on the
command line. To perform either an RTL, mixed, or gate-level time-based analysis,
you need to specify the CalculatePower command with the arguments required for
the type of analysis you want to perform. There are arguments that are required for
all time-based analyses, some for gate-level only and some for RTL only.
Required Options for all Time-Based Analyses

Use these arguments to provide various types of required inputs:
 -activity_file your_simulation_file
This option specifies an input stimulus file generated due to a functional simulator
run. The file may be in FSDB, VCD or IAF (generated by Apache PLI routines)
format. You must specify either -activity_file or -vectorless_input_file for an
average power analysis. CalculatePower automatically determines the type of the
simulation activity file.
 -scenario_file your_scenario_file
This option specifies the scenario file you generated using the Elaborate
command. For more information, see Getting Your Design into PowerArtist.
 -synlib_files {file_name1 file_name2 ...}
Adds the specified file or Tcl list of files to the list of Liberty technology files.
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Although not required, you will most likely want to use the start_time and -finish_time
options. For details see, Setting Timing Windows for Time-Based Power Analysis.
-top_instance top_simulation_instance
Specifies the full hierarchical name of the top-level module in the simulation
hierarchy.
Additional Arguments Required for Gate-Level Only

In addition to the options in the previous section, you must specify the following
arguments if you are running a gate-level analysis:
 -gate_level_netlist true
Specify this option if you want to performs a gate-level analysis.
 -interval_size seconds
Specifies the minimum time interval in seconds for which power will be reported.
The way in which the time-based analyzer calculates power depends on this
value.
If you specify an interval of size T >= 1 ns, the time-based analyzer will:
1 Breaks up the time-steps in your activity file into buckets of width T.
2 Calculates the total dynamic energy for every arc that matches during all time
steps processed for that interval.
3 Divides the dynamic energy by T.
4 Adds in the static power. This is the total power that will be displayed for that
interval.
If you do not specify an interval, then PowerArtist performs an instantaneous
analysis. For each time step in the activity file, PowerArtist:
1 Calculates the total dynamic energy for every arc that matches during that time
step.
2 Divides the energy by 1 ns to get power.
3 Adds in the static power. This is the total power that will be displayed for that
time step.
If you specify an interval of size T < 1 ns, PowerArtist generates a warning and
performs an instantaneous power analysis instead.
Additional Arguments Required for RTL and Mixed Analysis Only

In addition to the required options for all analyses, you must specify the following
arguments if you are running an RTL or mixed RTL-gate analysis:
 -reference_clock clock_name
Specifies the reference clock that controls when a clock starts and the length of its
period.
Apache Design, Inc.

 -active_edge auto | positive | negative

Specifies the edge of the clock that defines the start point for the first interval.
— positive: starts the clock when the first clock transition goes to 1.
— negative: starts the clock when the first clock transition goes to 0.
— auto: starts clock when the first clock transition goes to either 0 or 1.
Default: auto
 -num_clock_cycles int
Sets the interval size as a number of clock cycles. The interval size is the period
of the block into which PowerArtist will split the simulation. It is recommended that
you choose an interval greater than 1% of the total simulation time.
Default: 0
For additional options, see the CalculatePower entry in the PowerArtist Reference
Manual.
Setting Timing Windows for Time-Based Power Analysis

When performing a time-based power analysis, it is recommended that you make
sure that the -start_time and -finish_time options are set to be the leading edge of a
clock and the trailing edge of a clock, respectively. Then you need to select the
interval size used by your analysis. This is controlled by the -interval_size for gate-
level netlists and the -reference_clock_active_edge and -num_clock_cycles options
for everything else.
In general, the interval size should be a multiple of the clock period. The number of
clock periods impacts the performance and granularity of your analysis. Smaller
intervals take longer but give you more data.
At the gate level, you should, in general, set the -interval_size to be no less than one
clock cycle. For everything else, you will be setting the -num_clock_cycles option.
Every interval will require an average power analysis of the entire design. The size
should be no less than one clock cycle. The resulting waveforms will look more
realistic than if you had used arbitrary values for -start_time, -finish_time, and -
interval_size.
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Running the Analysis
Running the Analysis

It is recommended that you use a PowerArtist command file to run your time-based
power analysis. This analysis is controlled by the CalculatePower command.
Sample Command File for Gate-Level Time-Based Power Analysis
CalcualtePower -analysis_type time_based \
-activity_file design.vcd \
-clock_file clocks.tcl \
-finish_time 20ns \
-gate_level_netlist true \
-scenario_file design.scn \
-start_time 10ns \
-synlib_files ../libs/memories.lib ../libs/core.lib ../libs/ios.lib \
-time_based_report_file design.rpt
You can also run this command from the ptshell command line. The following three
examples assume that you are running with “-gate_level_netlist true” set; your
top_instance, scenario file and Liberty files have been specified. So these have not
been shown for clarity.
Example 1
CalculatePower -analysis_type time_based -interval_size 1e-9

This command performs a time-based analysis breaking your simulation time into 1
ns bins. In addition to generating design.rpt, it will generate a power waveform file in
CalculatePower.ptcl. The design.rpt file will contain a simple report for the top-level
instance in the design.
Example 2

-fsdb_output_file design.fsdb -ptcl_output_file design.ptcl
-output_current true
This command performs the same time-base analysis as Example 1 but will
generate current over time waveforms that will be stored in design.fsdb (fsdb format)
and design.ptcl (ptcl format).
Example 3
MonitorInstances -name top.core1

-fsdb_output_file design.fsdb -ptcl_output_file design.ptcl
-output_current true
These two commands performs a similar time-based analysis as in Example 2, but
the report and the waveform file outputs will include only hierarchical instance
top.core1. Note that all children instances will have their values included in the
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Understanding and Reviewing Outputs and Results of the Time-Based Analysis
information generated for top.core1. This is controlled by the MonitorInstances

command. For further control, you can also use the MonitorFast and MonitorArcs
commands.
 Sample Command File for RTL Time -Based Power Analysis
-active_edge positive \
-calculate_log CalculatePowerTimeBasedBatch.log \
-fsdb_output_file $design.TimeBasedBatch.fsdb \
-power_db_name $design.TimeBasedBatch.pdb \
-time_based_report_file $design.TimeBasedBatch.rpt \
-time_based_write_power_db true \
This example shows you how to perform a time-based analysis on a design that is
not entirely gate level. In this case, you do not specify the -gate_level_netlist true
option.
Understanding and Reviewing Outputs and Results of the Time-Based

Analysis
After the analysis is complete, the following outputs are generated:
 A log file whose name you can set using the CalculatePower -calculate_log
option.
 A report file containing an ASCII representation of the power analysis results.
 Waveforms in either the FSDB format or PowerArtist Tcl-based format that holds
the current and power over time information you requested. Waveforms are not
stored in the report file.
Contents of the ASCII Report File

If you specify, “-time_based_report_file mychip.rpt”, CalculatePower will generate an
ASCII report that contains the following information:
 A header section that provides the following information:
— The date of the power analysis
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— The particular version of the software used to perform the analysis

— The options applied during this run
— Summary information on the simulation run including simulation duration, start
and finish times
— The power supply values that were used
— The initial input transition time
— Monitor file name
— Wire load mode and model information
 Section 1: Power Contribution. This section is divided into the following sub-
sections:
— Category Power Summary. This group power section lists for each group:
 The category name
 Average power for all elements in the category broken into static, dynamic
and total power
 The maximum power in Watts
 One or more time steps in your simulation at which the maximum power
occurred.
— Instance Power Summary. This section lists for each monitored instance:
 Average power for all children of the instance (or just the instance itself if it
were a cell in a library) broken into static, dynamic and total power
 The maximum power in Watts
 One or more time steps in your simulation that the maximum power occurred
 The instance name at the end of the line because this field may be arbitrarily
long.
 Section 2: Detailed Instance Power. This section provides a per instance power
consumption report.
 Section 3: Clock Power Consumption. For details on this section, see Clock
Power Consumption.
 Section 4: Inferred Buffer Tree Power. If your design required buffer trees be
generated for high fanout nets, this section describes the affected nets and how
the buffer tree was created.
For a sample time-based power report, you can run through the analysis tutorial and
produce either the top.BatchTimeBased.rpt (generated by the command-line flow) or
the top.TimeBased.rpt files (generated by the wizard flow).
Generating and Viewing Waveforms

The CalculatePower -analysis_type time_based command can generate waveforms
of current and power over time for the categories and instances that you specified
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using the MonitorInstances command. You have your choice of two formats: FSDB or
PTCL.
If you specified the FSDB format (by specifying the CalculatePower -fsdb_output_file
option) you can load and display the waveforms in PowerArtist using the Apache
Waveform Viewer available in the PowerCanvas (select Tools > Waveform Viewer).
A sample waveform is shown in Figure 81.
Figure 81 Sample Power-Over-Time Waveform
Measuring the Distance Between Two Data Points

Once you are viewing a particular waveform of interest, you can measure the
distance between two data points on the waveform. To do so, you can use the ruler
feature as follows:
1. Place your cursor over an area on the waveform and press the “r” button to start
the ruler. You can now drag the ruler to any data point on the waveform and mark
it using the “m” key. A colored box (same color as the waveform) will appear at the
marked data point. This box includes the coordinates of the data point and the
delta x (dx) and delta y (dy) values from the first data point to second data point.
The dx value = (X of the end point) - (X of the start point), which the dy value = Y
of the end point) - (Y of the start point). Also, a copy of the ruler is recorded on the
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plot. You can continue measuring the distance to additional data points, or if you
are done, simply press the “r” key again to turn off the active ruler. Marked ruler(s)
will stay on the plot.
The following figure shows one measurement from a single data point.
Figure 82 Measuring Distance between Data Points
This feature is useful for presenting data in a presentation or in printed form. If you
want to present waveform data in printed form, it is recommended that you change
the background color to white (to save ink when printing) by selecting Toggle
background color from the options menu.
For more information on how to use the waveform viewer, see Using the Waveform
Viewer.
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If you specified an -interval_size that is less than 1ns for a gate-level design,
PowerArtist will perform an instantaneous power computation.
Figure 83 Sample Waveform in PTCL Format for Instantaneous Analysis
If you specified the FSDB format (using the -fsdb_output_file option) you can also
view that file in the Apache Waveform Viewer (or use Verdi to view your waveforms).
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Using Results
Using Results
You can use the results from a time-based power analysis in a number of ways. First,
peak power and current information can be used during the physical design process
to size your power busses. By selecting various hierarchical instances in your design
that will correspond to physical blocks, you can get a good idea of the power grid
needs on a block-by-block basis. Second, the total peak power and current values
can give you some idea of the power supply needs your chip will have. Third, by
examining areas of the waveform that have large swings in power or current from
one time step to the next, you can get an idea of any di/dt issues. The following
section describes how you can use the waveforms if you are a CoolTime user.
Using Peak Power or Current Information in CoolTime

Currently, if you want to perform a dynamic voltage drop analysis using CoolTime,
you must study the activity of your simulation trace using PowerArtist’s vector
analysis. You will typically choose the clock cycle that has the highest activity as your
clock cycle of interest. This generally will correspond to your peak power cycle as
well.
Using the time-based power analyzer, you can view waveforms that show either
power or current over time and determine the best clock cycle to analyze. You can
then use this information when performing your vector analysis to select the cycle of
interest.
Monitoring Flop Clock Activity

Flop clock activity (FCA) is a measure of the efficiency of the clock gating in your
design and can be monitored using time-based power analysis. The FCA feature
monitors the activity of clock pins on registers in your design. A low FCA number
implies that clocks are well gated. Conversely, a high FCA number indicates that the
clocks have not been well gated (due to either inefficient enables or non-enabled
registers) or the mode captured in the simulations requires clocks to toggle.
The FCA feature works at the RT level of abstraction only for both feedback MUX
topologies and for instantiated clock gates. The reports are in the form of PTCL
graphs (flop clock activity and average flop clock activity as a function of time) as
well as a text version which includes minimum, maximum and average counts of
flops whose clocks toggled during an interval expressed as a number and a
percentage. It also includes a total flop count per hierarchical instance per clock
domain. You can specify a list of hierarchical instances that you want FCA to monitor
using the MonitorToggleInstances command as shown:
MonitorToggleInstances -instances {top top.core1 top.core1.u1
top.core1.t1 top.core1.r1}
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This example tells PowerArtist to monitor the five specified instances. It then
generates results for each hierarchical instance you specified per clock domain as a
waveform in either the PTCL or FSDB file you specify.
To use this feature you must specify the following CalculatePower options:
-analysis_type time_based
-num_clock_cycles int
-reference_clock clock_name
-flop_clock_activity file_name_prefix
The interval size is the same across all clocks and determined by the arguments to
the -reference_clock and -num_clock_cycles options. The sample results waveforms
and text file on the following pages were generated with the full-chip analysis tutorial
using the following CalculatePower options:
-analysis_type time_based
-num_clock_cycles 20
-reference_clock top.clk
-flop_clock_activity fca
As an example, if you specify “fca” as the file_name_prefix argument to the

-flop_clock_activity option, the time-based analyzer creates the following three files:
 fca.txt
This is a text report that provides minimum/maximum/average statistics per clock
domain per specified instances. This is for both flop clock activity and average flop
clock activity metrics (see definitions below). The report includes both a number
and a percentage as a function of total flops. It also reports the total number of
flops (bits) for each instance per clock-domain. For a sample text report, see
Contents of the ASCII Report File.
 fca_avg.ptcl
This is a PTCL graph that shows averaged flop clock activity over time for all
monitored clocks and instances. The x-axis is the simulation time and the y-axis is
the average clock activity for the inferred register bits contained in that instance.
This differs from the fca.ptcl in that the numbers here are derated by the total
number of flops in the block.
 fca.ptcl
This is a PTCL graph that shows absolute flop clock activity over time for all
monitored clocks and instances. The x-axis is simulation time and the y-axis is the
absolute number of inferred register bits whose clocks toggled for that hierarchical
instance in that time step.
It is recommended that you use the two PTCL graphs together to investigate any
potential power bugs. You can open both the fca_avg.ptcl and the fca.ptcl graphs
place them both on the View tab as shown in the following sample.
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Sample Flop Clock Activity Graphs

The following figure shows both the average flop clock activity graph (on top) and the
absolute graph.
Figure 84 Sample Waveform in PTCL Format for Instantaneous Analysis
Looking at the average flop clock activity in the top graph, you can see that the
transmit clock domain (t1_top.clk) in brown is active when the receive clock domain
(r1_top.clk) in green is inactive and vice-versa. You can also see that the pci clock
domain (top.pci_clk) is always on, indicating that this could be a good candidate for
clock gating. To determine whether it’s worth your time to clock gate the pci clock,
you would need to check the absolute waveforms (displayed on the bottom half of
this figure). Looking at them here, you can see that there are approximately 20 flops
being clocked in the receive block (ut0|top.core1.r1_top.pci_clk) and even more in
the transmit block (ut0|top.core1.t1_top.pci_clk). Therefore, this could indicate a
power bug. To see the exact values, you can either hover your mouse on the
waveforms or read the text report (as shown on the next page).
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Sample Flop Clock Activity Report
Flop Clock Activity Report

==========================
Date : Wed Apr 13 11:21:15 2011
Program : PowerTheater Time Based Engine (64 Bit Linux) 2010.2.3PreAlpha (11 Apr 2011)
Interval Size : 303 ns

Reference Clock : top.clk
Number of clock cycle(s) : 20 clock cycle(s)
Min, Max, Average Clocked Flop Statistics

=========================================
Instance: top
Clock: top.clk There are 453 flops defined in hierarchical instance “top” and its chil-
Number of Flops : 453 dren that are driven by top.clock. top and its children.
Flop Clock Activity:
Minimum : 206 (45.4%) There existed one or more intervals where:
Maximum : 249 (55%) the minimum # of registers whose clock toggled was 206; the maximum
Average : 230 (50.8%) was 249;
Average Flop Clock Activity:

Minimum : 0.454 (45.4%) On average over all of the intervals, the minimum of # of clocks that
Maximum : 0.408 (55%) toggled was 45.4%; the maximum was 55%; and the average was
Average : 0.368 (50.8%)
50.8%.
<snip>
Instance: top.core1.r1
Clock: top.clk
Number of Flops : 77
Minimum : 1 (1.3%)
Maximum : 13 (16.9%)
Average : 5.98 (7.77%)
Minimum : 0.013 (1.3%)
Maximum : 0.169 (16.9%)
Average : 0.0777 (7.77%)
Clock: top.pci_clk
Minimum : 19 (100%)
Maximum : 19 (100%)
Average : 19 (100%)
Minimum : 1 (100%)
Maximum : 1 (100%)
Average : 1 (100%)
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<snip>
Instance: top.core1.t1
Clock: top.clk
Minimum : 1 (1.3%)
Maximum : 13 (16.9%)
Average : 7.12 (9.25%)
Minimum : 0.013 (1.3%)
Maximum : 0.169 (16.9%)
Average : 0.0925 (9.25%)
Clock: top.pci_clk
Minimum : 87 (100%)
Maximum : 87 (100%)
Average : 87 (100%)
Minimum : 1 (100%)
Maximum : 1 (100%)
Average : 1 (100%)
<snip>
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287
Chapter 11
Analyzing Vectorless Average Power 11
Flow Overview
You can use PowerArtist to run a vectorless power analysis. To do so, you need to
employ the following flow:
1. Run the Elaborate command to build a scenario file.
2. Create a Vectorless Activity File (VAF) that contains the activity information.
3. Run the CalculatePower command with the “-vectorless_input_file file_name.vaf”
option.
Vectorless power analysis is a convenient way to quickly generate “what-if”
scenarios that give you a good idea of what your power may be in various situations.
Accurate power numbers come from simulation-based analysis.
Creating the VAF File

The VAF is used to specify activity and duty cycle information for critical signals in
the design. This section describes the commands used in the VAF. For complete
syntax and examples for all of the commands in this section, see the individual
command descriptions in the PowerArtist Reference Manual.
You can use wild cards for net names and port names in the commands used in the
VAF.It may be easiest to create an OADB script that automatically generates the
commands. You can start with the sample scripts available in the following directory:
$POWERTHEATER_ROOT/examples/OpenAccess
Setting the Frequency and Duty Cycle for Clock Nets

You must specify the frequency or activity and duty cycle information for every clock
net in the design using the SetNetStimulus command.
Example
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CHAPTER 11 — Analyzing Vectorless Average Power PowerArtist™ User Guide 288
SetNetStimulus -net top.clock -frequency 1e+08 -duty 0.6

This example sets the frequency for the net top.clock to 100 MHz. It also sets the
duty cycle to 0.6 (the default is 0.5).
If you performed clock gating using integrated clock gating cells, you should also set
the gated clock output frequency. To set the frequency for gated clock nets, you
would use the SetNetStimulus command.
Setting the Frequency for Primary Inputs

You must specify the frequency or activity for all of the primary inputs of the design
using the SetNetStimulus command or the SetPortStimulus command. If a net is
connected to a module, you can set the frequency using either the SetNetStimulus or
SetPortStimulus. For the SetPortStimulus command, you specify the hierarchical
path to the instance and then the port name. For the SetNetStimulus command, you
specify the hierarchical path to the net.
Example 1
SetPortStimulus -instance top -port addr -frequency 1e+08
This example sets a frequency of 100 Mhz to all bits of port addr of instance top.
Example 2
SetNetStimulus -net {top.we} -frequency 1e+6 -duty .8
This example sets a frequency of 1 Mhz and a duty cycle of .8. to net top.we.
You may be inclined to set the same frequency for all of your primary inputs and
doing so may be fine, depending on the goals you are trying to achieve. However,
you should give this careful consideration as setting all of the primary inputs to one
value will greatly impact accuracy.
Setting the Frequency for Ports of a Specific Type

You can use the SetPortStimulus command with the -type option to set the frequency
(and duty cycle) on ports of a specific type—input, output or both.
Example
SetPortStimulus -port b* -type input -frequency 1e+08
This example sets a frequency of 100 Mhz for all input ports that start with b.
Setting the Duty Cycle of Critical Control Signals that are Not Primary Inputs
Suppose that there are critical signals that are tied to a particular value that you want
to remain constant. These constant values can be controlled by supplying a duty
cycles of 0 (constant 0) or 1 (constant 1).
Example
SetNetStimulus -net {top.alu.globalEn} -duty 1
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This example sets the duty cycle of top.alu.globalEn to be a constant 1. Using the
SetNetStimulus command in this way accomplishes what case analysis does for
static timing analysis.
Setting the Activity and Duty Cycle for Busses Driven by Tri-Stated Signals
If a signal has multiple drivers that are tri-states, you should set the desired activity
and duty cycle for the bus that represents the combination of all the tri-stated signals
using the SetNetStimulus command.
Setting the Frequency and Duty Cycle on Leaf-Level Instances

You can use the SetPortStimulus command to set the frequency and duty cycle on all
of the input and output nets of a specified leaf-level instance.
Example
SetPortStimulus -instance inst –port * –frequency f –duty d
Setting the Frequency for Memories

You must specify the port frequencies for critical ports on your memories. You can
use the SetNetStimulus or SetPortStimulus commands for this. Setting these is
critical because memories account for a significant portion of the power of your chip.
Output port frequencies must be set as well to enable correct power calculation and
because the CalculatePower command cannot propagate activities and duty cycles
through memories. Instances in the downstream cone of logic from a memory need
these values to compute their power correctly.
Example
SetPortStimulus -instance rxchan.dpmem.m0.m1 -port *
-frequency 2.76e+7
This example sets the average frequency for all ports of memory instance
rxchan.dpmem.m0.m1 to 27.6 Mhz.
Handling Blackbox Instances

PowerArtist cannot propagate activity or duty cycles during a power analysis on any
instances that were black-boxed during the Elaborate run; therefore, for every output
port of the instance, you must specify the activity, frequency, and duty cycle using the
SetPortStimulus command.
Example
SetPortStimulus -instance top.myblackbox -port * -type output
-frequency 1e+5 -duty .7
This example sets a frequency of .1 Mhz and the duty cycle of .7 to all output ports
on blackbox instance top.myblackbox.
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Understanding Common Warning Messages

If you do not use your VAF commands carefully, you may create certain conditions
where conflicting settings are being attempted on the same object. In these cases,
PowerArtist will generate an warning message indicating the conflict and how it is
being resolved. This section provides some examples of conditions (cases) under
which you will see certain warning messages.
Example 1: Mixing Commands or Using SetInstanceStimulus Commands

If you specify the SetInstanceStimulus command, you will see a warning message
indicating that it is now obsolete. Also, if the command setting conflict, you will see a
message that indicates how PowerArtist is handling the conflicting settings. For
example, if you had the following command settings:
SetPortStimulus –port P1 –frequency f1 –duty d1 -instance inst1
SetInstanceStimulus -instance inst2 –frequency f2 –duty d2
SetInstanceStimulus -instance inst3 –frequency f3 –duty d3
you would see the following warning messages:

The 'SetInstanceStimulus' command will no longer be supported in a future release.
Please start using 'SetNetStimulus' and 'SetPortStimulus'
Following commands are trying to set frequency/activity/duty values on the same net 'N'
SetPortStimulus for inst1.p1 frequency 'f1' duty 'd1' ( command 1 : foo.vaf)
SetInstanceStimulus for inst2 frequency 'f2' duty 'd2' ( command 2 : foo.vaf)
SetInstanceStimulus for inst3 frequency 'f3' duty 'd3' ( command 3 : foo.vaf)
last specified data, frequency 'f3' duty 'd3', will be used.
Example 2: Two Net Names that Resolve to the Same Net

If you have two command settings with net names that resolve the same net you will
get an warning message. For example, if you have the following command settings:
SetNetStimulus –net top.a –frequency f1 –duty d1
SetNetStimulus –net top.module.a –frequency f2 –duty d2
you will see the following warning message:

SetNetStimulus for top.a frequency 'f1' duty 'd1' ( command 1 : foo.vaf)
SetINetStimulus for top.module.a frequency 'f2' duty 'd2' ( command 2 : foo.vaf)
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Example 3: Conflicting Value Setting for the Same Object (Net/Port)

If you have two commands that are trying to set different values on the same object
(net/port) you will get a warning message. For example, if you have the following
command settings:

SetPortStimulus for inst1.P1 frequency 'f1' duty 'd1' ( command 1 : foo.vaf)
Example 4: Conflicts Caused by Wild Cards

If you use a wild card with your commands, you could create a situation where there
are conflicting settings for the same object. For example, if you have the following
command settings:
SetPortStimulus –port P* –frequency f1 –duty d1 -instance inst1
SetNetStimulus –net N – frequency f3 –duty d3

SetPortStimulus for inst1.P* frequency 'f1' duty 'd1' ( command 1 : foo.vaf)
SetNetStimulus for N frequency 'f3' duty 'd3' ( command 3 : foo.vaf)
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Note: The following material is not available in this version
of the Power Artist User Guide:
o Chapter 4 - PowerArtist Tutorial Part II : Power Reduction
o Chapter 12 - Examining and Implementing Power Reduction

Opportunities
377
Chapter 13
Performing Functional Verification of

RTL Changes 13
Introduction
You can perform functional verification of changes made to the RTL by power
reduction using one of three verification methods. You may choose to use one of the
industry-standard formal verification tools, you may use the nCompare™ utility from
SpringSoft or, you may want to perform a functional simulation of your design.
Using Standard Verification Tools by Defining ADS_PA_FV

PowerArtist encapsulates sequential changes inside an ìfdef ADA_PA_FV
conditional compilation directive such as the following:
ìfdef ADS_PA_FV
assign enable = 1'b1;
èlse
reg enable;
always @(posedge ck_in)
begin
enable <= next;
end
èndif
If you want to use the industry-standard tools, such as Conformal™or Formality™,

you can set the ADS_PA_FV conditional compilation directive in your tool of choice.
Defining ÀDS_PA_FV in your Conformal or Formality setup replaces the delay
register with a constant wire, which stops the formal verification from producing an
error when encountering additional registers.
Limitations of the this Approach
The value of this approach may be limited. Although it does verify that PowerArtist
RTL changes have not impacted any other functionality in the design, apart from the
new enables, it does not verify the impact of the new enables on the functionality.
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CHAPTER 13 — Performing Functional Verification of RTL Changes PowerArtist™ User Guide 378
Generating a Rule File to use in the nCompare Utility (Beta)

assistance.
The Verdi™ debug system from SpringSoft includes a powerful waveform

comparison tool called nCompare™. This approach involves generating a rule file
from the PowerArtist power database that you can then load into nCompare. If you
usually use Verdi for functional verification, you may find this method useful. Using
this method, you do not need to compare all of the signals as you would without a
rule file. To generate this rule file, you need to run the WriteReductionCompareFile
(Beta) command.
Use Model
Use the following flow to run a functional verification with a rule file:
1. Run the ReducePower command to generate a power database.
2. This step is optional. If you want to compare signal changes due to all accepted
reductions (not only those that are rewritten) you can generate a rule file at this
point by specifying the WriteReductionCompareFile (Beta) command with the “-
reduction_compare_type auto” command-line option1. You are also required to
specify the power database, the top instance name, and the name for the output
rule file. For example,
WriteReductionCompareFile -power_db_name design.pdb
-top_instance test.top
-reduction_compare_output_rule_file design.pdb.rc
-reduction_compare_type auto
You can also use the optional arguments to the WriteReductionCompareFile to
perform various functions as described here:
-reduction_compare_error_report_file error_report_file_name
Specifies the name of the file into which nCompare will output any mismatch error
messages. You can use the nce2report SpringSoft utility to generate a readable
text/html report as follows
nce2report -i error_report_file_name ...
-reduction_compare_golden_sim_file file_name
Specifies the path to the original FSDB file. If you do not specify this, PowerArtist
will use a place holder variable (set GoldenFSDB golden_fsdb_name) in the rules
file that you will later need to edit (see step 6).
1. As with all command file commands, you can use pt_set variables in your run script
instead of command-line options.
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-reduction_compare_secondary_sim_file file_name
Specifies the path to the new FSDB file that you get when you re-simulate your
design using the rewritten RTL. If you do not specify this option, PowerArtist will
use a place holder variable (set SecondaryFSDB fsdb_file_name) in the rule file
that you will later need to edit (see step 6).
If you specify these options in the command, you will not need to perform hand
editing of the rule file (as described in step 6). For a full list of options, see the
WriteReductionCompareFile (Beta) command description.
If you want to generate a rule file for only the rewritten reductions, you can skip
this step.
3. Run the RewriteRTL command. You will use the resulting Verilog start up file (.vc)
with the accepted RTL changes that you accepted.
4. Run the WriteReductionCompareFile command at this point to generate a rule file
for the reductions that were rewritten by the RewriteRTL command. You can set
the “-reduction_compare_type rw” option (or not specify it at all since “rw” is the
default).
5. Re-simulate your design using the .vc file generated by the rewrite process.
This will produce the updated FSDB file that you will then specify in your rule file.
6. Perform any necessary hand editing of the rule file.
For example, you may have to add the name of the updated FSDB file in the
SecondaryFSDB variable setting.
set SecondaryFSDB <Specify_Secondary_Fsdb_Here>
You can also specify this name when you generate the rule file (if you know it
already) by specifying the -reduction_compare_secondary_sim_file option, to the
WriteReductionCompareFile command. Doing so will automatically set the
SecondaryFSDB variable in the rule file to the correct name.
7. Run the nCompare utility on the rule file using the following command:
nCompare -rule rule_file
Note: You can generate a formatted report that is easy to read in either text or
HTML format using the nce2report utility:
nce2report -i error_file ... additional_options
You can also view the results using the nWave™ tool, also from SpringSoft.
Apache Design, Inc.

Flow Diagram
The following flow diagram illustrates the process for generating an nCompare rule
file to for functional verification of RTL changes (as detailed in the previous section).
Original
FSDB
ReducePower
pwr database
(.pdb)
RewriteRTL
WriteReductionCompareFile
rule file
.vc file
Re-Simulate Design Modified nCompare

FSDB
Figure 89 Typical RTL Verification Flow Using the nCompare Utility
Sample Output Rule File

The following sample rule file was generated by the WriteReductionCompareFile
(Beta) command.
################################################################################
# Apache Design, Inc.
#
# File Type : PowerArtist/XP nCompare waveform comparison rule file
# Version : 2010.1.3PreAlpha (64 Bit Linux) 31 Aug 2010
# Design Name : top
# Date of Generation : 31 Aug, 2010 14:16:02 IST
Apache Design, Inc.

#
# Options used -
# -power_db_name : design.pdb
# -reduction_compare_error_report_file : design.pdb.rc.nce
# -reduction_compare_golden_sim_file : test.orig.fsdb
# -reduction_compare_output_rule_file : design.pdb.rc
# -reduction_compare_secondary_sim_file : test.post.fsdb
# -reduction_compare_type : auto; all the signals due to
accepted reductions
# -top : top
# -top_instance : test.top
#
################################################################################
#
# open golden and revised simulation files
#
set GoldenFSDB test.orig.fsdb --> If this is not set, you will need to set it
before using nCompare.
set SecondaryFSDB test.post.fsdb --> If this is not set, you will need to set it
before using nCompare.
cmpOpenFsdb $GoldenFSDB $SecondaryFSDB
#
# set default hierarchy delimiter as "."
#
cmpSetDelimiter .
#
# set maximum errors to 1500 snd maximum per signal errors to 10
#
cmpSetCmpOption -MaxError 1500 -MaxErrorPerSignal 10
#
# compare input and output ports
#
cmpSetSignalPair test.top.clk
cmpSetSignalPair test.top.we
cmpSetSignalPair test.top.me
cmpSetSignalPair test.top.sel_mem_next
cmpSetSignalPair test.top.addr\[0\]
<snip> ...
cmpSetSignalPair test.top.qout\[31\]
#
# compare GMC registers
#
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cmpSetSignalPair test.top.mem01.Q\[31\]
cmpSetSignalPair test.top.mem01.Q\[30\]
<snip> ...
cmpSetSignalPair test.top.mem01.LSI_SCAN_OUT
#
# all mismatch error messages will be output to design.pdb.rc.nce
#
cmpSetReport design.pdb.rc.nce
#
# start comparision
#
cmpCompare
Performing Functional Simulation

If you want to perform functional simulation of your rewritten design, you will want to
know the impact of the power reduction techniques that PowerArtist applied. The
code modifications performed vary with each PowerBot. For details on the code
modifications done by the LNR, GMC and Prism PowerBots, see the following
sections:
 Form of the Code Modifications for LNR
 Form of the Code Modifications for GMC
 Form of Code Modifications for Prism
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383
Chapter 14
Analyzing the Effects of Power Gating

with Proprietary Commands 14
Introduction
Defining voltage domains and performing power gating can help to aggressively
reduce power. Early visibility into design trade-offs involving these techniques at the
RT level of abstraction can be valuable. There are two methods for exploring multiple
voltage domains and performing power gating in PowerArtist—using only PowerArtist
proprietary commands or using a combination of proprietary commands and CPF or
UPF commands. This chapter describes a method for exclusively using PowerArtist
proprietary commands to explore multiple voltage domains, define power domains
and perform either a simulation-based or a vectorless analysis of power domains.
Using Common File Formats
For information on using the CPF or UPF file formats, see Using Standard File
Formats. Note that if you intend to use UPF as input, you still need to thoroughly
read this chapter. The Using a UPF Input Flow (Beta) and Using a CPF Input Flow
(Beta) sections describe only that portion of the overall flow that UPF or CPF can
replace, the remaining steps in the flow are described only in the following sections
in this chapter.
 Required Inputs for Power Gating
 Special Option to the Elaborate Command
 Setting up Your Command File for Power Gating
 Performing Simulation-Based Power Analysis with Power Gating
 Performing Vectorless Power Analysis with Power Gating
 Understanding the Output Reports for Power Gating Analysis
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CHAPTER 14 — Analyzing the Effects of Power Gating with Proprietary Commands PowerArtist™ User Guide 384
Required Inputs for Power Gating

The following inputs are required for this flow:
 Libraries in Liberty format with required power gating attributes. For more
information, see Defining Libraries.
 RTL source files in which Verilog begin blocks and VHDL processes are named
where you want to control the default cell selection for retention flops and latches.
For more information, see Creating Source Files.
 A PowerArtist command file
The command file contains all of the Tcl commands used to specify inputs such as
clocks, defines libraries to be used in various portions of your design, virtual
supplies, voltage and power domains and wire load models. In a vectorless
analysis, while defining a virtual supply, the ON condition must be a constant 0 or
constant 1. In simulation-based analysis, that condition can be any legal boolean
expression of the design nets in the target language.
 A scenario file representing the RTL or mixed RTL and gate design
Use the Elaborate command to create your scenario file. If you are performing a
vectorless power analysis, the amount of instantiated gate-level logic should be
small (to almost non-existent) as to minimize any problems with propagating
activity through gates. For complete details on creating a scenario file, see Getting
Your Design into PowerArtist. In addition, see the Special Option to the Elaborate
Command for information specific to power gating. You may also analyze an
entire gate-level design. However, you must not use the -gate_level_netlist switch
on either the Elaborate or CalculatePower commands. Otherwise, you will be
prevented from performing a power gating analysis.
 If you are using a simulation-based flow, you will also need an activity file in either
FSDB, VCD or IAF file formats. The VCDe format is generated by Apache PLI
routines. For more information on activity file formats, see Acquiring Simulation
Data.
 The reference clock name
If you are using a simulation-based flow, you must specify a reference clock. This
is the fastest clock in the design. It is used to calculate activity factors. All other
signals will be assumed to be toggling slower than this signal.
 The number of clock cycles per calculation interval
If you are using a simulation-based flow, once the number of clock cycles is
reached, the time-based analyzer performs an average power calculation for that
interval. This process is repeated from the -start_time to the -finish_time giving
you a power-over-time curve.
 Vectorless input file
This is required if you are running a vectorless flow. For details, see Performing
Vectorless Power Analysis with Power Gating.
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Defining Libraries
To use the power gating feature, you must add the following attribute to the
appropriate Liberty library.
 power_gating_cell
This is a cell-level attribute that indicates that the given cell is a retention flop or
latch. You will use the MapRetentionCell command to map a type of retention cell
specified by the value of this attribute to a particular always block.
A portion of a typical Liberty retention flip-flop cell definition might look like:
cell (retflop) {
rail_connection (PVDD, VDD);
rail_connection (PVDDC, VDDC);
power_gating_cell : LOW;
leakage_power () {
value : 2.72E+01;
when : "RET";
power_level : VDDC;
}
leakage_power () {
value : 5.91E+03;
when : "RET";
power_level : VDD;
}
leakage_power () {
value : 2.89E+01;
when : "!RET";
power_level : VDDC;
}
leakage_power () {
value : 5.89E+03;
when : "!RET";
power_level : VDD;
}
pin (RET) {
internal_power () {
power_level : VDDC;
...
}
internal_power {} {
power_level : VDD;
...
}
}
...
}
Apache Design, Inc.

Creating Source Files
Creating Source Files

Apache has established a convention that allows you to control how and when
retention flops and latches will be selected when doing default cell selection. This
convention relies on the use of named begin blocks for Verilog or named process
statements for VHDL.
In your library, you will have a variety of retention cells. By understanding how your
design operates, you may want to control which latches or flops from your power
libraries are chosen at a very fine level of granularity. In Verilog, this will normally be
down to the always @ block level and to the process level in VHDL. The following
sample fragments of Verilog and VHDL demonstrate its use:
Sample Verilog
module top(....);
...
always @(posedge clock)
begin : tag1
out1 = in1;
end

begin : tag2
out2 = in2;
end

begin : tag3
out3 = in3;
end
endmodule
Sample VHDL
architecture synth of top is

...
begin
tag1: process (clock)
begin
if (clock = '1' and clock'event) then
out1 = in1;
end if
end process
tag2: process (clock)

begin
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Special Option to the Elaborate Command
out2 = in2;
end if
end process
tag3:process (clock)
begin
out3 = in3;
end if
end process
end synth;
Later sections will show how to control default cell selection so that out1 can be one
type of retention flop, out2 can be another and out3 can be a third type.
Special Option to the Elaborate Command

To use power gating, you will need to specify the “-tag_blocks true” option to the
Elaborate command in your Tcl file. The resulting tags will be used later in the
MapRetentionCell command to control retention cell default cell selection.
Setting up Your Command File for Power Gating

When running any type of PowerArtist analysis, you need to do the following:
 Define how you want your clocks inferred using the SetClockNet command.
 Ensure that the wire load models are being selected correctly to ensure that
interconnect capacitance is being estimated correctly.
 Define output loads. For details see Using Apache Default Wire Load Models for
Capacitance Analysis.
In addition, for a power gating flow you will need to do the following:
 Define which libraries are used by which hierarchical instances.
 Define virtual supplies (design rails) that are associated with library power rails.
 Define power domains. For this, you need to:
— Define the virtual supplies associated with a hierarchical instance.
— Define the power gating condition that controls the virtual supply.
 Optionally, define the mapping for retention cells.
Defining Library Associations

As part of the power gating flow, you need to define which libraries will be used for
power analysis for various hierarchical instances using the SetLibrary command.
Assigning one or more libraries to an instance controls the following:
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Setting up Your Command File for Power Gating
 Default cell selection for the RTL power models;

 Wire load model selection for use in estimating interconnect capacitance for the
instance (if your libraries contain wire load models);
 Gate-level power models for instantiated cells;
 Power rail names that are available for use by voltage and power domains.
For complete details on how to use the SetLibrary command, including syntax and
examples, see Handling Designs with Multiple Libraries.
Defining Virtual Supplies

As part of the power gating flow, you need to define virtual supplies. Virtual supplies
are used by PowerArtist to perform “what-if” experiments with respect to voltage
islands or derating the voltages in libraries. They are also used for power gating
applications. To define virtual supplies, you need to specify the CreateVirtualSupply
command. For more information on using this command see, For complete details,
see Creating a Virtual Supply.
Defining Power Domains

To use power gating, you will have to create voltage and power domains. To do this,
you need to use the CreateDomain command. For complete details, see Assigning a
Virtual Supply to a Hierarchical Instance.
Defining Retention Cell Mapping

As part of the power gating flow, you need to define the assignment of retention flops
and latches to particular inferred register and latch instances. This is done by naming
Verilog begin blocks or VHDL process statements (as described in Creating Source
Files) and then providing the MapRetentionCell command for the named begin
blocks or process statements.
Sample Command File for a Power Gating Flow

The following sample command file includes the set up commands, library
definitions, virtual supply definitions, etc. for a power gating flow:
# Power Gating Settings

#SetLibrary -instance {top.core1.u1 top.core1.a1 top.core1.s1} -library {hvt lvt}
# Power gating specific settings #

...
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Performing Simulation-Based Power Analysis with Power Gating

Performing Simulation-Based Power Analysis with Power Gating

To run a time-based power analysis that includes power gating, create a command
file that contains the CalculatePower command with the appropriate options for time-
based analysis, for example:
# Power analysis for simulation-based power gating flow #

-time_based_upf_in_file my.upf \
-activity_file my_file.iaf \
-synlib_files {my_lib1.lib my_lib2.lib} \
-top_instance top \
-finish_time 20ns -start_time 20ns \
-reference_clock myclock.clk \
-time_based_report_file time_based.rpt \
-time_based_write_power_db true
You can just add this CalculatePower command specification to the command file
you created in the following section (that includes the SetLibrary,
CreateVirtualSupply, etc. commands) or you can source that .tcl file from this one
using the “source” command.
Performing Vectorless Power Analysis with Power Gating

To perform a vectorless power analysis that takes into account power gating, you
need all of the inputs listed in the section Required Inputs for Power Gating except
those specific to time-based analysis. In addition, you need to create a vectorless
activity file that you then specify to the CalculatePower command in your command
file using the -vectorless_input_file options, for example:
# Power analysis for vectorless power gating flow #

-vectorless_input_file my_file.vaf \
-top_instance top \
-average_report_file average.rpt \
-average_write_power_db true
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Understanding the Output Reports for Power Gating Analysis
Creating a Vectorless Activity File

Vectorless power analysis requires a Vectorless Activity File (.vaf). The .vaf file is an
ASCII format file created using your favorite text editor whose format is defined in
Analyzing Vectorless Average Power.
To get reasonable power analyses, the .vaf file must:
 Accurately define the frequency and duty cycle for your clocks and primary IOs of your
design.
 For clock gating, specify the frequency and duty cycles of enable signals.
 Specify the read/write frequencies for the memories in your design.

Reports generated when analyzing the effects of power gating include additional
sections over the basic power report.
Sample Report for Simulation-Based Analysis

The Time Based Power Report contains the Detailed Instance Power section that
identifies the power and voltage domains with the type name “domain”.
2. Detailed Instance Power

==========================
Average Power(Watts) Type Model Instance

Static Dynamic Total Name Name Name
------ ------- ----- ---- ---- ----
236.97uW 26.314mW 26.551mW domain domain_0
0W 0W 0W user -inst1
0W 0W 0W user -inst2
0W 0W 0W CELL1 --inst_imp
0W 0W 0W user -inst_switch
0W 0W 0W SWITCH1 --inst2_switch
275.01nW 0W 275.01nW user -io_inst
33pW 0W 33pW and --#381
< snip >
After the Total power per supply section (not shown), there a section called “Power
Per Domain”. This section provides power numbers for each defined power domain,
both for average power and On Power. The average power is the overall average
which includes power consumption for times when the power domain is on and off.
Apache Design, Inc.

Conversely, the “On Power” is the average power consumed only when the power
domain is switched on.
4. Power Per Domain

===================
Average Power (Watts) On Power (Watts) Domain

Static Dynamic Total Static Dynamic Total Name
------ ------- ----- ------ ------- ----- ----
118.74uW 24.841mW 24.96mW 118.81uW 24.856mW 24.975mW domain_0
Lastly, there a section called “Power Domain Summary”. This section provides
information on the power domains set up for this design. Information includes library
names and details of the virtual supplies (including On condition setting, analysis
voltage, and static and dynamic power numbers).
5. Power Domain Summary

=======================
Domain domain_0
----------------------
Library typical
File: ../typical.lib
Library typical1
File: ../typical1.lib
Library typical2
File: ../typical2.lib
Virtual Supply: VDDSW_0
Library Supplies:
typical1.VDD
typical2.VDD
typical3.VDD
typical4.VDD
typical.VDD
Estimation Voltage: 1.2 V (from Tcl file)
On condition: domain1_on & ! domain2_on
Average Static Power: 116.33uW
Average Dynamic Power: 23.404mW
On Static Power: 116.41uW
On Dynamic Power: 23.419mW
Virtual Supply: VDDSW_1
Library Supplies:
typical4.VDDNW
typical.VDDNW
On condition: domain1_on & domain2_on
Average Static Power: 799.43nW
Apache Design, Inc.


On Static Power: 799.93nW
Sample Report for Vectorless Analysis

Vectorless analysis reports contain two changes beyond normal time-based analysis.
First, the Internal Power Consumption section highlights the power for each domain
by setting the Model to “domain”. This is shown in the following excerpt.

=============================
Power(Watts)
Component Model Supply Static Dynamic Total
--------- ----- ------ ------ ------- -----
instance_1 user VDD_typ 26.9nW 226mW 226mW
#48 and VDD_typ 35.9pW 1.64nW 1.68nW
#55 comparator VDD_typ 506pW 3mW 3mW
#56 comparator VDD_typ 502pW 2.92mW 2.92mW
ra1 domain VDD_typ 3.56nW 40.5mW 40.5mW
#1 latch VDD_typ 568pW 13.9mW 13.9mW
#2 latch VDD_typ 1.14nW 17.3mW 17.3mW
<snip>
Total internal power 26.9nW 226mW 226mW
Secondly, this report also includes a section called “Power Domain Summary”. This
section provides information on the power domains defined for this design.
Information includes library names and details of the virtual supplies (including On
condition setting, analysis voltage, and static and dynamic power numbers
associated with the supply).

=======================
Domain instance_1.ra2
-----------------------
Library typical
File: typical.lib
Library typical2.db
File: typical2.small.lib
Virtual Supply: VDD_typ
Library Supplies:
typical.vdd
On condition: 1
Static Power: 26.9nW
Dynamic Power: 226mW
<snip>
Apache Design, Inc.

Virtual Supply: VDDNSW

Library Supplies:
typical2.db.VDDNW
On condition: On
Static Power: 0W
Dynamic Power: 0W
Domain instance_1.ra1
-----------------------
Library typical
File: typical.lib
Library typical2.db
File: typical2.small.lib
Virtual Supply: VDD_typ
Library Supplies:
typical.vdd
On condition: 1
Static Power: 26.9nW
Dynamic Power: 226mW
<snip>
Virtual Supply: VDDNSW1
Library Supplies:
typical2.db.VDDNW
On condition: 1
Static Power: 0W
Dynamic Power: 0W
Apache Design, Inc.

Apache Design, Inc.

395
Chapter 15
Using Standard File Formats 15
Introduction
PowerArtist supports three power formats:
 Proprietary PowerArtist commands
 CPF commands
 UPF commands
The proprietary commands are a superset of the supported commands in both UPF
and CPF formats. These proprietary commands create a superset data model that
gets extended as PowerArtist supports more commands in either the CPF or UPF
standards. CPF and UPF are not translated in the proprietary commands but instead
are mapped directly to the underlying data model. This chapter describes the CPF
and UPF formats. It also includes a small section on using SDC.
 Using a CPF Input Flow (Beta)
 Using a CPF Output Flow (Beta)
 Using a UPF Input Flow (Beta)
 Using an SDC Input Flow
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CHAPTER 15 — Using Standard File Formats PowerArtist™ User Guide 396
Using a CPF Input Flow (Beta)

assistance.
PowerArtist allows you to specify multiple voltage domains and power gating design
intent/constraints in the Common Power Format (CPF). You can perform power
gating analysis by creating multiple power domains in CPF and then providing the
nominal condition for these domains. PowerArtist performs an analysis based on the
power gating constraints that you specify. While you can mix and match CPF and the
PowerArtist proprietary commands, you can’t mix UPF and CPF commands.
CPF Input Use Model

Follow these high-level steps to perform power gating analysis with multiple power
domains in CPF:
1. Define the power domains, nominal conditions, library sets and other low-power
intent in the CPF format.
2. Specify power-related constraints using the CPF commands where available. For
example, to specify retention cell definitions, you need to use the
define_state_retention_cell, create_state_retention_rule and
update_state_retention_rules CPF commands.
3. Specify other power-related constraints using the PowerArtist proprietary
commands. For example, if you want to do a mixed-Vt analysis, you need to use
the SetVT command.
4. Run RTL power analysis with or without simulation vectors. For simulation-based
analysis, you will run the time-based analysis engine (CalculatePower -
analysis_type time_based). For vectorless analysis, run the average power
analysis engine (CalculatePower -analysis_type average).
5. To specify constraints in the CPF format, you must specify the any of the following
CalculatePower command options, depending on the type of analysis you are
performing:
 -average_cpf_in_file cpf_file_name
 -reduction_cpf_in_file cpf_file_name
 -time_based_cpf_in_file cpf_file_name
An example would be:
CalculatePower -time_based_cpf_in_file my.upf
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Sample CalculatePower Command for a Simulation-Based Analysis

-time_based_cpf_in_file my.upf \
-activity_file my_file.fsdb \
-synlib_files {my_lib1.lib my_lib2.lib}
-top_instance top \
Supported CPF 1.1 Commands

Though the software supports a subset of the total CPF 1.1 command set, it will read
CPF files that use all of the available commands. Commands not supported are
ignored. Similarly, the software ignores any command options that are specified but
not supported. PowerArtist supports the following CPF 1.1 commands (with the listed
options only):
create_global_connection -net net_name -pins pin_list [-domain domain]
create_ground_nets -nets net_list [-voltage float]

[-external_shutoff_condition expression]
create_nominal_condition -name string -voltage float
create_power_domain -name power_domain

[-default | -default -instances instance_list | -instances instance_list]
[-shutoff_condition expression]
create_power_mode -name string -domain_conditions domain_condition_list [-default]
create_power_nets -nets net_list [-voltage float]

[-external_shutoff_condition expression | -internal]
create_state_retention_rule -name string

{-domain power_domain | -instances instance_list} [-exclude instance_list]
define_library_set -name library_set -libraries library_list
define_state_retention_cell -cells cell_list [-library_set library_set] [-cell_type string]

{-restore_function expression | -save_function expression | -restore_function expression
-save_function expression}
end_design
set_array_naming_style string
set_cpf_version value
Apache Design, Inc.

set_design module
set_hierarchy_separator character
set_power_target {-leakage float | -dynamic float | -leakage float -dynamic float}
set_power_unit [pW | nW | uW | mW | W]
update_nominal_condition -name condition -library_set library_set
update_power_domain -name domain {-primary_power_net net_name |

-primary_ground_net net_name}
update_state_retention_rules -names rule_list {-cell_type string | -cells cell_list}
Sample CPF Input

The following example illustrates the use of CPF in PowerArtist.
# general commands
set_cpf_version 1.1
set_design top
set_array_naming_style \[%d\]
set_hierarchy_separator .
set_power_unit uW
# define the library sets

define_library_set -name LibSet_0 -libraries { ../../libs/apache/alf/alf_common/hvt.alf \
../../libs/apache/alf/alf_common/retn.alf \
../../libs/apache/alf/alf_vlog/mem.alf }
# create nominal conditions

create_nominal_condition -name NC_0 -voltage 1.10
# associate library sets with nominal conditions

update_nominal_condition -name NC_0 -library_set LibSet_0
# create power domains

create_power_domain -name PD_0 -default
create_power_domain -name PD_1 -instances { core1.r1 } -shutoff_condition { !rx_rq }
create_power_domain -name PD_2 -instances { core1.t1 } -shutoff_condition { !tx_rq }
# create power/ground nets

create_power_nets -nets {VDDRX RX_VDDNWS} -voltage 1.1 -external_shutoff_condition {!rx_rq}
create_ground_nets -nets RX_VRET -voltage 1.1 -external_shutoff_condition {rx_rq}
create_power_nets -nets { VDDTX TX_VDDNWS} -voltage 1.1 -external_shutoff_condition \
{!tx_rq}
create_ground_nets -nets TX_VRET -voltage 1.1 -external_shutoff_condition {tx_rq}
create_power_nets -nets VDDRX_new -voltage 1.1
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create_global_connection -net VDDRX -pins vdd -domain PD_1

create_global_connection -net VDDTX -pins vdd -domain PD_2
create_global_connection -net RX_VDDNWS -pins {VDDNW VDD } -domain PD_1
create_global_connection -net TX_VDDNWS -pins {VDDNW VDD } -domain PD_2
create_global_connection -net RX_VRET -pins VRET -domain PD_1
create_global_connection -net TX_VRET -pins VRET -domain PD_2
create_global_connection -net VDDRX_new -pins vdd -domain PD_0
# create power modes

create_power_mode -name PM_0 -domain_conditions { PD_0@NC_0 PD_1@NC_0 PD_2@NC_0 } \
-default
create_power_mode -name PM_1 -domain_conditions { PD_0@NC_0 PD_1@NC_0 }
create_power_mode -name PM_2 -domain_conditions { PD_0@NC_0 PD_2@NC_0 }
create_power_mode -name PM_3 -domain_conditions { PD_0@NC_0 }
#retention cells
define_state_retention_cell -cell_type CK_LOW -cells NRTCLDFFBQ_F1 -restore_function "RET"
create_state_retention_rule -name RULE1 -instances {core1.t1 core1.r1} -exclude \
{core1.t1.l1.* core1.r1.d1.*}
update_state_retention_rules -names RULE1 -cell_type CK_LOW
end_design
Sample PowerArtist Report Section for the CPF Flow

Using CPF to specify your power intent impacts the Power Domain Summary portion
of your report file. The input in the previous section may generate a report section
that looks like the following:

=======================
Domain top.PD_0
---------------
Library hvt
File: ../../libs/apache/alf/alf_common/hvt.alf
Library RETENTION_EXAMPLE_LIB
File: ../../libs/apache/alf/alf_common/retention.alf
Library Memories
File: ../../libs/apache/alf/alf_vlog/mem.alf
Virtual Supply: top.PD_0.VDDRX_new
Library Supplies:
hvt.vdd
lvt.vdd
Memories.vdd
RETENTION_EXAMPLE_LIB.vdd
Estimation Voltage: 1.1 V (from TCL file)
Average Dynamic Power: 963.97uW
Apache Design, Inc.

On Static Power: 4.4158uW

On Dynamic Power: 963.97uW
Virtual Supply: OtherVirtualSupplies_top.PD_0_1.32
Library Supplies:
iopad.VDD_1.320
Estimation Voltage: 1.32 V (from library power_supply)
On condition: 1
Average Static Power: 46.145mW
On Static Power: 46.145mW
Virtual Supply: OtherVirtualSupplies_top.PD_0_2.7
Library Supplies:
iopad.VDD_2.700
Estimation Voltage: 2.7 V (from library power_supply)
On condition: 1
Average Static Power: 0W
On Static Power: 0W
Domain top.PD_1
---------------
Library hvt
Library Memories
Virtual Supply: top.PD_1.VDDRX
Library Supplies:
hvt.vdd
lvt.vdd
Memories.vdd
On condition: top.rx_rq
Virtual Supply: top.PD_1.RX_VDDNWS
Library Supplies:
hvt.VDD
lvt.VDD
Memories.VDD
RETENTION_EXAMPLE_LIB.VDD
RETENTION_EXAMPLE_LIB.VDDNW
Apache Design, Inc.

On condition: top.rx_rq
Average Static Power: 380.62pW
On Static Power: 948.59pW
Virtual Supply: top.PD_1.RX_VRET
Library Supplies:
RETENTION_EXAMPLE_LIB.VRET
On condition: !top.rx_rq
Average Dynamic Power: 57.093nW
On Dynamic Power: 95.354nW
Domain top.PD_2
---------------
Library hvt
Library Memories
Virtual Supply: top.PD_2.VDDTX
Library Supplies:
hvt.vdd
lvt.vdd
Memories.vdd
On condition: top.tx_rq
Average Static Power: 1.1263mW
Virtual Supply: top.PD_2.TX_VDDNWS
Library Supplies:
hvt.VDD
lvt.VDD
Memories.VDD
RETENTION_EXAMPLE_LIB.VDD
RETENTION_EXAMPLE_LIB.VDDNW
On condition: top.tx_rq
Virtual Supply: top.PD_2.TX_VRET
Apache Design, Inc.

Library Supplies:
RETENTION_EXAMPLE_LIB.VRET
On condition: !top.tx_rq
Average Dynamic Power: 739.44nW
Key Points
In the power domain section of this report, note the following information:
 The name of a power domain specified in the CPF file is qualified with the scope
in which it is created.
 The name of a virtual supply specified in the CPF file is qualified with the power
domain for which it is created.
 The estimation voltage is the voltage of the power/ground nets specified with the
create_power_nets/create_ground_nets commands.
The “on condition” of the virtual supply is the on state condition of the domain if the
domain has its own on state condition. If the domain does not have its own on state
condition, then the on state condition of power/ground nets will be used.
Apache Design, Inc.

Using a CPF Output Flow (Beta)

assistance.
As a PowerArtist user, you may be accustomed to performing what-if analysis to

explore different power and voltage domain architectures and then trying to
determine the best possible combination to meet your power budget. If you are using
Multiple Supply Voltage (MSV) and Power Shut-Off (PSO) low power techniques in
your design, you can have PowerArtist write-out a file containing Common Power
Format (CPF) constraints. This CPF-out flow uses CPF constraints to capture your
MSV and PSO design intent.
You can then use these constraints with other tools like Cadence’s RTL Compiler™.
The CPF constraints are written in an ASCII format, allowing you to add to or modify
the generated CPF commands to fit your needs. Note that these commands may not
capture all of the information needed to synthesize the design and perform physical
design.
To use the CPF-out flow, you will need to specify the name of the CPF output using
the either the -average_cpf_output_file or the -time_based_cpf_output_file to the
CalculatePower command.
Example
CalculatePower -analysis_type average
-average_cpf_output_file example.cpf
When using a CPF-out flow, you will need to use particular options to existing MSV
and PSO Tcl commands in PowerArtist. These options correspond to the options
supplied in the CPF equivalent commands:
 -name domain_name option to the CreateDomain command
Specifies the name of the domain being created.
 -domain domain_name(s) option to the SetLibrary command
Specifies a list of domains in which all instances use cells from the specified
library list. This option is require for a CPF-out flow.
Example
SetLibrary -domain {PD0} -library {typical_1 typical_2}
SetLibrary -domain {PD1 PD2} -library {typical_3 typical_4}
The first command in the example specifies that all instances in the PDO domain
use cells from the two libraries: typical_1 and typical_2. The second command
specifies that all instances in domains PD1 and PD2 use cells from the two
libraries: typical_3 and typical_4.
Apache Design, Inc.

 -default on | off option to the CreateVirtualSupply command

Use this option to specify the state of the main power net of the domain (and
therefore the state of the domain) in the default power mode in CPF. It is optional
and the default value for this option is “on”.
The SetPowerTarget command is also used in a CPF-out flow.
Mapping PowerArtist Tcl Commands to Generated CPF

Commands
The following table shows lists the PowerArtist commands and the corresponding
CPF commands that are generated as part of the CPF-out flow.
PowerArtist Command Generated CPF Commands
SetLibrary -domain domain_name(s) define_library_set -name Libset_name

-library lib_name(s) -libraries lib_name(s)
If -instance is given, it is ignored. Notes:
 A unique Libset_name string is created.
 library_file_name is the library file name,
along with its path, that has the specified
library.
create_nominal_condition -name name

-voltage value
Notes:
 A unique name string is created. Also,
the voltage value is the estimation
voltage of the library set given with the
SetLibrary command.
update_nominal_condition -name NCname

-library_set Libset_name
Notes:
 This command is generated for each
define_library_set. The Libset_name is
the same as that in the define_library_set
command. Also, an NCname
corresponding to the Libset_name will be
used.
Apache Design, Inc.

CreateVirtualSupply -supply create_power_nets

power_rail_name -nets virtual_supply_name
-virtual_supply supply_name -voltage value
[-voltage voltage] [-external_shuttoff_condition value]
[-on condition] [-default on | off]
Notes:
Note: The power rail name must not be  A separate create_power_nets command
qualified by library name, for the CPF-out
flow. is generated for each
CreateVirtualSupply and voltage value as
given in the command.
 -external_shuttoff_condition:
— added for those virtual supplies with
the -on conditions that are not the
main power supply of a domain. Its
value is an inverted -on value.
— added for those virtual supplies with
the -on condition that are main power
supplies of a domain that do not have
any same voltage secondary supply
without an -on condition. Its value is
an inverted -on value.
CreateDomain -name domain_name create_power_domain -name domain_name

-instance instance_name(s) [-instances instance_name(s)]
-virtual_supply supply_name(s) [-default]
Notes:
 Generated for each CreateDomain
command.
 -default: Only the domain with the top
module name will have this.
Apache Design, Inc.

CreateDomain cont. update_power_domain

-name domain_name
-internal_power_net virtual_supply_name
Notes:
 The domain_name is same as that of the
create_power_domain command.
 The -internal_power_net value is the
name of the first virtual supply in the list
given by the CreateDomain command.
This net is treated as the main power
supply of the domain.
create_power_switch_rule -name name

-domain domain_name
-external_power_net virtual_supply_name
Notes:
 A unique name string is created.
 It is generated for the main power supply
of a domain, if:
— this main power supply has a “-on”
condition
— there exists an always on (that does
not have any -on condition) secondary
power supply in the domain, that has
the same voltage as the voltage of this
power supply.
 The -external_power_net value is the
secondary virtual supply that has no -on
condition specified.
create_global_connection
-domain domain_name
-net virtual_supply_name
-pins power_rail_name
Notes:
 Generated for each virtual supply name
in the list specified with the
CreateDomain command.
 The power_rail_name is the power rail
for that virtual supply.
Apache Design, Inc.

CreateDomain cont. create_power_mode -name mode_name

-domain_conditions domain_condition(s)
[-default]
Notes:
 An MSV design will have only one
create_power_domain command which
will have -default specified.
 A PSO design will contain 2^n modes
and therefore will create 2^n
create_power_mode commands. Where
n is the number of the domain that has a
-shutoff_condition.
 -default: Specifies that this mode is the
mode in which domains will be working
using the default value of their main
power supply as mentioned in their
corresponding CreateVirtualSupply
command
create_isolation_rule -name name

-isolation_condition expression
-from domain_list -isolation_target from
Notes:
 Created for all of the domains with a
-shutoff_condition.
 -isolation_condition is the power domain
-shutoff_condition
 -isolation_target is always “from”
create_level_shifter_rule -name name

-from domain_list -to domain_list
Notes:
 Generated for all domains with a lower
nominal_condition voltage value as -from
domain list to domains with a higher
nominal_condition voltage value as -to
domain list.
CpfIncludeFile -name file_name source file_name

Note:
 The file path can be relative or absolute.
Apache Design, Inc.

SetPowerTarget set_instance instance_name_relative_to_top

[-instance instance_name(s)]
-static static_value -dynamic dynamic_value set_design module_name_of_instance
Note:
set_power_target -leakage static_value
 If you do not specify -instance, the power -dynamic static_value
target is set for the top module instance
and only the set_power_target command end_design
is generated.
 You must specify either one or both of
the static/dynamic values.
These CPF commands are automatically set_cpf_version 1.0

generated by PowerArtist.
PowerArtist generates these commands as set_design top_module
part of the header commands in the CPF Note:
file. There are no equivalent commands in  The top_module is the top module in the
PowerArtist.
PowerArtist scenario file.
set_power_unit mW
Quick Reference Checklist for CPF Output Flow

This section provides a list of items to keep in mind while running a CPF-out flow.
 You must specify the name of the CPF output file using the either the
-average_cpf_output_file or -time_based_cpf_output_file options to the
CalculatePower command (either in average or time_based mode, respectively).
Example for Time-Based Analysis
CalculatePower -analysis_type time_based -time_based_cpf_output_file example.cpf
 You must have a CreateDomain command for the top-level module in the design.
 Each domain—including the domain of the top-level module—must be associated
with a SetLibrary command. The SetLibrary command must have the -domain
option.
 In the CreateVirtualSupply command, the supply name must not be qualified by
any library name. For example:
# The following will not work properly.

# CreateVirtualSupply -supply {Lib1.vdd} -virtual_supply {VDD_top}
# The following will work

CreateVirtualSupply -supply vdd -virtual_supply {VDD_top}
Apache Design, Inc.

 If you do not specify the -voltage option with the CreateVirtualSupply command,
the following will happen:
— The voltage value of the supply (power rail) corresponding to the domain’s
library set is selected as the voltage value for that net.
Example
CreateVirtualSupply -supply vdd -virtual_supply {VDD_top}
CreateDomain -name top -instance top -virtual_supply {VDD_top}
# Assume for the example that lib1 has a VDD power rail with a value of 2.5V
SetLibrary -domain {top} -library {lib1 lib2}
# Generated "create_power_nets " rule for "VDD_top" will have 2.5V as its
voltage value
create_power_nets -nets VDD_top -voltage 2.5
— For nets not associated with any Power domain, the voltage value is selected
as the first matching library supply (power rail) voltage from the libraries
specified in the in your command file.
 The first virtual supply in the list of virtual supplies specified with the
CreateDomain command should have a -voltage value matching the estimation
voltage of the library set to which that domain is associated. If a primary net has a
non-matching voltage, a create_nominal_condition CPF command with the virtual
supply’s voltage value is generated. This nominal_condition will not have a
corresponding update_nominal_condition and the following warning is issued:
Warning 1556: PrimaryNet VDD_typ1, of domain PD1 has voltage 2.5,
which is different than domain's library set estimation voltage
1.5 Creating a Nominal condition NC_2 with voltage 2.5 which will
not have library set associated to it through
update_nominal_condition in cpf_out file
 If you have multiple CreateVirtualSupply commands with same -virtual_supply
name, the following will happen:
— if the -supply values are different, then the same virtual supply is associated
with all of the supplies (power rail) from different CreateVirtualSupply
commands.
— the -voltage and -on values are taken only from the first CreateVirtualSupply
command.
Sample Input and Output for a CPF Flow

This section provides a sample of PowerArtist Tcl commands for a CPF output flow
and the corresponding CPF file that is generated.
Apache Design, Inc.

PowerArtist Tcl Commands
CpfIncludeFile -name ../LibDef.cpf
SetPowerTarget -static 0.030 -dynamic 0.250
# Note -domain rather than -instance for CPF out.

SetLibrary -domain {PD1 PD2 } -library {Lib1 Lib2}
SetLibrary -domain {PD3} -library {Lib3 Lib4}
CreateVirtualSupply -supply vdd -virtual_supply VDD -voltage 1.1 -default on

CreateVirtualSupply -supply vdd -virtual_supply VDD1 -voltage 1.1 -on \
{!(pcu_inst.pau[2])} -default on
CreateVirtualSupply -supply vdd -virtual_supply VDD2 -voltage 2.5 -on \
{!(pcu_inst.plu[2])} -default on
CreateDomain -name PD1 -instance {core core.alu_inst} -virtual_supply {VDD}

CreateDomain -name PD2 -instance {core.alu_inst.aui core.alu_inst.lui} \
-virtual_supply {VDD1 VDD}
CreateDomain -name PD3 -instance core.rf_inst -virtual_supply { VDD2}
MapRetentionCell -net {core.rf_inst.rf\\[7\\]* } -attribute CLK_FREE
Corresponding Generated CPF
set_cpf_version 1.0
source ../LibDef.cpf
set_design core
# define the library sets

define_library_set -name LibSet_0 -libraries {../libs/Lib1.lib ../libs/Lib2.lib}
define_library_set -name LibSet_1 -libraries {../libs/Lib3.lib ../libs/Lib4.lib}
# create nominal conditions

# associate libaray sets with nominal conditions

# create power domains

create_power_domain -name PD2 -instances { alu_inst.aui alu_inst.lui } \
-shutoff_condition { pcu_inst.pau[2] } \
-default_restore_edge { !(pcu_inst.pau[2]) } -default_save_edge { pcu_inst.pau[2] }
create_power_domain -name PD3 -instances { rf_inst } -shutoff_condition \
{ pcu_inst.plu[2] } -default_restore_edge { !(pcu_inst.plu[2]) } \
-default_save_edge { pcu_inst.plu[2] }
Apache Design, Inc.

create_power_domain -name PD1 -instances { alu_inst } -default
# declare power and ground nets

create_power_nets -nets VDD -voltage 1.1
create_power_nets -nets VDD1 -voltage 1.1 -internal
create_power_nets -nets VDD2 -voltage 2.5 \
-external_shutoff_condition { pcu_inst.plu[2] }
# create power modes

create_power_mode -name Mode_PD2_0_PD3_0 -domain_conditions { PD1@NC_0 }
create_power_mode -name Mode_PD2_1_PD3_0 -domain_conditions { PD2@NC_0 PD1@NC_0 }
create_power_mode -name Mode_PD2_0_PD3_1 -domain_conditions { PD3@NC_1 PD1@NC_0 }
create_power_mode -name Mode_PD2_1_PD3_1 -domain_conditions \
{ PD2@NC_0 PD3@NC_1 PD1@NC_0 } -default
# create rule for level shifter insertion

create_level_shifter_rule -name LS_0 -from { PD2 PD1 } -to { PD3 }
# create rule for isolation cell insertion

create_isolation_rule -name ISO_0 -isolation_condition { pcu_inst.pau[2] } \
-from { PD2 } -isolation_target from
create_isolation_rule -name ISO_1 -isolation_condition { pcu_inst.plu[2] } \
-from { PD3 } -isolation_target from
#create rule for power switch insertion

create_power_switch_rule -name SW_0 -domain PD2 -external_power_net VDD
# create global connections

create_global_connection -domain PD1 -net VDD -pins { vdd }
create_global_connection -domain PD2 -net VDD1 -pins { vdd }
create_global_connection -domain PD2 -net VDD -pins { vdd }
create_global_connection -domain PD3 -net VDD2 -pins { vdd }
# update power domains

update_power_domain -name PD2 -internal_power_net VDD1
update_power_domain -name PD3 -internal_power_net VDD2
update_power_domain -name PD1 -internal_power_net VDD
# specify power targets

set_power_unit mW
set_power_target -leakage 30 -dynamic 250
# create rule for state retention insertion

create_state_retention_rule -name CSRR_CLK_FREE -instances { \
rf_inst.rf[7][0] rf_inst.rf[7][1] rf_inst.rf[7][2] }
end_design
Apache Design, Inc.

Using a UPF Input Flow (Beta)

assistance.
This flow uses a combination of Unified Power Format (UPF) commands and
proprietary commands. PowerArtist allows you to specify multiple voltage domains
and power gating design intent/constraints in the UPF format. You can perform
power gating analysis by creating multiple power domains in UPF and then
establishing the power and ground supply connections for these domains. You can
selectively switch these on and off using power switches.
PowerArtist performs an analysis based on the power gating constraints that you
specify. Keep in mind that if you use UPF to define virtual supplies and power
domains, you still need to use the proprietary commands to define libraries, source
files, and other information. It is recommended that you read Analyzing the Effects of
Power Gating with Proprietary Commands before reading this section so that you
understand the scope of what UPF can replace within that greater flow.
UPF Input Use Model

Follow these high-level steps to perform power gating analysis with multiple power
domains in UPF:
1. Define the power domains, nominal conditions, library sets and other low-power
intent in the UPF format.
2. Specify power-related constraints using the UPF commands where available. For
example, to specify retention cell definitions, you need to use the
define_state_retention_cell, create_state_retention_rule and
update_state_retention_rules UPF commands.
3. Specify other power-related constraints using the PowerArtist proprietary
commands. For example, if you want to do a mixed-Vt analysis, you need to use
the SetVT command.
4. Run RTL power analysis with or without simulation vectors. For simulation-based
analysis, you will run the time-based analysis engine (CalculatePower -
analysis_type time_based). For vectorless analysis, run the average power
analysis engine (CalculatePower -analysis_type average).
5. For vectorless analysis, you should set the on_state option of the
create_power_switch UPF command to 0, 1, true or false. You should not provide
a net name as an on_state value because that means the switch will be
considered to be always on. In vectored analysis however, you can specify an
on_state with the net name.
Apache Design, Inc.

6. To specify constraints in the UPF format, you must specify the any of the following
CalculatePower command options, depending on the type of analysis you are
performing:
 -average_upf_in_file upf_file_name
 -reduction_upf_in_file upf_file_name
 -time_based_upf_in_file upf_file_name
An example would be:
CalculatePower -time_based_upf_in_file my.upf
Sample CalculatePower Command for a Simulation-Based Analysis

-time_based_upf_in_file my.upf \
-activity_file my_file.fsdb \
-top_instance top \
Supported UPF Commands and Options

PowerArtist supports the following UPF commands:
create_power_domain domain_name [-elements l list] [-include_scope]

[-scope inst_name]
create_supply_port port_name [-domain domain_name] [-direction in | out]
create_supply_net net_name -domain domain_name [-reuse]
create_power_switch switch_name -domain domain_name

-output_supply_port {port_name supply_net_name} -input_supply_port {port_name
supply_net_name} -control_port {port_name net_name} ... -on_state {state_name
input_supply_port {boolean_function}}
connect_supply_net net_name [-ports port_list] [-domain domain_name]

[-rail_connection rail_type]
set_domain_supply_net domain_name -primary_power_net supply_net_name

-primary_ground_net supply_net_name
add_port_state port_name {-state {name (nom | min nom max | o)} [-state ...]
set_scope inst_name
Apache Design, Inc.

Sample UPF Input

This file sample shows commands that can be used in a PowerArtist UPF file.
set_scope top_module/conb1
create_power_domain PD_top -elements {ra2} -scope top_module/conb1

create_power_domain PD_Hamsa -elements {ra1} -include_scope
add_domain_elements PD_top -elements ra3
create_supply_net VDD_core -domain PD_top

create_supply_net VDD_Hamsa -domain PD_top
create_supply_net VDD_Hamsa -domain PD_Hamsa -reuse
create_supply_port VSS_port -direction in
add_port_state VSS_port -state {OFF off}
connect_supply_net VDD_core -rail_connection VDDNW -domain PD_top

connect_supply_net VDD_Hamsa -rail_connection VDD -domain PD_top
create_power_switch sw_Hamsa \
-domain PD_Hamsa \
-input_supply_port {vin VDD_core} \
-output_supply_port {vout VDD_Hamsa} \
-control_port {ctrl 0} \
-control_port {abc 1} \
-on_state {on_state vin {ctrl && abc}}
create_supply_net VSS -domain PD_top

create_supply_net VSS -domain PD_Hamsa -reuse
connect_supply_net VSS -rail_connection VDDC -domain PD_top

connect_supply_net VSS -ports VSS_port
add_port_state sw_Hamsa/vout -state {ON 0.99 1.2 3}
set_domain_supply_net PD_Hamsa -primary_power_net VDD_Hamsa -primary_ground_net VSS

set_domain_supply_net PD_top -primary_power_net VDD_core -primary_ground_net VSS
Sample PowerArtist Report Section for the UPF Flow

Using UPF to specify your power intent impacts the Power Domain Summary portion
of your report file. The input in the previous section may generate a report section
that looks like the following:

=======================
Apache Design, Inc.

Domain top_level.PD_m1
----------------------
Library sc9_cmos11lp_base_rvt_tt_nominal_max_1p10v_25c
File: ../libs_converted/sc9_cmos11lp_base_rvt_tt_nominal_max_1p10v_25c.lib
Library sc9_cmos11lp_pmk_rvt_tt_nominal_max_1p10v_25c
File: ../libs_converted/sc9_cmos11lp_pmk_rvt_tt_nominal_max_1p10v_25c.lib
<snip>
Virtual Supply: top_level:PD_m1:VDD
Library Supplies:
sc9_cmos11lp_pmk_hvt_tt_nominal_max_1p10v_25c.VDDG
sc9_cmos11lp_pmk_rvt_tt_nominal_max_1p10v_25c.VDDG
Average Dynamic Power: 0W
On Static Power: 0W
On Dynamic Power: 0W
Virtual Supply: top_level:PD_m1:VSS
Library Supplies:
sc9_cmos11lp_base_hvt_tt_nominal_max_1p10v_25c.VSS
sc9_cmos11lp_base_rvt_tt_nominal_max_1p10v_25c.VSS
<snip>
Estimation Voltage: 0V (from TCL file)
Average Dynamic Power: 0W
On Static Power: 0W
On Dynamic Power: 0W
Virtual Supply: top_level:PD_m1:VDD_m1
Library Supplies:
sc9_cmos11lp_base_hvt_tt_nominal_max_1p10v_25c.VDD
sc9_cmos11lp_base_rvt_tt_nominal_max_1p10v_25c.VDD
<snip>
On condition: top_level.m1_power_ctrl
Key Points
In the power domain section of this report, note the following information:
 The name of a power domain specified in the UPF file is qualified with the scope
in which it is created.
 The name of a supply net specified in the UPF file is qualified with the scope and
domain name in which it is created.
 The estimation voltage is the voltage of the UPF port to which the supply net is
connected to in the UPF file.
Apache Design, Inc.

Using an SDC Input Flow
 The “on condition” of the virtual supply is the on state condition of the output port
of the power switch to which the supply net is connected to in UPF.
 The connect_supply_net command specifies the library rail connection of the
virtual supply to the library rail in that domain. This corresponds to the Library
Supplies section in the report for each virtual supply.
Additional items to note:
 The rail connection of all primary power supply nets of the domains must be
present in the UPF file. This connects the library rail to the supply net for the
domain where the primary power net is the supply net.
 PowerArtist does not support the power estimation of special cells such as switch
cells, isolation cells and level-shifter cells.

The SDC (Synopsys Design Constraints) Format is part of most methodologies. If
your flow relies on SDC, chances are that you already have captured some of the
information required for Apache power tools. Apache provides the ReadSDC utility
command to translate SDC information into PowerArtist Tcl commands.
Example
ReadSDC -sdc_files {clocks.sdc datapath.sdc}
-power_db_name top.pdb
Given this command, the software reads in two SDC files (clocks.sdc and
datapath.sdc); opens and reads power database rx40.pdb to validate netlist
information; writes out Tcl command file ReadSDC.scr; writes out transition time file
ReadSDC.tt; and writes out capacitance file ReadSDC.caps. Note that ReadSDC.tt
and ReadSDC.caps are included in ReadSDC.scr.
Using ReadSDC Output with a PowerArtist Command File

Using output generated by ReadSDC is as simple as using the command and
sourcing ReadSDC.scr in a Tcl file as shown below.
% ReadSDC -sdc_files {clocks.sdc datapath.sdc} -power_db_name top.pdb

% source ReadSDC.scr
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Mapping SDC commands to PowerArtist Tcl Commands

The following table shows a mapping of SDC 1.7 commands to PowerArtist Tcl
commands.
SDC Command PowerArtist Tcl Command
set_units PowerArtist uses this unit value to define units for the
rest of the numbers in the current SDC file.
create_clock SetClockNet -name <> -mode infer

-frequency <>
create_generated_clock SetClockNet -name <> -mode trace

-frequency <>
set_ideal_network SetClockNet -mode infer
set_propagated_clock SetClockNet -mode trace
set_clock_gating_check SetClockNet -gate_clock yes
set_ideal_transition CalculatePower -default_transition_time
set_input_transition CalculatePower -transition_time_file
set_load CalculatePower -capacitance_file
set_wire_load_mode SetWireLoadMode
set_wire_load_model SetWireLoadModel
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Sample SDC Input File
set_units -time ns -capacitance pF

create_clock -name clk -period 2 -waveform { 0 1 } [get_ports {clk}]
set_propagated_clock [get_clocks {clk}]
set_clock_transition 0.1 clk
create_generated_clock -name gen_clk1 -source [get_ports {clk}] -multiply_by 2 \
-master_clock [get_clocks {clk}] [get_pins {myRtl1/out}]
create_generated_clock -name gen_clk2 -source [get_ports {clk}] -multiply_by 4 \
[get_pins -hsc @ -hierarchical -regexp myRtl2@out]
set_clock_gating_check -setup 0.5 -hold 0.1 [get_clocks gen_clk]
set_ideal_transition 0.4 clk
set_input_transition 0.25 [get_ports pIn1]
set_load 0.08 [get_ports pOut]
set_wire_load_mode segmented
set_wire_load_model -name small {r t}
Sample Output Files

There are three output files generated by the ReadSDC command: a PowerArtist
command file a transition time file and a capacitance file.
Sample PowerArtist Command File

The ReadSDC utility generates, as one of its output files, a PowerArtist command
file, which may look similar to the following:
SetClockNet -name myRtl1.out -frequency 1e+09 -mode infer

SetClockNet -name myRtl2.out -frequency 2e+09 -mode infer
SetClockNet -name clk -frequency 5e+08 -mode trace
pt_set default_transition_time 4e-10
pt_set transition_time_file ReadSDC.tt
pt_set capacitance_file ReadSDC.caps
SetWireLoadMode enclosed
SetWireLoadModel -name small -net r t
You may have to edit the resulting command file, particularly if you are using it at the
RT level of abstraction. For example, you may want to add information on clock
gating constraint to the SetClockNet command or add the SetClockGatingStyle
command that is not present in SDC files.
Note also that the ReadSDC command uses the pt_set command when generating
the command file. Using pt_set variables is an alternative technique to specifying
options to commands, in this case the CalculatePower command. It is recommended
that you not delete these and replace them with options to the CalculatePower
command.
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Sample Transition Time Fie
sdc_top.pIn1 2.5e-10
Sample Cap File
sdc_top.pOut 8e-14
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421
Chapter 16
Acquiring Simulation Data 16
Introduction
This chapter describes how to acquire data from a simulation testbench so that
power analysis can provide the most accurate results. PowerArtist provides the three
approaches to acquiring of simulation data, all of which produce a simulation activity
file. In general, the approach that you choose will depend on your design language
(VHDL or Verilog), the level of abstraction and the simulator you are using. If you are
doing RTL VHDL designs, you should choose either FSDB or IAF since these
formats have the capability to store the composite data structure information that is
typical of VHDL designs. If you are doing RTL Verilog, then any approach will work. If
you are doing large gate-level designs (most likely in Verilog), the FSDB format is
preferred because it more efficiently stores toggle information. In general, if you can
create an FSDB file, use that approach. It is fast, compressed, complete and
consistent across all simulators in its naming conventions.
If you have instantiated gates in your design, you need to pay particular attention to
the amount of detail you capture in your format of choice. An instantiated gate may
be as simple as a flip-flop or as complex as a memory. Simply, if it has a power
model in Liberty format it is a gate. When your simulation runs, it will monitor and
write out the nets in your design. If the instance being monitored is a gate-level
instance, some simulators do not capture the nets local to the instance. Some of
these local nets represent the ports of the instance. Whether or not ports are
monitored for gate-level instances is very critical to know when performing power
analysis.
If you are going to perform an average power analysis, then you should be
monitoring the ports of all gate-level instances. If you are going to perform a time-
based power analysis, this is not required. You lose a little accuracy when trying to
perform an analysis of tri-state gates, but the improvement in performance is quite
significant.
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CHAPTER 16 — Acquiring Simulation Data PowerArtist™ User Guide 422
Using an FSDB Approach
PowerArtist supports the following simulations and simulation data formats:
Simulator Supported Formats
All Cadence Simulators FSDB, VCD, IAF
Mentor ModelSim FSDB, VCD, IAF
Synopsys VCS FSDB and VCD
 Using an FSDB Approach
 Using the Standard VCD Approach
 Using an IAF Approach
 Acquiring Simulation Data in Palladium Flows
 Troubleshooting Tips

It is recommended that you use FSDB files to get simulation data into PowerArtist.
You need to generate the FSDB (.fsdb) file using the Verdi™ product from SpringSoft
to obtain activity information from your simulator of choice. Using standard features
available with Verdi, you will capture your simulator trace in an FSDB file. Once you
have an FSDB file, you need to specify it using the -activity_file command-line option
when running the CalculatePower command.
Improving FSDB Performance

If you have FSDB files that are greater than 500MB in size, you may experience
performance problems with the processing of them. This will be especially true for
gate-level designs, most of which are Verilog. For such cases, you can improve
performance by running a SpringSoft utility called fsdb2vcd in the background. You
can either have PowerArtist call the SpringSoft utility automatically or you can do it
manually.
Automatic Technique for Running fsdb2vcd

If your design is written in either Verilog or Verilog 2001 and if you have fsdb2vcd in
your path, the CalculatePower command automatically runs fsdb2vcd. It will not run
fsdb2vcd for VHDL or System Verilog designs because the resulting VCD file will not
adequately capture the equivalent activity information as was in your FSDB file.
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If your design was Verilog or Verilog 2001 and you do not have fsdb2vcd in your
path, CalculatePower will generate a Warning message that lets you know you may
be missing an opportunity to improve your performance. Therefore, before running
CalculatePower, you should make sure that fsdb2vcd is in your path. Typically your
.cshrc file should include the following entry:
set path = (SPRINGSOFT_INSTALL_DIR/bin $path)
where SPRINGSOFT_INSTALL_DIR is the full path to your SpringSoft installation
directory. A specific example would be:
set path = (/system/pkg/springsoft/61v1/bin $path)
Manual Technique for Running fsdb2vcd

Use the following process to manually execute the fsdb2vcd utility:
1. Create the FSDB file
2. Use the SpringSoft fsdb2vcd utility to create a VCD file
Since you don’t want to store the VCD file on disk, you will need to use named pipes.
To do this, see Creating a Named Pipe to Manually Compress VCD Files. A sample
set of commands would be:
% ptshell
mknod myout p
fsdb2vcd my.fsdb -o myout &
CalculatePower -activity_file myout
Note: fsdb2vcd Utility Must be Valid for Autospawn to Work Properly

If you are using the fsdb2vcd autospawn feature (where the fsdb2vcd utility from
SpringSoft is autospawned for Verilog FSDB file processing) the fsdb2vcd utility must be
valid, otherwise CalculatePower will hang with the message “wwgaf: Note 2103: Design
prefix”. In such cases, the fsdb2vcd.log file present in the current directory will be empty. If
this happens, you will need to kill the GAF creation process manually, correct the fsdb2vcd
binary and then re-run CalculatePower.
Improving FSDB Capacity

If you are not manually running fsdb2vcd but allowing PowerArtist to read the FSDB
file directly, you can control the size of the FSDB file that must be loaded by the
database routines provided by SpringSoft. Specifically, you can reduce the total time
interval that must be loaded. To do this, you need to specify the -start_time/-
finish_time CalculatePower options.
Syntax
-start_time string
-finish_time string
Given these settings, only the value changes that occur between these times will be
loaded. This is the preferred method.
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Using the Standard VCD Approach
Generating a VCDe File from an FSDB File

There are times when you might want to see an ASCII representation of the FSDB
file. VCD is the ASCII representation of choice for most users. However, the VCD
informal standard does not have a way to represent the complex data structures that
System Verilog, Verilog 2001 or VHDL support. You must be aware of this if you use
the standard SpringSoft utility fsdb2vcd. Data may not be represented in the resulting
VCD file. If this is the case, you should run the ptFsdb2VcdPlus utility supplied as
part of the PowerArtist distribution kit. This utility takes in an FSDB file and outputs
the data in the Apache-proprietary enhanced VCD format, VCDe.
The following sample flow runs the ptFsdb2VcdPlus utility and then uses the
resulting file as an input to CalculatePower.
1. Use the ptFsdb2VcdPlus utility of PowerArtist to convert the FSDB file to a VCDe
file. The basic syntax of this utility is:
ptFsdb2VcdPlus -in fsdb_file_name -out vcde_file_name
-topinst top_inst_name -start start_time_for_analysis
-finish finish_time_for_analysis
If you intend to use the -start_time and -finish_time options in the CalculatePower
run, you should use it in VCDe generation itself instead—not in the
CalculatePower run. This reduces the size of the resulting VCDe file by
eliminating the unneeded transitions. Note that for this utility, the option names are
-start and -finish, which are different from the equivalent CalculatePower options.
2. Use the VCDe file to generate a GAF file and run power analysis using the
following command:
CalculatePower -enhanced_vcd true -activity_file vcde_file_name
-gaf_file gaf_file_name -synlib_files path_to_libraries
-top_instance top_inst_name
For details on the VCDe file format, see VCDe File Format in the PowerArtist
Reference Manual.

In the standard VCD (Value Change Dump) approach, you use commands provided
with the simulator to create a VCD file. The standard VCD approach uses standard
simulator facilities—for Verilog no special commands or options are required. While
Verilog simulators have standardized on one set of commands to create VCD files,
each VHDL simulator is slightly different. Also, because this approach creates a
large file, it is recommended that you compress the resulting VCD file while the
simulation is executing using a named pipe. To do this, see Creating a Named Pipe
to Manually Compress VCD Files.
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Writing a VCD File from a Verilog Simulator

The easiest way to write a VCD file is to add the following two lines to your Verilog
testbench:
$dumpvars;
$dumpfile ("your_vcd_filename");
Writing a VCD File from ModelSim

Use the following procedure to write a VCD file using the Mentor (MTI) ModelSim
simulator:
1. Execute the following commands before beginning simulation:
vcd file your_vcd_file_name
vcd add -r *
2. Execute the following command when the simulation is finished to ensure that all
data has been written to the VCD file:
vcd flush
Writing a VCD File from the Cadence NC-Sim Simulator

Use the following procedure to write a VCD file using the Cadence NC-Sim
simulator:
1. Execute the following commands before beginning simulation, either from the
command line or as part of a tcl input file:
database -open your_vcd_file_name -vcd
probe -database your_vcd_file_name -all -depth all
2. Execute the following command when the simulation is complete:
database -close your_vcd_file_name
Creating a Named Pipe to Manually Compress VCD Files

If you are a UNIX user, you’ve most likely used a pipe to pass data from one tool to
another. For example, the command line
ls | more
passes data from the first tool to the second using a pipe. This method does not work
if the first tool requires the name of a file to write data into, or if the second tool
requires the name of a file to read data from. Fortunately, UNIX provides a slightly
different method for that case, called a named pipe. You can execute a UNIX
command to create a special file that is actually a pipe. As the first tool writes data to
this file, it is buffered and sent to the second tool, just as if the pipe were specified on
the command line.
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Using an IAF Approach
The named pipe lets you run the simulator and a file compression program (for
example, compress or gzip) at the same time, passing data using a pipe. It is
recommended that you use gzip, because it is automatically detected by the wwgaf
conversion utility.
The Process
Use the following process to create a compressed VCD file using named pipe:
1. Edit the .v files to direct output to a file to be used as a named pipe, for example:
$dumpfile("my_pipe")
2. Compile the various files.
3. In the simulation directory, execute the following UNIX command:
mknod my_pipe p
The mknod command is located in a system directory that may not be in your
execution path, usually /etc or /usr/sbin.
4. Execute the simulator and start your compression program. Both must be done in
the background.
Example
mysim -f startup_file &
gzip < my_pipe > dump.vcd.gz &
In this example, the name of the simulator executable is mysim and gzip is your
compression program. You can delete my_pipe when the compression program is
finished. In the example the characters “<” and “>” are UNIX redirection
characters. Using these characters redirects the output of my_pipe to the input of
gzip. The output of gzip is directed into a file called dump.vcd.gz.
Note:
The wwgaf utility automatically recognizes gzip files, therefore, you do not need to pipe
gzipped files in wwgaf. If you use any other compression program, you will have to pipe
data into wwgaf, for example:
uncompress -c my_vcd_file.vcd | wwgaf -iaf -
Using an IAF Approach

In the IAF (Intermediate Activity File) approach, you need to link special purpose
code provided by PowerArtist into one of the supported simulators to create an IAF
file. In this approach, you need to link one of the supported VHDL or Verilog
simulators with PowerArtist utilities to create an IAF file. If you want to create an IAF,
contact Apache Design for instructions.
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Acquiring Simulation Data in Palladium Flows

Many of today’s largest designs create tens of Gigabytes of simulation data. Even
when capturing the data in the FSDB file format, the data size can be enormous.
When a simulator generates this much data, it not only creates huge files that need
to be stored on disk, but it significantly decreases the performance of the simulator.
Hardware emulators and accelerators exacerbate this problem because you can run
much larger test patterns on hardware than you can with a software simulator.
The Palladium™ series of accelerators/emulators from Cadence has the ability to
output toggle information in FSDB or VCD file formats. They also have the ability to
take a list of nets that should be monitored and record only the toggle information for
those nets in the resulting FSDB or VCD file. PowerArtist requires critical nets to be
monitored to perform an accurate average power analyses. The Elaborate command
accepts the following option:
-list_required_traces file_name
The specified file will contain the nets that need to be monitored. This file will be
formatted so that it contains one net name per line. The net name contains its
hierarchical instance name path in the design. For example, if you specify the
following option to Elaborate:
-list_required_traces trace.dat
the file trace.dat will be created in your current working directory and will have the
following format:
top.in[1]
top.in[2]
top.clk
You will then write a simple script that post-processes this file into the format your
Palladium hardware requires and include the resulting file as part of your Palladium
setup environment. The resulting FSDB or VCD file will only contain the toggle
information for those nets.
This flow works for both RTL, mixed RTL and gate, and pure gate-level designs. The
following nets are monitored in your design:
 Nets connected to all of the primary ports (inputs and outputs) of the design.
 Nets connected to all of the ports of instantiated gates that are recognized as:
— Memories
— IO cells
— Flip-flops
— Latches
— ICGCs (Integrated Clock Gating Cells)
— Macro cells with pin counts greater than 10 and that are not flip-flops
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— Macro cells with bussed pins

— Tri-states
— MUX select line (not output or input ports)
 Nets connected to all the ports of inferred elements (RTL components) that are
recognized as:
— Registers
— Latches
— Tri-states
— Regfiles
— Latchfiles
— MUX/UNMUX select line (not output or input ports)
If your design contains RTL code, then perhaps the net that needs to be monitored is
an inferred net that would not be present in your design source code. Therefore,
what would need to be monitored would be all the named nets that form the
immediate fan-in cone of logic for the inferred net. Therefore, Elaborate will trace
back from an inferred net through inferred combinational logic instances (and, or,
nand, nor, xor, xnor, connect and connect_inv) until it reaches the set of named
signals that would be needed to capture the toggling activity for that signal.
Palladium will convert everything to uppercase so you need to run Elaborate with the
-case_insensitive option as well as with the -list_required_traces option. The output
list will contain IOs, state points and clock enable signals for monitoring in the
Palladium simulation. You will need to convert the output list to uppercase. You can
do this easily by using the “tr [a-z] [A-Z]” command. The resulting FSDB output from
Palladium will be 15-20X smaller in size without sacrificing accuracy. The additional
advantage for Palladium is that the simulations are now much faster and there no
need to maintain terabytes of data. After running Elaborate, run CalculatePower with
the default pin-based estimation (that is, the -arc_based_estimation option is set to
“false” as it is by default).
For additional information, see Analyzing Average Power Using a SAIF File.
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Troubleshooting Tips
Missing 'timescale in Verilog

The most common error in using Verilog to acquire simulation data is leaving out the
timescale specification for the simulator.
The first line of your Verilog testbench should set the simulation time scale, as shown
in the following example.
'timescale 1 ns / 1 ns
If your Verilog file does not include a specification of the simulation time, the
simulator uses a default value. For some simulators, the default is one second per
clock cycle. If your signal changes every clock cycle but the simulator time step
defaults to one second, when you import this data and run an analysis with a clock of
10 Mhz, the simulation data for the signal indicates that it changes only once per 10
million clocks. This results in a very low estimate of power for that net and the
modules it drives.
Zero Length activities.iaf File

If you are performing a small simulation using the Intermediate Activity File approach
and the activities.iaf file contains no data, exit the simulator. The simulator might not
be closing the .iaf file until it exits. This means that there is still buffered data in the
gzip process which is not written until its input file is closed.
Problems with ModelSim

ModelSim uses an internal environment variable to point to the binary executables
for its tools. The $MODEL_TECH environment variable is maintained by the tool and
should not be manually reset (as noted in the ModelSim documentation). If you were
to set it, you could have problems trying to use make_mti_mapfile executable
because the modelsim.ini in the ModelSim installation uses this environment variable
to point to other modelsim.ini files.
others = $MODEL_TECH/../modeltech/modelsim.ini
Therefore, if you had set $MODEL_TECH it is possible that the above path would not
resolve to the correct location. If you run into this situation, simply unset the
environment variable:
unsetenv MODEL_TECH
The make_mti_mapfile executable will then use ModelSim utilities to return a value
for $MODEL_TECH.
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Zero Delay Simulation

If you are performing a mixed RTL/gate simulation (for example when pads are
instantiated in your design) you need to know if a zero delay simulation run created
your simulation results. There are three reasons for this.
First, it will cause inputs and outputs of cells that have power models to change in
the same time step. Simulators often don’t ensure that when they create simulation
traces either via PLI routines or VCD files, that input changes will always appear
before output changes.
When PowerArtist executes the “CalculatePower -analysis_type average” command
when performing an arc-based analysis, it checks to see if certain transition
sequences happen in the VCD file and matches those to power vectors in your .lib
libraries. It does not sort all of the changes that happen in a time step to ensure that
inputs change before outputs—doing so for most gate-level designs would be
prohibitively expensive. Taking this method into account, it’s possible in this scenario
for an output to toggle but have no corresponding vector; therefore, power will be
underestimated.
If you perform unit delay simulation or back-annotate delay information to your
simulation, the output will change in a later time step and a power vector will be
matched, assuming that one is present in your library files. This problem does not
occur when you specify the “CalculatePower -analysis_type time_based -zero_delay
true” command. The “-zero_delay true” option setting forces the time-based power
calculator to try to re-order events that happen in each time step so output changes
follow input changes. This switch will improve your results but you will incur
increased run time due to the sorting of signal toggles for every time step in your
simulation file.
A second reason for not using zero delay simulation is that zero-duration glitches will
occur. These are multiple toggles on nets that occur during the same time cycle.
These may result in too many power arcs being matched and power being over
estimated. This problem is also addressed if you specify the “CalculatePower -
analysis_type time_based -zero_delay true” command.
To accurately analyze power, you must at a minimum use unit delay simulation and
at best back-annotate delays and simulate your design.
The following example is a section of a VCD file that exhibits both problems:
#40551
0T"
0S"
#136520
1S"
1T"
0S"
0T"
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In this example, S” represents an input to a buffer. T” is the output. Notice at timestep

#40551 that the output toggles before the input so a potential power arc match is
missed here. Timestep #136520 shows the same net toggling multiple times in one
time step. In this case, the arc missed in #40551 is actually recorded as being
recognized twice here.
A third reason for not using zero delay simulation only occurs if you are using VCS,
the function simulator from Synopsys. VCS eliminates simple buffers like those found
in the clock network. The generated VCD file has all nets in the clock network
sharing the same VCD id code, which causes poor performance when running
“CalculatePower -analysis_type average”. When this happens, the CalculatePower
log file contains an error message that all nets will not be monitored.
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433
Chapter 17
Generating Etcl Files for CoolTime 17
Introduction
If you use Apache’s CoolTime product and want to do simulation-based voltage drop
analysis, you will need an Etcl file (also called a seed vector) generated by
PowerArtist. You can generate an Etcl file for use in CoolTime by using one of two
methods. You can generate it while performing a vector analysis (activity-based) or
while performing a time-based power analysis (power-based). The design you are
analyzing must be at the gate level of abstraction.
This chapter is divided into the following sections:
 Generating an Activity-Based Etcl File
 Generating a Power-Based Etcl File
For detailed information on the format of the Etcl file, see Etcl File Format in the
PowerArtist Reference Manual.
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CHAPTER 17 — Generating Etcl Files for CoolTime PowerArtist™ User Guide 434
Generating an Activity-Based Etcl File

Generating an activity-based Etcl file requires you to perform three steps:
1. Perform a vector analysis using the GenerateActivityWaveforms and DefineGroup
commands. Before performing this step, you will need to Elaborate your design.
2. Examine the resulting waveforms in the Apache Waveform Viewer. Select the
clock cycle(s) of interest noting the start and finish simulation times that encloses
the cycle(s).
3. Generate the Etcl file using the GenerateEtclFile command.
Performing a Vector Analysis

When you perform the vector analysis, you can use either the clock-cycle mode or
the time-based mode. In selecting the mode to run, consider that you will want to do
the analysis at a very fine level of granularity. Most likely you will want your analysis
interval size to be 1 clock cycle. This will allow you to see rapid changes in activity
which could indicate a potential di/dt issue. The clock-cycle mode is probably the
easiest way to perform this analysis.
It is recommended that you create a script called, for example, gaw.tcl. In this script,
you will first need to define at least one group using the DefineGroup command. At a
minimum, you should have one group represent the top module of your design. The
following sample script performs vector analysis using the clock-cycle mode:

set design top
-activity_waveform_clock_edge pos \
-activity_waveform_clock_name top.clk \
-activity_waveform_group_list { top } \
-activity_waveform_graph_type activity_per_cycle \
-activity_waveform_cycles_per_interval 1 \
-activity_waveform_start_time 52ns \
-activity_waveform_log GenerateActivityWaveformBatch.log \
The GenerateActivityWaveforms command in this script starts its processing at the

first positive edge of top.clk after the start time of 52 ns. It performs a clock-cycle
mode analysis for the next 1000 clock cycles because the cycles per interval is set to
1.
Depending on the options you specify to GenerateActivityWaveforms, this process
will generate either an FSDB or a PTCL file with one waveform captured for each
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group you defined using the DefineGroup command(s). Based on the sample script,
there will be one waveform generated (for group top) in FSDB format (specified -
fsdb_output_file option).
You would then run this script using the following command:
ptshell -tcl gaw.tcl
When the analysis is complete, you will see the resulting output files
(GenerateActivityWaveformBatch.log, top_activity.fsdb, etc.) in your run directory.
Analyzing the Waveform

Examining the resulting waveform(s) requires you to load the resulting waveform
output file into the Apache Waveform Viewer. At this point, you now need to decide
what problem you want to analyze answering the following questions:
 Are you concerned about a high average sustained current with a potential high
peak current?
 Are you concerned about a rapid shift from a low current to a much higher current
which may cause a di/dt problem?
While activity does not completely correlate with power, the shape of the activity
waveform should give you some insight into how you can narrow-down your analysis
window. As a results of this analysis, you want to come away with a start and finish
time that encompass the clock cycles you want to analyze.
Controlling the Precision of the Data in the Etcl File

The precision of data output in the ETCL file will be determined by extracting the
precision data from the VCD file. If this is not adequate, you can set the environment
variable PA_PRECISION to override these values, for example:
setenv PA_PRECISION 15
sets the ETCL precision to be in fempto seconds.
Generating the Etcl File

Once you have the start and finish times you recorded while analyzing your
waveforms, the process of generating the Etcl file is easy. Take the start and finish
time for the clock cycles of interest and apply them to the GenerateEtclFile
command. To do so, you would create a Tcl script called, for example, gef.tcl. Given
a start time of 152ns and a finish time of 160nS, your script might look like the
following sample:
ReadLibrary lib1.lib
GenerateEtclFile \
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-etcl_finish_time 160ns \
-etcl_file top.etcl \
-etcl_start_time 152ns \
-mixed_sim_prob_estimation true \
-scenario_file top.Batch.scn
You would then run this script using the following command:
ptshell -tcl gef.tcl
Standard activity analysis parameters like Liberty libraries, scenario files are
required. The resulting file top.etcl is what you would pass to CoolTime.
Using a Name Mapped Flow

You can also use an RTL simulation file to act as the stimulus file for Etcl generation.
The Name Mapping Flow section describes how to do this in detail. The only
difference is that before the GenerateActivityWaveforms and GenerateEtclFile
commands, you have to specify the SetNameMapFile command to supply the name
mapping file and then you have to supply the -use_rtl_sim_data option for both
commands. See the following extended sample scripts from the following section.
Using a name mapping flow, the sample gaw.tcl file becomes:
SetNameMapFile -mapfile mapfile.dat -format conformal

set design top
-activity_waveform_clock_edge pos \
-activity_waveform_clock_name top.clk \
-activity_waveform_group_list { top } \
-activity_waveform_graph_type activity_per_cycle \
-activity_waveform_cycles_per_interval 1 \
-activity_waveform_start_time 52ns \
-log GenerateActivityWaveformBatch.log \
-use_rtl_sim_data true
Using a name mapping flow, the sample gef.tcl becomes:
SetNameMapFile -mapfile mapfile.dat -format conformal

GenerateEtclFile \
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-use_rtl_sim_data true
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Generating a Power-Based Etcl File

To generate a power-based Etcl file, you have two choices. You can choose to have
PowerArtist automatically select the clock cycle with the highest activity and then
generate an Etcl file for that single clock cycle. Alternatively, you can perform a time-
based power analysis, look at the waveforms interactively and then run the
GenerateEtclFile command to generate an Etcl file that covers multiple clock cycles.
Automatically Selecting the Highest Activity Clock Cycle

If you want to generate an Etcl file for the clock cycle with the highest activity, you
can use this method to have PowerArtist do so automatically.
1. Run a time-based power analysis using the CalculatePower -analysis_type
time_based command. The key CalculatePower options needed to perform this
operation are:
 -etcl_file
 -peak_cycle_file
 -peak_cycle_processing_mode auto
 -reference_clock
Using the tutorial design as in the activity-base Etcl generation section, a sample
command would be:
CalculatePower -analysis_type time-based \

-active_edge pos \
-peak_cycle_file pcf.tcl \
-peak_cycle_processing_mode auto \
The “peak_cycle_processing_mode auto” instructs PowerArtist to identify the peak

cycle automatically. When this command completes, you will see the pcf.tcl file in
your working directory. This file contains a studio_setup_time_based command.
This command has the following syntax:
studio_setup_time_based start_time end_time etcl_file_name
The start_time and end_time is the start/end of the cycle of highest activity, for
example:
studio_state_setup_time_based 15ns 25ns top.etcl
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The start time of the cycle of interest is 15ns and the end time is 25ns. The
etcl_file_name value is the value of the etcl_file passed as an option to the
CalculatePower command.
2. Run the GenerateEtclFile command as instructed in the activity-based flow. Here,
you will have to feed forward the data in the pcf.tcl file into the same
GenerateEtclFile command. The example here would be:
GenerateEtclFile \
-scenario_file top.Batch.scn
The start_time (15ns) and end_time (25ns) values in the pcf.tcl file are used here
in the GenerateEtclFile command (end_time in this command is called
finish_time). The results file, top.etcl, is what you would specify to CoolTime.
Manually Selecting Single or Multiple Clock Cycles of Interest

If you want to perform a voltage drop analysis over multiple clock cycles, you can
use this manual method to generate an Etcl file that captures the clock cycles of
interest.
1. Run a time-based power analysis using the CalculatePower -analysis_type
time_based command.
If you run in the auto mode as in the previous example, CalculatePower
determines the peak power cycle. But if you want to analyze di/dt issues,
sustained worst case power or analyze the results over multiple cycles, you will
need to interactively analyze the power-over-time waveforms generated by a time-
based power calculation. Use CalculatePower -analysis_type time_based and
determine your start and finish time that encloses your clock cycle(s) of interest.
Be sure to specify the “-peak_cycle_processing_mode interactive” option to
CalculatePower.
2. Run the GenerateEtclFile command as instructed in the activity-based flow
At the end of step 1, you have your start and end time, now just run the
GenerateEtclFile command as instructed in the activity-based flow.
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441
Chapter 18
Writing OpenAccess Database

Applications 18
Introduction
This chapter describes how you can develop OpenAccess database (OADB)
applications and how to apply them in PowerArtist. Note that you can find
OpenAccess programming samples in the $POWERTHEATER_ROOT/examples/
OpenAccess directory. For a list of OADB commands, see Open Access Database
Access Utilities.
 Introduction to OADB Programming
 Using the PowerArtist API to Write an OpenAccess Application
 PowerArtist Netlist Properties
 Writing a Native OpenAccess Application
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CHAPTER 18 — Writing OpenAccess Database Applications PowerArtist™ User Guide 442
Introduction to OADB Programming
Introduction to OADB Programming

OpenAccess is a collaborative effort managed by the Silicon Integration Initiative™,
commonly referred to as Si2. A key goal of the effort is to provide an open EDA
standard for IC design access and supporting software. A critical deliverable is a
production proven database that all EDA vendors could use as the repository for
their design data. The PowerArtist analyzers (controlled by the CalculatePower and
ReducePower commands) generate an OpenAccess database (OADB) that contains
the design netlist translated from the scenario file created by the Elaborate
command, which they then augment with power information. The power information
contains:
 Netlists that represent the clock networks in your design and the design itself.
 Reduction results data.
 Properties that represent calculated or extracted power data associated with the
nets, instances and pins of your design.
OpenAccess provides an Application Programming Interface (API) that software
developers may use to develop C++ applications. OpenAccess also provides a Tcl
binding for those developers who wish to write Tcl applications rather than C++
applications. PowerArtist contains a Tcl API layer that makes use of the OpenAccess
API.
If you decide to develop a native OpenAccess application, the OpenAccess
community provides a tremendous amount of documentation that developers must
consult to develop applications. It is beyond the scope of Apache Design to train end
users to develop OpenAccess applications. However, as an Si2 member and an
OpenAccess Coalition member, Apache is allowed to share this documentation with
end users. If you want to write native OpenAccess applications, please contact your
local sales team and they will make the documentation available to you. You may
also join Si2 to support the OpenAccess effort and to gain other benefits as well. Visit
www.openeda.org for more information.
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PowerArtist Netlist Properties

As described earlier, PowerArtist stores netlists in OpenAccess. It also stores
properties attached to instances, pins and nets. Once you have a handle to an
instance, pin or net, you can use the following command to extract a particular
attribute:
ptoa::getPropVal object_handle property_name
To retrieve the handle, use an appropriate “get” command. For example, for a net,
you can use the following commands:
set net [oa::getNet $terminal]

set dutyCycle [ptoa::getPropVal $net Duty_Cycle]
For an occurrence instance, you can use the following commands:
set topOccurrence [oa::getTopOccurrence $design]

set occurrenceInstance [oa::getOccInst $topOccurrence]
set power [ptoa::getPropVal $occurrenceInstance Total_Power]
Apache is continually expanding the legal attributes you can retrieve off of each of
the element types. The attributes names are case sensitive and must be used
exactly as shown.
[Jay, this section should probably be changed right? Right now it reads like these
properties are only for the ptoa:: style commands. Do the new properties
Instance Properties
PowerArtist stores the following instance properties:
 Float/Double Values
— Static_Power: static power for the instance (in Watts). For a hierarchical
instance, this is the sum of static power values of all of the children leaf and
hierarchical instances.
— Dynamic_Power: dynamic power for the instance in watts. For a hierarchical
instance, this is the sum of dynamic power values of all of the children leaf and
hierarchical instances.
— Total_Power: the sum of the static and dynamic power values. For a
hierarchical instance, it’s the sum of static and dynamic power values of all the
child instances (leaf as well as hierarchical) in that instance.
— Clock_Power: inferred clock tree power consumed by the instance.
— Leaf_Total_Power: the sum of the total power of all of the leaf-level instances in
the hierarchical instance. As an example, suppose that module “top” has two
children leaf-level instances top.#25 (an inferred instance) and top.mem1 (an
instantiated memory) and one child hierarchical instance, top.block1. Given this
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information, then the Leaf_Total_Power of “top” = Total_Power of top.#25 plus

Total_Power of top.mem1. Furthermore, the Total_Power of “top” = the
Total_Power of top.#25 plus the Total_Power of top.mem1 plus Total_Power of
top.block1.
— Forced_Power_Values: power value specified by the SetPower command.
 String Values
— Wireload_Model: the wire load model used to estimate the capacitance for the
instance.
— File_Name: the file name containing the instance definition if a hierarchical
instance, or a gate-level instantiation, or the file containing the module that
caused the inferred instance.
— Clock_Gated: the clock gating status, which can have any of the following
values:
 None—the register instance is not clock gated.
 Inferred—the register has an inferred ICGC.
 Instantiated—the register instance has an instantiated ICGC.
 Inferred and Instantiated—the register instance has an inferred and an
instantiated ICGC.
 Integer Values
— Line_Number: the line number of the instance in File_Name.
— File_Type: the type of HDL used to define the instance, which can have any of
the following values:
 0—invalid
 1—defined in a Liberty file
 2—verilog
 3—system verilog
 4—vhdl
 5—blackbox
Net Properties
PowerArtist stores the following net properties:
— Wire_Cap: estimated wire capacitance in farads
— Duty_Cycle: calculated duty cycle
— Avg_Activity: average activity value
— Frequency: frequency number in Hertz
— Transition_Time: transition time of the net
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— Net_Power: power consumed by the net

 String Values
— Cap_Source: the source of the net capacitance; it can be a wire load model if
net capacitance was calculated or the name of a user specified file, such as a
SPEF, if net capacitance was annotated.
Pin Properties
PowerArtist stores the following pin properties:
— Cap: pin capacitance if the pin is an input pin; load capacitance (that is, the sum
of wire capacitance and capacitance of input load pins) if the pin is an output
pin.
Module Properties
PowerArtist stores the following module properties:
 String Values
— Func_Type: module function type
— File_Name: the name of file where the module is defined
 Integer Values
— File_Type: the type of HDL used to define the instance, which can have any of
the following values:
 0—invalid
 1—defined in a Liberty file
 2—verilog
 3—system verilog
 4—vhdl
 5—blackbox
— Func_Type: for inferred and instantiated leaf level modules
 0—invalid
 1—AND
 2—NAND
 3—NOR
 4—OR
 5—XOR
 6—XNOR
 7—INV
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 8—BUFFER
 9—MUX
 10—FULL_ADDER
 11—MEMORY
 12—PAD
 13—FLOP
 14—LATCH
 15—CORE
 16—HALF_ADDER
 17—ICGC
— Line_Num: the line number where the module is defined in File_Name
— Area: the sum of the area of all the instances in the module
Hierarchical Instance Properties

PowerArtist stores the following hierarchical instance properties:
— Register_Static_Power: this is the sum of the static power values of all
registers in the instance and all registers of the instance’s hierarchical children.
— Register_Dynamic_Power: this is the sum of the dynamic power values of all
— Register_Load_Power: this is the sum of the switching power values of all
— Latch_Static_Power: this is the sum of the static power values of all latches in
the instance and all latches of the instance’s hierarchical children.
— Latch_Dynamic_Power: this is the sum of the dynamic power values of all
latches in the instance and all latches of the instance’s hierarchical children.
— Latch_Load_Power: this is the sum of the switching power values of all
— Memory_Static_Power: this is the sum of static power values of all the
memories in the instance and memories of the instance’s hierarchical children
— Memory_Dynamic_Power: this is the sum of dynamic power of all the
memories of the instance and all memories of the instance’s hierarchical
children.
— Memory_Load_Power: this is the sum of the switching power values of all
memories in the instance and all memories in the instance’s hierarchical
children.
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Writing a Native OpenAccess Application
— Logic_Static_Power: this is the sum of the static power values of all

combinational elements in the instance and the instance’s hierarchical children.
— Logic_Dynamic_Power: this is the sum of the dynamic power values of all
— Logic_Load_Power: this is the sum of the switching power values of all
— Clock_Load_Power: this is the sum of the switching power values of all clock
tree elements in the instance and all clock tree elements of the instance’s
hierarchical children.
— Pad_Static_Power: this is the sum of the static power values of all pad
elements in the instance and all pad elements in the instance’s hierarchical
children.
— Pad_Dynamic_Power: this is the sum of the dynamic power values of all pad
elements in the instance all pad elements in the instance’s hierarchical children.
— Bbox_Static_Power: this is the sum of static power values of all blackbox
elements in the instance and instance’s hierarchical children.
— Bbox_Dynamic_Power: this is the sum of dynamic power values of all the
blackbox elements in the instance and the instance’s hierarchical children.
— Bbox_Load_Power: this is the sum of switching power values of all the
blackbox elements in the instance and the instance’s hierarchical children.

If you want to write an application using the API provided by Si2 as part of their
OpenAccess package, this section describes how you can do it. You will most likely
use the API layer described in Using the PowerArtist API to Write an OpenAccess
Application to write your applications. This layer, while potentially slower, is much
easier to use.
Contents of the Documentation Package

The documentation package you will receive from Apache (upon request) as a
PowerArtist user contains the following:
 50MBs of HTML help files that explain the C++ API and how to write Tcl
applications.
 A PDF file, OpenAccess22fourthEdCD.si2.pdf, that is the OpenAccess Release
2.2 API tutorial. This contains over 600 pages of documentation on how to
effectively write OpenAccess applications.
 An example that shows how to retrieve netlist and power information from an
OpenAccess database created by PowerArtist using the Tcl binding.
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There is a good amount of information available because the scope of OpenAccess

is vast. It not only has to store logical information like netlists, but all the physical
information required to manufacture an IC. PowerArtist uses only a fraction of the
total data model.
Basic Requirements for a Native OpenAccess Tcl Application

To write a native OpenAccess Tcl application, your development infrastructure must
meet the following requirements:
 Have Tcl version 8.4 or greater installed on your system. This tclsh enables the Tcl
OpenAccess API. Version 8.4.6 is the version that was used for testing.
 Have PowerArtist 2007.3 or greater installed. This version supports reading and
writing OpenAccess databases from the power analyzers. It also contains libraries
that your Tcl application must dynamically load that translate your Tcl procedure
calls into C++ API calls to access the database.
Power data is stored as properties using OpenAccess Application Defined (AppDef)
extensions. OpenAccess 2.2 does not support a generic method to access AppDef
extensions.PowerArtist contains a shared library that you must load that provides a
Tcl interface to access these properties.
Flow for Writing a Native Tcl Application

Use the following steps when writing a native Tcl Application. Note that there is a
Bourne script available to do the first three steps for you (see Using a Script).
1. Make sure that you have access to the following runtime libraries. These are
required to write even the most basic application:
— OpenAccess shared libraries.
— Apache Design shared library providing the AppDef extension.
— Standard gnu C++ shared libraries
All of these libraries are provided as part of the PowerArtist distribution. You must
make these libraries part of your LD_LIBRARY_PATH. For example, you can do
the following:
# pt-arch is an Apache script that returns the machine architecture

# to enable loading of platform dependent binaries and libraries.
setenv ADS_ARCH `pt-arch`

setenv LD_LIBRARY_PATH \ $POWERTHEATER_ROOT/lib/$ADS_ARCH:$POWERTHEATER_ROOT/lib/
oa/lib/$ADS_ARCH/opt:$LD_LIBRARY_PATH
Note: The “setenv LD_LIBRARY_PATH” command while very long must be on

one line and not broken across multiple lines as shown here.
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The C++ libraries are located in lib and the OpenAccess and AppDef extensions
are located in lib/oa/lib.
2. Make sure the Tcl package autoloader knows the location of these routines. While
there are several ways to do this, the easiest is to set the TCLLIBPATH
environment variable as follows:
setenv TCLLIBPATH $POWERTHEATER_ROOT/lib/oa/lib/$ADS_ARCH/opt
3. Make sure that version 8.4 tclsh is in your path. For example, you could set it as:
set path = (/system/pkg/tcl/8.4.6/bin/i686-pc-linux-gnu $path)
The rest of this document assumes that you have become familiar with OpenAccess
by reading the HTML and PDF documentation as well as the short example. A critical
section for you to read in the HTML documentation is one called “Tcl Bindings for the
OpenAccess API”. That is required reading before proceeding any further.
Using a Script
You may want to consider using the Bourne shell script, ptoatclsh, that is provided in
the distribution. This script performs three separate functions:
 It implements the LD_LIBRARY_PATH changes described in Step 1 and sets the
TCLLIBPATH in Step 2.
 It checks to make sure that the tclsh in your path is at least version 8.4 or above.
 It launches that tclsh with any parameters you pass it. A sample use would be:
> ptoatclsh
%
This would put you into the tclsh command shell. Another use would be:
ptoatclsh my.tcl
This executes the Tcl file my.tcl and returns.
4. At the beginning of your Tcl program you need to load the Tcl packages. This can
be done in the following manner:
package require oa
package require ptoa
The package command loads the Tcl command extensions into the current Tcl
interpreter. The “oa” in the first line represents the OpenAccess Tcl commands
and “ptoa” represents the PowerArtist OpenAccess Tcl commands required to
access power properties. If you just want to access netlist information, but don’t
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want power properties, you can eliminate this last line. To verify that the packages
have been loaded correctly, run the following two commands:
info command oa::*

info command ptoa::*
These should return a list of supported commands. If nothing gets returned, the
packages have not loaded successfully.
5. If you want to access power properties and not just netlist information using the
standard OpenAccess data model, then you need to do one final step. Just after
you open the design, you need to do an “attach” that tells the PowerArtist routines
the location of your OpenAccess design.
set design [oa::DesignOpen $libraryName $topCell $viewName $viewType r]

ptoa::attach $design
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Using the PowerArtist API to Write an OpenAccess Application

The PowerArtist API leverages knowledge you may have acquired writing
applications for other EDA tools. It provides several layers of utilities that you can
use to write a Tcl-based application that manipulates data stored in your power
database that is itself an OADB. You can use these utilities to do the following:
 Map between PowerArtist, OpenAccess and industry standard synthesis product
design representations of design object names.
 Perform design navigation functions similar to what Unix provides for manipulating
the Unix file system. Example utilities and their Unix equivalents include dcd (cd),
and dpush/dpop (pushd/popd).
 Query the power database. Example utilities include getModule, getModuleNets, and
getFlops.
 Traverse the netlist in complex ways. Example utilities include getFanout and
getSrcPin.
 Create detailed reports in the .csv format. Example utilities include reportPath and
reportCGEfficiency.
All of the utilities return 0, 1 or lists of design object path names.
With these utilities, you can access all of the netlist information contained in your
design and extract data generated by a power analysis. If you want to write a Tcl
application that uses the standard Si2 OpenAccess calls instead, please read section
Writing a Native OpenAccess Application.
Getting Started
Running a PowerArtist OADB application involves the following steps:
1. Create the power data using the CalculatePower command.
2. Launch ptshell.
3. While in the ptshell, source the power database file (.pdb) to locate the
OpenAccess database you want to analyze.
4. Run your application by sourcing the appropriate Tcl files.
The following sections describe steps 3 and 4 in more detail.
Sourcing Your PDB File

Once you create the PDB file, launch the ptshell. As outlined in Using the
PowerArtist Shell, there are many ways to do this. The example below is merely an
illustration of the simplest way. Suppose that you have run the analysis tutorial and
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created a power database file called top.AverageBatch.pdb. The contents of the .pdb
file look similar to the following:
# This file is a collection of other files.

#
# Primarily, the OADB directory and any other files required
# by openaccess.
#
# There is intentionally no scoping to the name, so that multiple
# Tcl namespaces can source this file and interpret the options
# appropriately.
#
# Generated by software version: 2010.2.2
setResults -oaDir top.BatchLib -topInst top
Now, in the directory containing top.AverageBatch.pdb, you would start the ptshell:
ptshell –artist
At this point, you will see the following type of information displayed in your Unix
window:
PowerArtist/XP Shell (64 Bit Linux) R2010.2.2 (23 Mar 2011)

Copyright 1995-2011 by Apache Design, Inc.
Welcome to PowerArtist/XP
ptshell: Note 1093: Removing stacksize limit
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
# Sourcing INI file: /pkg/pt/ptshell.ini
# Sourcing INI file: /projs00/analysis/full_chip/ptshell.ini
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Work Dir = /projs00/analysis/full_chip/ptshell_work
Log File = /projs00/analysis/full_chip/full_chip.log
Key File = /projs00/analysis/full_chip/full_chip.key
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
full_chip_ptshell %
At this point, you will source the .pdb file as follows:

source top.AverageBatch.pdb
As the pdb file is processed, data structures are being built that ensure adequate API
performance. When the process completes, you will see the following output in your
Unix window:
# INFO: OADB: Initializing interface.

# INFO: OADB: Lib 'top.AverageBatchLib' read.
# INFO: OADB: Available views: ‘netlist’
# INFO: OADB: Design ‘top’ opened in netlist view.
# INFO: OADB: Building module/inst cache for ‘/top’
# INFO: OADB: Read 79 modules, 1821 instances, 29558 pins
# INFO: OADB: Building cell primitives cache.
# INFO: OADB: Done.
0
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The return code of 0 at the end can be tested to ensure automatically that the pdb
file successfully loaded. If it did not load successfully, the return code would be 1. For
instance, you can catch the failure by doing something like the following:
set passFail [catch {source top.AverageBatch.pdb}]

if {$passFail != 0} {
puts “Failure!”
}
Sourcing your Application

At this point, you are ready to source your Tcl files that implement your particular
application. A very simple application that you can run is one that returns the module
type name for a hierarchical instance in the design. You can either enter the following
commands in a file and source the file or type them directly at the ptshell prompt. For
example, again using the tutorial design, you can type the following commands at
the ptshell prompt:
set name [getModule /top/core1]

clogic
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
puts $name
clogic
#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Using the Design Navigation Utilities

In a power database, the design tree and inferred clock-trees are saved as top-level
netlist-design objects. For the tutorial design, the top-level netlist-design objects are:
 design object, /top,
 clock-tree design objects /clk, /pci_clk, and /tck
The design object is hierarchical and the clock-tree design objects are flat.
PowerArtist provides a set of design navigation utilities that mimic Unix directory
traversal (cd) and listing (ls) utilities and allow you to navigate through the design
hierarchy and list design contents. These are built on the notion of “current design
directory” and “design root”. Similar concepts are supported in many Synopsys
applications as well as the CPF and UPF standards. The current design directory is
analogous to your current working directory in the Unix file system. The design root
is analogous to your home directory. By setting the design root to a design object (be
it your actual design or a clock design object) you can then set your current design
directory to some point in your overall design hierarchy. Then all references to design
elements can be specified relative to that point. Therefore, your design directory
specification may be an absolute or a relative design path. These paths will
correspond to a hierarchical instance in your design tree.
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The following Design Navigation Utilities are available and are fully documented (full
syntax and examples) in the PowerArtist Reference Manual:
Utility Short Description
dcd Sets the current design directory to the specified design directory
dpush Pushes the current working directory to a directory stack and then
sets the current working directory to be the design directory
dpop Pops the directory stack and sets the current design directory to the
directory that was on the top of the design stack
dirs Lists the design directory stack
dpwd Lists the current working directory
dls Lists the contents of the design directory
show Shows pseudo-Verilog for the specified instance path or module.
To view the full descriptions, simply click on the blue utility names (this will take you
to the PowerArtist Reference Manual).
Using the Netlist Traversal Utilities

You can use the netlist traversal utilities to easily extract different types of date from
from the netlist. For example, you can retrieve a list of pins for a specified net.
The following netlist traversal utilities are available and are fully documented (full
syntax and examples) in the PowerArtist Reference Manual:
getAssociatedNet Returns the path name for the net associated with the
specified pin path
getConnectedPins Returns a list of pins connected to the specified net
getSrcPin Returns the path name of the driving source pin of the
specified pin or net.eturns the path name of the driving
source pin of the specified pin or net
getSinkPins Returns a list of path names of the sink pins driven by the
specified pin (or net)
getFanout Returns a list of path names of fanout endpoints from a
specified pin
getFanin Returns a list of path names of fanin startpoints from a
specified pin.
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Using the Design Query Utilities

You can use the design query utilities to retrieve a variety of information from your
design. For example, you can get a list of flop instances, module names, module port
names, etc. The following design query utilities are available and are fully
documented (full syntax and examples) in the PowerArtist Reference Manual:
getFlops Returns a list of flop instance paths

getModule Returns the module name of the instance.
getModulePorts Returns bit-blasted port names of the module in the form of

a list of tuples {bit_port_name dir}
getModuleNets Returns a list of net name paths that are local to the
specified instance or module
getModuleInsts Returns a list of instances of the specified inst path or
module name. Names are relative to the specified inst path
or module name
getInstsOfModuleType Returns a list of instance path names with the specified
module type name
getPinDirection Returns a direction of the pin as input, output or inputOutput
getRelatedPins Returns a list path names of related pins of this

combinational instance pin
getPropVal Returns the value of the specified property for the given
object path (pin, net or instance)
isRoot Determines if the specified instance or module is the root
design root
isLeaf Determines if the specified instance or module is a leaf
isFlop Determines if the specified instance or module is a flop
isLatch Determines if the specified instance or module a latch
isMemory Determines if the specified instance or module is a memory
isSequential Determines if the specified instance or module is a flop,

latch or memory
isComb Determines if the specified instance or module is a
combinational device
isConnect Determines if the specified instance or module is a connect
primitive, buffer or inverter
isPin Determines if the specified path is a pin
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getCGs Returns a list of integrated clock gating cells (ICGCs)
getRegisterCGs Returns a list of clock gating instances gating the register
getCGRegisters Returns the register instances being gated by the specified

clock gating instance
Using the Analysis Reporting Utilities

You can use the analysis reporting utilities to report power analysis information for
various parts of your design. The following netlist traversal utilities are available and
are fully documented (full syntax and examples) in the PowerArtist Reference Manual:
reportPath Reports the power along a specified path

reportPower Returns the power associated with a given instance or all
instances in a given module
reportCGEfficiency Generates a comprehensive report of all inferred and
instantiated ICGCs in the design
Using the Reduction Reporting Utilities

PowerArtist provides two reduction reporting utilities that you can use to collate
multiple reduction reports: readReductions and collateReductions.
readReductions Reads one or more .csv report files generated by the

ReducePower command and builds up an in-memory
representation of them
collateReductions Reads in CSV files and generates a collated report based
on the data filter options you specify
These utilities work off of data generated by PowerArtist’s ReportReductions

command. Use the following flow to take advantage of these utilities:
1. Elaborate the design using the Elaborate command.
2. Perform a power reduction analysis using the ReducePower command.
3. Generate a .csv file of the reductions using the ReportReductions command.
4. Optionally iterate steps 2 and 3 using different stimulus files to obtain reduction
data over a variety of different operating modes and conditions.
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5. Run the readReductions utility once reading all CSV files generated in the
sequence of steps 2-4.
6. Run the collateReductions command to read in the CSV files you created during
step 5 and generate a formatted report. This report allows you to determine the
best reductions to implement over all of the ReducePower scenarios you ran in
step 3.
See the PowerArtist Reference Manual for complete syntax and examples of
readReductions and collateReductions utilities.
Using the Power Database Mapping Utilities

The power database mapping utilities map names and objects between the
PowerArtist namespace and the power database namespace defined by
OpenAccess. You mostly likely will not need to use these utilities unless you are
using API provided as part of the standard OpenAccess distribution. Utilities also
exist that translate power database utilities to netlist names more closely associated
with industry standard synthesis tools.
pa2oa Converts a PowerArtist name to a power database name

oa2pa Converts a power database name to the equivalent
PowerArtist name
oa2nl Converts a power database name to a netlist name
nl2pa Converts a netlist name to a PowerArtist name
pa2nl Converts a PowerArtist name to a netlist name
nl2oa Converts a netlist name to a power database name
getObject Returns the power database object for the specified the
object path
getOccObject Returns the power database occurrence object for the
specified object path
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458
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PowerArtist™ User Guide 459
Index
Symbols toggle grid 188 activity-based 434

using zoom-in 184 power-based 438
.ini (initialization file) 11
viewing FSDB files 180
sample 12
viewing PTCL files 184 F
.rpt (power analysis report) 71
waveform names 184
.srpt (power report file) 127 forward clock tracing, controlling 231
sample 128 frequencies, net (reporting) 79
$ADS_ARCH 448 C FSDB support
$EDITOR 39 capacitance estimation automatic running of fsdb2vcd 422
$LD_LIBRARY_PATH 448 specifying wire load models 213 improving capacity 423
$MODEL_TECH 429 CGE improvement 174 improving performance 422
$PA_PRECISION 435 in prism 174 manual running of fsdb2vcd 423
$POWERTHEATER_ROOT 5 in simple reductions 160 functional verification 378
$PT_APPLY_SMW 85, 316 clock domain power consumption 77
$PT_DISABLE_APSH 10 Clock Enable Condition Linter (CEC) Pow-
G
$PT_PACE_CLK_DONT_USE 218 erBot 345
clock gating Gate Memory Clock (GMC) PowerBot 322
$PTSHELL_INI 12
by technique, in power reduction report gate-level power analysis 271
$TCLLIBPATH 449
131 average analysis 249
flow 233 time-based analysis 271
A clock gating efficiency, See, CGE 160 Graphical User Interface (GUI)
activity analysis clock gating summary (in power report) 76 See PowerCanvas GUI
creating graphs 241 clock gating, enhanced 234 graphs, activity
design flow 241 clock power analysis 229 creating 241
ADS_ARCH environment variable 448 viewing 67
clock power report 74
ADS_PA_FV, defining 377 clock tracing order 76
Apache Waveform Viewer H
adding/deleting notes 187, 189
E hierarchical RTL rewrite 372
adjusting the height of plots 188
hierarchy browser
adjusting waveform thickness 188 EDITOR environment variable 39
coloring by power 31
comparing waveforms in one plot 189 enhanced clock gating 234
showing instances in schematic 32
deleting a plot 186 environment variables
HSPICE 180
deleting waveforms 184 ADS_ARCH 448
displaying waveforms from HSPICE 185 EDITOR 39
displaying waveforms from Spectre 185 LD_LIBRARY_PATH 448 I
marking data points 187 MODEL_TECH 429 inferred buffer tree power report 78
measurements and annotations 187 PA_PRECISION 435 initialization file (.ini) 11, 12
navigation menu 186 POWERTHEATER_ROOT 5 instantiated clock tree capacitance, estimat-
options menu 185 PT_APPLY_SMW 85, 316 ing 233
pan up, pan down 186 PT_DISABLE_APSH 10
ruler feature 187 PT_PACE_CLK_DONT_USE 218
supported waveform sources 180 PTSH_INI 12 K
taking a snapshot 185 TCLLIBPATH 449 key file 12
tearing tabs 189 environment, setting the 5 changing the default name 12
toggle background color 188 etcl file, generating
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INDEX PowerArtist™ User Guide 460
L models 202 Prism PowerBot 324

power reduction properties dialog 33
LD_LIBRARY_PATH environment variable
design flow 294 PT_APPLY_SMW environment variable
448
linter PowerBots 335
hierarchical clock gating 238 85, 316
inferring buffer trees for high-fanout nets PT_DISABLE_APSH environment variable
238 10
M recommended flow 294 PT_PACE_CLK_DONT_USE environment
Memory Power Linter (MEM) PowerBot 336 sample report file 128 variable 218
metacomments, VHDL 199 setting up clock gating 235 ptshell
MODEL_TECH environment variable 429 algorithm 236 basic features 10
MUX Power Linter (MUX) PowerBot 337 flow 235 key file generation 12
techniques in power report 127 ptshKeyFile variable 12
tutorial 82 ptshLogFile variable 12
O viewing results 297 starting the GUI from 9
Observability Don’t Care (ODC) PowerBot power reduction clock gating report PTSHELL_INI environment variable 12
331 description 131 ptshKeyFile Tcl variable 12
OpenAccess, programming 442 sample 131
ptshLogFile Tcl variable 12
power reduction report
description 127
P sample 128 R
pa_modules.v file 359 power supplies reduction, See power reduction
PA_PRECISION environment variable 435 creating user 223 Register Power Linter (REG) PowerBot 344
PACE models 217 power-aware models 202 reports
capacitance models 217 PowerBots power analysis report (.rpt) 71
clock distribution models 217 flow diagram 298 power reduction (.srpt) 127
impact on output files 219 flow for using 299 power reduction clock gating (_cg.srpt)
precedence of 218 for power reduction 305 131
peak power analysis identifying wasted power 335 RTL rewrite
design flow 271 PowerBots, running debug switches 349
power analysis CEC 345 directory organization 349
analyzing clock power 229 DOI 307 flow 347
average flow 245 GMC 322 form of code modifications for LNR 350
block-level tutorial 53 LEC 309 formal verification of rewritten code 367
command line LNR 305 format of the rewritten code 350
modes, simulation 246 MEM 336 general form of code modifications 362
generating a clock tree 25, 56 MUX 337 GMC powerbot code modifications 355
GUI tutorial, average flow 45 ODC 331 hierarchical flow 372
GUI tutorial, time-based flow 49 Prism 324 inputs 347
modal analysis 24 REG 344 internal process flow 348
peak analysis flow 271 SMW 314 LNR gate-level simulation 355
report (.rpt) 71 PowerCanvas GUI Prism powerbot code modifications 358
time-based flow 25 edit menu 138 using the wizard 124
tutorial help menu 139 warnings and errors 370
See also tutorial 15 manipulating the clock tree 157 RTL Rewrite wizard 125
using a SAIF file 265 normal vs. optimal views for Prism dia- rule file, generating (for nCompare) 378
vectorless flow 287 log 177 sample rule file 380
viewing results in the GUI 31 properties dialog 33
with mixed-vt (threshold voltage) 225 smart source browser, using 147
power macros 202 tools menu 138
S
built-in (default) macros 202 view menu 138 SAIF files 265
default models 202 waveform viewer 180 basic format 265
macro map file 203 POWERTHEATER_ROOT environment flow for using 265
-macro_directories option 203 variable 5 sdpd format 265
replacing simulation schematic display
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opening properties dialog 33 reviewing results in the PowerCan-

using 32 vas 93
SetCellDefaultFanout command 231 scheduling auto RTL changes 104
SetClockBuffer command 229 scheduling multiple RTL changes si-
SetClockNet command 229, 230 multaneously 105
SetDefaultFanout command 230 scheduling Prism opportunities for
SetHighFanoutNet command 238 auto RTL rewrite 115
SetNetProperty command 230 using the command files 84
simple reductions dialog, column header viewing cones of logic 109, 111
definitions 149, 159 wizard flow 119
simple reductions dialog, in tutorial 95
simulation activity V
creating analysis graphs 241 VAF file
selecting a vector analysis type 241 description 287
defining design phase groups 240 sample from tutorial 56
GenerateActivityWaveforms command VCD file
242 compressing manually 425
running vector analysis in design flow creating
241 from Leapfrog 425
simulation activity file 421 from ModelSim 425
simulation activity, analyzing 239 from Verilog 425
simulation testbench vector analysis
acquiring data (troubleshooting) 429 batch flow 28, 242
SPEF processing creating analysis graphs 241
hierarchical 211 DefineGroup command 242
Split Memory Word (SMW) PowerBot 314 defining groups 240
synthesis-aware models 202 design flow 241
System Verilog GenerateActivityWaveforms command
licensing 3 242
GUI flow (tutorial) 42
T selecting a type 241
viewing FSDB or PTCL files 244
TCLLIBPATH environment variable 449 verification, functional 377
threshold voltage, mixed (power analysis) using a rule file 378
225 VHDL design
time-based power analysis 271 compiling into library 199
tutorial metacomment processing 199
power analysis voltage values
block-level 53 characterization voltage 221
gate-level 69 estimation voltage 221
RTL full-chip 19
viewing results in the PowerCanvas
31 W
with a mixed-vt cell library 61 waveforms, viewing
with clock gating 60 See also Apache Waveform Viewer 180
with power gating 66 wire load models 213
with voltage islands 64 setting Tcl commands 214
reduction 82 WriteReductionCompareFile command 378
basic flow 85 wwgaf conversion utility 426
examining linter reduction results
116
examining Prism results 107
Z
filtering reduction results 101 zero delay simulation 430
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PowerArtist 1

Software Release 2011.1.3

© 2011 Apache Design, Inc.

© 2011 Apache Design, Inc. All rights reserved.

Trademarks and Registered Trademarks

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© 2011 Apache Design, Inc.

CHAPTER 1 Installing and Setting Up PowerArtist

CHAPTER 2 Using the PowerArtist Shell

CHAPTER 3 PowerArtist Tutorial Part 1: Power Analysis

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Contents of the Analysis Directory ................................................................. 17

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Pad Power Consumption................................................................................ 73

CHAPTER 4 PowerArtist Tutorial Part II: Power Reduction

CHAPTER 5 Using the PowerCanvas

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Using the Edit Menu ..................................................................................... 138

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Displaying Waveforms from an HSPICE or Spectre Simulation................... 185

CHAPTER 6 Getting Your Design into PowerArtist

CHAPTER 7 Preparing for Power Analysis

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CHAPTER 8 Analyzing Simulation Activity

CHAPTER 9 Analyzing Simulation-Based Average Power

CHAPTER 10 Analyzing Time-Based Power

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Understanding the Inputs for a Time-Based Power Analysis.................................. 272

CHAPTER 11 Analyzing Vectorless Average Power

CHAPTER 12 Examining and Implementing Power Reduction Opportunities

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Recommended Flow for Implementing Power Reductions ..................................... 294

CHAPTER 13 Performing Functional Verification of RTL Changes

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Using Standard Verification Tools by Defining ADS_PA_FV .................................. 377

CHAPTER 14 Analyzing the Effects of Power Gating with Proprietary Commands

CHAPTER 15 Using Standard File Formats

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Using a UPF Input Flow (Beta) ............................................................................... 412

CHAPTER 16 Acquiring Simulation Data

CHAPTER 17 Generating Etcl Files for CoolTime

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CHAPTER 18 Writing OpenAccess Database Applications

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Installing and Setting Up PowerArtist 1

Supported Operating Systems

Installing the Software

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Installing Licenses and FLEXlm

Note that any user can do this—you don’t have to be “root”.

Understanding License File Entries

FEATURE sptPowerGating apacheda 2012.10 15-feb-2012 20 \

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Support for Multiple License Servers