PowerArtist 1

Command-Line Flow 2
3
4
Quick Start Guide 5

Software Release 2011.1.3

© 2011 Apache Design, Inc.

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 1

Introduction
This Quick Start Guide focuses on the PowerArtist command-line flow, which is
designed to allow you to specify all inputs and commands in a single Tcl command
file. This method is good for new users to learn the tool and for expert users to set-
up batch runs.
To get started, it is recommended that you use the Tcl command-line flow templates
in the following PowerArtist installation area:
$POWERTHEATER_ROOT/examples/command_files
You can also use the scripts for the tutorials in the following location:
$POWERTHEATER_ROOT/tutorial/analysis
or
$POWERTHEATER_ROOT/tutorial/reduction
You can use these templates as a starting point when setting up PowerArtist on a
new design. The Elaborate and CalculatePower commands are two typical
commands that you would use in a PowerArtist command file. For example:
CalculatePower -average_report_file design.rpt

Alternatively, you could specify the options to a few of the total command set
implemented by PowerArtist using the pt_set command, which is similar to the Tcl
“set” command. For example, you could specify the following command combination:
pt_set average_report_file design.rpt
CalculatePower

This command combination is equivalent to the previous CalculatePower command

example that uses the -average_report_file option. In this guide, the commands are
specified with the command-line options instead of pt_set variables.

Organization of this Quick Start Guide

The following subjects are covered in this Quick Start Guide:
 Starting a PowerArtist Tcl Command-Line Run
 Understanding the PowerArtist Inputs
 Reading in .lib Models
 Compiling and Elaborating Your Design
 Reading the Simulation Activity File
 Running Vector Analysis
 Power Analysis Setup
 Running Average Power Analysis

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Starting a PowerArtist Tcl Command-Line Run PowerArtist Quick Start Guide 2

 Running Time-Based Power Analysis

 Running Power Reduction Analysis
 Rewriting the RTL
 Generating Synthesis Constraints

Starting a PowerArtist Tcl Command-Line Run

To run a PowerArtist command-line flow, you need to start from the Tcl shell “ptshell”.
% ptshell
You can run PowerArtist in one of the following ways:
 Specify commands directly from the ptshell prompt:

> ptshell
ptshell % source run_Analysis_setup.tcl
ptshell % Elaborate

 Specify a Tcl script, containing all commands and options, using the -tcl option on
the ptshell command line.
For example, for power analysis you could specify the following:
ptshell -tcl run_Analysis.tcl
To run power reduction and RTL rewrite, you also need to specify the -artist
option:
ptshell -artist -tcl run_Reduction.tcl

Understanding the PowerArtist Inputs

PowerArtist requires the following inputs to calculate power for an RTL or gate-level
design:
 RTL/gate-level design—supported formats are Verilog, VHDL, System Verilog, or
a mix of any of these three HDLs.
 Simulation activity (VCD/FSDB)—PowerArtist requires a “level-0 dump” VCD or
FSDB file for activity information.
 Power libraries—characterized libraries in Liberty format (.lib).
 Wire load models/SPEF.
 Clock definitions—PowerArtist can infer the clock trees for RTL or pre-CTS gate-
level designs, and it can trace existing clock trees for post-CTS gate-level
designs. You need to specify the root clocks and clock buffers to infer a clock tree.
To trace a clock tree, only root clock names are required.

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Reading in .lib Models PowerArtist Quick Start Guide 3

Reading in .lib Models

Use the ReadLibrary command to specify the Liberty libraries (.libs) required to
perform a power estimation of your design. These include libraries for your memories
and IOs as well as the libraries needed to synthesize the design.
ReadLibrary -name lib_file_name
You could also specify the -synlib_files command-line option to the CalculatePower
or ReducePower commands.

Compiling and Elaborating Your Design

When you run the Elaborate command, PowerArtist compiles and elaborates the
RTL/gate-level design and creates a scenario file based on the commands and
options you specify. Before running the Elaborate command, you need to specify the
appropriate commands to compile your design files:
 For a VHDL design, PowerArtist requires you to specify VHDL files in compilation
order. You also need to specify the standard VHDL libraries. You can specify
VHDL files using the CompileFile command.
CompileFile -type vhdl -file file_name [-87 yes | no]
[-93 yes | no] -library library_name
Sample Standard VHDL Library

global env
AddLibrary SYNOPSYS ww_synopsys
AddLibrary STD ww_std
AddLibrary IEEE ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/standard_93.vhd \
-93 yes -library ww_std
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/std_1164.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/syn_arit.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/syn_unsi.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/syn_textio.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/syn_attr.vhd \
-93 yes -library ww_synopsys
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/syn_misc.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src numeric_bit.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/ \
numeric_std.vhd\ -93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/timing_p.vhd \
-93 yes -library ww_ieee

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Compiling and Elaborating Your Design PowerArtist Quick Start Guide 4

CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/prmtvs_p.vhd \

-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/prmtvs_b.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/timing_b.vhd \
-93 yes -library ww_ieee
CompileFile -type vhdl -file $env(POWERTHEATER_ROOT)/pthdl_src/syn_sign.vhd \
-93 yes -library ww_ieee

 For Verilog designs, the common way of specifying Verilog files is to specify a
start-up file (that contains a list of Verilog files) using the following command-line
option:
-verilog_startup_file file_name
Example
-verilog_startup_file top.vc
Sample Verilog Start up File
+incdir+../rtl/include
+define+SYNTHESIS
../rtl/top.v
-y ../verilog_dir
-v cell.v

Note the following about this sample file:

— The +include+ directive specifies the directory containing the include files.
— The +define+ specifies `ifdef variables.
— You must specify a synthesizable RTL/gate-level design to PowerArtist. Do not
specify testbench or Verilog simulation models.
You then need to specify the Elaborate command with the appropriate options.
 Specify the verilog_2001 option for Verilog 2001 using the following option:
-verilog_2001 true
 Specify the system_verilog option for System Verilog using the following option:
-system_verilog true
Alternatively, you can specify Verilog files using CompileFile commands, for
example:
CompileFile -type verilog -file top.v -2001 yes
CompileFile -type verilog -file top.v -sv yes

This is useful in a mixed-design flow.

 Specify the top-level module in your design:
-top top_level_module_name
 To override top-level parameter values, you can specify the following option:
-parameter_maps var1=value1:var2=value2

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Compiling and Elaborating Your Design PowerArtist Quick Start Guide 5

 Specify the name of the scenario file to be created using the following option:
-scenario_file scn_file_name
 If you have a gate-level design, specify a gate-level netlist using the following
option:
-gate_level_netlist true
 Write the power database by specifying the following option:
-elaborate_write_power_db true
 Specify the name for the log file for the Elaborate run using the following option:
-elaborate_log Elaborate.log

Sample Elaborate Command

Elaborate \
-elaborate_write_power_db true \
-elaborate_log ElaborateBatch.log \
-power_db_name Batch.pdb \
-scenario_file Batch.scn \
-top txrx \
-verilog_2001 true \
-verilog_startup_file txrx.vc

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Running Vector Analysis PowerArtist Quick Start Guide 6

Running Vector Analysis

You should analyze your vectors before you use them for power analysis and
reduction. Vector analysis displays the activity in the design with respect to time. It
helps identify the following:
 Whether or not the testbench is creating the expected activity.
 Whether or not there are any blocks that are active when they should be off. It
helps to identify power bugs.
 The optimal simulation time window that best represents the mode of operation
you want to analyze.
You can perform vector analysis in one of two modes: activity per cycle or average
frequency per interval. Both modes are run using the GenerateActivityWaveforms
command.
Before you can run vector analysis, you need to define instance groups using the
DefineGroup command:
DefineGroup group_name [hierarchical_instance_name(s)]
Example
DefineGroup memory_groups {top.core1.m1 top.core1.m2}
Each defined group will have a separate waveform in the output file (FSDB or PTCL).

Reading the Simulation Activity File

As part of the GenerateActivityWaveforms command, you need to specify activity
files in the form of VCD, gzipped VCD or FSDB files. You will also need to specify the
$scope statement path to the instance that corresponds to the top module you
specified with the Elaborate command.
 To specify the name of the activity file, use the following option:
-activity_file activity_file_name
 To specify the hierarchical instance name of the top-level module in the VCD/
FSDB, use the following option:
-top_instance top_instance_name
Note that if the simulation activity file does not contain activity information for all
instances in the design, you will see a warning message similar to the following:

wwgaf: Warning 2046: Simulation data missing.

There are 80 instances in the SCN file
which are missing from the simulation data (-iaf).
80 missing / 343 total = 23% missing
This means either:
1. the -topinst option specifies the wrong instance,
2. the design hierarchy changed between the time you
ran simulation and the time you created the SCN file, or

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Running Vector Analysis PowerArtist Quick Start Guide 7

3. the design hierarchy was not properly monitored

during simulation.
The following instances weren't found:
top.cg_inst1
top.cg_inst2
………………

When you see this warning, you must carefully examine the cause of the missing
instances. Using an activity file with poor activity coverage may not give realistic
power numbers. PowerArtist can propagate activity through such instances
missing activity data. If you are convinced you can use activity propagation
through these instances to calculate power, then specify the following option:
-mixed_sim_prob_estimation true

Using the Activity per Cycle Mode

The activity per clock cycle mode allows you to trace the activity in the design (or a
group of instances in the design) at every clock cycle or a number of clock cycles. To
use this mode, you must specify the GenerateActivityWaveforms command with the
following specific options.
 To specify the reference clock name, use the following option:
-activity_waveform_clock_name clock_name
 To specify the clock edge to be considered the start point for any clock cycle, use
the following option:
-activity_waveform_clock_edge (pos | neg | auto)
 To specify the analysis start clock cycle using the following option:
-activity_waveform_start_clock_cycle int
 To specify the number of clock cycles that constitute one interval, use the
following option:
-activity_waveform_cycles_per_interval int
 To specify the number of intervals using the following option:
-activity_waveform_number_of_intervals integer| all
To run vector analysis from the starting clock cycle for the entire VCD/FSDB, use
the following option:
-activity_waveform_number_of_intervals all
 To specify the groups for which activity waveforms are to be generated (and that
you earlier defined using the DefineGroup command) use the following option:
-activity_waveform_group_list {group1 group2 group3 ...}
 Set the activity_waveform_graph_type to activity_per_cycle for activity per cycle
analysis:
-activity_waveform_graph_type activity_per_cycle

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Running Vector Analysis PowerArtist Quick Start Guide 8

Using the Average Frequency Over a Specified Interval Mode

Use this mode to trace the average frequency of the design (or group of instances in
the design) at every specified time interval. Note that you must specify the time value
for the following options in units of fs, ps, ns, us or ms.
 Specify start time using the following option:
-activity_waveform_start_time time
 Specify interval size using the following option:
-activity_waveform_interval_size time
 Specify number of intervals:
-activity_waveform_number_of_intervals int
 Specify the groups, defined using the DefineGroup command, for which you want
to generate activity waveforms using the following option:
-activity_waveform_group_list {group1 group2 group3 ...}
 Set the activity_waveform_graph_type to frequency_per_interval for activity per
cycle analysis:
-activity_waveform_graph_type frequency_per_interval

Controlling the Output for Vector Analysis

For either of the these types of vector analyses you need to specify the form of the
output:
 You can generate an output waveform in FSDB (.fsdb) format by specifying the
following option:
-fsdb_output_file file_name.fsdb
 You can also generate a graph in PTCL (.ptcl) format by specifying the following
option:
-ptcl_output_file file_name.ptcl
 You can specify a name for the log file for vector analysis by setting the following
option:
-activity_waveform_log file_name.log
By default, the log file is called Waveform.log.

Sample Command File for Vector Analysis

The following sample file defines five groups to be traced, sets the top module of the
design to “top”, and then runs a vector analysis using the
GenerateActivityWaveforms command with the applicable command-line options.

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Running Vector Analysis PowerArtist Quick Start Guide 9

Here, the vector analysis traces the average frequency of the defined instance
groups.

DefineGroup top { top }

DefineGroup core { top.core1 }
DefineGroup pci { top.core1.p1 }
DefineGroup rxchan { top.core1.r1 }
DefineGroup txchan { top.core1.t1 }

set design top

GenerateActivityWaveforms \
-activity_file ../design_data/rtl_sim/activities.vcd \
-activity_waveform_group_list { top core pci rxchan txchan } \
-activity_waveform_graph_type frequency_per_interval \
-activity_waveform_interval_size 15160ps \
-activity_waveform_number_of_intervals 400 \
-activity_waveform_start_time 6014730ps \
-fsdb_output_file top_activity.fsdb \
-activity_waveform_log GenerateActivityWaveforms.log \
-scenario_file top.scn \
-top_instance txrx_tst.top1

This command generates an FSDB file named top_activity.fsdb.

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Power Analysis Setup PowerArtist Quick Start Guide 10

Power Analysis Setup

After vector analysis, you will next run either an average or a time-based power
(power vs. time) power analysis using the CalculatePower command. Before you run
power analysis, you need to do some common setup steps. You could include the
setup commands in the same script as your analysis commands, but it may be better
to put them into a separate script that you can then source from your analysis script.

Common Setup for Clock Definitions

Before you run a power analysis, you need to define the clocks in your design.
 Use the SetClockNet command to specify each clock in the design.
SetClockNet -name (clock_net_name | pin_name) -mode (infer | trace)
-gate_clock (true | false) [other_options...]
For RTL and pre-CTS designs, specify “-mode infer” to infer the clock tree. For
post-CTS designs, specify “-mode trace” to trace an existing clock tree in the
design. To predict the effects of synthesis clock gating, set the -gate_clock option
to true. If you will not be using clock gating, set this option to off. See more below
on SetClockGatingStyle.
 If you specify “-mode infer” you must specify root, branch and leaf clock buffers for
clock tree inferencing using the SetClockBuffer command:
SetClockBuffer -type (root | branch | leaf) -name buffer_name
-library library_name -fanout buffer_fanout
Note: The library name you specify with the -library option is the logical library
name that is present in the .lib with library() attribute.
 Use the SetClockGatingStyle command to specify the clock gating cell to be used:
SetClockGatingStyle [-min_bit_width bit_width]
-clock_cell_attribute gating_cell_type
-gating_cells gating_cell_name:logical_library_name
You need to specify the clock_gating_integrated_cell attribute in the library with
the -clock_cell_attribute option. PowerArtist looks for it in the .lib to determine the
clock gating cell. If clock_gating_integrated_cell is present in the .lib as:
clock_gating_integrated_cell : "latch_posedge_precontrol";
then specify latch_posedge_precontrol with the -clock_cell_attribute option. You
can explicitly select the clock gating cells using the -gating_cells option. If you
specify the
-gating_cells option, then the -clock_cell_attribute is optional.
 Similar to clock buffer inferencing, use the SetHighFanoutNet command to infer
buffer trees for high fanout nets in the design:
SetHighFanoutNet -fanout max_signal_fanout

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Power Analysis Setup PowerArtist Quick Start Guide 11

SetBuffer -type (root | branch | leaf) -name buffer_name

-library library_name -fanout buffer_fanout

Sample Clock Definition Commands

You could use the following sample lines in your run script to define clocks in your
design.

# Clock Gating Commands

SetClockNet -name top.clk -mode infer -gate_clock yes

SetClockNet -name top.pci_clk -mode infer
SetClockNet -name top.tck -mode infer
SetClockGatingStyle -clock_cell_attribute latch_posedge_precontrol
SetClockBuffer -type root -name SEQCLKBUFX4MTH -library hvt -fanout 2
SetClockBuffer -type branch -name SEQCLKBUFX8MTH -library hvt -fanout 2
SetClockBuffer -type leaf -name SEQCLKBUFX8MTH -library hvt -fanout 60

Defining Memories for Power Analysis

If you want to be able to determine the sum of the power for all of your memories,
you need to define the instantiated memories of your design using the DefineMemory
command. The complete definition for the command is in the Running Power
Reduction Analysis section. The key options you will need to specify for power
analysis are -library and optionally -cell.

Setup for Power Prototyping

PowerArtist allows prototyping of the following power management techniques at
RTL:
 Clock gating
 Mixed-Vt
 Power Gating
 Voltage Islands
The setup for clock gating is discussed in the Common Setup for Clock Definitions
section. For more complete information on all of these power management
techniques, see the PowerArtist User Guide and the PowerArtist Reference Manual.
The analysis tutorial in the PowerArtist User Guide takes you through each of these
techniques.

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Power Analysis Setup PowerArtist Quick Start Guide 12

Mixed-Vt Setup
If you want to run a mixed-Vt power analysis, do the following setup before running
the CalculatePower command.
 Specify the libraries that you want to use for cell selection:
SetLibrary -instance inst_name(s) -library lib_name(s)
Example
SetLibrary -instance top -library {hvt_library lvt_library}
Note that you must specify the logical library name, which is specified in the .libs
using library() attribute.
 Classify cells into different Vt types:
Cells are placed into different Vt categories in the .lib using the following
attributes:
— At the library level:
default_threshold_voltage_group : "string" ;
— At the cell level:
threshold_voltage_group : "string" ;
The string value specifies the voltage threshold type.
If the .libs do not contain these attributes, categorize the cells using the
SetVoltageThreshold command.
SetVoltageThreshold -group threshold_group -pattern cell_pattern_list
Example
SetVoltageThreshold -group LVT -pattern { *_TL1 *_TL2 }
SetVoltageThreshold -group HVT -pattern { *_TH }
 Specify the mixed-vt percentage for cell selection using the SetVT command:
SetVT -mode percentage -instance {instance_list}
-vt_group {threshold_group_list}
Example
SetVT -mode percentage -instance {top.block1 top.block2} -vt_group
{HVT:70 LVT:30}

Setup for Capacitance Estimation

PowerArtist has numerous ways to estimate capacitances for your interconnect:
1. Wire load models from your .libs
2. SPEF files for a gate design extracted from the physical design
3. PACE models (which are covered in the User Guide)

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Power Analysis Setup PowerArtist Quick Start Guide 13

4. A default wire load model shipped with PowerArtist (also covered in the User
Guide)

Specifying Wire Load Models

To get started using wire load models, you need to specify some additional Tcl
commands and a few specific options to the CalculatePower command.
 To specify the load on primary outputs, use the following CalculatePower option:
-default_output_load load_value
Example
-default_output_load 5e-15
The capacitance unit is Farads.
 To specify the library containing wire load models, use the following
CalculatePower option:
-wireload_library library_name
Note that you must specify the logical library name.
 To specify the wire load mode, use the following Tcl command:
SetWireLoadMode (top | enclosed)
The default setting for this command is enclosed.
 If you specify the wire load mode as “top”, you also need to specify the wire load
model using the following command:
SetWireLoadModel [-name model_name] -instance inst_name(s)
-library lib_name [-scaling_factor factor]
 In the absence of wire load models in the .libs, you can use the PowerArtist
default wire load models. You can scale these default wire load models with the
following command:
SetCapEstimation -technology technology_size [-scale scale_factor]

Reading in SPEF Files

You can either read in single SPEF files or multiple SPEF files. You can read in one
or more SPEF files using the ReadParasitics command. To specify different SPEF
files to different hierarchical instances in the design use the following command:
ReadParasitics -path hierarchical_inst_name -file SPEF_file_name
If you have one SPEF file, then specify the top-level module in the design with the -
path option; otherwise, specify one ReadParasitics command for each SPEF file.

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Running Average Power Analysis PowerArtist Quick Start Guide 14

Reading in SDC Files

PowerArtist can read in SDC files and translate the information into the following
PowerArtist commands/command-line options:
 SetClockNet
 SetWireLoadMode
 SetWireLoadModel
 -default_transition_time float
 -transition_time_file slopes_file
 -capacitance_file load_file
The command line options are created are for the CalculatePower command.
The ReadSDC command reads in the SDC files and the power database (.pdb) file
generated using the Elaborate command.
ReadSDC -sdc_files {file_name1 file_name2 ...}
-top top_inst [-sdc_command string]
[-transition_time_file file_name] [-capacitance_file file_name]
[-sdc_out_file file_name] [-sdc_log file_name]
[-power_db_name file_name]
When running the ReadSDC command, you should specify the -sdc_files, -
sdc_out_file, and -top options. Your SDC file should have a units command. If it does
not, supply a units command (in " ") to the -sdc_command option to ensure that
PowerArtist uses the proper units. You can then source the output of the ReadSDC
command in the PowerArtist command file.

Running Average Power Analysis

In addition to the common setup commands and CalculatePower options described
in the previous section, if you want to run an average analysis, you need to specify
the following additional CalculatePower options.
 To tell PowerArtist to run an average analysis, specify the following option:
-analysis_type average
 To specify the name of the activity file, use the following option:
-activity_file activity_file_name
The activity file can be either FSDB or VCD.
 To specify the hierarchical instance name of the top-level module in the VCD/
FSDB, use the following option:
-top_instance top_instance_name
 To specify a GAF file, use the following option:
-gaf_file design.gaf

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Running Average Power Analysis PowerArtist Quick Start Guide 15

You must specify a GAF file when running either an average power analysis or
power reduction. The GAF file is an intermediate file generated when the activity
file is parsed. This allows you to run multiple power analysis and reductions
without the runtime overhead of parsing the simulation file again. The GAF file
contains average frequency information for all named nets and power arcs in the
design.
 To use a GAF generated by a previous run, specify the following option:
-use_existing_gaf true
 To specify the name of the scenario file you created when you elaborated the
design, use the following option:
-scenario_file scn_file_name
 To specify start and finish times for the simulation window for the average analysis
use the following options:
-start_time time
-finish_time time
The time values need to be an integer that can be in any of these units: fs, ps, ns,
us, ms and s.
Example
-start_time 10us
-finish_time 11us
You can identify the start_time and finish_time by looking at the activity-over-time
waveform generated using vector analysis.
 To control the output of the report file for an average analysis, use the following
option:
-average_report_options options
Commonly used reporting options include:
0—prints net switching power (internal load power) in a separate section
p—reports power for all hierarchical parent instances
c—reports power due to register clock pin switching in the “Clock Power” section.
By default, it is reported as part of the register power.
g—reports frequencies of named nets
a—reports area information
V—reports power per supply
Note that you can specify a concatenated list of options to the -
average_report_options option
-average_report_options 0pg
 To specify the average power report file name, use the following option:
-average_report_file report_file_name

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Running Average Power Analysis PowerArtist Quick Start Guide 16

 To have PowerArtist write out a power database (PDB) file, use the following
option:
-average_power_db true
 To specify the name of the power database (PDB) file, use the following option:
-power_db_name name.pdb
The default pdb name is top_level_model.pdb.
 To run gate-level power analysis in high effort mode (arc-based mode)—which
produces higher accuracy with longer run times—specify the following option:
-arc_based_estimation true
In pin-based estimation, accuracy is compromised by about 5%, but it provides
better performance.
 To specify the log file name for your average run, use the following option:
-calculate_log calculate_average.log

Sample CalculatePower Command for Average Power Analysis

The following sample CalculatePower command runs an average power analysis.

CalculatePower -analysis_type average \

-activity_file ../design_data/rtl_sim/activities.vcd \
-average_report_file $design.AverageBatch.rpt \
-average_report_options agip \
-average_write_power_db true \
-default_output_load 3.9e-11 \
-finish_time 12135580ps \
-gaf_file Average.gaf \
-calculate_log AverageAnalysis.log \
-power_db_name AverageBatch.pdb \
-scenario_file Batch.scn \
-start_time 6014730ps \
-top_instance txrx.top1 \
-wireload_library hvt

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Running Time-Based Power Analysis PowerArtist Quick Start Guide 17

Running Time-Based Power Analysis

PowerArtist allows you to perform a power-over-time (time-based) analysis at RTL
and at the gate level.

Specifying Instances to Monitor

For time-based analysis, you need to specify instances (or group of instances) to be
monitored using MonitorInstances command.
MonitorInstances (-group group_name(s) | (-name instance_name(s))
[-monitor_dynamic_trace yes | no] [-monitor_static_trace yes | no]
[-all true | false]
The legal group names are memory, io, clock, register, latch, inferredbuffer and
other.

# Instances to monitor in the design

MonitorInstances -name top.core1.t1 -all 1
MonitorInstances -name top.core1.r1 -all 1

If you do not specify a MonitorInstances command, PowerArtist traces peak power

only for the top-level module.

Setting Options Specific to Time-Based Analysis

In addition to the common power analysis options, to run a time-based analysis, you
need to set specific options to the CalculatePower command.
 To instruct PowerArtist to run a time-based analysis, use the following option:
-analysis_type time_based
 To specify the output waveform name, use one or both of the following options:
-fsdb_output_file file_name
-ptcl_output_file file_name
This will generate either an FSDB or PTCL file, respectively.
 To trace power over time for only a part of the total simulation duration of the
FSDB/VCD, specify start_time and finish_time options:
-start_time time
-finish_time time
The following options are required to setup power-per-cycle at RTL:
 To specify a reference clock use the following option:
-reference_clock clock_net_name
The reference_clock option determines the start and end of an interval. The clock
net specified with reference_clock should be the fastest free-running clock in the
design.

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Running Time-Based Power Analysis PowerArtist Quick Start Guide 18

 To specify the active clock edge which defines the start point of first interval, use
the following option:
-active_edge (positive | negative | auto
 To specify the number of clock cycles that constitute an interval, use the following
option:
-num_clock_cycles integer
The following options are required to setup power-per-interval analysis for a gate-
level design:
 To specify a gate level netlist use the following option:
-gate_level_netlist true
 To specify the interval size in time units, use the following option:
-interval_size float

Sample Command to Run Time-Based Power Analysis

The following sample CalculatePower command runs a time-based power analysis:

CalculatePower -analysis_type time_based \

-active_edge positive \
-activity_file ../design_data/rtl_sim/activities.vcd \
-fsdb_output_file TimeBased.fsdb \
-default_output_load 3.9e-11 \
-finish_time 12135580ps \
-calculate_log CalculatePowerTimeBased.log \
-num_clock_cycles 20 \
-power_db_name TimeBasedBatch.pdb \
-reference_clock top.clk \
-save_clock_trees_netlist true \
-scenario_file $design.Batch.scn \
-start_time 6071580ps \
-time_based_report_file TimeBasedBatch.rpt \
-time_based_write_power_db true \
-top_instance txrx_tst.top1 \
-use_scan_flops true \
-wireload_library hvt \

Monitoring Flop Clock Activity for RTL Designs

Flop clock activity provides a measure of clock gating efficiency in your RTL design.
It monitors the activity at the clock pins of registers while accounting for the effects of
clock gating. The “CalculatePower -analysis_type time_based” specification also
generates the flop_clock_activity waveform.
To generate flop clock activity waveforms in addition to power-over-time waveforms,
do the following:

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Running Power Reduction Analysis PowerArtist Quick Start Guide 19

 Specify the instances that you want to monitor for flop clock activity:
MonitorToggleInstances -instance instance_name(s)
 Add the following option to your CalculatePower command:
-flop_clock_activity file_name_prefix
This option specifies a prefix for the flop clock activity output files. The prefix “fca”
is commonly used.
As you would for any time-based run, be sure to specify the -num_clock_cycles and
-reference_clock_name options to CalculatePower as well.

Running Power Reduction Analysis

Power reduction is controlled by the ReducePower command. Before you can run
this command, you need to do some setup, such as defining memories.
 Define memories and memory control signals for the GMC PowerBot, using the
DefineMemory command:
DefineMemory -library library_set
-access_enable access_enable_ports
-read_address read_address_ports
-write_address write_address_ports -data pin_name(s)
-memory_enable memory_enable_or_select_ports
[-cell cell_list]
Example for a Single Port Clocked SRAM
DefineMemory -library RR12BX32_lib \
-access_enable { *WE } \
-memory_enable { ME TME } \
-read_address { *ADR* } \
-write_address { *ADR* } \
-data { D* Q* TD* }

You must specify this command before the ReducePower command in your script.
 Specify the minimum bit-width of a candidate register for the Prism PowerBot
using the following command:
SetDatapathWidth width
The default minimum bit width is 8. You must specify this command before the
ReducePower command in your script.
To run power reduction, you need to specify the ReducePower command with the
appropriate options. The following list provides the options that are most commonly
used.
 To specify the class of reductions you want to run, use the following option:
-reduction_classes all | linter | logic | memory | clock

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Running Power Reduction Analysis PowerArtist Quick Start Guide 20

By default, PowerArtist runs all reductions except SplitMemoryWords (SMW). To

run SMW, you must specify the following environment variable before running
reduction:
PT_APPLY_SMW 1
 To specify the reduction power report file name, use the following option:
-reduction_report_file report_file_name
 To specify the name of PDB file use the following option:
-power_db_name name.pdb
 To specify the name of the log file for the reduction run, use the following option:
-reduction_log ReducePower.log
 To overwrite the existing power database, specify the following option:
-reduction_overwrite_power_db true
If not set, PowerArtist incrementally updates the reduction data for all the
reductions that are enabled without updating the average power numbers
calculated from the previous run.
 If you want to be able to probe the clock tree, include the following option:
-save_clock_trees_netlist true

Sample Command to Run Power Reduction Analysis

The following sample ReducePower command runs power reduction analysis.

ReducePower \
-activity_file ../design_data/rtl_sim/txrx_sleep.vcd.gz \
-reduction_report_file Batch.srpt \
-reduction_overwrite_power_db true \
-default_output_load 3.9e-11 \
-finish_time 12135580ps \
-gaf_file Batch.gaf \
-reduction_log ReducePowerBatch.log \
-power_db_name Batch.pdb \
-save_clock_trees_netlist true \
-scenario_file Batch.scn \
-start_time 6071580ps \
-top_instance txrx_tst.top1 \
-wireload_library hvt \

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Rewriting the RTL PowerArtist Quick Start Guide 21

Rewriting the RTL

You need to use the RewriteRTL command to run automatic RTL rewrite. To access
the original RTL, the RewriteRTL command requires that you set the options that are
also specified for the Elaborate command such as the following:
 -verilog_startup_file file_name
 -top top_level_module_name
 -verilog_2001 true
You also need to specify some additional options.
 To specify the power database (.pdb) file generated during the power reduction
process, use the following command.
-power_db_name pdb_file_name
The rewrite process uses this file to determine the required RTL changes.
 To tell the rewrite process to update the power database, you must specify the
following command:
-elaborate_write_power_db true
 To specify the directory to which the rewritten RTL should be rewritten, use the
following command:
-output_rtl_dir_name output_dir_name
 To specify the name of the output start-up file generated during the RTL rewrite
process, use the following command:
-output_startup_file file_name
 To specify the rewrite report file name that contains a list of modified RTL files,
use the following command:
-output_report_file rewrite_report_file
 To specify the rewrite log file name, use the following command:
-rewrite_log_file file_name.log
 To set the name of the log file for the rewrite process, use the following command:
-rewrite_log file_name.log

Sample Command to Run RTL Rewrite

The following command sample runs the rewrite process.

RewriteRTL \
-elaborate_write_power_db true \
-rewrite_log RTLRewriteBatch.log \
-output_rtl_dir_name ./rewrite.Batch \
-power_db_name $design.Batch.pdb \
-rewrite_report_file rewriteBatch.rpt \

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Generating Synthesis Constraints PowerArtist Quick Start Guide 22

-top txrx_tst.top1 \
-verilog_2001 true \
-verilog_startup_file txrx.vc

Generating Synthesis Constraints

PowerArtist can complement synthesis tools by generating constraints for more
effective clock gating. To generate synthesis constraints, you need to do the
following:
1. Run the ReducePower command specifying all of its required options and some
special options to the SetClockNet command.
You need to specify the “-gate_clock false” option setting on any clock net for
which you want to generate power gating synthesis constraints. This enables the
Local Explicit Clock Enable (LEC) clock gating PowerBot. LEC stores power
savings from each clock gating opportunity in the power database.
2. Use the CreateGraph command to plot a graph of cumulative power savings.
Typically, the cumulative power saved rapidly increases and then begins to
saturate (see the following graph generated by the CreateGraph command).

99% power savings with

<50% clock gates

Clock gates waste

power

Clock gates are

ineffective

Figure 1 Output from the CreateGraph Command

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Generating Synthesis Constraints PowerArtist Quick Start Guide 23

The synthesis constraints feature has two benefits:

— It excludes registers (by default) that increase power consumption when clock
gated.
— It helps reduce clock skew by reducing the number of integrated clock gating
cells in your clock distribution network.You can choose to eliminate the
ineffective clock gates by specifying the -cumulative_savings option to the
WriteClockGatingConstraints command (or the equivalent pt_set
constraints_savings option).
3. Use the WriteClockGatingConstraints command to create a synthesis constraints
file for your synthesis tool (PowerCompiler) to exclude from clock gating those
registers that either cause power to increase or are ineffective in saving power
when clock gated. Currently, you can generate synthesis constraints in the
PowerCompiler format only. Ask your application engineer for a script that
converts PowerCompiler constraints to RTL Compiler constraints if you use RTL
Compiler from Cadence Design Systems Inc.

Using the CreateGraph Command

The CreateGraph command generates a graph of data related to clock gating
opportunities. The syntax is as follows:
CreateGraph -graph_class clock -power_db_name file_name
[-graph_output_file file_name] [-graph_log file_name]
[-graph_type power_savings]
You must specify the following information to this command.
 To specify the class of the graph as “clock”, use the following option:
-graph_class clock
This generates graph data related to clock gating opportunities.
 To specify the name of the power database, use the following option:
-power_db_name file_name
 To specify the graph output file name, use the following option:
-graph_output_file file_name
If you don’t specify this option, the PTCL is output to the log file, which by default
is named CreateGraph.log.
 To specify the graph type, use the following option:
-graph_type power_savings
This generates a cumulative power savings curve as a function of the number of
RTL reduction opportunities.

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Generating Synthesis Constraints PowerArtist Quick Start Guide 24

Sample CreateGraph Command

The following sample CreateGraph command generates a graph of cumulative
power savings as a function of the number of RTL reduction opportunities.

CreateGraph -class clock -power_db_name my.pdb \

-graph_output_file power_savings.ptcl

The resulting PTCL file is called power_savings.ptcl

Using the WriteClockGatingConstraints Command

The WriteClockGatingConstraints command generates synthesis constraints to
exclude registers from clock gating. The syntax is as follows
WriteClockGatingConstraints -power_db_name pdb_file
-constraints_savings float -top module_name
[-constraints_bus_naming_style string] [-constraints_log file_name]
[-constraints_output_file file_name]
[-constraints_synthesis_tool PC]
You must specify the following information to this command.
 To specify the name of the power database, use the following option:
-power_db_name file_name
 To specify the cumulative savings:
-constraints_savings float
 To specify top-level module name, use the following option:
-top module_name
 To specify the bus naming style, use the following option:
-constraints_bus_naming_style string
 To specify the name of the log file for this command, use the following option:
-constraints_log Constraints.log
 To specify the synthesis constraints output file, use the following option:
-constraints_output_file file_name

Sample WriteClockGatingConstraints Command

WriteClockGatingConstraints -power_db_name my.pdb \

-constraints_savings 20e-3 -top txrx \
-constraints_bus_naming_style %s_%d \
-constraints_output_file exclude_pc.tcl

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Using the Command-Line Help and Other Documentation PowerArtist Quick Start Guide 25

Using the Command-Line Help and Other Documentation

PowerArtist has a built-in mechanism for listing the syntax for any of the command
file commands.
 To list all options for a command type:
ptshell -cmd "command_name -help"
Example
ptshell -cmd "CalculatePower -help"
 To list all pt_set power analysis variables, do the following:
ptshell -cmd "pt_set"
 To list all pt_set power reduction variables, do the following:
ptshell -artist -cmd "pt_set"

Accessing User Guides and Reference Manuals

For further details on the PowerArtist commands described in this guide and sample
scripts and flows, see the following separate PDF files:
$POWERTHEATER_ROOT/doc/PowerArtistUserGuide.pdf
$POWERTHEATER_ROOT/doc/PowerArtistRef.pdf
You can email Apache support personnel at [email protected].

Accessing the Tutorials

The PowerArtist User Guide includes two tutorials:
PowerArtist Tutorial Part 1: Power Analysis
PowerArtist Tutorial Part II: Power Reduction
Many of the examples in this guide are taken from these tutorials. It is strongly
suggested that you use run through the tutorials to become familiar with the flow and
outputs of both the analysis and power reduction features.

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Using the Command-Line Help and Other Documentation PowerArtist Quick Start Guide 26

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