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Verilog Palnitkar Solutions Chapter 10

This document contains exercises related to modeling timing and delays in Verilog. It discusses different delay models including distributed, lumped, and path delay models. It provides examples of writing Verilog modules using specify blocks to describe timing constraints and path delays for D flip-flops. The exercises involve writing Verilog modules for circuits using different delay models and specifying path delays and timing checks.

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Aahnaf Mustafiz 1631698043
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378 views6 pages

Verilog Palnitkar Solutions Chapter 10

This document contains exercises related to modeling timing and delays in Verilog. It discusses different delay models including distributed, lumped, and path delay models. It provides examples of writing Verilog modules using specify blocks to describe timing constraints and path delays for D flip-flops. The exercises involve writing Verilog modules for circuits using different delay models and specifying path delays and timing checks.

Uploaded by

Aahnaf Mustafiz 1631698043
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 10

Chapter 10. Timing and Delays


10.6 Exercises
1. What type of delay model is used in the following circuit? Write the Verilog
description for the module Y.

My answer:
Distributed Delay.

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2. Use the largest delay in the module to convert the circuit to a lumped
delay model. Using a lumped delay model, write the Verilog description for
the module Y.

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My answer:

3. Compute the delays along each path from input to output for the circuit in
Exercise 1. Write the Verilog description, using the path delay model. Use
specify blocks.
My answer:

4. Consider the negative edge-triggered with the asynchronous reset D-


flipflop shown in the figure below. Write the Verilog description for the
module D_FF. Show only the I/O ports and path delay specification. Describe
path delays, using parallel connection.

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My answer:

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5. Modify the D-flipflop in Exercise 4 if all path dealys are 5 units. Describe
the path delays, using full connections to q and qbar.
My answer:

6. Assume that a six-delay specification is to be specified for all path delays.


All path delays are equal. In the specify block, define parameters
t_01=4,t_10=5,t_0z=7,t_z1=2,t_1z=3,t_z0=8. Use the D-flipflop in Exercise 4
and write the six-delay specification for all paths, using full connections.

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My answer:

7. In Exercise 4,modify the delay specification for the D-flipflop if the delays
are dependent on the value of d as follws:
clock -> q = 5 for d = 1'b0, clock -> q= 6 otherwise
clock -> qbar = 4 for d = 1'b0, clock ->qbar = 7 otherwise
All other delays are 5 units.
My answer:

8. For the D-flipflop in Exercise 7, add timing checks for the D_flipflop in the
specify block as follows:
The minimum setup time for d with respect to clock is 8.
The minimum hold time for d with respect to clock is 4.
The reset signal is active high. The minimum width of a reset pulse is 42.
My answer:

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