Pmc20-E 06
Pmc20-E 06
Programming technique
Contents
Introduction............................................................ 3
Programming technique ......................................... 4
Operations.......................................................... 5
Operands ............................................................ 9
Operating mode of the controller....................... 10
Logic operations .................................................... 12
Operation L, LN................................................. 12
Operation A, AN................................................ 12
Operation O, ON................................................ 12
Operation =, =N ................................................. 13
Operation AB..................................................... 14
Operation OB..................................................... 14
Word operations..................................................... 21
Read and write operations.................................. 21
Word logic operations............................................ 27
Uses.................................................................... 28
Counters ................................................................. 29
Operations.......................................................... 29
Comparison operations .......................................... 31
Arithmetic .............................................................. 33
Digital timers ......................................................... 37
Operations.......................................................... 37
Shift operations (bit/digit)...................................... 41
Bit shift operations............................................. 41
Digit shift operations ......................................... 43
Shift digit to the left ........................................... 44
Digit shift to the right......................................... 45
Rotate digit to the left ........................................ 46
Rotate digit to the right ...................................... 47
Introduction
This section describes the SELECONTROL® programming technique. The program
examples show how the operations work. The data registers D 15.56 ... D 15.62 are
frequently used in the examples.
The contents of these registers are shown directly by controller systems which have an
integrated LC-display. In the case of a controller having no display, the current contents
of the registers can be displayed on a terminal at any time while in the RUN mode by
means of the command VIEW, e.g. V) D 15.56.
All the other data registers can also be used for programming purposes.
Information relating specifically to the Controller, such as the address ranges can be
found in Section "Programming".
Programming technique
The program consists of a sequence of control instructions. The format of these control
instructions for the SELECONTROL® PMC is based on the recommendations of the
DIN 19239 Standard.
A control instruction is made up as follows:
Control instruction
O peration O perand
0102 L I 01.07
M odule address
C onnection term ina l
The mnemonic abbreviations used for the operands have been based on expressions in
the English language.
The instruction set used for the SELECONTROL® PMC programming technique is
made up of 70 operations in total.
Thanks to this high performance instruction set, even complex automation tasks can be
easily, quickly and clearly programmed.
Operations
Logical operations: reading
L Load
LN Load Not
A And
AN And Not
O Or
ON Or Not
XO Exclusive-Or
XON Exclusive-Or-Not
AB And-Block
OB Or-Block
Triggering
TRG Trigger
Data transport
FTW Fetch Word
FTB Fetch Byte
FTD Fetch Digit
STW Store Word
STB Store Byte
STD Store Digit
Comparison operations
LT Less than
LTE Less than or equal
EQ Equal
GT Greater than
GTE Greater than or equal
Arithmetic operations
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
FTR Fetch Aux.-Reg.
Timing operations
TF Timer fast (0,1s)
TS Timer slow (1,0s)
Counting operations
CU Count Up
CD Count Down
Shift/Rotate operations
SFL Shift left 1 digit to the left
SFR Shift right1 digit to the right
Block operations
BSU Block shift-up
BSD Block shift-down
BR Block reset
MDD Copy D-Block to D-Block
MDR Copy D-Block to R-Block
MRD Copy R-Block to D-Block
MRR Copy R-Block to R-Block
Step counters
INC Increment Step counter content +1
DEC Decrement Step counter content -1
Jump instructions
JP Jump unconditionally
JCF Jump conditionally on false
JCT Jump conditionally on true
LB Jump destination label
JS Jump to sub-routine
RET Return from sub-routine
Indirect addressing
FIR Fetch indirect R-register Read indirect R-register
FID Fetch indirect D-register Read indirect D-register
SIR Store indirect R-register Write to indirect R-register
SID Store indirect D-register Write to indirect D-register
Code conversion
BID Binary into BCD
DEB BCD into Binary
Look-Up-Table
LKP Look-Up-Table Read table
Data output
SOH serial out hex Output data in hex-code via the serial port
SOD serial out digit Output data in ASCII-code via the serial port
Programm organization
EP End of Program
NOP No Operation
BITBUS communication
TRM Transfers a message from a PMC D-register block to a transmit mailbox
RCV Reads a message received in the receive mailbox into a PMC D-register
block
Operands
Each operand is made up of the data type and an address.
Data types
The data types are designated as follows:
Input I
Output O
Marker M
Special-Marker M
Stepcounter S
Data Register D
Constant K
Real Register R
Address ranges
The address ranges of the data types are shown in Section "Programming".
I/O phase
R ead-in inputs
Line N o. W rite to outputs
X XX X E nd of program (E P )
The cycle time depends on the length of the program and the nature of the command
instructions.
The 1-bit logic operations called for in the user-program are carried out in the logic-unit
(LU). The result of a logic operation is always deposited in the result register (RR). All
logic operations refer to the RR.
The multi-bit operations are carried out by the arithmetic logic unit (ALU). A "DRIVE"
is necessary in such cases i.e. the 1-bit result register must be set to 1 (RR=1).
The result of a multi-bit operation is always deposited in the multi-bit result register
(MRR). All multi-bit operations refer to the MRR.
The influence on the result registers (RR and MRR) by the individual operations is
shown in the tables in Section "Programming".
A B ,OB
ZS
D A TA B IT (1bit)
LU RR
D A TA B IT (1bit) 1 bit
D R IV E
M RR D A T A W O R D (16 bit)
ALU
D A T A W O R D (16 bit)
AUXMRR
4 D IG IT
A R IT H M E T IC E R R O R FL A G
(S pec ia l m a rk er M 40.07 )
LU = Logic-Unit
ALU = Arithmetic-Logic-Unit (activated only if drive present, RR=1)
RR = Result-Register
ZS = Intermediate memory
MRR = Multibit-Result-Register
AUXMRR = Auxiliary-Multibit-Result-Register (for arithmetic operations)
Logic operations
Operation L, LN
A network is always opened with the following operations:
Operation
L LOAD
LN LOAD NOT
Operation A, AN
The A (And) operation corresponds to the series connection of a closing contact. Using
this operation, the operand and the content of RR are subjected to an AND operation
and the result is deposited in RR.
When the A operation is used with a data register D xx.xx as the operand, RR = 1 if the
content of D = 0000.
The AN (And Not) negation corresponds to the series connection of an opening contact.
Operation O, ON
The O (Or) operation corresponds to the parallel connection of a closing contact. Using
this operation, the operand and the content of RR are subjected to an OR operation and
the result is deposited in RR.
When the O operation is used with a data register D xx.xx as the operand, RR = 1 if the
content of D = 0000.
The ON (Or Not) negation corresponds to the parallel connection of an opening contact.
Operation =, =N
The = (Then) operation has the effect of assigning a logical conclusion to an operand
(e.g. an output). The result deposited in RR is transferred to the output.
The =N (Then Not) negation corresponds to the assignment of an inverse logical result.
(Output = 1 if RR = 0).
The assignment = is always dependent on the current result of the logic operation.
Program example:
Ladder diagram: Function block diagram:
I 00.00
I 00.01
I 00.00 I 00.01 I 00.02 I 00.02
≥1
I 00.03
I 00.03
&
I 00.04
I 00.04 &
O 01.00 O 01.00
Program:
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 O I 00.01 Or input
0002 O I 00.02 Or input
0003 A I 00.03 And input
0004 A I 00.04 And input
0005 = O 01.00 Then output
0006 EP End of program
Operation AB
The AB (And Block) operation serves to simplify programming by replacing the need
for brackets.
The operation AB links the contents of RR with that of ZS. The result of the operation
is deposited in RR.
AB operations are used without operands. (Implicit)
Operation OB
The OB (Or Block) function serves to simplify programming by replacing brackets.
The operation OB links the contents of RR with that of ZS. The result of the operation
is deposited in RR.
The OB operation is used without operands. (Implicit)
Example:
Ladder diagram: Instruction list LI (Program):
L I 00.00 If input
I 00.00 I 00.02 A I 00.01 And input
L I 00.02 If input
I 00.01 I 00.03 A I 00.03 And input
OB Or Block
O 01.00 = O 01.00 Then output
EP End of program
R esult
1
I 0 0.00 L I 00 .00 RR
I 0 0.00
I 0 0.01
2
I 0 0.01 R R A I 0 0.0 1 RR
4
I 0 0.02 L I 00 .02 RR ZS
I 0 0.02
I 0 0.03 5
I 0 0.03 R R A I 0 0.0 3 RR
OB
6
RR
Programm
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 O I 00.02 Or input
0002 L I 00.01 If input
0003 O I 00.03 Or input
0004 AB And Block (Implicit)
0005 = O 01.03 Then output
0006 EP End of program
Programm
Line No. Operation Operand Remark
0000 L I 00.04 If input
0001 A I 00.05 And input
0002 L I 00.06 If input
0003 A I 00.07 And input
0004 OB Oder Block
0005 = O 01.07 Then output
0006 EP End of program
Function diagram:
Input signal
O utput sign al
Program
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 TRG M 16.00 Trigger auxiliary marker
0002 XO O 01.05 Unequal output
0003 = O 01.05 Then output
0004 EP End of program
Operation S, R
If the result of an operation is logic 1 (RR = 1), the operand (such as an output) is set to
logic 1 by the operation S (SET) or it is reset to logic 0 by the operation R (RESET).
The combination of the S and R operations corresponds to a flip-flop (latch).
In view of the sequential program execution, the dominant operation of the two (S or R)
is always that which occurred as the last in the program sequence.
In contrast to the = operation, the operand remains set after an S operation until the right
conditions occur for an R operation.
Program example
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 S O 01.00 Set output O 01.00
0002 L I 00.01 If input I 00.01
0003 R O 01.00 Reset output O 01.00
0004 EP End of program
Operation TRG
The operation TRG (TRIGGER) can be used to generate pulses. A pulse is generated
from the positive-going edge of the input signal.
The pulse is formed using an auxiliary marker (M xx.xx) or an output (O xx.xx).
The length of the pulse corresponds to one program cycle (not just to the EP).
Auxiliary marker
Output (pulse)
tc tc: Cycle time
Auxiliary marker
Output (pulse)
tc: cycle time tc
Word operations
Besides logic operations (bit-operations), the SELECONTROL® programming
technique also supports digit, byte and word operations.
Write operations
STW STORE WORD Write Word
STB STORE BYTE Write byte
STD STORE DIGIT Write digit
The inputs, outputs and markers can be accessed bit, digit, byte, or word-wise, thus:
Every individual bit is accessed in bit-operations. Bit-operations are used for logic
processing.
Examples:
Instruction Access
L I 00.01 Load (bit) I 00.01 (bit 1)
A M 17.09 And (bit) M 17.09 (bit 9)
1 digit (= 4 bits) is always accessed with digit-operations. The sub-divisions are fixed,
i.e. it is not possible to process the bits 02 ... 05 simultaneously with a digit-operation.
Examples:
Instruction Access
FTD I 03.04 Read digit I 03.04 (bit 04 ... 07)
STD O 01.12 Write digit O 01.12 (bit 12 ... 15)
1 byte (= 8 bits) is always accessed with byte-operations. The sub-divisions are fixed,
i.e. it is not possible to process the bits 04 ... 12 simultaneously with a byte-operation.
Examples:
Instructions Access
FTB I 00.08 Read byte I 00.08 (bit 08 ... 15)
STB O 01.00 Write byte O 01.00 (bit 00 ... 07)
Examples:
Instruction Access
FTW O 01.00 Read Word O 01.00 (bit 00 ... 15)
STW M 16.00 Write Word M 16.00 (bit 00 ... 15)
Examples:
Instruction Access
FTB D 00.00 Load data register D 00.00 (byte 00)
FTB D 15.56 Load data register D 15.56 (byte 56)
Examples:
Instruction Access
FTW D 15.62 Load data register D 15.62 (byte 62+63)
FTW D 10.04 Load data register D 10.04 (byte 04+05)
Program example
The data-word at input module 00 is to be read when I 00.00 is active (RR = 1). The
binary data word is to be sent to the output module 01.
Note: If the special marker M 40.00 (logic 1) is used as the drive, word operations
will be carried out continuously because RR will always = 1.
Program
Line No. Operation Operand Remark
0000 L M 40.00 If marker is logical 1
0001 FTB I 00.08 Read byte from module 00
0002 STB O 01.00 Write byte to module 01
0003 EP End of program
Example:
MRR before:
1 1 0 0 0 0 1 1 1 0 1 0 1 1 1 1
D or K as operand
1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 0
MRR after:
1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 Operation AW
1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 Operation OW
0 1 1 0 0 1 1 0 0 1 0 1 1 1 1 1 Operation XOW
The logic operations are performed between the individual corresponding bits and the
final result is placed in the multi-bit result register (MRR).
Uses
• Masking
(comparisons, masking and checking of bit patterns)
• Auxiliary arithmetic operations
• Supervision of input variables
(digital 16-bit values via digital or analog input modules)
• Clearing the multi-bit result register, MRR (AW K 00000)
Program example
The statuses at inputs I 00.00 ... I 00.07 have to be compared with the statuses at inputs
I 00.08 ... I 00.15.
Any differences should activate the appropriate output O 01.00 ... O 01.07.
Program
Line No. Operation Operand Remark
0000 L M 40.00 If marker = logical 1
0001 FTB I 00.00 Read byte from module 00.00
0002 STB D 15.60 Write to data register
0003 FTB I 00.08 Read byte from module 00.08
(MRR before)
0004 XOW D 15.60 EXOR (difference)
0005 STB O 01.00 Write byte to module 01
(MRR after)
0006 EP End of program
Counters
Operations
Instruction
CU COUNT UP
CD COUNT DOWN
The data register contains the current counter content. The data register, and therefore
the content of the corresponding counter, can be altered in the RUN mode with the
MODIFY command.
RR is set to 1 if a data register overflows during a CU operation (transition from 9999 -
> 0000). Because of this, the counters can be readily cascaded to form an arbitrarily
long chain.
Program example
Down-counter with preset input and output comparison at the value 0000.
Comparison operations
Instruction
LT LESS THAN
LTE LESS THAN OR EQUAL
EQ EQUAL
GT GREATER THAN
GTE GREATER THAN OR EQUAL
The LT/LTE operations examine the value in the multi-bit result register to see whether
it is less than (less than or equal to) the value of a constant or a data register.
The EQ operation examines the value in the multi-bit result register to see whether it is
the same as the value of a constant or a data register.
The GT/GTE operations examine the value in the multi-bit result register to see
whether it is greater than (greater than or equal to) the value of a constant or a data
register.
The comparison operations are only executed if RR = 1.
The special marker M 40.00 (logic 1) sets RR = 1 so that the comparison can be carried
out continuously.
If the conditions for the comparison are fulfilled, RR is set to 1, if not, RR is set to 0.
Besides comparisons of BCD values, it is also possible to compare hex values.
Program example
The output O 01.00 has to be set if the counter status D 15.60 reaches or exceeds the
value 5.
Program
Line No. Operation Operand Remark
0000 L I 00.00 If counter input
0001 CU D 15.60 Count upwards data
register
0002 L M 40.00 If marker = logical 1
0003 FTW D 15.60 Read data register
0004 GTE K 00005 Compare whether
content
of D 15.60 > 5
0005 = O 01.00 Then output
0006 EP End of program
11.08.93, 396.0432 System manual, page 6.31
Comparison operations Programming technique
The EQ (EQUAL) operation can be cascaded to compare values that are greater than 4-
bits wide. If the first comparison condition is fulfilled (RR = 1), then the second
comparison is also carried out. The output is set to active if both sets of conditions are
fulfilled.
Program example
Output O 01.00 has to be activated when the data registers contain the BCD value of
53,974,298.
Program
Line No. Operation Operand Remark
0000 L M 40.00 If marker = logical 1
0001 FTW D 15.60 Read data register
0002 EQ K 04298 Examine whether
content
of D 15.60 = 4298
0003 FTW D 15.62 Read data register
0004 EQ K 05397 Examine whether
content
of D 15.62 = 5397
0005 = O 01.00 Then output
0006 (EP)
Check program
Line No. Operation Operand Remark
0006 L I 00.00 If input
0007 FTW K 05397 Read constant
0008 STW D 15.62 Write in data
register
0009 L I 00.01 If input
0010 FTW K 04305 Read constant
0011 STW D 15.60 Write in data
register
0012 L I 00.03 If input
0013 CD D 15.60 Count down
0014 L I 00.04 If input
0015 CU D 15.60 Count up
0016 EP End of program
Arithmetic
The SELECONTROL® programming technique is capable of performing the four basic
mathematical operations with 4-digit operands:
Instruction
ADD Addition
SUB Subtraction
MUL Multiplication
DIV Division
A constant (K kkkkk) or a data register (D nn.nn) serves as the operand. All the
operations refer to the integer value in the first quadrant (whole positive values).
The arithmetic operations are only executed if RR = 1.
As long RR = 1, the arithmetic operations will be carried out during every program
cycle.
For this reason, the TRG (TRIGGER) operation is used in the following program
example.
The special marker, M 40.09 (carry/borrow), is set if the result of an addition is greater
than 9999 or the result of a subtraction is less than 0000. This special marker retains its
status until the next mathematical operation is performed.
Addition and subtraction are performed with arbitrary values. Any carry or borrow sets
the special marker M 40.09.
The value 38 is deposited in data register D 15.60 after the program has been executed.
The remainder (54) is deposited in data register D 15.56.
If the two figures in a division operation are not divisible, the remainder is placed in the
AUX-MRR.
Digital timers
Operations
Instruction
TF TIMER FAST (0,1s clock)
TS TIMER SLOW (1,0s clock)
Output
I 00.01 O 01.01
Output
D 15.62
Digital timers can also be formed by using special markers (time rate) together with
counters:
Special marker M 40.02 (0,1s rate)
Special marker M 40.03 (1,0s rate)
Special marker M 40.04 (0,01s rate)
The time delay can be interrupted by interrupting the input signal (I 00.00).
Uses:
• Data manipulations of all kinds,
(e.g. multiplication or division of values by 10, 100 or 1000)
• Formatting the contents of registers
• Operations with masks
(in conjunction with AW (AND WORD) and OW (OR WORD))
Digit in MRR
4 7 8 3 Status of MRR before an SFL operation
Program example
The content of data register D 15.60 is to be shifted by two places to the left and the
result stored in register D 15.56.
Digit in MRR
4 7 8 3 Status of MRR before an SFR operation
The most or least significant digit is lost after each SFL or SFR operation respectively!
Digit in MRR
4 7 8 3 Status of MRR before an RTL
Program example
The contents of data register D 15.60 have to be rotated by 1 position to the left and the
result stored in register S 15.56.
D ig it in M R R
4 7 8 3 S ta tu s of M R R be fo re a n R T R
3 4 7 8 S ta tus o f M R R after a n R T R
The operations BSU and BSD shift a data block of 64 bytes (32 words) by one word
unit (i.e. by 2 bytes or 16 bits).
The effect of these operations is to move the contents of the MRR into the first word of
the defined block while the last word of the defined block is transferred to the MRR or
vice-versa.
The operations only operate on data register blocks and are only executed if RR = 1.
BSU (Block-shift-up)
D 0 9.63 D 09.62
D 0 9.61 D 09.60
B S U D 09.00
D 0 9.03 D 09.02
D 0 9.01 D 09.00
M ulti-bit-result
M RR
register
The operations can be cascaded so that whole block groups can be shifted.
D 1 5.63 D 15.62
D 1 5.01 D 1 5.00
B S U D 14.00
B S U D 15.00
D 14.63 D 14.62
D 14.01 D 14.00
M RR
Uses:
Setting up FIFO data register blocks (First In/First Out) for the chronological-sequential
storage or output of data.
Typical applications
• Cyclic processing of incoming external data.
(binary or hexadecimal as well as BCD values)
• Chronological storage of addresses in sorting tasks.
Program example
The value 3579 has to be continuously shifted through the data register block
D 15.00 ... D 15.62, at a 1-second clock rate (i.e. a round-shift) :
BSD (Block-shift-down)
The BSD operation has the effect of shifting the data register block downwards i.e. in
the direction of decreasing line-number values.
D 1 0.63 D 10.62
D 1 0.61 D 10.60
B S D D 10.00
D 1 0.03 D 10.02
D 1 0.01 D 10.00
M RR
BR (Block Reset)
This operation sets all the values in the defined data register block to 0000. It is only
executed if RR = 1.
Effect:
All the data registers in the block from D 15.00 to D 15.63 will be reset to 0000.
The commands enable any block from a D or R register to be copied to any other D or
R register.
The command is not executed if RR = 0 or the command is jumped over by a jump
command.
The following diagram shows how the command works:
63 63
nn
M DD
M DR
bb M RD
M RR
copy
yy
00 00
D (R ) aa D (R ) xx
An arithmetic error flag is set and the command is not executed if any of these
parameters is a pseudotetrade (A ... F) or is not within the given range.
This flag is also set if the sum of (bb+nn) or (yy+nn) exceeds 64.
Since all the parameters are defined during the running period (RUN-mode), the values
can therefore also be calculated. The blocks are hence addressed in an indirect way (-->
very high flexibility).
Program example
A 1-byte block has to be copied when the input I 00.00 is activated.
Source address is the value from constant K 01556 (Register D 15.56)
Destination address is the value from constant K 01560 (Register D 15.60)
The command MDD is to be used since the source and destination addresses define the
D-register.
Program check
In the RUN-mode, preset the data register D 15.56 to the constant K 98.
Instruction: M) D 1556 K 98
Program example
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 O I 00.01 Or input
0002 A S 05.00 And SZ 05 to step 00
0003 S S 05.01 Set SZ 05 to step 01
0004 L I 00.05 If input
0005 A S 05.01 And SZ 05 to step 01
0006 S S 05.99 Set SZ 05 to step 99
0007 EP End of program
Program example
The content of the step counter for sequence 07 is to be read and the value obtained is to
be written into data register D 15.60.
Example 1:
Line No. Operation Operand Remark
0000 L M 40.00 Special marker logical 1
0001 FTB S 07.00 Read step counter 07
0002 STB D 15.60 Write data register
0003 EP
Example 2:
The step counter is set to the value that is contained by the data register 15.56.
The operations INC and DEC increase and decrease the step counter content by 1
respectively.
Program example:
The display shows the steps 0 ... 10 at 1s intervals.
Line No. Operation Operand Remark
0000 L M 40.03 If clock = 1.0s
0001 TRG M 16.00 Trigger auxiliary marker
0002 INC S 07.00 Increments SC 07
0003 L S 07.11 If SC 07 is at step 11
0004 S S 07.00 Set SC 07 to step 00
0005 EP End of program
I 00 .0 4
Cylinder 1
I 00 .0 1 I 00 .0 2
I 00 .0 3
O 01 .0 0
Cylinder 2
I 00 .0 0
O 0 1 .0 1
Start
Path-time diagram
I 00 .0 0
I 00 .0 1
I 00 .0 3 I 0 0 .0 2 I 0 0 .0 4 5 se c I 00 .0 3 I 0 0 .0 1
O 0 1 .0 0
t
O 0 1 .0 1
Code-conversion operations
Instruction Remark
BID Binary into BCD
DEB Decimal into Binary
These operations operate on the multi-bit result register MRR and are only executed if
RR = 1.
The value read from the MRR is put back into the MRR after being converted.
MRR before
0 0 0 1 1 0 0 1 0 1 1 0 1 1 1 1 MRR
BID
MRR after
0 1 1 0 0 1 0 1 0 0 0 1 0 0 0 1 MRR
Uses:
BID: Conversion of binary values (for example, from analog input modules) into
decimal values for further processing with arithmetic functions.
DEB: Conversion of decimal values into binary values for output purposes (for
example, via output modules) or to binary-based peripherals.
Program examples:
Conversion from binary into decimal form
Line No. Operation Operand Remark
0000 L M 40.00 If special marker = logical 1
0001 FTB I 00.00 Read input module 00.00
0002 BID Convert binary into digital
0003 STB D 15.60 Display (decimal)
0004 STB O 01.00 Output decimal
0005 EP End of program
Note: The special marker, M 40.07 (arithmetic error), is set if the decimal
equivalent exceeds the value of 9999 as a result of a code changing operation.
Table-Look-Up operation
The LKP operation provides a simple and fast means of accessing a table having 256
freely assignable places for 2-digit values.
The operation is executed if RR = 1
Table
MRR before LKP
n n 2 1
Table addresses nn nn nn nn
20 ... 27
nn 75 nn nn
n n 7 5
MRR after LKP
The table addresses (e.g. such as 21 in the above example) can originate from data
registers, step counters or input modules.
Example:
FTB S 12.00 The current step in step counter number 12 supplies the address
for the table.
Instruction
T) XX.nn
Table
00 ... 07 nn nn nn nn
08 ... 0F nn nn nn nn
10 ... 17 nn nn nn nn
Table- address 1A 18 ... 1F nn nn 43 nn
20 ... 27 nn nn nn nn
Program example
Table-Values:
9
8
7
6
5
4
3
2
1
0 Counter values
0 1 2 3 4 5 6 7 8 9 10 Register D 15.60
Task:
'Follow' the shape shown above at 1 second intervals, using a step counter and with the
aid of the look-up table.
Display: Counter via reg. D 15.60, table-value via reg. D 15.56.
Solution:
Data register D 15.60 is incremented by 1 up to a content of 9 at 1s intervals. The
values in data register D 15.60 represent the addresses in the table where the
corresponding values 0, 1, 3, 6, 8 and 9 are stored.
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 A M 40.03 And marker rate 1s
0002 CU D 15.60 Count upwards
0003 L M 40.00 Drive (RR = 1)
0004 FTW D 15.60 Load data register
0005 GT K 00009 Compare whether content
of D 15.60 is greater than 9
0006 R D 15.60 Reset D-register
0007 L I 00.00 If input
0008 FTW D 15.60 Read data register
0009 DEB Code conversion
0010 LKP Read the Look-Up-Table
0011 STW D 15.56 Display table value
0012 EP End of program
Indirect addressing
Instruction Remark
FIR D nn.mm Fetch Indirect R-Register
FID D nn.mm Fetch Indirect D-Register
SIR D nn.mm Store Indirect R-Register
SID D nn.mm Store Indirect D-Register
The data register D nn.mm is used as a pointer. The content of the D-register is
therefore the address.
The command is only executed if RR = 1.
Indirect fetch and store instructions are always word-orientated. The pointer works in a
word-orientated way, too (16-bit address).
The diagrams below explain the functions of these instructions:
Data output
Data output via the RS 232 interface
The SELECONTROL® programming technique supports the output of data via the
RS 232C (V24) interface under software control.
Instruction: Remark:
SOH Serial out hex Output in hexadecimal form
SOD Serial out digit Output as ASCII characters
Data is written to the output buffer (FIFO) from the multi-bit result register (MRR) with
the operations SOH and SOD.
The output buffer can store a maximum of 256 characters.
One character is automatically transferred to the interface after each program cycle in
the I/O phase.
The commands are only executed if RR = 1.
Program example
The character "A" should be presented on a display.
The ASCII table quotes a hex value of 41 for the character "A".
See ASCII table in appendix.
Program example
The contents of the data register D 15.60 should be output to an ASCII terminal every
second.
Since the display is written from left to right, the most significant digit has to be output
first.
Jump operations
This possibilities of the SELECONTROL® programming technique enables freely
programmable PMC sequential routines to be prepared with arbitrary jumps backwards
and forwards.
The jump operations which follow are additional aids to program construction which
make it possible to skip parts of the program.
Instruction Remark
JP Jump unconditionally
JCT Jump conditionally on true
JCF Jump conditionally on false
LB LABEL (jump destination)
JS Jump to sub-routine
RET Return (from jump address)
The jump operations affect the cycle time; lengthening or shortening it as the case
might be.
Example:
Line No. Operation Operand Remark
xxxx JCT K 000kk Jump to label LB K 000kk
(if condition is fulfilled)
Skipped program part
yyyy LB K 000kk Jump address label LB K 000kk
Unconditional jump
Instruction Remark
JP Unconditional jump
This jump is made, irrespective of the result of the preceding logic operation, to a jump
address given by a label (LB) in the program.
Example:
Line No. Operation Operand Remark
xxxx JP K 000kk Jump to label LB K 000kk
---- -- - -----
---- -- - ----- Skipped program part
---- -- - -----
yyyy LB K 000kk Jump address label LB K 000kk
Program example:
A subsequent part of the program has to be skipped if the input I 00.00 has been
activated.
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 JCT K 00027 Jump program part till label 27
0002 L M 40.03 If clock 1.0 sec.
0003 CU D 15.56 Count up
0004 L I 00.00 If input
0005 = O 01.00 Then output
0006 LB K 00027 Label (jump mark) 27
0007 EP End of program
Logic operations in the jumped part of the program are executed and RR is changed.
Multi-bit operations are not executed and neither are the instructions =, =N, S, STW,
STB, STD, etc.
Only forward jumps can be made with the JP, JCT and JCF commands. Backward
jumps would conflict with the scanner principle. If the jump destination (label) is not
given at all, or is not given before the jump instruction, the following part of the
program up to the EP will be jumped.
Nesting and over-lapping of jumps as well as common jump destinations (label LB) are
generally permissible for various jumps.
Jump to a sub-routine
Instruction: Remark
JS Jump to a sub-routine
Example:
Line No. Operation Remark
The sub-routine can be called any number of times. The cycle time will, however, be
extended.
Time-critical processes can be controlled by means of the sub- routine command. The
sub-routine acts as a fast scanner within the main scanner i.e. it is a short program that
can be called at the critical moment.
Program example:
Line No. Operation Operand Remark
0000 L I 00.00 If input
0001 AN M 16.00 And Not marker
0002 FTW D 15.60 Read data register
0003 ADD K 00001 Add constant
0004 STW D 15.60 Write to data register
0005 RET End of sub-routine
0006 NOP
0007 JS Jump to sub-routine
0008 NOP
0009 JS Jump to sub-routine
0010 NOP
0011 L I 00.00 If input
0012 AN M 16.00 And not marker
0013 FTW D 15.56 Read data register
0014 ADD K 00001 Add constant
0015 STW D 15.56 Write to data register
0016 S M 16.00 Set inhibiting marker
0017 EP End of program
Once the input I 00.00 has been activated the sub-routine (lines 0000 ... 0005) will be
executed three times after which the data register D 15.60 will have the value 3.
After the last part of the program (lines 0006 ... 0017) has been executed, the value in
register D 15.56 will be 1 and the inhibiting marker M 16.00 will be set.
The operations FTW, ADD and STW will not be executed in any following program
cycles.