SCHEME OF COURSE WORK

Course Title :Digital IC Applications

Course Code :13EC1108 LTPC 4103
Program: :B.Tech
Specialization: : Electronics and Communication Engineering
Semester :IV
Prerequisites : Electronic Devices, Electronic Circuits, Switching Theory and Logic Design.
Courses to which :
it is a prerequisite

Course Outcomes (Cos):

1 Gain Knowledge on different logic families.

2 Analyze CMOS steady state and dynamic electrical behavior
3 Comprehend concepts of VHDL.
4 Design and model combinational and sequential logic circuits using VHDL.
5 Discuss internal structure, Read and Write timing operations of Memories.

Course Outcomes versus Program Outcomes:

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 S M M S M
CO2 S M M M M
CO3 M S M
CO4 S M M M
CO5 M M M

S - Strongly correlated, M - Moderately correlated, Blank - No correlation

Assessment Methods: Assignment / Quiz / Seminar / Case Study / Mid-Test / End Exam
 Teaching- Assessment
Course
Week Topic /Contents Sample questions Learning Method &
Outcomes
Strategy Schedule
1 Introduction to CO1 1. Design a 4-input CMOS OR- Lecture/ Assignment
logic families, AND-INVERT gate. Explain the Design I/Quiz-I/Mid-I
CMOS logic. circuit with the help of logic diagram
and function table?
2. Design f = (A+BC)’ using CMOS
logic.
2 CMOS steady state CO2 1. Derive the expressions for rise Lecture/ Assignment
and dynamic time and fall time of a CMOS Problem I/Quiz-I/Mid-I
electrical behavior. inverter. solving
2. Analyze the fall time of CMOS
inverter output with RL = 100Ω, VL
= 2.5V and CL =100PF. Assume VL
as stable state voltage.
3 NMOS, PMOS, CO1 1. Design f = (A+BC)’ using NMOS Lecture/ Assignment
RTL, DCTL. logic. Design/ I/Quiz-I/Mid-I
2. Design & Explain the operation of Problem
2-input NAND gate using RTL. solving
4 DTL, HTL, IIL. CO1 1. Design & Explain the operation of Lecture/ Assignment
2-input NAND gate using DTL. Problem I/Quiz-I/Mid-I
2. Explain the operation of inverter solving
using IIL.
5 TTL, Schottky CO1 1. Draw the circuit diagram of basic Lecture/ Assignment
TTL, Emitter TTL NAND gate and explain the Problem I/Quiz-I/Mid-I
coupled logic, three parts with the help of solving
Comparison of functional operation.
logic families. 2. Compare CMOS, TTL and ECL
with reference to logic levels, D.C
noise margin, propagation delay and
fan-out.
6 CMOS logic CO2 1. What is interfacing? How it can be Lecture/ Assignment
families, done. Problem I/Quiz-I/Mid-I
CMOS/TTL 2. Explain about low voltage CMOS solving
interfacing, low logic and interfacing.
voltage CMOS
logic and
interfacing,
Familiarity with
standard 74xx and
CMOS 40xx series
ICs-specifications.
7 Introduction to CO3 1. Write VHDL code for prime Lecture/ Assignment
VHDL, Program number detector using conditional Discussion I/Quiz-I/Mid-I
structure, data signal assignment statement.
types and 2. List out various data types of
constants, VHDL. Explain each one with
operators, data example.
flow design
elements
8 Behavioral design CO3 1. List out various types of Lecture/ Assignment
elements, structural-flow design elements of Discussion I/Quiz-I/Mid-I
Structural design VHDL. Explain any one with
elements, functions example.
and procedures, 2. Explain with example the syntax
libraries and and the function of the following
packages, VHDL statements?
simulation and (a) Process statement
 synthesis. (b) If, else and else if statements
(c) Case statement
(d) Loop statement
9 Mid-Test-1 -- --------- ------ ----------
10 Decoders, CO4 1. Design 5 to 32 decoder using 3 to Lecture/ Assignment
encoders. 8 decoders. Design/ II/Quiz-II/Mid-II
2. Write behavioral VHDL program Programming
for a 74x148.
11 Three state devices, CO4 1. Design a 32 to 1 multiplexer using Lecture/ Assignment
Multiplexers and four 74×151 multiplexers and Design/ II/Quiz-II/Mid-II
demultiplexers. 74X139 decoder? Write a VHDL Programming
program for the Same in Structural
flow style.
2. Design a 3 input 5 bit multiplexer.
Write the truth table and draw the
logic diagram. Provide the dataflow
VHDL program of the same.
12 Code Converters, CO4 1. Design and write VHDL code for Lecture/ Assignment
Parity circuits, 3 bit binary to gray code converter. Design/ II/Quiz-II/Mid-II
comparators. 2. Design 8 bit comparator using Programming
74x85 ICs. And write structural style
VHDL code.
13 Adders & CO4 1. Design a full adder using two half Lecture/ Assignment
subtractors, Basic adders and write VHDL code for it Design/ II/Quiz-II/Mid-II
Concepts of ALUs, using structural design modeling. Programming
Combinational 2. Design a 4×4 combinational
multipliers. multiplier and write the necessary
VHDL program in data flow model.
14 Barrel shifter, CO4 1. Design a barrel shifter for 8-bit Lecture/ Assignment
floating-point using three control inputs. Write a Design/ II/Quiz-II/Mid-II
encoder, dual VHDL program for the same in data Programming
priority encoder. flow style.
2. Write VHDL code for fixed point
to floating point conversion.
15 Latches and flip- CO4 1. Write VHDL code for JK F/F. Lecture/ Assignment
flops, PLDs, 2. Write VHDL code for 4 bit shift Design/ II/Quiz-II/Mid-II
Counters, shift register. Programming
register. 3. Design 4 bit up counter and write
VHDL code.
16 ROM - Internal CO5 1. What is ROM? Explain the Lecture/ Assignment
structure, 2D- internal ROM structure with logic Discussion II/Quiz-II/Mid-II
decoding diagram of 8x4 diode ROM.
commercial types, 2. Explain the commercial ROM
timing and types.
applications.
17 Static RAM - CO5 1. Define timing parameters for Read Lecture/ Assignment
Internal structure, operations in a static RAM with Discussion II/Quiz-II/Mid-II
SRAM timing, Timing diagram.
standard SRAMS, 2. What is the difference between
synchronous SRAM and DRAM.? Explain
SRAMS, Dynamic DRAM read – cycle Timing.
RAM - Internal
structure, timing,
synchronous
DRAMs.
18 Mid-Test 2 ------ -----------
19/20 END EXAM ------ ------