Computer Architecture: CS/B.TECH (CSE-NEW) /SEM-4/CS-403/2012
Computer Architecture: CS/B.TECH (CSE-NEW) /SEM-4/CS-403/2012
CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012
2012
COMPUTER ARCHITECTURE
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The figures in the margin indicate full marks.
10 1 = 10
i) A pipeline stage
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a) is sequencial circuit
b) is combinational circuit
circuits
d) none of these.
a) Truth table
b) Excitation table
c) Reservation table
d) Periodic table.
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Scalable Processor Archite ture
t.c
b) Superscalar Processor A RISC Computer
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characteristic ?
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instructions
b) No specialized register
c) No storage/storage instruction
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CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012
a) NUMA b) UMA
c) COMA d) ccNUMA.
non-Neumann architecture ?
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a) MISD b) MIMD
c) SISD b) SIMD.
a) 1 b) 2
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c) 3 d) 4.
memory organizations ?
following architectures ?
a) VLIW processor
c) Super pipelined
d) None of these.
x)
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Which of the following is not the cause of possible data
hazard ?
t.c
a) RAR b) RAW
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c) WAR d) WAW.
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GROUP – B
( Short Answer Type Questions )
Answer any three of the following. 3 5 = 15
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statement.
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CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012
design ?
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GROUP – C
( Long Answer Type Questions )
t.c
Answer any three of the following. 3 15 = 45
that processor ?
speed-up ?
c)
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Discuss briefly two approaches to handle branch
hazards.
t.c
d) Consider a 4-stage pipeline that consists of Instruction
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2+5+4+4
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CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012
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30% and branching related instructions 20%. The
cycles consumed by these types of instructions are 2,
5, and 10 respectively. What will b the execution time
for a 4 GHz processor to execute your program ?
t.c
2+5+3+5
3+3+3+3+3
a) Vector stride
d) Cluster Computer
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t.c
bu
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