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Computer Architecture: CS/B.TECH (CSE-NEW) /SEM-4/CS-403/2012

This document contains a summary of a computer architecture exam, including: - Multiple choice and short answer questions about topics like pipeline stages, cache memory, and processor architectures. - Long answer questions asking about differences between computer organization and architecture, approaches to handle branch hazards in pipelines, and characteristics of multiprocessor systems. - Short notes questions about additional topics such as vector stride, non-von Neumann architectures, cache coherence, cluster computers, and Amdahl's law.

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Avik Mitra
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0% found this document useful (0 votes)
175 views8 pages

Computer Architecture: CS/B.TECH (CSE-NEW) /SEM-4/CS-403/2012

This document contains a summary of a computer architecture exam, including: - Multiple choice and short answer questions about topics like pipeline stages, cache memory, and processor architectures. - Long answer questions asking about differences between computer organization and architecture, approaches to handle branch hazards in pipelines, and characteristics of multiprocessor systems. - Short notes questions about additional topics such as vector stride, non-von Neumann architectures, cache coherence, cluster computers, and Amdahl's law.

Uploaded by

Avik Mitra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 8

Name : ……………………………………………………………

Roll No. : …………………………………………………………

Invigilator's Signature : ………………………………………..

CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012
2012
COMPUTER ARCHITECTURE

Time Allotted : 3 Hours Full Marks : 70

om
The figures in the margin indicate full marks.

Candidates are required to give their answers in their own words


as far as practicable
t.c
GROUP – A
bu

( Multiple Choice Type Questions )

1. Choose the correc alternatives for the following :


yw

10 1 = 10

i) A pipeline stage
m

a) is sequencial circuit

b) is combinational circuit

c) consists of both sequential and combinational

circuits

d) none of these.

4452 [ Turn over


CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012

ii) Utilization pattern of successive stages of a

synchronous pipeline can be specified by

a) Truth table

b) Excitation table

c) Reservation table

d) Periodic table.

iii) SPARC stands for

a) om
Scalable Processor Archite ture
t.c
b) Superscalar Processor A RISC Computer
bu

c) Scalable Processor A RISC Computer

d) Scalable Pipeline Architecture.


yw

iv) Which of the following is not RISC architecture

characteristic ?
m

a) Simplified and unified format of code of

instructions

b) No specialized register

c) No storage/storage instruction

d) Small register file.

4452 2
CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012

v) The time to access shared memory is same in which of

the following shared momory multiprocessor models ?

a) NUMA b) UMA

c) COMA d) ccNUMA.

vi) Which of the following architectures corresponds to

non-Neumann architecture ?

om
a) MISD b) MIMD

c) SISD b) SIMD.

vii) In absence of TLB, to access a physical memory


t.c
location in a paged-memory system how many memory

accesses are required ?


bu

a) 1 b) 2
yw

c) 3 d) 4.

viii) A direct mapped cache memory with n blocks is


m

nothing but which of the following set associative cache

memory organizations ?

a) 0-way set associative

b) 1-way set associative

c) 2-way set associative

d) n-way set associative.

4452 3 [ Turn over


CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012

ix) Portability is definitely an issue for which of the

following architectures ?

a) VLIW processor

b) Super Scalar processor

c) Super pipelined

d) None of these.

x)

om
Which of the following is not the cause of possible data

hazard ?
t.c
a) RAR b) RAW
bu

c) WAR d) WAW.
yw

GROUP – B
( Short Answer Type Questions )
Answer any three of the following. 3 5 = 15
m

2. “Instruction execution throughput increases in proportion

with the number of pipeline stages.” Is it true ? Justify your

statement.

3. What are multiprocessor, multi-computer and multi-core

systems ? Compare CISC and RISC computer architectures.

4452 4
CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012

4. Describe Flynn’s classification of computer architecture.

5. How is a block chosen for replacement in set-associative

cache to resolve a cache miss ?

6. How does principle of locality help in memory hierarchy

design ?

om
GROUP – C
( Long Answer Type Questions )
t.c
Answer any three of the following. 3 15 = 45

7. a) What is the difference between Computer Organization


bu

and Computer Ar hitecture ?


yw

b) Why does the equation to calculate the CPU-time of a

program often expressed in terms of average CPI of


m

that processor ?

c) A 30% enhancement in speedup for a component of the

processor has been proposed for a new architecture. If

the enhancement is usable only for 50% for the time,

what is fraction of the time must enhancement be used

to achieve an overall speedup of 10 ?

4452 5 [ Turn over


CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012

d) What are the different approaches taken by pipeline

processor to handle branch instructions ? Briefly

illustrate any two approaches. 3+2+5+5

8. a) What are the major hurdles to achieve this ideal

speed-up ?

b) Discuss data hazard briefly.

c)
om
Discuss briefly two approaches to handle branch

hazards.
t.c
d) Consider a 4-stage pipeline that consists of Instruction
bu

Fetch (IF), Instruction Decode (ID), Execute ( Ex ) and

Write Back WB stages. The times taken by these


yw

stages ar 50 ns, 60 ns, 110 ns and 80 ns

respectively. The pipeline registers are required after


m

every pipeline stage, and each of these pipeline register

consumes 10 ns delay. What is the speedup of the

pipeline under ideal conditions compare to the

corresponding non-pipelined implementation ?

2+5+4+4

4452 6
CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012

9. a) What do you mean by multiple issue processor ?

b) Briefly describe the VLIW processor architecture.

c) What are the differences between superscalar


processor and V.L.I.W processor ?

d) Suppose your program consists of 2500 instructions.


The proportion of different kinds of instructions in the
program is as follow :

Data transfer instruction 50%, arithmetic instruction

om
30% and branching related instructions 20%. The
cycles consumed by these types of instructions are 2,
5, and 10 respectively. What will b the execution time
for a 4 GHz processor to execute your program ?
t.c
2+5+3+5

10. a) Discuss briefly MIMD architecture.


bu

b) What is the significance of interconnection network in


multiprocessor architecture ?
yw

c) An 8 kB 4-way set associative write back cache is


organized as multiple blocks, each of 32-byte size.
Assume that the processor generates 36 bits
m

addresses. Calculate the total size of memory required


by cache controller to store the tags for cache ?

d) What are the approaches to improve miss penalty ?

e) A CPU generates 32-bit virtual addresses. The page


size is 4 kB. The processor has a TLB which can hold a
total of 256 page table entries. The TLB is 8-way set
associative. Calculate the TLB tage size.

3+3+3+3+3

4452 7 [ Turn over


CS/B.TECH (CSE-NEW)/SEM-4/CS-403/2012

11. Write short notes on any three of the following : 3 5

a) Vector stride

b) Non von Neumann architecture characteristics

c) Cache coherence problem and its solution

d) Cluster Computer

e) Amdahl’s law and its significance.

om
t.c
bu
yw
m

4452 8

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