Name: Pritam Panigrahi

Section: A, Roll No: 55, Subject: VLSI Design Lab (EC792)

Full Adder
Source Code (Dataflow):

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b,c: in std_logic;
sum,carry: out std_logic);
end full_adder;
architecture dataflow of full_adder is
begin
sum <= (a xor b) xor c;
carry <= (a and b) or (b and c) or (c and a);
end dataflow;

Source Code (Behavioral):

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b,c: in std_logic;
sum,carry: out std_logic);
end entity;
architecture behavioral of full_adder is
begin
process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
sum <= '0'; carry <= '0';
elsif(a='0' and b='0' and c='1')then
sum <= '1'; carry <= '0';
elsif(a='0' and b='1' and c='0')then
sum <= '1'; carry <= '0';
elsif(a='0' and b='1' and c='1')then
sum <= '0'; carry <= '1';
elsif(a='1' and b='0' and c='0')then
sum <= '1'; carry <= '0';
elsif(a='1' and b='0' and c='1')then
sum <= '0'; carry <= '1';

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elsif(a='1' and b='1' and c='0')then
sum <= '0'; carry <= '1';
else
sum <= '1'; carry <= '1';
end if;
end process;
end behavioral;

Source Code (Structural):

library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(p,q: in std_logic;
r,s: out std_logic);
end entity;
architecture dataflow of half_adder is
begin
r <= p xor q;
s <= p and q;
end dataflow;

library ieee;
use ieee.std_logic_1164.all;
entity or_gate is
port(x,y: in std_logic;
z: out std_logic);
end entity;
architecture dataflow of or_gate is
begin
z <= x or y;
end dataflow;

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b,c: in std_logic;
sum,carry: out std_logic);
end entity;
architecture structural of full_adder is
component half_adder is
port(p,q: in std_logic;
r,s: out std_logic);
end component;
component or_gate is
port(x,y: in std_logic;
z: out std_logic);

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end component;
signal s0,s1,s2: std_logic;
begin
u1: half_adder port map(p=>a,q=>b,r=>s0,s=>s1);
u2: half_adder port map(p=>s0,q=>c,r=>sum,s=>s2);
u3: or_gate port map(x=>s2,y=>s1,z=>carry);
end structural;

Test bench:

library ieee;
use ieee.std_logic_1164.all;
entity full_adder_tb is
end entity;
architecture tb of full_adder_tb is
component full_adder is
port(a,b,c: in std_logic;
sum,carry: out std_logic);
end component;
signal a,b,c,sum,carry: std_logic;
begin
uut: full_adder port map(a=>a,b=>b,c=>c,sum=>sum,carry=>carry);
stim: process
begin
a <= '0'; b <= '0'; c <= '0'; wait for 10 ns;
a <= '0'; b <= '0'; c <= '1'; wait for 10 ns;
a <= '0'; b <= '1'; c <= '0'; wait for 10 ns;
a <= '0'; b <= '1'; c <= '1'; wait for 10 ns;
a <= '1'; b <= '0'; c <= '0'; wait for 10 ns;
a <= '1'; b <= '0'; c <= '1'; wait for 10 ns;
a <= '1'; b <= '1'; c <= '0'; wait for 10 ns;
a <= '1'; b <= '1'; c <= '1'; wait;
end process;
end tb;

Output:

JK Flip-flop
Source Code:

library ieee;

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use ieee.std_logic_1164.all;
entity jk_ff is
port(j,k,clk,rst: in std_logic;
q,qbar: out std_logic);
end jk_ff;
architecture behavioral of jk_ff is
begin
process(clk,rst)
variable qn: std_logic;
begin
if(rst='1')then
qn := '0';
elsif(clk'event and clk='1')then
if(j='0' and k='0')then
qn := qn;
elsif(j='0' and k='1')then
qn := '0';
elsif(j='1' and k='0')then
qn := '1';
elsif(j='1' and k='1')then
qn := not qn;
else
null;
end if;
else
null;
end if;
q <= qn;
qbar <= not qn;
end process;
end behavioral;

Test bench:

library ieee;
use ieee.std_logic_1164.all;
entity jk_ff_tb is
end entity;
architecture tb of jk_ff_tb is
component jk_ff is
port(j,k,clk,rst: in std_logic;
q,qbar: out std_logic);
end component;

signal j,k,clk,rst: std_logic;

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uut: jk_ff port map(j=>j,k=>k,clk=>clk,rst=>rst,q=>q,qbar=>qbar);
clock: process
begin
clk <= '1'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
end process;
stim: process
begin
j <= '0'; k <= '0'; rst <= '0'; wait for 20 ns;
j <= '0'; k <= '0'; rst <= '1'; wait for 20 ns;
j <= '0'; k <= '1'; rst <= '0'; wait for 20 ns;
j <= '0'; k <= '1'; rst <= '1'; wait for 20 ns;
j <= '1'; k <= '0'; rst <= '0'; wait for 20 ns;
j <= '1'; k <= '0'; rst <= '1'; wait for 20 ns;
j <= '1'; k <= '1'; rst <= '0'; wait for 20 ns;
j <= '1'; k <= '1'; rst <= '1'; wait for 20 ns;
end process;
end tb;

Output:

Synchronous Up Counter
Source Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity up_counter is
port(clk,rst: in std_logic;
count: inout std_logic_vector(3 downto 0));
end entity;
architecture behavioral of up_counter is
begin
process(clk,rst)
begin
if(rst='1')then
count <= "0000";
elsif(rising_edge(clk))then
count <= count + 1;
end if;

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end process;
end behavioral;

Test bench:

library ieee;
use ieee.std_logic_1164.all;
entity up_counter_tb is
end entity;
architecture tb of up_counter_tb is
component up_counter is
port(clk,rst: in std_logic;
count: inout std_logic_vector(3 downto 0));
end component;
signal clk,rst: std_logic := '1';
signal count: std_logic_vector(3 downto 0);
begin
uut: up_counter port map(clk=>clk,rst=>rst,count=>count);
clock: process
begin
rst <= '0';
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
end tb;

Output:

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