Cop8Cbr9/Cop8Ccr9/Cop8Cdr9 8-Bit CMOS Flash Microcontroller With 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout

Virtual EEPROM, 10-Bit A/D and Brownout
COP8CBR9/COP8CCR9/COP8CDR9 8-Bit CMOS Flash Based Microcontroller with 32k Memory,

August 2003
COP8CBR9/COP8CCR9/COP8CDR9
8-Bit CMOS Flash Microcontroller with 32k Memory,
1.0 General Description tions requiring a full featured, in-system reprogrammable
controller with large memory and low EMI. The same device
The COP8CBR/CCR/CDR9 Flash microcontrollers are is used for development, pre-production and volume produc-
highly integrated COP8™ Feature core devices, with 32k tion with a range of COP8 software and hardware develop-
Flash memory and advanced features including Virtual EE- ment tools.
PROM, A/D, High Speed Timers, USART, and Brownout
Reset. This single-chip CMOS device is suited for applica-
Device included in this datasheet:
Flash Program
RAM Brownout I/O
Device Memory Packages Temperature
(bytes) Voltage Pins
(bytes)
44 LLP,
37,39,49,
COP8CBR9 32k 1k 2.7V to 2.9V 44/68 PLCC, −40˚C to +85˚C
59
48/56 TSSOP
44 LLP,
37,39,49, −40˚C to +85˚C
COP8CCR9 32k 1k 4.17V to 4.5V 44/68 PLCC,
59 −40˚C to +125˚C
48/56 TSSOP
44 LLP,
37,39,49, −40˚C to +85˚C
COP8CDR9 32k 1k No Brownout 44/68 PLCC,
59 −40˚C to +125˚C
48/56 TSSOP
2.0 Features n MICROWIRE/PLUS (Serial Peripheral Interface

Compatible)
KEY FEATURES n Clock Doubler for 20 MHz operation from 10 MHz
n 32 kbytes Flash Program Memory with Security Feature Oscillator, with 0.5 µs Instruction Cycle
n Virtual EEPROM using Flash Program Memory n Thirteen multi-source vectored interrupts servicing:
n 1 kbyte volatile RAM — External Interrupt
n 10-bit Successive Approximation Analog to Digital — USART (2)
Converter (up to 16 channels) — Idle Timer T0
n 100% Precise Analog Emulation — Three Timers (each with 2 interrupts)
n USART with onchip baud generator — MICROWIRE/PLUS Serial peripheral interface
n 2.7V – 5.5V In-System Programmability of Flash — Multi-Input Wake-up
— Software Trap
n High endurance -100k Read/Write Cycles
n Idle Timer with programmable interrupt interval
n Superior Data Retention - 100 years
n 8-bit Stack Pointer SP (stack in RAM)
n Dual Clock Operation with HALT/IDLE Power Save
Modes n Two 8-bit Register Indirect Data Memory Pointers
n Three 16-bit timers: n True bit manipulation
— Timers T2 and T3 can operate at high speed (50 ns n WATCHDOG and Clock Monitor logic
resolution) n Software selectable I/O options
— Processor Independent PWM mode — TRI-STATE ® Output/High Impedance Input
— External Event counter mode — Push-Pull Output
— Input Capture mode — Weak Pull Up Input
n Brown-out Reset (COP8CBR9/CCR9) n Schmitt trigger inputs on I/O ports
OTHER FEATURES n High Current I/Os
n Single supply operation: n Temperature range: –40˚C to +85˚C and –40˚C to
— 2.7V–5.5V (−40˚C to +85˚C) +125˚C (COP8CCR9/CDR9)
— 4.5V–5.5V (−40˚C to +125˚C) n Packaging: 44 and 68 PLCC, 44 LLP, 48 and 56 TSSOP
n Quiet Design (low radiated emissions) n True In-System, real time emulation and debug tools
n Multi-Input Wake-up with optional interrupts available
COP8™ is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS101374 www.national.com

3.0 Block Diagram
10137401
4.0 Ordering Information

Part Numbering Scheme
COP8 CB R 9 H VA 8
Family and Program Program
Package
Feature Set Memory Memory No. Of Pins Temperature
Type
Indicator Size Type
CB = Low Brownout Voltage R = 32k 9 = Flash H = 44 Pin LQ = LLP 7 = -40 to +125˚C
CC = High Brownout Voltage I = 48 Pin MT = TSSOP 8 = -40 to +85˚C
CD = No Brownout k = 56 Pin VA = PLCC
L = 68 Pin
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Table of Contents
1.0 General Description ..................................................................................................................................... 1
2.0 Features ....................................................................................................................................................... 1
3.0 Block Diagram .............................................................................................................................................. 2
4.0 Ordering Information .................................................................................................................................... 2
5.0 Connection Diagrams ................................................................................................................................... 6
6.0 Architectural Overview ............................................................................................................................... 10
6.1 EMI REDUCTION .................................................................................................................................... 10
6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...................................................................... 10
6.3 DUAL CLOCK AND CLOCK DOUBLER ................................................................................................. 10
6.4 TRUE IN-SYSTEM EMULATION ............................................................................................................ 10
6.5 ARCHITECTURE ................................................................................................................................... 10
6.6 INSTRUCTION SET ............................................................................................................................... 10
6.6.1 Key Instruction Set Features ............................................................................................................. 10
6.6.2 Single Byte/Single Cycle Code Execution ....................................................................................... 10
6.6.3 Many Single-Byte, Multi-Function Instructions .................................................................................. 10
6.6.4 Bit-Level Control ................................................................................................................................ 11
6.6.5 Register Set ....................................................................................................................................... 11
6.7 PACKAGING/PIN EFFICIENCY .............................................................................................................. 11
7.0 Absolute Maximum Ratings ....................................................................................................................... 12
8.0 Electrical Characteristics ............................................................................................................................ 12
9.0 Pin Descriptions ......................................................................................................................................... 18
9.1 EMULATION CONNECTION ................................................................................................................... 20
10.0 Functional Description .............................................................................................................................. 20
10.1 CPU REGISTERS ................................................................................................................................. 20
10.2 PROGRAM MEMORY ........................................................................................................................... 20
10.3 DATA MEMORY .................................................................................................................................... 20
10.4 DATA MEMORY SEGMENT RAM EXTENSION .................................................................................. 21
10.4.1 Virtual EEPROM .............................................................................................................................. 22
10.5 OPTION REGISTER ............................................................................................................................. 22
10.6 SECURITY ............................................................................................................................................ 23
10.7 RESET ................................................................................................................................................... 23
10.7.1 External Reset ................................................................................................................................. 24
10.7.2 On-Chip Brownout Reset ................................................................................................................. 24
10.8 OSCILLATOR CIRCUITS ...................................................................................................................... 26
10.8.1 Oscillator .......................................................................................................................................... 26
................................................................................................................................................................... 0
10.8.2 Clock Doubler .................................................................................................................................. 27
10.9 CONTROL REGISTERS ....................................................................................................................... 27
10.9.1 CNTRL Register (Address X'00EE) ................................................................................................. 27
10.9.2 PSW Register (Address X'00EF) ..................................................................................................... 27
10.9.3 ICNTRL Register (Address X'00E8) ................................................................................................ 27
10.9.4 T2CNTRL Register (Address X'00C6) ............................................................................................. 27
10.9.5 T3CNTRL Register (Address X'00B6) ............................................................................................. 27
10.9.6 HSTCR Register (Address X'00AF) ................................................................................................ 28
10.9.7 ITMR Register (Address X'00CF) .................................................................................................... 28
10.9.8 ENAD Register (Address X'00CB) .................................................................................................. 28
11.0 In-System Programming ........................................................................................................................... 28
11.1 INTRODUCTION ................................................................................................................................... 28
11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 28
11.3 REGISTERS .......................................................................................................................................... 29
11.3.1 ISP Address Registers ..................................................................................................................... 29
11.3.2 ISP Read Data Register .................................................................................................................. 29
11.3.3 ISP Write Data Register ................................................................................................................... 29
11.3.4 ISP Write Timing Register ................................................................................................................ 29
11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 30
11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 30
11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 31
11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 31
11.8 USER ISP AND VIRTUAL E2 ................................................................................................................ 32
11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM ....................... 34
11.10 FLASH MEMORY DURABILITY CONSIDERATIONS ........................................................................ 34
12.0 Timers ....................................................................................................................................................... 35
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Table of Contents (Continued)
12.1 TIMER T0 (IDLE TIMER) ...................................................................................................................... 35

12.1.1 ITMR Register .................................................................................................................................. 36
12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................ 36
12.2.1 Timer Operating Speeds .................................................................................................................. 36
12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 36
12.2.3 Mode 2. External Event Counter Mode ........................................................................................... 37
12.2.4 Mode 3. Input Capture Mode .......................................................................................................... 37
12.3 TIMER CONTROL FLAGS .................................................................................................................... 38
13.0 Power Saving Features ............................................................................................................................ 38
13.1 POWER SAVE MODE CONTROL REGISTER .................................................................................... 39
13.2 OSCILLATOR STABILIZATION ............................................................................................................. 40
13.3 HIGH SPEED MODE OPERATION ...................................................................................................... 40
13.3.1 High Speed Halt Mode .................................................................................................................... 40
13.3.1.1 Entering The High Speed Halt Mode ......................................................................................... 40
13.3.1.2 Exiting The High Speed Halt Mode ........................................................................................... 40
13.3.1.3 HALT Exit Using Reset .............................................................................................................. 40
13.3.1.4 HALT Exit Using Multi-Input Wake-up ....................................................................................... 40
13.3.1.5 Options ....................................................................................................................................... 41
13.3.2 High Speed Idle Mode ..................................................................................................................... 41
13.4 DUAL CLOCK MODE OPERATION ...................................................................................................... 42
13.4.1 Dual Clock HALT Mode ................................................................................................................... 42
13.4.1.1 Entering The Dual Clock Halt Mode .......................................................................................... 42
13.4.1.2 Exiting The Dual Clock Halt Mode ............................................................................................. 42
13.4.1.5 Options ....................................................................................................................................... 42
13.4.2 Dual Clock Idle Mode ...................................................................................................................... 42
13.5 LOW SPEED MODE OPERATION ....................................................................................................... 43
13.5.1 Low Speed HALT Mode ................................................................................................................... 43
13.5.1.1 Entering The Low Speed Halt Mode ......................................................................................... 43
13.5.1.2 Exiting The Low Speed Halt Mode ............................................................................................ 43
13.5.1.5 Options ....................................................................................................................................... 43
13.5.2 Low Speed Idle Mode ...................................................................................................................... 44
13.6 MULTI-INPUT WAKE-UP ...................................................................................................................... 45
14.0 USART ..................................................................................................................................................... 45
14.1 USART CONTROL AND STATUS REGISTERS ................................................................................... 46
14.2 DESCRIPTION OF USART REGISTER BITS ...................................................................................... 46
14.3 ASSOCIATED I/O PINS ........................................................................................................................ 47
14.4 USART OPERATION ............................................................................................................................ 48
14.4.1 Asynchronous Mode ........................................................................................................................ 48
14.4.2 Synchronous Mode .......................................................................................................................... 48
14.5 FRAMING FORMATS ............................................................................................................................ 48
14.6 USART INTERRUPTS .......................................................................................................................... 49
14.7 BAUD CLOCK GENERATION .............................................................................................................. 49
14.8 EFFECT OF HALT/IDLE ....................................................................................................................... 51
14.9 DIAGNOSTIC ........................................................................................................................................ 51
14.10 ATTENTION MODE ............................................................................................................................. 51
14.11 BREAK GENERATION ........................................................................................................................ 51
15.0 A/D Converter ........................................................................................................................................... 51
15.1 OPERATING MODES ........................................................................................................................... 52
15.1.1 A/D Control Register ........................................................................................................................ 52
15.1.1.1 Channel Select ........................................................................................................................... 52
15.1.1.2 Multiplexor Output Select ........................................................................................................... 53
15.1.1.3 Mode Select ............................................................................................................................... 54
15.1.1.4 Prescaler Select ......................................................................................................................... 54
15.1.1.5 Busy Bit ...................................................................................................................................... 54
15.1.2 A/D Result Registers ....................................................................................................................... 54
15.2 A/D OPERATION ................................................................................................................................... 55
15.2.1 Prescaler .......................................................................................................................................... 55
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Table of Contents (Continued)
15.3 ANALOG INPUT AND SOURCE RESISTANCE CONSIDERATIONS .................................................. 55

16.0 Interrupts .................................................................................................................................................. 56
16.1 INTRODUCTION ................................................................................................................................... 56
16.2 MASKABLE INTERRUPTS ................................................................................................................... 56
16.3 VIS INSTRUCTION ............................................................................................................................... 57
16.3.1 VIS Execution .................................................................................................................................. 58
16.4 NON-MASKABLE INTERRUPT ............................................................................................................ 59
16.4.1 Pending Flag .................................................................................................................................... 59
16.4.2 Software Trap .................................................................................................................................. 59
16.4.2.1 Programming Example: External Interrupt ................................................................................. 60
16.5 PORT L INTERRUPTS .......................................................................................................................... 61
16.6 INTERRUPT SUMMARY ....................................................................................................................... 61
17.0 WATCHDOG/Clock Monitor ..................................................................................................................... 61
17.1 CLOCK MONITOR ................................................................................................................................ 62
17.2 WATCHDOG/CLOCK MONITOR OPERATION .................................................................................... 62
17.3 WATCHDOG AND CLOCK MONITOR SUMMARY .............................................................................. 63
17.4 DETECTION OF ILLEGAL CONDITIONS ............................................................................................ 63
18.0 MICROWIRE/PLUS .................................................................................................................................. 63
18.1 MICROWIRE/PLUS OPERATION ......................................................................................................... 64
18.1.1 MICROWIRE/PLUS Master Mode Operation .................................................................................. 64
18.1.2 MICROWIRE/PLUS Slave Mode Operation .................................................................................... 64
18.1.2.1 Alternate SK Phase Operation and SK Idle Polarity ................................................................. 65
19.0 Memory Map ............................................................................................................................................ 66
20.0 Instruction Set .......................................................................................................................................... 67
20.1 INTRODUCTION ................................................................................................................................... 67
20.2 INSTRUCTION FEATURES .................................................................................................................. 67
20.3 ADDRESSING MODES ......................................................................................................................... 68
20.3.1 Operand Addressing Modes ............................................................................................................ 68
20.3.2 Tranfer-of-Control Addressing Modes .............................................................................................. 69
20.4 INSTRUCTION TYPES ......................................................................................................................... 69
20.4.1 Arithmetic Instructions ...................................................................................................................... 70
20.4.2 Transfer-of-Control Instructions ....................................................................................................... 70
20.4.3 Load and Exchange Instructions ..................................................................................................... 70
20.4.4 Logical Instructions .......................................................................................................................... 70
20.4.5 Accumulator Bit Manipulation Instructions ....................................................................................... 70
20.4.6 Stack Control Instructions ................................................................................................................ 70
20.4.7 Memory Bit Manipulation Instructions ............................................................................................. 70
20.4.8 Conditional Instructions ................................................................................................................... 70
20.4.9 No-Operation Instruction .................................................................................................................. 70
20.5 REGISTER AND SYMBOL DEFINITION .............................................................................................. 70
20.6 INSTRUCTION SET SUMMARY .......................................................................................................... 72
20.7 INSTRUCTION EXECUTION TIME ...................................................................................................... 73
21.0 Development Support .............................................................................................................................. 76
21.1 TOOLS ORDERING NUMBERS FOR THE COP8 FLASH FAMILY DEVICES ................................... 76
21.2 COP8 TOOLS OVERVIEW ................................................................................................................... 78
21.3 WHERE TO GET TOOLS ..................................................................................................................... 79
22.0 Revision History ....................................................................................................................................... 80
23.0 Physical Dimensions ................................................................................................................................ 83
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5.0 Connection Diagrams
10137403
Top View
Plastic Chip Package
10137402
See NS Package Number V44A
Top View
Plastic Chip Package
See NS Package Number V68A
10137455
Top View
LLP Package
See NS Package Number LQA44A
10137456
Top View
TSSOP Package
See NS Package Number MTD48
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5.0 Connection Diagrams (Continued)
10137457
Top View
TSSOP Package
See NS Package Number MTD56
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TABLE 1. Pinouts for All Packages

In System
44-Pin 48-Pin 56-Pin 68-Pin
Port Type Alt. Fun Emulation 44-Pin LLP
PLCC TSSOP TSSOP PLCC
Mode
L0 I/O MIWU or Low Speed OSC In 16 11 11 15 22
L1 I/O MIWU or CKX or Low Speed 17 12 12 16 23
OSC Out
L2 I/O MIWU or TDX 18 13 13 17 24
L3 I/O MIWU or RDX 19 14 14 18 25
L4 I/O MIWU or T2A 20 15 15 19 26
L5 I/O MIWU or T2B 21 16 16 20 27
L6 I/O MIWU or T3A 22 17 17 21 28
L7 I/O MIWU or T3B 23 18 18 22 29
G0 I/O INT Input 7 2 2 2 3
a
G1 I/O WDOUT POUT 8 3 3 3 4
G2 I/O T1B Output 9 4 4 4 5
G3 I/O T1A Clock 10 5 5 5 6
G4 I/O SO 11 6 6 6 11
G5 I/O SK 12 7 7 7 12
G6 I SI 13 8 8 8 13
G7 I CKO 14 9 9 9 14
D0 O 42 37 41 49 58
D1 O 43 38 42 50 59
D2 O 44 39 43 51 60
D3 O 1 40 44 52 61
D4 O 2 41 45 53 62
D5 O 3 42 46 54 63
D6 O 4 43 47 55 64
D7 O 5 44 48 56 65
E0 I/O 47 54
E1 I/O 48 55
E2 I/O 56
E3 I/O 57
E4 I/O 67
E5 I/O 68
E6 I/O 1
E7 I/O 2
C0 I/O 11 18
C1 I/O 12 19
C2 I/O 13 20
C3 I/O 14 21
C4 I/O 23 30
C5 I/O 24 31
C6 I/O 25 32
C7 I/O 26 33
A0 I/O ADCH0 33 39 46
A1 I/O ADCH1 34 40 47
A2 I/O ADCH2 36 31 35 41 48
A3 I/O ADCH3 37 32 36 42 49
A4 I/O ADCH4 38 33 37 43 50
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TABLE 1. Pinouts for All Packages (Continued)

In System
44-Pin 48-Pin 56-Pin 68-Pin
Port Type Alt. Fun Emulation 44-Pin LLP
PLCC TSSOP TSSOP PLCC
Mode
A5 I/O ADCH5 39 34 38 44 51
A6 I/O ADCH6 40 35 39 45 52
A7 I/O ADCH7 41 36 40 46 53
B0 I/O ADCH8 24 19 19 27 34
B1 I/O ADCH9 25 20 20 28 35
B2 I/O ADCH10 26 21 21 29 36
B3 I/O ADCH11 27 22 22 30 37
B4 I/O ADCH12 28 23 23 31 38
B5 I/O ADCH13 or A/D MUX OUT 29 24 24 32 39
B6 I/O ADCH14 or A/D MUX OUT 30 25 25 33 40
B7 I/O ADCH15 or A/DIN 31 26 26 34 41
F0 I/O 7
F1 I/O 8
F2 I/O 9
F3 I/O 10
DVCC VCC 35 30 32 38 17, 45
DGND GND 32 27 27 35 16, 42
AVCC 34 29 31 37 44
AGND 33 28 28 36 43
CKI I 15 10 10 10 15
RESET I RESET 6 1 1 1 66
a. G1 operation as WDOUT is controlled by Option Register bit 2.
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6.0 Architectural Overview be bypassed by jumpers on the final application board, can
provide for software and hardware debugging using actual
6.1 EMI REDUCTION production units.
The COP8CBR/CCR/CDR devices incorporate circuitry that 6.5 ARCHITECTURE
guards against electromagnetic interference - an increasing
The COP8 family is based on a modified Harvard architec-
problem in today’s microcontroller board designs. National’s
ture, which allows data tables to be accessed directly from
patented EMI reduction technology offers low EMI clock
program memory. This is very important with modern
circuitry, gradual turn-on output drivers (GTOs) and internal
microcontroller-based applications, since program memory
Icc smoothing filters, to help circumvent many of the EMI
is usually ROM or EPROM, while data memory is usually
issues influencing embedded control designs. National has
RAM. Consequently constant data tables need to be con-
achieved 15 dB–20 dB reduction in EMI transmissions when
tained in non-volatile memory, so they are not lost when the
designs have incorporated its patented EMI reducing cir-
microcontroller is powered down. In a modified Harvard ar-
cuitry.
chitecture, instruction fetch and memory data transfers can
6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL be overlapped with a two stage pipeline, which allows the
EEPROM next instruction to be fetched from program memory while
the current instruction is being executed using data memory.
The device includes a program in a boot ROM that provides This is not possible with a Von Neumann single-address bus
the capability, through the MICROWIRE/PLUS serial inter- architecture.
face, to erase, program and read the contents of the Flash
memory. The COP8 family supports a software stack scheme that
allows the user to incorporate many subroutine calls. This
Additional routines are included in the boot ROM, which can capability is important when using High Level Languages.
be called by the user program, to enable the user to custom- With a hardware stack, the user is limited to a small fixed
ize in system software update capability if MICROWIRE/ number of stack levels.
PLUS is not desired.
Additional functions will copy blocks of data between the 6.6 INSTRUCTION SET
RAM and the Flash Memory. These functions provide a In today’s 8-bit microcontroller application arena cost/
virtual EEPROM capability by allowing the user to emulate a performance, flexibility and time to market are several of the
variable amount of EEPROM by initializing nonvolatile vari- key issues that system designers face in attempting to build
ables from the Flash Memory and occasionally restoring well-engineered products that compete in the marketplace.
these variables to the Flash Memory. Many of these issues can be addressed through the manner
The contents of the boot ROM have been defined by Na- in which a microcontroller’s instruction set handles process-
tional. Execution of code from the boot ROM is dependent ing tasks. And that’s why the COP8 family offers a unique
on the state of the FLEX bit in the Option Register on exit and code-efficient instruction set - one that provides the
from RESET. If the FLEX bit is a zero, the Flash Memory is flexibility, functionality, reduced costs and faster time to mar-
assumed to be empty and execution from the boot ROM ket that today’s microcontroller based products require.
begins. For further information on the FLEX bit, refer to Code efficiency is important because it enables designers to
Section 4.5, Option Register. pack more on-chip functionality into less program memory
space (ROM, OTP or Flash). Selecting a microcontroller with
6.3 DUAL CLOCK AND CLOCK DOUBLER less program memory size translates into lower system
The device includes a versatile clocking system and two costs, and the added security of knowing that more code can
oscillator circuits designed to drive a crystal or ceramic be packed into the available program memory space.
resonator. The primary oscillator operates at high speed up
to 10 MHz. The secondary oscillator is optimized for opera- 6.6.1 Key Instruction Set Features
tion at 32.768 kHz. The COP8 family incorporates a unique combination of in-
The user can, through specified transition sequences struction set features, which provide designers with optimum
(please refer to 13.0 Power Saving Features), switch execu- code efficiency and program memory utilization.
tion between the high speed and low speed oscillators. The
unused oscillator can then be turned off to minimize power 6.6.2 Single Byte/Single Cycle Code Execution
dissipation. If the low speed oscillator is not used, the pins The efficiency is due to the fact that the majority of instruc-
are available as general purpose bidirectional ports. tions are of the single byte variety, resulting in minimum
The operation of the CPU will use a clock at twice the program space. Because compact code does not occupy a
frequency of the selected oscillator (up to 20 MHz for high substantial amount of program memory space, designers
speed operation and 65.536 kHz for low speed operation). can integrate additional features and functionality into the
This doubled clock will be referred to in this document as microcontroller program memory space. Also, the majority
‘MCLK’. The frequency of the selected oscillator will be instructions executed by the device are single cycle, result-
referred to as CKI. Instruction execution occurs at one tenth ing in minimum program execution time. In fact, 77% of the
the selected MCLK rate. instructions are single byte single cycle, providing greater
code and I/O efficiency, and faster code execution.
6.4 TRUE IN-SYSTEM EMULATION
On-chip emulation capability has been added which allows 6.6.3 Many Single-Byte, Multi-Function Instructions
the user to perform true in-system emulation using final The COP8 instruction set utilizes many single-byte, multi-
production boards and devices. This simplifies testing and function instructions. This enables a single instruction to
evaluation of software in real environmental conditions. The accomplish multiple functions, such as DRSZ, DCOR, JID,
user, merely by providing for a standard connector which can LD (Load) and X (Exchange) instructions with post-
incrementing and post-decrementing, to name just a few
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6.0 Architectural Overview (Continued) ability to set, reset and test any individual bit in the data
memory address space, including memory-mapped I/O ports
examples. In many cases, the instruction set can simulta- and associated registers.
neously execute as many as three functions with the same
single-byte instruction. 6.6.5 Register Set
JID: (Jump Indirect); Single byte instruction decodes exter- Three memory-mapped pointers handle register indirect ad-
nal events and jumps to corresponding service routines dressing and software stack pointer functions. The memory
(analogous to “DO CASE” statements in higher level lan- data pointers allow the option of post-incrementing or post-
guages). decrementing with the data movement instructions (LOAD/
LAID: (Load Accumulator-Indirect); Single byte look up table EXCHANGE). And 15 memory-mapped registers allow de-
instruction provides efficient data path from the program signers to optimize the precise implementation of certain
memory to the CPU. This instruction can be used for table specific instructions.
lookup and to read the entire program memory for checksum
calculations. 6.7 PACKAGING/PIN EFFICIENCY
RETSK: (Return Skip); Single byte instruction allows return Real estate and board configuration considerations demand
from subroutine and skips next instruction. Decision to maximum space and pin efficiency, particularly given today’s
branch can be made in the subroutine itself, saving code. high integration and small product form factors. Microcon-
troller users try to avoid using large packages to get the I/O
AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These
needed. Large packages take valuable board space and
instructions use the two memory pointers B and X to effi-
increase device cost, two trade-offs that microcontroller de-
ciently process a block of data (simplifying “FOR NEXT” or
signs can ill afford.
other loop structures in higher level languages).
The COP8 family offers a wide range of packages and does
6.6.4 Bit-Level Control not waste pins.
Bit-level control over many of the microcontroller’s I/O ports
provides a flexible means to ease layout concerns and save
board space. All members of the COP8 family provide the
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7.0 Absolute Maximum Ratings Total Current out of GND Pin (Sink) 200 mA
(Note 1) Storage Temperature Range −65˚C to +140˚C
If Military/Aerospace specified devices are required, ESD Protection Level 2 kV (Human Body
please contact the National Semiconductor Sales Office/ Model)
Distributors for availability and specifications.
Note 1: Absolute maximum ratings indicate limits beyond which damage to
Supply Voltage (VCC) 7V the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
Voltage at Any Pin −0.3V to VCC +0.3V
Total Current into VCC Pin (Source) 200 mA
8.0 Electrical Characteristics

DC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter Conditions Min Typ Max Units
Operating Voltage 2.7 5.5 V
Power Supply Rise Time 10 50 x 106 ns
Power Supply Ripple (Note 2) Peak-to-Peak 0.1 VCC V
Supply Current (Note 3)
High Speed Mode
CKI = 10 MHz VCC = 5.5V, tC = 0.5 µs 13.2 mA
CKI = 3.33 MHz VCC = 4.5V, tC = 1.5 µs 6 mA
Dual Clock Mode
CKI = 10 MHz, Low Speed OSC = 32 kHz VCC = 5.5V, tC = 0.5 µs 13.2 mA
CKI = 3.33 MHz, Low Speed OSC = 32 kHz VCC = 4.5V, tC = 1.5 µs 6 mA
Low Speed Mode
Low Speed OSC = 32 kHz VCC = 5.5V 60 103 µA
HALT Current with BOR Disabled (Note 4)
High Speed Mode VCC = 5.5V, CKI = 0 MHz <2 10 µA
Dual Clock Mode VCC = 5.5V, CKI = 0 MHz, Low
<5 17 µA
Speed OSC = 32 kHz
Low Speed Mode VCC = 5.5V, CKI = 0 MHz, Low
<5 17 µA
Speed OSC = 32 kHz
Idle Current (Note 3)
High Speed Mode
CKI = 3.33 MHz VCC = 4.5V, tC = 1.5 µs 1.2 mA
Dual Clock Mode
CKI = 3.33 MHz, Low Speed OSC = 32 kHz VCC = 4.5V, tC = 1.5 µs 1.2 mA
Low Speed Mode
Supply Current for BOR Feature VCC = 5.5V 45 µA
High Brownout Trip Level (BOR Enabled) 4.17 4.28 4.5 V
Low Brownout Trip Level (BOR Enabled) 2.7 2.78 2.9 V
Input Levels (VIH, VIL)
Logic High 0.8 VCC V
Logic Low 0.16 VCC V
Internal Bias Resistor for the CKI
0.3 1.0 2.5 MΩ
Crystal/Resonator Oscillator
Hi-Z Input Leakage VCC = 5.5V −0.5 +0.5 µA
Input Pullup Current VCC = 5.5V, VIN = 0V −50 −210 µA
Port Input Hysteresis 0.25 VCC V
www.national.com 12
8.0 Electrical Characteristics (Continued)
DC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)

Output Current Levels
D Outputs
Source VCC = 4.5V, VOH = 3.8V −7 mA
VCC = 2.7V, VOH = 1.8V −4 mA
Sink (Note 7) VCC = 4.5V, VOL = 1.0V 10 mA
VCC = 2.7V, VOL = 0.4V 3.5 mA
All Others
Source (Weak Pull-Up Mode) VCC = 4.5V, VOH = 3.8V −10 µA
VCC = 2.7V, VOH = 1.8V −5 µA
Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.8V −7 mA
VCC = 2.7V, VOH = 1.8V −4 mA
Sink (Push-Pull Mode) (Note 7) VCC = 4.5V, VOL = 1.0V 10 mA
VCC = 2.7V, VOL = 0.4V 3.5 mA
TRI-STATE Leakage VCC = 5.5V −0.5 +0.5 µA
Allowable Sink Current per Pin 15 mA
Maximum Input Current without Latchup (Note 5) ± 200 mA
RAM Retention Voltage, VR (in HALT Mode) 2.0 V
Input Capacitance 7 pF
Load Capacitance on D2 1000 pF
Voltage on G6 to Force Execution from Boot G6 rise time must be slower than
2 x VCC VCC + 7 V
ROM(Note 8) 100 ns
G6 Rise Time to Force Execution from Boot ROM 100 nS
Input Current on G6 when Input > VCC VIN = 11V, VCC = 5.5V 500 µA
Flash Memory Data Retention 25˚C 100 yrs
Flash Memory Number of Erase/Write Cycles See Table 13, Typical Flash
105 cycles
Memory Endurance
AC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C)

Instruction Cycle Time (tC)
Crystal/Resonator 4.5V ≤ VCC ≤ 5.5V 0.5 DC µs
2.7V ≤ VCC < 4.5V 1.5 DC µs
Flash Memory Page Erase Time See Table 13, Typical
Flash Memory 1 ms
Endurance
Flash Memory Mass Erase Time 8 ms
Frequency of MICROWIRE/PLUS in
2 MHz
Slave Mode
MICROWIRE/PLUS Setup Time (tUWS) 20 ns
MICROWIRE/PLUS Hold Time (tUWH) 20 ns
MICROWIRE/PLUS Output Propagation
150 ns
Delay (tUPD)
Input Pulse Width
Interrupt Input High Time 1 tC
Interrupt Input Low Time 1 tC
Timer 1 Input High Time 1 tC
13 www.national.com
AC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)

Timer 1 Input Low Time 1 tC
Timer 2, 3 Input High Time (Note 6) 1 MCLK or tC
Timer 2, 3 Input Low Time (Note 6) 1 MCLK or tC
Output Pulse Width
Timer 2, 3 Output High Time 150 ns
Timer 2, 3 Output Low Time 150 ns
USART Bit Time when using External 6 CKI
CKX periods
USART CKX Frequency when being
2 MHz
Driven by Internal Baud Rate Generator
Reset Pulse Width 1 tC
tC = instruction cycle time.
Note 2: Maximum rate of voltage change must be < 0.5 V/ms.

Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F, G0,
and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to VCC; A/D converter and clock
monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must
be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.
Note 7: Absolute Maximum Ratings should not be exceeded.
Note 8: Vcc must be valid and stable before G6 is raised to a high voltage.
A/D Converter Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C unless

otherwise noted) (Single-ended mode only)
Resolution 10 Bits
DNL VCC = 5V ±1 LSB
DNL VCC = 3V, ±1 LSB
−20˚C ≤ TA ≤ +85˚C
INL VCC = 5V ±3 LSB
INL VCC = 3V, ±4 LSB
−20˚C ≤ TA ≤ +85˚C
Offset Error VCC = 5V +2.5, −1 LSB
Offset Error VCC = 3V, ± 2.5 LSB
−20˚C ≤ TA ≤ +85˚C
Gain Error VCC = 5V +0.5, −2.5 LSB
Gain Error VCC = 3V, ± 2.5 LSB
−20˚C ≤ TA ≤ +85˚C
Input Voltage Range 2.7V ≤ VCC < 5.5V 0 VCC V
Analog Input Leakage Current 0.5 µA
Analog Input Resistance (Note 9) 6k Ω
Analog Input Capacitance 7 pF
Conversion Clock Period 4.5V ≤ VCC < 5.5V 0.8 30 µs
2.7V ≤ VCC < 4.5V 1.2 30 µs
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A/D Converter Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C unless

otherwise noted) (Single-ended mode only) (Continued)
Conversion Time (including S/H Time) 15 A/D
Conversion
Clock
Cycles
Operating Current on AVCC AVCC = 5.5V 0.2 0.6 mA
Note 9: Resistance between the device input and the internal sample and hold capacitance.
DC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C)

Operating Voltage 4.5 5.5 V
6
Power Supply Rise Time 10 50 x 10 ns
Power Supply Ripple (Note 2) Peak-to-Peak 0.1 VCC V
Supply Current (Note 3)
High Speed Mode
CKI = 3.33 MHz VCC = 4.5V, tC = 1.5 µs 7 mA
Dual Clock Mode
CKI = 3.33 MHz, Low Speed OSC = 32 kHz VCC = 4.5V, tC = 1.5 µs 7 mA
Low Speed Mode
HALT Current with BOR Disabled (Note 4)
High Speed Mode VCC = 5.5V, CKI = 0 MHz <4 40 µA
Dual Clock Mode VCC = 5.5V, CKI = 0 MHz, Low
<9 50 µA
Speed OSC = 32 kHz
Low Speed Mode VCC = 5.5V, CKI = 0 MHz, Low
<9 50 µA
Speed OSC = 32 kHz
Idle Current (Note 3)
High Speed Mode
Dual Clock Mode
Low Speed Mode
Supply Current for BOR Feature VCC = 5.5V 45 µA
High Brownout Trip Level (BOR Enabled) 4.17 4.28 4.5 V
Input Levels (VIH, VIL)
Logic High 0.8 VCC V
Logic Low 0.16 VCC V
Internal Bias Resistor for the CKI
0.3 1.0 2.5 MΩ
Crystal/Resonator Oscillator
Hi-Z Input Leakage VCC = 5.5V −3 +3 µA
Input Pullup Current VCC = 5.5V, VIN = 0V −40 −250 µA
Port Input Hysteresis 0.25 VCC V
15 www.national.com
DC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C) (Continued)

Output Current Levels
D Outputs
Source VCC = 4.5V, VOH = 3.8V −6.3 mA
Sink (Note 7) VCC = 4.5V, VOL = 1.0V 9 mA
All Others
Source (Weak Pull-Up Mode) VCC = 4.5V, VOH = 3.8V −9 µA
Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.8V −6.3 mA
Sink (Push-Pull Mode) (Note 7) VCC = 4.5V, VOL = 1.0V 9 mA
TRI-STATE Leakage VCC = 5.5V −3 +3 µA
Allowable Sink Current per Pin 1 mA
Maximum Input Current without Latchup (Note 5) ± 200 mA
RAM Retention Voltage, VR (in HALT Mode) 2.0 V
Input Capacitance 7 pF
Load Capacitance on D2 1000 pF
Voltage on G6 to Force Execution from Boot G6 rise time must be slower than
2 x VCC VCC + 7 V
ROM(Note 8) 100 ns
G6 Rise Time to Force Execution from Boot ROM 100 nS
Input Current on G6 when Input > VCC VIN = 11V, VCC = 5.5V 500 µA
AC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C)

Instruction Cycle Time (tC)
Crystal/Resonator 4.5V ≤ VCC ≤ 5.5V 0.5 DC µs
Output Propagation Delay RL =2.2k, CL = 100 pF
Frequency of MICROWIRE/PLUS in
2 MHz
Slave Mode
MICROWIRE/PLUS Setup Time (tUWS) 20 ns
MICROWIRE/PLUS Hold Time (tUWH) 20 ns
MICROWIRE/PLUS Output Propagation
150 ns
Delay (tUPD)
Input Pulse Width
Interrupt Input High Time 1 tC
Interrupt Input Low Time 1 tC
Timer 1 Input High Time 1 tC
Timer 1 Input Low Time 1 tC
Timer 2, 3 Input High Time (Note 6) 1 MCLK or tC
Timer 2, 3 Input Low Time (Note 6) 1 MCLK or tC
Output Pulse Width
Timer 2, 3 Output High Time 150 ns
Timer 2, 3 Output Low Time 150 ns
USART Bit Time when using External 6 CKI
CKX periods
USART CKX Frequency when being
2 MHz
Driven by Internal Baud Rate Generator
Reset Pulse Width 0.5 tC
tC = instruction cycle time.
Note 10: Maximum rate of voltage change must be < 0.5 V/ms.
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AC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C) (Continued)

Note 11: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 12: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F,
G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to VCC; A/D converter and
clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC
when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins
must be limited to < (VCC + 7V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
Note 14: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.
Note 15: Absolute Maximum Ratings should not be exceeded.
Note 16: Vcc must be valid and stable before G6 is raised to a high voltage.
A/D Converter Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C)

(Single-ended mode only)
Resolution 10 Bits
DNL VCC = 5V ±1 LSB
INL VCC = 5V ±3 LSB
Offset Error VCC = 5V +2.5, −1 LSB
Gain Error VCC = 5V +0.5, −2.5 LSB
Input Voltage Range 4.5V ≤ VCC < 5.5V 0 VCC V
Analog Input Leakage Current 0.5 µA
Analog Input Resistance (Note 9) 6k Ω
Analog Input Capacitance 7 pF
Conversion Clock Period 4.5V ≤ VCC < 5.5V 0.8 30 µs
Conversion Time (including S/H Time) 15 A/D
Conversion
Clock
Cycles
Operating Current on AVCC AVCC = 5.5V 0.2 0.6 mA
Note 17: Resistance between the device input and the internal sample and hold capacitance.
10137405
FIGURE 1. MICROWIRE/PLUS Timing
17 www.national.com
9.0 Pin Descriptions under software control as shown below:
The COP8CBR/CCR/CDR I/O structure enables designers CONFIGURATION DATA Port Set-Up
Register Register
to reconfigure the microcontroller’s I/O functions with a
single instruction. Each individual I/O pin can be indepen- 0 0 Hi-Z Input
dently configured as output pin low, output high, input with (TRI-STATE Output)
high impedance or input with weak pull-up device. A typical 0 1 Input with Weak Pull-Up
example is the use of I/O pins as the keyboard matrix input 1 0 Push-Pull Zero Output
lines. The input lines can be programmed with internal weak 1 1 Push-Pull One Output
pull-ups so that the input lines read logic high when the keys
are all open. With a key closure, the corresponding input line Port A is an 8-bit I/O port. All A pins have Schmitt triggers on
will read a logic zero since the weak pull-up can easily be the inputs. The 44-pin package does not have a full 8-bit port
overdriven. When the key is released, the internal weak and contains some unbonded, floating pads internally on the
pull-up will pull the input line back to logic high. This elimi- chip. The binary value read from these bits is undetermined.
nates the need for external pull-up resistors. The high cur- The application software should mask out these unknown
rent options are available for driving LEDs, motors and bits when reading the Port A register, or use only bit-access
speakers. This flexibility helps to ensure a cleaner design, program instructions when accessing Port A. These uncon-
with less external components and lower costs. Below is the nected bits draw power only when they are addressed (i.e.,
general description of all available pins. in brief spikes). Additionally, if Port A is being used with some
VCC and GND are the power supply pins. All VCC and GND combination of digital inputs and analog inputs, the analog
pins must be connected. inputs will read as undetermined values and should be
Users of the LLP package are cautioned to be aware that the masked out by software.
central metal area and the pin 1 index mark on the bottom of Port A supports the analog inputs for the A/D converter. Port
the package may be connected to GND. See figure below: A has the following alternate pin functions:
A7 Analog Channel 7
A6 Analog Channel 6
A5 Analog Channel 5
A4 Analog Channel 4
A3 Analog Channel 3
A2 Analog Channel 2
A1 Analog Channel 1
A0 Analog Channel 0
Port B is an 8-bit I/O port. All B pins have Schmitt triggers on
the inputs. If Port B is being used with some combination of
digital inputs and analog inputs, the analog inputs will read
as undetermined values. The application software should
mask out these unknown bits when reading the Port B
10137470
register, or use only bit-access program instructions when
accessing Port B.
FIGURE 2. LLP Package Bottom View Port B supports the analog inputs for the A/D converter. Port
B has the following alternate pin functions:
CKI is the clock input. This can be connected (in conjunction B7 Analog Channel 15 or A/D Input
with CKO) to an external crystal circuit to form a crystal B6 Analog Channel 14 or Analog Multiplexor Output
oscillator. See Oscillator Description section.
B5 Analog Channel 13 or Analog Multiplexor Output
RESET is the master reset input. See Reset description
B4 Analog Channel 12
section.
B3 Analog Channel 11
AVCC is the Analog Supply for A/D converter. It should be
connected to VCC externally. This is also the top of the B2 Analog Channel 10
resistor ladder D/A converter used within the A/D converter. B1 Analog Channel 9
AGND is the ground pin for the A/D converter. It should be B0 Analog Channel 8
connected to GND externally. This is also the bottom of the Port C is an 8-bit I/O port. The 44-pin device does not offer
resistor ladder D/A converter used within the A/D converter. Port C. The unavailable pins are not terminated. A read
The device contains up to six bidirectional 8-bit I/O ports (A, operation on these unterminated pins will return unpredict-
B, C, E, G and L) and one 4-bit I/O port (F), where each able values. On this device, the associated Port C Data and
individual bit may be independently configured as an input Configuration registers should not be used. All C pins have
(Schmitt trigger inputs on ports L and G), output or TRI- Schmitt triggers on the inputs. Port C draws no power when
STATE under program control. Three data memory address unbonded.
locations are allocated for each of these I/O ports. Each I/O Port E is an 8-bit I/O Port. The 44-pin device does not offer
port has three associated 8-bit memory mapped registers, Port E. The unavailable pins are not terminated. A read
the CONFIGURATION register, the output DATA register and operation on these unterminated pins will return unpredict-
the Pin input register. (See the memory map for the various able values. On this device, the associated Port E Data and
addresses associated with the I/O ports.) Figure 3 shows the
I/O port configurations. The DATA and CONFIGURATION
registers allow for each port bit to be individually configured
www.national.com 18
9.0 Pin Descriptions (Continued) L4 Multi-input Wake-up or T2A (Timer T2A Input/Output)
L3 Multi-Input Wake-up and/or RDX (USART Receive)
Configuration registers should not be used. All E pins have
L2 Multi-Input Wake-up or TDX (USART Transmit)
Schmitt triggers on the inputs. Port E draws no power when
unbonded. L1 Multi-Input Wake-up and/or CKX (USART Clock) (Low
Speed Oscillator Output)
Port F is a 4-bit I/O Port. All F pins have Schmitt triggers on
the inputs. L0 Multi-Input Wake-up (Low Speed Oscillator Input)
The 68-pin package has fewer than eight Port F pins, and Port D is an 8-bit output port that is preset high when RESET
contains unbonded, floating pads internally on the chip. The goes low. The user can tie two or more D port outputs
binary values read from these bits are undetermined. The (except D2) together in order to get a higher drive.
application software should mask out these unknown bits Note: Care must be exercised with the D2 pin operation. At
when reading the Port F register, or use only bit-access RESET, the external loads on this pin must ensure that the
program instructions when accessing Port F. The uncon- output voltages stay above 0.7 VCC to prevent the chip from
nected bits draw power only when they are addressed (i.e., entering special modes. Also keep the external loading on
in brief spikes). D2 to less than 1000 pF.
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All pins
have Schmitt Triggers on their inputs. Pin G1 serves as the
dedicated WATCHDOG output with weak pull-up if the
WATCHDOG feature is selected by the Option register.
The pin is a general purpose I/O if WATCHDOG feature is
not selected. If WATCHDOG feature is selected, bit 1 of the
Port G configuration and data register does not have any
effect on Pin G1 setup. G7 serves as the dedicated output
pin for the CKO clock output.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin, the associated bits in the data and configu-
ration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeros.
10137406
The device will be placed in the HALT mode by writing a “1”
to bit 7 of the Port G Data Register. Similarly the device will
FIGURE 3. I/O Port Configurations
be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter-
nate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
Config. Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:

G7 CKO Oscillator dedicated output
G6 SI (MICROWIRE/PLUS Serial Data Input)
10137407
G5 SK (MICROWIRE/PLUS Serial Clock)
G4 SO (MICROWIRE/PLUS Serial Data Output) FIGURE 4. I/O Port Configurations — Output Mode
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G1 WDOUT WATCHDOG and/or Clock Monitor if WATCH-
DOG enabled, otherwise it is a general purpose I/O
G0 INTR (External Interrupt Input)
G0 through G3 are also used for In-System Emulation.
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
Port L supports the Multi-Input Wake-up feature on all eight
pins. Port L has the following alternate pin functions:
L7 Multi-Input Wake-up or T3B (Timer T3B Input)
L6 Multi-Input Wake-up or T3A (Timer T3A Input/Output)
L5 Multi-Input Wake-up or T2B (Timer T2B Input)
19 www.national.com
9.0 Pin Descriptions (Continued) addressing space with separate address buses. The archi-
tecture, though based on the Harvard architecture, permits
transfer of data from Flash Memory to RAM.
10.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tC) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
10137408 S is the 8-bit Data Segment Address Register used to extend
the lower half of the address range (00 to 7F) into 256 data
FIGURE 5. I/O Port Configurations — Input Mode segments of 128 bytes each.
SP is the 8-bit stack pointer, which points to the subroutine/
9.1 EMULATION CONNECTION interrupt stack (in RAM). With reset the SP is initialized to
RAM address 06F Hex. The SP is decremented as items are
Connection to the emulation system is made via a 2 x 7 pushed onto the stack. SP points to the next available loca-
connector which interrupts the continuity of the RESET, G0, tion on the stack.
G1, G2 and G3 signals between the COP8 device and the
rest of the target system (as shown in Figure 6). This con- All the CPU registers are memory mapped with the excep-
nector can be designed into the production pc board and can tion of the Accumulator (A) and the Program Counter (PC).
be replaced by jumpers or signal traces when emulation is
10.2 PROGRAM MEMORY
no longer necessary. The emulator will replicate all functions
of G0 - G3 and RESET. For proper operation, no connection The program memory consists of 32,768 bytes of Flash
should be made on the device side of the emulator connec- Memory. These bytes may hold program instructions or con-
tor. stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS
instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 00FF Hex. The program memory
reads 00 Hex in the erased state. Program execution starts
at location 0 after RESET.
If a Return instruction is executed when the SP contains 6F
(hex), instruction execution will continue from Program
Memory location 7FFF (hex). If location 7FFF is accessed by
an instruction fetch, the Flash Memory will return a value of
00. This is the opcode for the INTR instruction and will cause
a Software Trap.
For the purpose of erasing and rewriting the Flash Memory,
it is organized in pages of 128 bytes.
10.3 DATA MEMORY

The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers and the USART (with the exception of the
10137409 IDLE timer). Data memory is addressed directly by the in-
struction or indirectly by the B, X and SP pointers.
FIGURE 6. Emulation Connection The data memory consists of 1024 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
10.0 Functional Description also decremented and tested with the DRSZ (decrement
The architecture of the device is a modified Harvard archi- register and skip if zero) instruction. The memory pointer
tecture. With the Harvard architecture, the program memory registers X, SP, B and S are memory mapped into this space
(Flash) is separate from the data store memory (RAM). Both at address locations 0FC to 0FF Hex respectively, with the
Program Memory and Data Memory have their own separate other registers being available for general usage.
www.national.com 20
10.0 Functional Description range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
(Continued)
to XX7F. This organization allows a total of 256 data seg-
The instruction set permits any bit in memory to be set, reset ments of 128 bytes each with an additional upper base
or tested. All I/O and registers (except A and PC) are segment of 128 bytes. Furthermore, all addressing modes
memory mapped; therefore, I/O bits and register bits can be are available for all data segments. The S register must be
directly and individually set, reset and tested. The accumu- changed under program control to move from one data
lator (A) bits can also be directly and individually tested. segment (128 bytes) to another. However, the upper base
Note: RAM contents are undefined upon power-up. segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
10.4 DATA MEMORY SEGMENT RAM EXTENSION contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data seg-
Data memory address 0FF is used as a memory mapped
ment extension.
location for the Data Segment Address Register (S).
The instructions that utilize the stack pointer (SP) always
The data store memory is either addressed directly by a
reference the stack as part of the base segment (Segment
single byte address within the instruction, or indirectly rela-
0), regardless of the contents of the S register. The S register
tive to the reference of the B, X, or SP pointers (each
is not changed by these instructions. Consequently, the
contains a single-byte address). This single-byte address
stack (used with subroutine linkage and interrupts) is always
allows an addressing range of 256 locations from 00 to FF
located in the base segment. The stack pointer will be initial-
hex. The upper bit of this single-byte address divides the
ized to point at data memory location 006F as a result of
data store memory into two separate sections as outlined
reset.
previously. With the exception of the RAM register memory
from address locations 00F0 to 00FF, all RAM memory is The 128 bytes of RAM contained in the base segment are
memory mapped with the upper bit of the single-byte ad- split between the lower and upper base segments. The first
dress being equal to zero. This allows the upper bit of the 112 bytes of RAM are resident from address 0000 to 006F in
single-byte address to determine whether or not the base the lower base segment, while the remaining 16 bytes of
address range (from 0000 to 00FF) is extended. If this upper RAM represent the 16 data memory registers located at
bit equals one (representing address range 0080 to 00FF), addresses 00F0 to 00FF of the upper base segment. No
then address extension does not take place. Alternatively, if RAM is located at the upper sixteen addresses (0070 to
this upper bit equals zero, then the data segment extension 007F) of the lower base segment.
register S is used to extend the base address range (from Additional RAM beyond these initial 128 bytes, however, will
0000 to 007F) from XX00 to XX7F, where XX represents the always be memory mapped in groups of 128 bytes (or less)
8 bits from the S register. Thus the 128-byte data segment at the data segment address extensions (XX00 to XX7F) of
extensions are located from addresses 0100 to 017F for the lower base segment. The additional 892 bytes of RAM in
data segment 1, 0200 to 027F for data segment 2, etc., up to this device are memory mapped at address locations 0100
FF00 to FF7F for data segment 255. The base address to 017F through 0700 to 077F hex.
range from 0000 to 007F represents data segment 0.
Figure 7 illustrates how the S register data memory exten-
sion is used in extending the lower half of the base address
21 www.national.com
10.0 Functional Description (Continued)
10137410
FIGURE 7. RAM Organization
10.4.1 Virtual EEPROM 10.5 OPTION REGISTER

The Flash memory and the User ISP functions (see Section The Option register, located at address 0x7FFF in the Flash
5.7), provide the user with the capability to use the flash Program Memory, is used to configure the user selectable
program memory to back up user defined sections of RAM. security, WATCHDOG, and HALT options. The register can
This effectively provides the user with the same nonvolatile be programmed only in external Flash Memory programming
data storage as EEPROM. Management, and even the or ISP Programming modes. Therefore, the register must be
amount of memory used, are the responsibility of the user, programmed at the same time as the program memory. The
however the flash memory read and write functions have contents of the Option register shipped from the factory read
been provided in the boot ROM. 00 Hex.
One typical method of using the Virtual EEPROM feature
would be for the user to copy the data to RAM during system
initialization, periodically, and if necessary, erase the page of
Flash and copy the contents of the RAM back to the Flash.
www.national.com 22
10.0 Functional Description 10.6 SECURITY
(Continued) The device has a security feature which, when enabled,
prevents external reading of the Flash program memory. The
The format of the Option register is as follows: security bit in the Option Register determines, whether se-
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
curity is enabled or disabled. If the security feature is dis-
abled, the contents of the internal Flash Memory may be
WATCH
Reserved SECURITY Reserved DOG HALT FLEX read by external programmers or by the built in
MICROWIRE/PLUS serial interface ISP. Security must be
Bits 7, 6 These bits are reserved and must be 0. enforced by the user when the contents of the Flash
Bit 5 Memory are accessed via the user ISP or Virtual EE-
=1 Security enabled. Flash Memory read and write PROM capability.
are not allowed except in User ISP/Virtual E2 com- If the security feature is enabled, then any attempt to exter-
mands. Mass Erase is allowed. nally read the contents of the Flash Memory will result in the
=0 Security disabled. Flash Memory read and write value FF (hex) being read from all program locations (except
are allowed. the Option Register). In addition, with the security feature
enabled, the write operation to the Flash program memory
Bits 4, 3 These bits are reserved and must be 0.
and Option Register is inhibited. Page Erases are also inhib-
Bit 2 ited when the security feature is enabled. The Option Reg-
=1 WATCHDOG feature disabled. G1 is a general ister is readable regardless of the state of the security bit by
purpose I/O. accessing location FFFF (hex). Mass Erase Operations are
=0 WATCHDOG feature enabled. G1 pin is possible regardless of the state of the security bit.
WATCHDOG output with weak pullup. The security bit can be erased only by a Mass Erase of the
Bit 1 entire contents of the Flash unless Flash operation is under
the control of User ISP functions.
=1 HALT mode disabled.
Note: The actual memory address of the Option Register is
=0 HALT mode enabled.
7FFF (hex), however the MICROWIRE/PLUS ISP routines
Bit 0 require the address FFFF (hex) to be used to read the
=1 Execution following RESET will be from Flash Option Register when the Flash Memory is secured.
Memory. The entire Option Register must be programmed at one time
=0 Flash Memory is erased. Execution following RE- and cannot be rewritten without first erasing the entire last
SET will be from Boot ROM with the MICROWIRE/ page of Flash Memory.
PLUS ISP routines.
The COP8 assembler defines a special ROM section type, 10.7 RESET
CONF, into which the Option Register data may be coded. The device is initialized when the RESET pin is pulled low or
The Option Register is programmed automatically by pro- the On-chip Brownout Reset is activated. The Brownout
grammers that are certified by National. Reset feature is not available on the COP8CDR9.
The user needs to ensure that the FLEX bit will be set when
the device is programmed.
The following examples illustrate the declaration of the Op-
tion Register.
Syntax:
[label:].sect config, conf
.db value ;1 byte, 10137411
;configures
;options FIGURE 8. Reset Logic
.endsect
Example: The following sets a value in the Option Register The following occurs upon initialization:
and User Identification for a COP8CBR9HVA7. The Option Port A: TRI-STATE (High Impedance Input)
Register bit values shown select options: Security disabled, Port B: TRI-STATE (High Impedance Input)
WATCHDOG enabled HALT mode enabled and execution
Port C: TRI-STATE (High Impedance Input)
will commence from Flash Memory.
Port D: HIGH
.chip 8CBR
.sect option, conf Port E: TRI-STATE (High Impedance Input)
.db 0x01 ;wd, halt, flex Port F: TRI-STATE (High Impedance Input)
.endsect Port G: TRI-STATE (High Impedance Input). Exceptions: If
... Watchdog is enabled, then G1 is Watchdog output. G0
.end start and G2 have their weak pull-up enabled during RESET.
Note: All programmers certified for programming this family Port L: TRI-STATE (High Impedance Input)
of parts will support programming of the Option Register.
PC: CLEARED to 0000
Please contact National or your device programmer supplier
for more information. PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
23 www.national.com
10.0 Functional Description 10.7.1 External Reset
(Continued) The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
T2CNTRL: CLEARED tion cycle to guarantee a valid reset. During Power-Up ini-
T3CNTRL: CLEARED tialization, the user must ensure that the RESET pin of a
HSTCR: CLEARED device without the Brownout Reset feature is held low until
the device is within the specified VCC voltage. Any rising
ITMR: Cleared except Bit 6 (HSON) = 1 edge on the RESET pin while VCC is below the specified
Accumulator, Timer 1, Timer 2 and Timer 3: operating range may cause unpredictable results. An R/C
RANDOM after RESET circuit on the RESET pin with a delay 5 times (5x) greater
WKEN, WKEDG: CLEARED than the power supply rise time is recommended. Reset
should also be wide enough to ensure crystal start-up upon
WKPND: RANDOM
Power-Up.
SP (Stack Pointer):
RESET may also be used to cause an exit from the HALT
Initialized to RAM address 06F Hex mode.
B and X Pointers: A recommended reset circuit for this device is shown in
UNAFFECTED after RESET with power already applied Figure 9.
S Register: CLEARED
RAM:
UNAFFECTED after RESET with power already applied
USART:
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
ANALOG TO DIGITAL CONVERTER:
ENAD: CLEARED
10137412
ADRSTH: RANDOM
ADRSTL: RANDOM FIGURE 9. Reset Circuit Using External Reset
ISP CONTROL:
ISPADLO: CLEARED 10.7.2 On-Chip Brownout Reset
ISPADHI: CLEARED When enabled, the device generates an internal reset as
PGMTIM: PRESET TO VALUE FOR 10 MHz CKI VCC rises. While VCC is less than the specified brownout
WATCHDOG (if enabled): voltage (Vbor), the device is held in the reset condition and
The device comes out of reset with both the WATCHDOG the Idle Timer is preset with 00Fx (240–256 tC). When VCC
logic and the Clock Monitor detector armed, with the reaches a value greater than Vbor, the Idle Timer starts
WATCHDOG service window bits set and the Clock Moni- counting down. Upon underflow of the Idle Timer, the internal
tor bit set. The WATCHDOG and Clock Monitor circuits reset is released and the device will start executing instruc-
are inhibited during reset. The WATCHDOG service win- tions. This internal reset will perform the same functions as
dow bits being initialized high default to the maximum external reset. Once VCC is above the Vbor and this initial Idle
WATCHDOG service window of 64k T0 clock cycles. The Timer time-out takes place, instruction execution begins and
Clock Monitor bit being initialized high will cause a Clock the Idle Timer can be used normally. If, however, VCC drops
Monitor error following reset if the clock has not reached below the selected Vbor, an internal reset is generated, and
the minimum specified frequency at the termination of the Idle Timer is preset with 00Fx. The device now waits until
reset. A Clock Monitor error will cause an active low error VCC is greater than Vbor and the countdown starts over.
output on pin G1. This error output will continue until When enabled, the functional operation of the device, at
16–32 T0 clock cycles following the clock frequency frequency, is guaranteed down to the Vbor level.
reaching the minimum specified value, at which time the
G1 output will go high.
www.national.com 24
10.0 Functional Description (Continued)
10137413
FIGURE 10. Brownout Reset Operation
One exception to the above is that the brownout circuit will filtering of VCC be done to ensure that the brownout feature
insert a delay of approximately 3 ms on power up or any time works correctly. Power supply decoupling is vital even in
the VCC drops below a voltage of about 1.8V. The device will battery powered systems.
be held in Reset for the duration of this delay before the Idle There are two optional brownout voltages. The part numbers
Timer starts counting the 240 to 256 tC. This delay starts as for the three versions of this device are:
soon as the VCC rises above the trigger voltage (approxi-
COP8CBR, Vbor = low voltage range
mately 1.8V). This behavior is shown in Figure 10.
COP8CCR, Vbor = high voltage range
In Case 1, VCC rises from 0V and the on-chip RESET is
undefined until the supply is greater than approximately COP8CDR, BOR is disabled.
1.0V. At this time the brownout circuit becomes active and Refer to the device specifications for the actual Vbor volt-
holds the device in RESET. As the supply passes a level of ages.
about 1.8V, a delay of about 3 ms (td) is started and the Idle High brownout voltage devices are guaranteed to operate at
Timer is preset to a value between 00F0 and 00FF (hex). 10MHz down to the brownout voltage. Low brownout voltage
Once VCC is greater than Vbor and td has expired, the Idle devices are guaranteed to operate at 3.33MHz down to the
Timer is allowed to count down (tid). brownout voltage. Devices are not guaranteed to operate
Case 2 shows a subsequent dip in the supply voltage which at 10MHz down to the low brownout voltage.
goes below the approximate 1.8V level. As VCC drops below Under no circumstances should the RESET pin be allowed
Vbor, the internal RESET signal is asserted. When VCC rises to float. If the on-chip Brownout Reset feature is being used,
back above the 1.8V level, td is started. Since the power the RESET pin should be connected directly to VCC. The
supply rise time is longer for this case, td has expired before RESET input may also be connected to an external pull-up
VCC rises above Vbor and tid starts immediately when VCC is resistor or to other external circuitry. Any rising edge on the
greater than Vbor. RESET pin while VCC is below the specified operating range
Case 3 shows a dip in the supply where VCC drops below may cause unpredictable results. The output of the brownout
Vbor, but not below 1.8V. On-chip RESET is asserted when reset detector will always preset the Idle Timer to a value
VCC goes below Vbor and tid starts as soon as the supply between 00F0 and 00FF (240 to 256 tC). At this time, the
goes back above Vbor. internal reset will be generated.
If the Brownout Reset feature is enabled, the internal reset If the BOR feature is disabled, then no internal resets are
will not be turned off until the Idle Timer underflows. The generated and the Idle Timer will power-up with an unknown
internal reset will perform the same functions as external value. In this case, the external RESET must be used. When
reset. The device is guaranteed to operate at the specified BOR is disabled, this on-chip circuitry is disabled and draws
frequency down to the specified brownout voltage. After the no DC current.
underflow, the logic is designed such that no additional The contents of data registers and RAM are unknown fol-
internal resets occur as long as VCC remains above the lowing the on-chip reset.
brownout voltage.
The device is relatively immune to short duration negative-
going VCC transients (glitches). It is essential that good
25 www.national.com
10.0 Functional Description Section 7.0 Power Saving Features. The low speed oscillator
utilizes the L0 and L1 port pins. References in the following
(Continued)
text to CKI will also apply to L0 and references to G7/CKO
will also apply to L1.
10.8.1 Oscillator
CKI is the clock input while G7/CKO is the clock generator
output to the crystal. An on-chip bias resistor connected
between CKI and CKO is provided to reduce system part
count. The value of the resistor is in the range of 0.5M to 2M
(typically 1.0M). Table 2 shows the component values re-
quired for various standard crystal values. Resistor R2 is
on-chip, for the high speed oscillator, and is shown for
reference. Figure 12 shows the crystal oscillator connection
10137414
diagram. A ceramic resonator of the required frequency may
be used in place of a crystal if the accuracy requirements are
FIGURE 11. Reset Circuit Using Power-On Reset
not quite as strict.
10.8 OSCILLATOR CIRCUITS

The device has two crystal oscillators to facilitate low power
operation while maintaining throughput when required. Fur-
ther information on the use of the two oscillators is found in
High Speed Oscillator Low Speed Oscillator
10137416
10137415
FIGURE 12. Crystal Oscillator
TABLE 2. Crystal Oscillator Configuration, C2 can be trimmed to obtain the desired frequency. C2
TA = 25˚C, VCC = 5V should be less than or equal to C1.
CKI Freq. Note: The low power design of the low speed oscillator
R1 (kΩ) R2 (MΩ) C1 (pF) C2 (pF) makes it extremely sensitive to board layout and load ca-
(MHz)
pacitance. The user should place the crystal and load ca-
0 On Chip 18 18 10 pacitors within 1cm. of the device and must ensure that the
0 On Chip 18 18 5 above equation for load capacitance is strictly followed. If
these conditions are not met, the application may have
0 On Chip 18–36 18–36 1
problems with startup of the low speed oscillator.
5.6 On Chip 100 100–156 0.455
0 20 ** ** 32.768
TABLE 3. Startup Times
kHz*
*Applies to connection to low speed oscillator on port pins L0 and L1 only. CKI Frequency Startup Time
**See Note below. 10 MHz 1–10 ms
The crystal and other oscillator components should be 3.33 MHz 3–10 ms
placed in close proximity to the CKI and CKO pins to mini-
1 MHz 3–20 ms
mize printed circuit trace length.
The values for the external capacitors should be chosen to 455 kHz 10–30 ms
obtain the manufacturer’s specified load capacitance for the 32 kHz (low speed oscillator) 2–5 sec
crystal when combined with the parasitic capacitance of the
trace, socket, and package (which can vary from 0 to 8 pF).
The guideline in choosing these capacitors is:
Manufacturer’s specified load cap = (C1 * C2) / (C1 + C2) +
Cparasitic
www.national.com 26
10.0 Functional Description 10.9.3 ICNTRL Register (Address X'00E8)
(Continued) Unused LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7 Bit 0
10.8.2 Clock Doubler
This device contains a frequency doubler that doubles the The ICNTRL register contains the following bits:
frequency of the oscillator selected to operate the main LPEN L Port Interrupt Enable (Multi-Input
microcontroller core. The details of how to select either the Wake-up/Interrupt)
high speed oscillator or low speed oscillator are described in,
T0PND Timer T0 Interrupt pending
Power Saving Features. When the high speed oscillator
connected to CKI operates at 10 MHz, the internal clock T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
frequency is 20 MHz, resulting in an instruction cycle time of µWPND MICROWIRE/PLUS interrupt pending
0.5 µs. When the 32 kHz oscillator connected to L0 and L1 is µWEN Enable MICROWIRE/PLUS interrupt
selected, the internal clock frequency is 64 kHz, resulting in T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
an instruction cycle of 152.6 µs. The output of the clock edge
doubler is called MCLK and is referenced in many places
within this document. T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
10.9 CONTROL REGISTERS
10.9.4 T2CNTRL Register (Address X'00C6)
10.9.1 CNTRL Register (Address X'00EE) T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 Bit 7 Bit 0
Bit 7 Bit 0
The T2CNTRL register contains the following bits:
The Timer1 (T1) and MICROWIRE/PLUS control register T2C3 Timer T2 mode control bit
contains the following bits: T2C2 Timer T2 mode control bit
T1C3 Timer T1 mode control bit T2C1 Timer T2 mode control bit
T1C2 Timer T1 mode control bit T2C0 Timer T2 Start/Stop control in timer
T1C1 Timer T1 mode control bit modes 1 and 2, Timer T2 Underflow Interrupt
T1C0 Timer T1 Start/Stop control in timer Pending Flag in timer mode 3
modes 1 and 2. T1 Underflow Interrupt T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
Pending Flag in timer mode 3 RA in mode 1, T2 Underflow in mode 2, T2A
MSEL Selects G5 and G4 as MICROWIRE/PLUS capture edge in mode 3)
signals SK and SO respectively T2ENA Timer T2 Interrupt Enable for Timer Underflow
IEDG External interrupt edge polarity select or T2A Input capture edge
(0 = Rising edge, 1 = Falling edge) T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
SL1 & SL0 Select the MICROWIRE/PLUS clock divide ture edge
by (00 = 2, 01 = 4, 1x = 8) T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
10.9.2 PSW Register (Address X'00EF)
10.9.5 T3CNTRL Register (Address X'00B6)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0 T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
Bit 7 Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag The T3CNTRL register contains the following bits:
C Carry Flag T3C3 Timer T3 mode control bit
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA T3C2 Timer T3 mode control bit
in mode 1, T1 Underflow in Mode 2, T1A capture T3C1 Timer T3 mode control bit
edge in mode 3) T3C0 Timer T3 Start/Stop control in timer
T1ENA Timer T1 Interrupt Enable for Timer Underflow modes 1 and 2, Timer T3 Underflow Interrupt
or T1A Input capture edge Pending Flag in timer mode 3
EXPND External interrupt pending T3PNDA Timer T3 Interrupt Pending Flag (Autoreload
BUSY MICROWIRE/PLUS busy shifting flag RA in mode 1, T3 Underflow in mode 2, T3A
capture edge in mode 3)
EXEN Enable external interrupt
T3ENA Timer T3 Interrupt Enable for Timer Underflow
GIE Global interrupt enable (enables interrupts)
or T3A Input capture edge
The Half-Carry flag is also affected by all the instructions that
T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-
affect the Carry flag. The SC (Set Carry) and R/C (Reset
ture edge
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC, T3ENB Timer T3 Interrupt Enable for T3B Input capture
SUBC, RRC and RLC instructions affect the Carry and Half edge
Carry flags.
27 www.national.com
10.0 Functional Description ADCH2 ADC channel select bit
(Continued) ADCH1 ADC channel select bit
ADCH0 ADC channel select bit
10.9.6 HSTCR Register (Address X'00AF)
ADMOD Places the ADC in single-ended or differential
Reserved T3HS T2HS mode.
Bit 7 Bit 0 MUX Enables the ADC multiplexor output.
The HSTCR register contains the following bits: PSC Switches the ADC clock between a divide by one
or a divide by sixteen of MCLK.
T3HS Places Timer T3 in High Speed Mode.
ADBSY Signifies that the ADC is currently busy perform-
T2HS Places Timer T2 in High Speed Mode. ing a conversion. When set by the user, starts a
conversion.
10.9.7 ITMR Register (Address X'00CF)
LSON HSON DCEN CCKS

EL RSVD ITSEL2 ITSEL1 ITSEL0 11.0 In-System Programming
Bit 7 Bit 0
11.1 INTRODUCTION
The ITMR register contains the following bits: This device provides the capability to program the program
LSON Turns the low speed oscillator on or off. memory while installed in an application board. This feature
HSON Turns the high speed oscillator on or off. is called In System Programming (ISP). It provides a means
of ISP by using the MICROWIRE/PLUS, or the user can
DCEN Selects the high speed oscillator or the low provide his own, customized ISP routine. The factory in-
speed oscillator as the Idle Timer Clock. stalled ISP uses the MICROWIRE/PLUS port. The user can
CCKSEL Selects the high speed oscillator or the low provide his own ISP routine that uses any of the capabilities
speed oscillator as the primary CPU clock. of the device, such as USART, parallel port, etc.
RSVD This bit is reserved and must be 0.
ITSEL2 Idle Timer period select bit. 11.2 FUNCTIONAL DESCRIPTION
ITSEL1 Idle Timer period select bit. The organization of the ISP feature consists of the user flash
program memory, the factory boot ROM, and some registers
ITSEL0 Idle Timer period select bit. dedicated to performing the ISP function. See Figure 13 for
a simplified block diagram. The factory installed ISP that
10.9.8 ENAD Register (Address X'00CB) uses MICROWIRE/PLUS is located in the Boot ROM. The
ADCH3 ADCH2 ADCH1 ADCH0 ADMOD MUX PSC ADBSY size of the Boot ROM is 1K bytes and also contains code to
Channel Select Mode Mux Out Prescale Busy facilitate in system emulation capability. If a user chooses to
Select write his own ISP routine, it must be located in the flash
Bit 7 Bit 0 program memory.
The ENAD register contains the following bits:

ADCH3 ADC channel select bit
10137417
FIGURE 13. Block Diagram of ISP
As described in 10.5 OPTION REGISTER, there is a bit, the erased state, the FLEX bit = 0 and the device will
FLEX, that controls whether the device exits RESET execut- power-up executing from Boot ROM. When FLEX = 0, this
ing from the flash memory or the Boot ROM. The user must assumes that either the MICROWIRE/PLUS ISP routine or
program the FLEX bit as appropriate for the application. In external programming is being used to program the device. If
www.national.com 28
11.0 In-System Programming TABLE 5. Low Byte of ISP Address
(Continued) ISPADLO
using the MICROWIRE/PLUS ISP routine, the software in
Addr 7 Addr 6 Addr 5 Addr 4 Addr 3 Addr 2 Addr 1 Addr 0
the boot ROM will monitor the MICROWIRE/PLUS for com-
mands to program the flash memory. When programming
the flash program memory is complete, the FLEX bit will 11.3.2 ISP Read Data Register
have to be programmed to a 1 and the device will have to be The Read Data Register (ISPRD) contains the value read
reset, either by pulling external Reset to ground or by a back from a read operation. This register can be accessed
MICROWIRE/PLUS ISP EXIT command, before execution from either flash program memory or Boot ROM. This regis-
from flash program memory will occur. ter is undefined on Reset.
If FLEX = 1, upon exiting Reset, the device will begin ex-
ecuting from location 0000 in the flash program memory. The
assumption, here, is that either the application is not using TABLE 6. ISP Read Data Register
ISP, is using MICROWIRE/PLUS ISP by jumping to it within ISPRD
the application code, or is using a customized ISP routine. If Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
a customized ISP routine is being used, then it must be Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
programmed into the flash memory by means of the
MICROWIRE/PLUS ISP or external programming as de-
scribed in the preceding paragraph. 11.3.3 ISP Write Data Register
The Write Data Register (ISPWR) contains the data to be
11.3 REGISTERS written into the specified address. This register is undeter-
There are six registers required to support ISP: Address mined on Reset. This register can be accessed from either
Register Hi byte (ISPADHI), Address Register Low byte flash program memory or Boot ROM. The Write Data register
(ISPADLO), Read Data Register (ISPRD), Write Data Reg- must be maintained for the entire duration of the operation.
ister (ISPWR), Write Timing Register (PGMTIM), and the
Control Register (ISPCNTRL). The ISPCNTRL Register is TABLE 7. ISP Write Data Register
not available to the user.
ISPWR
11.3.1 ISP Address Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
The address registers (ISPADHI & ISPADLO) are used to
specify the address of the byte of data being written or read.
For page erase operations, the address of the beginning of 11.3.4 ISP Write Timing Register
the page should be loaded. For mass erase operations,
The Write Timing Register (PGMTIM) is used to control the
0000 must be placed into the address registers. When read-
width of the timing pulses for write and erase operations. The
ing the Option register, FFFF (hex) should be placed into the
value to be written into this register is dependent on the
address registers. Registers ISPADHI and ISPADLO are
frequency of CKI and is shown in Table 8. This register must
cleared to 00 on Reset. These registers can be loaded from
be written before any write or erase operation can take
either flash program memory or Boot ROM and must be
place. It only needs to be loaded once, for each value of CKI
maintained for the entire duration of the operation.
frequency. This register can be loaded from either flash
Note: The actual memory address of the Option Register is program memory or Boot ROM and must be maintained for
7FFF (hex), however the MICROWIRE/PLUS ISP routines the entire duration of the operation. The MICROWIRE/PLUS
require the address FFFF (hex) to be used to read the ISP routine that is resident in the boot ROM requires that this
Option Register when the Flash Memory is secured. Register be defined prior to any access to the Flash memory.
Refer to 11.7 MICROWIRE/PLUS ISP for more information
TABLE 4. High Byte of ISP Address on available ISP commands. On Reset, the PGMTIM regis-
ter is loaded with the value that corresponds to 10 MHz
ISPADHi
frequency for CKI.
Addr 15 Addr 14 Addr 13 Addr 12 Addr 11 Addr 10 Addr 9 Addr 8
29 www.national.com
11.0 In-System Programming (Continued)
TABLE 8. PGMTIM Register Format

PGMTIM
Register Bit CKI Frequency Range
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 25 kHz–33.3 kHz
0 0 0 0 0 0 1 0 37.5 kHz–50 kHz
0 0 0 0 0 0 1 1 50 kHz–66.67 kHz
0 0 0 0 0 1 0 0 62.5 kHz–83.3 kHz
0 0 0 0 0 1 0 1 75 kHz–100 kHz
0 0 0 0 0 1 1 1 100 kHz–133 kHz
0 0 0 0 1 0 0 0 112.5 kHz–150 kHz
0 0 0 0 1 0 1 1 150 kHz–200 kHz
0 0 0 0 1 1 1 1 200 kHz–266.67 kHz
0 0 0 1 0 0 0 1 225 kHz–300 kHz
0 0 0 1 0 1 1 1 300 kHz–400 kHz
0 0 0 1 1 1 0 1 375 kHz–500 kHz
0 0 1 0 0 1 1 1 500 kHz–666.67 kHz
0 0 1 0 1 1 1 1 600 kHz–800 kHz
0 0 1 1 1 1 1 1 800 kHz–1.067 MHz
0 1 0 0 0 1 1 1 1 MHz–1.33 MHz
0 1 0 0 1 0 0 0 1.125 MHz–1.5 MHz
0 1 0 0 1 0 1 1 1.5 MHz–2 MHz
0 1 0 0 1 1 1 1 2 MHz–2.67 MHz
0 1 0 1 0 1 0 0 2.625 MHz–3.5 MHz
0 1 0 1 1 0 1 1 3.5 MHz–4.67 MHz
0 1 1 0 0 0 1 1 4.5 MHz–6 MHz
0 1 1 0 1 1 1 1 6 MHz–8 MHz
0 1 1 1 1 0 1 1 7.5 MHz–10 MHz
R R/W R/W R/W R/W R/W R/W R/W
11.4 MANEUVERING BACK AND FORTH BETWEEN be frozen until the breakpoint condition is cleared. If an
FLASH MEMORY AND BOOT ROM interrupt occurs while the key is set, the key will expire
When using ISP, at some point, it will be necessary to before interrupt service is complete. It is recommended that
maneuver between the flash program memory and the Boot the software globally disable interrupts before setting the
ROM, even when using customized ISP routines. This is key. The Key register is a memory mapped register. Its
because it’s not possible to execute from the flash program format when writing is shown in Table 9. In normal operation,
memory while it’s being programmed. it is not necessary to test the KEY bit before using the JSRB
instruction. The additional instructions required to test the
Two instructions are available to perform the jumping back
key may cause the key to time-out before the JSRB can be
and forth: Jump to Boot (JSRB) and Return to Flash (RETF).
executed.
The JSRB instruction is used to jump from flash memory to
Boot ROM, and the RETF is used to return from the Boot
ROM back to the flash program memory. See 20.0 Instruc- TABLE 9. KEY Register Write Format
tion Set for specific details on the operation of these instruc- KEY When Writing
tions.
The JSRB instruction must be used in conjunction with the 1 0 0 1 1 0 X X
Key register. This is to prevent jumping to the Boot ROM in
the event of run-away software. For the JSRB instruction to Bits 7–2: Key value that must be written to set the KEY bit.
actually jump to the Boot ROM, the Key bit must be set. This
Bits 1–0: Don’t care.
is done by writing the value shown in Table 9 to the Key
register. The Key is a 6 bit key and if the key matches, the 11.5 FORCED EXECUTION FROM BOOT ROM
KEY bit will be set for 8 instruction cycles. The JSRB instruc-
tion must be executed while the KEY bit is set. If the KEY When the user is developing a customized ISP routine, code
does not match, then the KEY bit will not be set and the lockups due to software errors may be encountered. The
JSRB will jump to the specified location in the flash memory. normal, and preferred, method to recover from these condi-
In emulation mode, if a breakpoint is encountered while the tions is to reprogram the device with the corrected code by
KEY is set, the counter that counts the instruction cycles will either an external parallel programmer or the emulation
www.national.com 30
11.0 In-System Programming 5. Pull RESET High.
(Continued) 6. After a delay of at least three instruction cycles, remove
the high voltage from G6.
tools. As a last resort, when this equipment is not available,
there is a hardware method to get out of these lockups and
force execution from the Boot ROM MICROWIRE/PLUS
routine. The customer will then be able to erase the Flash
Memory code and start over.
The method to force this condition is to drive the G6 pin to
high voltage (2 x VCC) and activate Reset. The high voltage
condition on G6 must not be applied before VCC is valid and
stable, and must be held for at least 3 instruction cycles
longer than Reset is active. This special condition will by-
pass checking the state of the Flex bit in the Option Register 10137466
and will start execution from location 0000 in the Boot ROM.
In this state, the user can input the appropriate commands, FIGURE 14. Circuit Diagram for Implementing the 2 x
using MICROWIRE/PLUS, to erase the flash program VCC
memory and reprogram it. If the device is subsequently reset
before the Flex bit has been erased by specific Page Erase
11.6 RETURN TO FLASH MEMORY WITHOUT
or Mass Erase ISP commands, execution will start from
HARDWARE RESET
location 0000 in the Flash program memory. The high volt-
age (2 x VCC) on G6 will not erase either the Flex or the After programming the entire program memory, including
Security bit in the Option Register. The Security bit, if set, options, it is necessary to exit the Boot ROM and return to
can only be erased by a Mass Erase of the entire contents of the flash program memory for program execution. Upon
the Flash Memory unless under the control of User ISP receipt and completion of the EXIT command through the
routines in the Application Program. MICROWIRE/PLUS ISP, the ISP code will reset the part and
begin execution from the flash program memory as de-
While the G6 pin is at high voltage, the Load Clock will be
scribed in the Reset section. This assumes that the FLEX bit
output onto G5, which will look like an SK clock to the
in the Option register was programmed to 1.
MICROWIRE/PLUS routine executing in slave mode. How-
ever, when G6 is at high voltage, the G6 input will also look
11.7 MICROWIRE/PLUS ISP
like a logic 1. The MICROWIRE/PLUS routine in Boot ROM
monitors the G6 input, waits for it to go low, debounces it, National Semiconductor provides a program, which is avail-
and then enables the ISP routine. CAUTION: The Load clock able from our web site at www.national.com/cop8, that is
on G5 could be in conflict with the user’s external SK. It is up capable of programming a device from the parallel port of a
to the user to resolve this conflict, as this condition is con- PC. The software accepts manually input commands and is
sidered a minor issue that’s only encountered during soft- capable of downloading standard Intel HEX Format files.
ware development. The user should also be cautious of Users who wish to write their own MICROWIRE/PLUS ISP
the high voltage applied to the G6 pin. This high voltage host software should refer to the COP8 FLASH ISP User
could damage other circuitry connected to the G6 pin Manual, available from the same web site. This document
(e.g. the parallel port of a PC). The user may wish to includes details of command format and delays necessary
disconnect other circuitry while G6 is connected to the high between command bytes.
voltage. The MICROWIRE/PLUS ISP supports the following features
VCC must be valid and stable before high voltage is applied and commands:
to G6. • Write a value to the ISP Write Timing Register. NOTE:
The correct sequence to be used to force execution from This must be the first command after entering
Boot ROM is : MICROWIRE/PLUS ISP mode.
1. Disconnect G6 from the source of data for MICROWIRE/ • Erase the entire flash program memory (mass erase).
PLUS ISP. • Erase a page at a specified address.
2. Apply VCC to the device. • Read Option register.
3. Pull RESET Low. • Read a byte from a specified address.
4. After VCC is valid and stable, connect a voltage between • Write a byte to a specified address.
2 x VCC and VCC+7V to the G6 pin. Ensure that the rise • Read multiple bytes starting at a specified address.
time of the high voltage on G6 is slower than the mini-
mum in the Electrical Specifications. Figure 14 shows a • Write multiple bytes starting at a specified address.
possible circuit dliagram for implementing the 2 x VCC. • Exit ISP and return execution to flash program memory.
Be aware of the typical input current on the G6 pin when The following table lists the MICROWIRE/PLUS ISP com-
the high voltage is applied. The resistor used in the RC mands and provides information on required parameters and
network, and the high voltage used, should be chosen to return values.
keep the high voltage at the G6 pin between 2 x VCC and
VCC+7V.
31 www.national.com
TABLE 10. MICROWIRE/PLUS ISP Commands

Command
Command Function Parameters Return Data
Value (Hex)
PGMTIM_SET Write Pulse Timing 0x3B Value N/A
Register
PAGE_ERASE Page Erase 0xB3 Starting Address of N/A
Page
MASS_ERASE Mass Erase 0xBF Confirmation Code N/A (The entire Flash
Memory will be erased)
READ_BYTE Read Byte 0x1D Address High, Address Data Byte if Security not
Low set. 0xFF if Security set.
Option Register if address
= 0xFFFF, regardless of
Security
BLOCKR Block Read 0xA3 Address High, Address n Data Bytes if Security
Low, Byte Count (n) not set.
High, Byte Count (n) n Bytes of 0xFF if
Low Security set.
0 ≤ n ≤ 32767
WRITE_BYTE Write Byte 0x71 Address High, Address N/A
Low, Data Byte
BLOCKW Block Write 0x8F Address High, Address N/A
Low, Byte Count (0 ≤ n
≤ 16), n Data Bytes
EXIT EXIT 0xD3 N/A N/A (Device will Reset)
INVALID N/A Any other invalid N/A
command will be
ignored
Note: The user must ensure that Block Writes do not cross a 64 byte boundary within one operation.
11.8 USER ISP AND VIRTUAL E2 • Copy a block of data from RAM into flash program
The following commands will support transferring blocks of memory.
data from RAM to flash program memory, and vice-versa. • Copy a block of data from program flash memory to RAM.
The user is expected to enforce application security in this The following table lists the User ISP/Virtual E2 commands,
case. required parameters and return data, if applicable. The com-
• Erase the entire flash program memory (mass erase). mand entry point is used as an argument to the JSRB
NOTE: Execution of this command will force the device instruction. Table 12 lists the Ram locations and Peripheral
into the MICROWIRE/PLUS ISP mode. Registers, used for User ISP and Virtual E2, and their ex-
• Erase a page of flash memory at a specified address. pected contents. Please refer to the COP8 FLASH ISP User
Manual for additional information and programming ex-
• Read a byte from a specified address.
amples on the use of User ISP and Virtual E2.
• Write a byte to a specified address.
www.national.com 32
TABLE 11. User ISP/Virtual E2 Entry Points

Command/ Command
Function Parameters Return Data
Label Entry Point
cpgerase Page Erase 0x17 Register ISPADHI is loaded by the user N/A (A page of memory beginning at
with the high byte of the address. ISPADHI, ISPADLO will be erased)
Register ISPADLO is loaded by the
user with the low byte of the address.
cmserase Mass Erase 0x1A Accumulator A contains the N/A (The entire Flash Memory will be
confirmation key 0x55. erased)
creadbf Read Byte 0x11 Register ISPADHI is loaded by the user Data Byte in Register ISPRD.
with the high byte of the address.
cblockr Block Read 0x26 Register ISPADHI is loaded by the user n Data Bytes, Data will be returned
with the high byte of the address. beginning at a location pointed to by
Register ISPADLO is loaded by the the RAM address in X.
X pointer contains the beginning RAM
address where the result(s) will be
returned.
Register BYTECOUNTLO contains the
number of n bytes to read
(0 ≤ n ≤ 255). It is up to the user to
setup the segment register.
cwritebf Write Byte 0x14 Register ISPADHI is loaded by the user N/A
Register ISPWR contains the Data
Byte to be written.
cblockw Block Write 0x23 Register ISPADHI is loaded by the user N/A
Register BYTECOUNTLO contains the
number of n bytes to write (0 ≤ n ≤ 16).
The combination of the
BYTECOUNTLO and the ISPADLO
registers must be set such that the
operation will not cross a 64 byte
boundary.
X pointer contains the beginning RAM
address of the data to be written.
It is up to the user to setup the
segment register.
exit EXIT 0x62 N/A N/A (Device will Reset)
uwisp MICROWIRE/ 0x00 N/A N/A (Device will be in
PLUS MICROWIRE/PLUS ISP Mode. Must be
ISP Start terminated by MICROWIRE/PLUS ISP
EXIT command which will Reset the
device)
33 www.national.com
TABLE 12. Register and Bit Name Definitions

Register RAM
Purpose
Name Location
ISPADHI High byte of Flash Memory Address 0xA9
ISPADLO Low byte of Flash Memory Address 0xA8
ISPWR The user must store the byte to be written into this register before jumping into the 0xAB
write byte routine.
ISPRD Data will be returned to this register after the read byte routine execution. 0xAA
ISPKEY The ISPKEY Register is required to validate the JSRB instruction and must be loaded 0xE2
within 6 instruction cycles before the JSRB.
BYTECOUNTLO Holds the count of the number of bytes to be read or written in block operations. 0xF1
PGMTIM Write Timing Register. This register must be loaded, by the user, with the proper value 0xE1
before execution of any USER ISP Write or Erase operation. Refer to Table 8 for the
correct value.
Confirmation Code The user must place this code in the accumulator before execution of a Flash Memory A
Mass Erase command.
KEY Must be transferred to the ISPKEY register before execution of a JSRB instruction. 0x98
11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING the same location in Flash memory. Two writes to
ISP ROUTINES IN BOOT ROM the same location without an intervening erase will
1. The hardware will disable interrupts from occurring. The produce unpredicatable results including possible
hardware will leave the GIE bit in its current state, and if disturbance of unassociated locations.
set, the hardware interrupts will occur when execution is
returned to Flash Memory. Subsequent interrupts, dur- 11.10 FLASH MEMORY DURABILITY CONSIDERATIONS
ing ISP operation, from the same interrupt source will be The endurance of the Flash Memory (number of possible
lost. Interrupts may occur between setting the KEY Erase/Write cycles) is a function of the erase time and the
and executing the JSRB instruction. In this case, the lowest temperature at which the erasure occurs. If the device
KEY will expire before the JSRB is executed. It is, is to be used at low temperature, additional erase operations
therefore, recommended that the software globally can be used to extend the erase time. The user can deter-
disable interrupts before setting the Key. mine how many times to erase a page based on what
2. The security feature in the MICROWIRE/PLUS ISP is endurance is desired for the application (e.g. four page
guaranteed by software and not hardware. When ex- erase cycles, each time a page erase is done, may be
ecuting the MICROWIRE/PLUS ISP routine, the security required to achieve the typical 100k Erase/Write cycles in an
bit is checked prior to performing all instructions. Only application which may be operating down to 0˚C). Also, the
the mass erase command, write PGMTIM register, and customer can verify that the entire page is erased, with
reading the Option register is permitted within the software, and request additional erase operations if desired.
MICROWIRE/PLUS ISP routine. When the user is per-
forming his own ISP, all commands are permitted. The TABLE 13. Typical Flash Memory Endurance
entry points from the user’s ISP code do not check for
security. It is the burden of the user to guarantee his own Low End of Operating Temp Range
security. See the Security bit description in 10.5 OPTION Erase −40˚C −20˚C 0˚C 25˚C > 25˚C
REGISTER for more details on security. Time
3. When using any of the ISP functions in Boot ROM, the 1 ms 60k 60k 60k 100k 100k
ISP routines will service the WATCHDOG within the
2 ms 60k 60k 60k 100k 100k
selected upper window. Upon return to flash memory,
the WATCHDOG is serviced, the lower window is en- 3 ms 60k 60k 60k 100k 100k
abled, and the user can service the WATCHDOG any- 4 ms 60k 60k 100k 100k 100k
time following exit from Boot ROM, but must service it
5 ms 70k 70k 100k 100k 100k
within the selected upper window to avoid a WATCH-
DOG error. 6 ms 80k 80k 100k 100k 100k
4. Block Writes can start anywhere in the page of Flash 7 ms 90k 90k 100k 100k 100k
memory, but cannot cross half page or full page bound- 8 ms 100k 100k 100k 100k 100k
aries.
5. The user must ensure that a page erase or a mass
erase is executed between two consecutive writes to
www.national.com 34
12.0 Timers • WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
The device contains a very versatile set of timers (T0, T1, T2
and T3). Timers T1, T2 and T3 and associated autoreload/ • Start up delay from BOR
capture registers power up containing random data. Figure 15 is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
12.1 TIMER T0 (IDLE TIMER) Bits 11 through 15 of the ITMR register can be selected for
The device supports applications that require maintaining triggering the IDLE Timer interrupt. Each time the selected
real time and low power with the IDLE mode. This IDLE bit underflows (every 4k, 8k, 16k, 32k or 64k selected
mode support is furnished by the IDLE Timer T0, which is a clocks), the IDLE Timer interrupt pending bit T0PND is set,
16-bit timer. The user cannot read or write to the IDLE Timer thus generating an interrupt (if enabled), and bit 6 of the Port
T0, which is a count down timer. G data register is reset, thus causing an exit from the IDLE
As described in 13.0 Power Saving Features, the clock to the mode if the device is in that mode.
IDLE Timer depends on which mode the device is in. If the In order for an interrupt to be generated, the IDLE Timer
device is in High Speed mode, the clock to the IDLE Timer is interrupt enable bit T0EN must be set, and the GIE (Global
the instruction cycle clock (one-fifth of the CKI frequency). If Interrupt Enable) bit must also be set. The T0PND flag and
the device is in Dual Clock mode or Low Speed mode, the T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
clock to the IDLE Timer is the 32 kHz clock. For the remain- tively. The interrupt can be used for any purpose. Typically, it
der of this section, the term “selected clock” will refer to the is used to perform a task upon exit from the IDLE mode. For
clock selected by the Power Save mode of the device. more information on the IDLE mode, refer to 13.0 Power
During Dual Clock and Low Speed modes, the divide by 10 Saving Features.
that creates the instruction cycle clock is disabled, to mini- The Idle Timer period is selected by bits 0–2 of the ITMR
mize power consumption. register Bit 3 of the ITMR Register is reserved and should
In addition to its time base function, the Timer T0 supports not be used as a software flag. Bits 4 through 7 of the ITMR
the following functions: Register are used by the dual clock and are described in
• Exit out of the Idle Mode (See Idle Mode description) 13.0 Power Saving Features.
10137418
FIGURE 15. Functional Block Diagram for Idle Timer T0
TABLE 14. Idle Timer Window Length Idle Timer Period

Idle Timer Period Dual Clock
ITSEL2 ITSEL1 ITSEL0 High Speed or
Dual Clock Mode Low Speed
ITSEL2 ITSEL1 ITSEL0 High Speed or Mode
Mode Low Speed
Mode 1 0 1 Reserved - Undefined
0 0 0 4,096 inst. 0.125 1 1 0 Reserved - Undefined
cycles seconds
1 1 1 Reserved - Undefined
0 0 1 8,192 inst. 0.25 seconds
cycles
The ITSEL bits of the ITMR register are cleared on Reset
0 1 0 16,384 inst. 0.5 seconds and the Idle Timer period is reset to 4,096 instruction cycles.
cycles
0 1 1 32,768 inst. 1 second
cycles
1 0 0 65,536 inst. 2 seconds
cycles
35 www.national.com
12.0 Timers (Continued) throughput. The user software services the timer block only
when the PWM parameters require updating. This capability
12.1.1 ITMR Register is provided by the fact that the timer has two separate 16-bit
reload registers. One of the reload registers contains the
LSON HSON DCEN CCK RSVD ITSEL2 ITSEL1 ITSEL0
SEL “ON” time while the other holds the “OFF” time. By contrast,
a microcontroller that has only a single reload register re-
quires an additional software to update the reload value
Bits 7–4: Described in 13.0 Power Saving Features. (alternate between the on-time/off-time).
Note: Documentation for previous COP8 devices, which in- The timer can generate the PWM output with the width and
cluded the Programmable Idle Timer, recommended the user duty cycle controlled by the values stored in the reload
write zero to the high order bits of the ITMR Register. If registers. The reload registers control the countdown values
existing programs are updated to use this device, writing and the reload values are automatically written into the timer
zero to these bits will cause the device to reset (see 13.0 when it counts down through 0, generating interrupt on each
Power Saving Features). reload. Under software control and with minimal overhead,
the PWM outputs are useful in controlling motors, triacs, the
RSVD: This bit is reserved and must be set to 0.
intensity of displays, and in providing inputs for data acqui-
ITSEL2:0: Selects the Idle Timer period as described in sition and sine wave generators.
Table 14, Idle Timer Window Length.
In this mode, the timer Tx counts down at a fixed rate of tC
Any time the IDLE Timer period is changed there is the (T2 and T3 may be selected to operate from MCLK). Upon
possibility of generating a spurious IDLE Timer interrupt by every underflow the timer is alternately reloaded with the
setting the T0PND bit. The user is advised to disable IDLE contents of supporting registers, RxA and RxB. The very first
Timer interrupts prior to changing the value of the ITSEL bits underflow of the timer causes the timer to reload from the
of the ITMR Register and then clear the T0PND bit before register RxA. Subsequent underflows cause the timer to be
attempting to synchronize operation to the IDLE Timer. reloaded from the registers alternately beginning with the
register RxB.
12.2 TIMER T1, TIMER T2, AND TIMER T3
Figure 16 shows a block diagram of the timer in PWM mode.
The device has a set of three powerful timer/counter blocks,
The underflows can be programmed to toggle the TxA output
T1, T2, and T3. Since T1, T2 and T3 are identical, except for
pin. The underflows can also be programmed to generate
the high speed operation of T2 and T3, all comments are
interrupts.
equally applicable to any of the three timer blocks which will
be referred to as Tx. Differences between the timers will be Underflows from the timer are alternately latched into two
specifically noted. pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control
Each timer block consists of a 16-bit timer, Tx, and two
enable flags, TxENA and TxENB, allow the interrupts from
supporting 16-bit autoreload/capture registers, RxA and
the timer underflow to be enabled or disabled. Setting the
RxB. Each timer block has two pins associated with it, TxA
timer enable flag TxENA will cause an interrupt when a timer
and TxB. The pin TxA supports I/O required by the timer
underflow causes the RxA register to be reloaded into the
block, while the pin TxB is an input to the timer block. The
timer. Setting the timer enable flag TxENB will cause an
timer block has three operating modes: Processor Indepen-
interrupt when a timer underflow causes the RxB register to
dent PWM mode, External Event Counter mode, and Input
be reloaded into the timer. Resetting the timer enable flags
Capture mode.
will disable the associated interrupts.
The control bits TxC3, TxC2, and TxC1 allow selection of the
Either or both of the timer underflow interrupts may be
different modes of operation.
enabled. This gives the user the flexibility of interrupting
12.2.1 Timer Operating Speeds once per PWM period on either the rising or falling edge of
the PWM output. Alternatively, the user may choose to inter-
Each of the Tx timers, except T1, have the ability to operate rupt on both edges of the PWM output.
at either the instruction cycle frequency (low speed) or the
internal clock frequency (MCLK). For 10 MHz CKI, the in-
struction cycle frequency is 2 MHz and the internal clock
frequency is 20 MHz. This feature is controlled by the High
Speed Timer Control Register, HSTCR. Its format is shown
below. To place a timer, Tx, in high speed mode, set the
appropriate TxHS bit to 1. For low speed operation, clear the
appropriate TxHS bit to 0. This register is cleared to 00 on
Reset.
HSTCR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit

1 0
0 0 0 0 0 0 T3HS T2HS
12.2.2 Mode 1. Processor Independent PWM Mode

One of the timer’s operating modes is the Processor Inde-
pendent PWM mode. In this mode, the timers generate a
“Processor Independent” PWM signal because once the
timer is set up, no more action is required from the CPU
which translates to less software overhead and greater
www.national.com 36
12.0 Timers (Continued)
12.2.4 Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode. In this mode, the reload registers serve
as independent capture registers, capturing the contents of
the timer when an external event occurs (transition on the
timer input pin). The capture registers can be read while
maintaining count, a feature that lets the user measure
elapsed time and time between events. By saving the timer
value when the external event occurs, the time of the exter-
nal event is recorded. Most microcontrollers have a latency
time because they cannot determine the timer value when
the external event occurs. The capture register eliminates
the latency time, thereby allowing the applications program
to retrieve the timer value stored in the capture register.
In this mode, the timer Tx is constantly running at the fixed tC
or MCLK rate. The two registers, RxA and RxB, act as
capture registers. Each register also acts in conjunction with
a pin. The register RxA acts in conjunction with the TxA pin
10137419 and the register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
FIGURE 16. Timer in PWM Mode trigger event occurs on its corresponding pin after synchro-
nization to the appropriate internal clock (tC or MCLK). Con-
trol bits, TxC3, TxC2 and TxC1, allow the trigger events to be
12.2.3 Mode 2. External Event Counter Mode specified either as a positive or a negative edge. The trigger
This mode is quite similar to the processor independent condition for each input pin can be specified independently.
PWM mode described above. The main difference is that the The trigger conditions can also be programmed to generate
timer, Tx, is clocked by the input signal from the TxA pin after interrupts. The occurrence of the specified trigger condition
synchronization to the appropriate internal clock (tC or on the TxA and TxB pins will be respectively latched into the
MCLK). The Tx timer control bits, TxC3, TxC2 and TxC1 pending flags, TxPNDA and TxPNDB. The control flag
allow the timer to be clocked either on a positive or negative TxENA allows the interrupt on TxA to be either enabled or
edge from the TxA pin. Underflows from the timer are latched disabled. Setting the TxENA flag enables interrupts to be
into the TxPNDA pending flag. Setting the TxENA control flag generated when the selected trigger condition occurs on the
will cause an interrupt when the timer underflows. TxA pin. Similarly, the flag TxENB controls the interrupts
In this mode the input pin TxB can be used as an indepen- from the TxB pin.
dent positive edge sensitive interrupt input if the TxENB Underflows from the timer can also be programmed to gen-
control flag is set. The occurrence of a positive edge on the erate interrupts. Underflows are latched into the timer TxC0
TxB input pin is latched into the TxPNDB flag. pending flag (the TxC0 control bit serves as the timer under-
Figure 17 shows a block diagram of the timer in External flow interrupt pending flag in the Input Capture mode). Con-
Event Counter mode. sequently, the TxC0 control bit should be reset when enter-
Note: The PWM output is not available in this mode since the ing the Input Capture mode. The timer underflow interrupt is
TxA pin is being used as the counter input clock. enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 18 shows a block diagram of the timer T1 in Input
Capture mode. T2 and T3 are identical to T1.
10137420
FIGURE 17. Timer in External Event Counter Mode
37 www.national.com
12.0 Timers (Continued) cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode
3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxENA Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
TxPNDB Timer Interrupt Pending Flag
TxENB Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (TxC3, TxC2 and TxC1) are
detailed in Table 15, Timer Operating Modes.
When the high speed timers are counting in high speed
mode, directly altering the contents of the timer upper or
lower registers, the PWM outputs or the reload registers is
not recommended. Bit operations can be particularly prob-
10137421 lematic. Since any of these six registers or the PWM outputs
can change as many as ten times in a single instruction
FIGURE 18. Timer in Input Capture Mode cycle, performing an SBIT or RBIT operation with the timer
running can produce unpredictable results. The recom-
mended procedure is to stop the timer, perform any changes
12.3 TIMER CONTROL FLAGS to the timer, the PWM outputs or reload register values, and
The control bits and their functions are summarized below. then re-start the timer. This warning does not apply to the
TxC3 Timer mode control timer control register. Any type of read/write operation, in-
cluding SBIT and RBIT may be performed on this register in
TxC2 Timer mode control
any operating mode.
TxC1 Timer mode control
TxC0 Timer Start/Stop control in Modes 1 and 2 (Pro-
TABLE 15. Timer Operating Modes

Interrupt A Interrupt B Timer
Mode TxC3 TxC2 TxC1 Description
Source Source Counts On
1 0 1 PWM: TxA Toggle Autoreload RA Autoreload RB tC or MCLK
1 1 0 0 PWM: No TxA Autoreload RA Autoreload RB tC or MCLK
Toggle
0 0 0 External Event Timer Underflow Pos. TxB Edge TxA Pos.
Counter Edge
2
0 0 1 External Event Timer Underflow Pos. TxB Edge TxA Neg.
Counter Edge
0 1 0 Captures: Pos. TxA Edge Pos. TxB Edge tC or MCLK
TxA Pos. Edge or Timer
TxB Pos. Edge Underflow
1 1 0 Captures: Pos. TxA Neg. TxB tC or MCLK
TxA Pos. Edge Edge or Timer Edge
TxB Neg. Edge Underflow
3
0 1 1 Captures: Neg. TxA Pos. TxB tC or MCLK
TxA Neg. Edge Edge or Timer Edge
TxB Pos. Edge Underflow
1 1 1 Captures: Neg. TxA Neg. TxB tC or MCLK
TxA Neg. Edge Edge or Timer Edge
TxB Neg. Edge Underflow
13.0 Power Saving Features applications demanding low power. The power budget con-
straints are also imposed on those consumer/industrial ap-
Today, the proliferation of battery-operated applications has plications where well regulated and expensive power supply
placed new demands on designers to drive power consump- costs cannot be tolerated. Such applications rely on low cost
tion down. Battery operated systems are not the only type of and low power supply voltage derived directly from the
www.national.com 38
13.0 Power Saving Features controller activities are stopped and power consumption is
reduced to a very low level. In this device, the HALT mode is
(Continued)
enabled and disabled by a bit in the Option register. The
“mains” by using voltage rectifier and passive components. IDLE mode is similar to the HALT mode, except that certain
Low power is demanded even in automotive applications, sections of the device continue to operate, such as: the
due to increased vehicle electronics content. This is required on-board oscillator, the IDLE Timer (Timer T0), and the Clock
to ease the burden from the car battery. Low power 8-bit Monitor. This allows real time to be maintained. During
microcontrollers supply the smarts to control battery- power save modes of operation, all on board RAM, registers,
operated, consumer/industrial, and automotive applications. I/O states and timers (with the exception of T0) are unal-
The device offers system designers a variety of low-power tered.
consumption features that enable them to meet the demand- Two oscillators are used to support the three different oper-
ing requirements of today’s increasing range of low-power ating modes. The high speed oscillator refers to the oscillator
applications. These features include low voltage operation, connected to CKI and the low speed oscillator refers to the
low current drain, and power saving features such as HALT, 32 kHz oscillator connected to pins L0 & L1. When using L0
IDLE, and Multi-Input Wake-Up (MIWU). and L1 for the low speed oscillator, the user must ensure that
This device supports three operating modes, each of which the L0 and L1 pins are configured for hi-Z input, L1 is not
have two power save modes of operation. The three operat- using CKX on the USART, and Multi-Input Wake-up for these
ing modes are: High Speed, Dual Clock, and Low Speed. pins is disabled.
Within each operating mode, the two power save modes are: A diagram of the three modes is shown in Figure 19.
HALT and IDLE. In the HALT mode of operation, all micro-
10137422
FIGURE 19. Diagram of Power Save Modes
13.1 POWER SAVE MODE CONTROL REGISTER oscillator. See the startup time table in the Os-
The ITMR control register allows for navigation between the cillator Circuits section.
three different modes of operation. It is also used for the Idle DCEN: This bit selects the clock source for the Idle
Timer. The register bit assignments are shown below. This Timer. If this bit = 0, then the high speed clock is
register is cleared to 40 (hex) by Reset as shown below. the clock source for the Idle Timer. If this bit = 1,
then the low speed clock is the clock source for
LSON HSON DCEN CCK RSVD ITSEL2 ITSEL1 ITSEL0
SEL the Idle Timer. The low speed oscillator must be
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 started and stabilized before setting this bit to a
1.
LSON: This bit is used to turn-on the low-speed oscilla- CCKSEL: This bit selects whether the high speed clock or
tor. When LSON = 0, the low speed oscillator is low speed clock is gated to the microcontroller
off. When LSON = 1, the low speed oscillator is core. When this bit = 0, the Core clock will be the
on. There is a startup time associated with this high speed clock. When this bit = 1, then the
oscillator. See the Oscillator Circuits section. Core clock will be the low speed clock. Before
HSON: This bit is used to turn-on the high speed oscil- switching this bit to either state, the appropriate
lator. When HSON = 0, the high speed oscillator clock should be turned on and stabilized.
is off. When HSON = 1, the high speed oscillator
is on. There is a startup time associated with this
39 www.national.com
13.0 Power Saving Features mode. The controller also stops the CKI pin from oscillating
during the HALT mode. The processor can be forced to exit
(Continued)
the HALT mode and resume normal operation at any time.
DCEN CCKSEL During normal operation, the actual power consumption de-
pends heavily on the clock speed and operating voltage
0 0 High Speed Mode. Core and Idle Timer
used in an application and is shown in the Electrical Speci-
Clock = High Speed fications. In the HALT mode, the device only draws a small
1 0 Dual Clock Mode. Core clock = High leakage current, plus current for the BOR feature (if en-
Speed; Idle Timer = Low Speed abled), plus any current necessary for driving the outputs.
Since total power consumption is affected by the amount of
1 1 Low Speed Mode. Core and Idle Timer
current required to drive the outputs, all I/Os should be
Clock = Low Speed configured to draw minimal current prior to entering the
0 1 Invalid. If this is detected, the Low HALT mode, if possible. In order to reduce power consump-
Speed Mode will be forced. tion even further, the power supply (VCC) can be reduced to
a very low level during the HALT mode, just high enough to
RSVD: This bit is reserved and must be 0. guarantee retention of data stored in RAM. The allowed
Bits 2–0: These are bits used to control the Idle Timer. See lower voltage level (VR) is specified in the Electrical Specs
12.1 TIMER T0 (IDLE TIMER) for the description section.
of these bits.
13.3.1.1 Entering The High Speed Halt Mode
Table 16 lists the valid contents of the four most significant
bits of the ITMR Register. Any other value is illegal. States The device enters the HALT mode under software control
are presented in the only valid sequence. Any attempt to when the Port G data register bit 7 is set to 1. All processor
make a transition to any state other than an adjacent valid action stops in the middle of the next instruction cycle, and
state will be ignored by the logic and the ITMR Register will power consumption is reduced to a very low level.
not be changed.
13.3.1.2 Exiting The High Speed Halt Mode
There is a choice of methods for exiting the HALT mode: a
TABLE 16. Valid Contents of Dual Clock Control Bits
chip Reset using the RESET pin or a Multi-Input Wake-up.
LSON HSON DCEN CCKSEL Mode
13.3.1.3 HALT Exit Using Reset
0 1 0 0 High Speed
A device Reset, which is invoked by a low-level signal on the
1 1 0 0 High Speed/Dual
RESET input pin, takes the device out of the HALT mode
Clock Transition and starts execution from address 0000H. The initialization
1 1 1 0 Dual Clock software should determine what special action is needed, if
1 1 1 1 Dual Clock/Low any, upon start-up of the device from HALT. The initialization
of all registers following a RESET exit from HALT is de-
Speed Transition
scribed in the Reset section of this manual.
1 0 1 1 Low Speed
13.3.1.4 HALT Exit Using Multi-Input Wake-up
13.2 OSCILLATOR STABILIZATION The device can be brought out of the HALT mode by a
Both the high speed oscillator and low speed oscillator have transition received on one of the available Wake-up pins.
a startup delay associated with them. When switching be- The pins used and the types of transitions sensed on the
tween the modes, the software must ensure that the appro- Multi-input pins are software programmable. For information
priate oscillator is started up and stabilized before switching on programming and using the Multi-Input Wake-up feature,
to the new mode. See Table 3, Startup Times for approxi- refer to the Multi-Input Wake-up section.
mate startup times for both oscillators. A start-up delay is required between the device wake-up and
the execution of program instructions, depending on the type
13.3 HIGH SPEED MODE OPERATION of chip clock. The start-up delay is mandatory, and is imple-
This mode of operation allows high speed operation for both mented whether or not the CLKDLY bit is set. This is be-
the main Core clock and also for the Idle Timer. This is the cause all crystal oscillators and resonators require some
default mode of the device and will always be entered upon time to reach a stable frequency and full operating ampli-
any of the Reset conditions described in the Reset section. It tude.
can also be entered from Dual Clock mode. It cannot be The IDLE Timer (Timer T0) provides a fixed delay from the
directly entered from the Low Speed mode without passing time the clock is enabled to the time the program execution
through the Dual Clock mode first. begins. Upon exit from the HALT mode, the IDLE Timer is
To enter from the Dual Clock mode, the following sequence enabled with a starting value of 256 and is decremented with
must be followed using two separate instructions: each instruction cycle. (The instruction clock runs at one-fifth
the frequency of the high speed oscillator.) An internal
1. Software clears DCEN to 0.
Schmitt trigger connected to the on-chip CKI inverter en-
2. Software clears LSON to 0. sures that the IDLE Timer is clocked only when the oscillator
has a large enough amplitude. (The Schmitt trigger is not
13.3.1 High Speed Halt Mode part of the oscillator closed loop.) When the IDLE Timer
The fully static architecture of this device allows the state of underflows, the clock signals are enabled on the chip, allow-
the microcontroller to be frozen. This is accomplished by ing program execution to proceed. Thus, the delay is equal
stopping the internal clock of the device during the HALT to 256 instruction cycles.
www.national.com 40
13.0 Power Saving Features disable HALT mode option will cause the microcontroller to
ignore any attempts to HALT the device under software
(Continued)
control. Note that this device can still be placed in the HALT
Note: To ensure accurate operation upon start-up of the mode by stopping the clock input to the microcontroller, if the
device using Multi-input Wake-up, the instruction in the ap- program memory is masked ROM. See the Option section
plication program used for entering the HALT mode should for more details on this option bit.
be followed by two consecutive NOP (no-operation) instruc-
tions.
13.3.1.5 Options
This device has two options associated with the HALT mode.
The first option enables the HALT mode feature, while the
second option disables HALT mode operation. Selecting the
10137423
FIGURE 20. Wake-up from HALT
13.3.2 High Speed Idle Mode As with the HALT mode, this device can also be returned to
In the IDLE mode, program execution stops and power normal operation with a reset, or with a Multi-Input Wake-up
consumption is reduced to a very low level as with the HALT input. Upon reset the ITMR register is cleared and the ITMR
mode. However, the high speed oscillator, IDLE Timer (Timer register selects the 4,096 instruction cycle tap of the Idle
T0), and Clock Monitor continue to operate, allowing real Timer.
time to be maintained. The device remains idle for a selected The IDLE Timer cannot be started or stopped under software
amount of time up to 65,536 instruction cycles, or 32.768 control, and it is not memory mapped, so it cannot be read or
milliseconds with a 2 MHz instruction clock frequency, and written by the software. Its state upon Reset is unknown.
then automatically exits the IDLE mode and returns to nor- Therefore, if the device is put into the IDLE mode at an
mal program execution. arbitrary time, it will stay in the IDLE mode for somewhere
The device is placed in the IDLE mode under software between 1 and the selected number of instruction cycles.
control by setting the IDLE bit (bit 6 of the Port G data In order to precisely time the duration of the IDLE state, entry
register). into the IDLE mode must be synchronized to the state of the
The IDLE Timer window is selectable from one of five values, IDLE Timer. The best way to do this is to use the IDLE Timer
4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this interrupt, which occurs on every underflow of the bit of the
value is made through the ITMR register. IDLE Timer which is associated with the selected window.
Another method is to poll the state of the IDLE Timer pending
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to
bit T0PND, which is set on the same occurrence. The Idle
keep track of elapsed time in the IDLE state. The IDLE Timer
Timer interrupt is enabled by setting bit T0EN in the ICNTRL
runs continuously at the instruction clock rate, whether or not
register.
the device is in the IDLE mode. Each time the bit of the timer
associated with the selected window toggles, the T0PND bit Any time the IDLE Timer window length is changed there is
is set, an interrupt is generated (if enabled), and the device the possibility of generating a spurious IDLE Timer interrupt
exits the IDLE mode if in that mode. If the IDLE Timer by setting the T0PND bit. The user is advised to disable
interrupt is enabled, the interrupt is serviced before execu- IDLE Timer interrupts prior to changing the value of the
tion of the main program resumes. (However, the instruction ITSEL bits of the ITMR Register and then clear the TOPND
which was started as the part entered the IDLE mode is bit before attempting to synchronize operation to the IDLE
completed before the interrupt is serviced. This instruction Timer.
should be a NOP which should follow the enter IDLE instruc- Note: As with the HALT mode, it is necessary to program two
tion.) The user must reset the IDLE Timer pending flag NOP’s to allow clock resynchronization upon return from the
(T0PND) before entering the IDLE mode.
41 www.national.com
13.0 Power Saving Features 13.4.1.3 HALT Exit Using Reset
(Continued) A device Reset, which is invoked by a low-level signal on the
RESET input pin, takes the device out of the Dual Clock
IDLE mode. The NOP’s are placed either at the beginning of mode and puts it into the High Speed mode.
the IDLE Timer interrupt routine or immediately following the
“enter IDLE mode” instruction. 13.4.1.4 HALT Exit Using Multi-Input Wake-up
For more information on the IDLE Timer and its associated The device can be brought out of the HALT mode by a
interrupt, see the description in the Timers section. transition received on one of the available Wake-up pins.
The pins used and the types of transitions sensed on the
13.4 DUAL CLOCK MODE OPERATION Multi-input pins are software programmable. For information
This mode of operation allows for high speed operation of on programming and using the Multi-Input Wake-up feature,
the Core clock and low speed operation of the Idle Timer. refer to 13.6 MULTI-INPUT WAKE-UP.
This mode can be entered from either the High Speed mode A start-up delay is required between the device wake-up and
or the Low Speed mode. the execution of program instructions. The start-up delay is
To enter from the High Speed mode, the following sequence mandatory, and is implemented whether or not the CLKDLY
must be followed: bit is set. This is because all crystal oscillators and resona-
1. Software sets the LSON bit to 1. tors require some time to reach a stable frequency and full
operating amplitude.
2. Software waits until the low speed oscillator has stabi-
lized. See Table 3. If the start-up delay is used, the IDLE Timer (Timer T0)
provides a fixed delay from the time the clock is enabled to
3. Software sets the DCEN bit to 1. the time the program execution begins. Upon exit from the
To enter from the Low Speed mode, the following sequence HALT mode, the IDLE Timer is enabled with a starting value
must be followed: of 256 and is decremented with each instruction cycle using
1. Software sets the HSON bit to 1. the high speed clock. (The instruction clock runs at one-fifth
2. Software waits until the high speed oscillator has stabi- the frequency of the high speed oscillatory.) An internal
lized. See Table 3, Startup Times. Schmitt trigger connected to the on-chip CKI inverter en-
sures that the IDLE Timer is clocked only when the high
3. Software clears the CCKSEL bit to 0.
speed oscillator has a large enough amplitude. (The Schmitt
trigger is not part of the oscillator closed loop.) When the
13.4.1 Dual Clock HALT Mode
IDLE Timer underflows, the clock signals are enabled on the
The fully static architecture of this device allows the state of chip, allowing program execution to proceed. Thus, the delay
the microcontroller to be frozen. This is accomplished by is equal to 256 instruction cycles. After exiting HALT, the Idle
stopping the high speed clock of the device during the HALT Timer will return to being clocked by the low speed clock.
mode. The processor can be forced to exit the HALT mode
Note: To ensure accurate operation upon start-up of the
and resume normal operation at any time. The low speed
device using Multi-input Wake-up, the instruction in the ap-
clock remains on during HALT in the Dual Clock mode.
plication program used for entering the HALT mode should
During normal operation, the actual power consumption de- be followed by two consecutive NOP (no-operation) instruc-
pends heavily on the clock speed and operating voltage tions.
used in an application and is shown in the Electrical Speci-
fications. In the HALT mode, the device only draws a small 13.4.1.5 Options
leakage current, plus current for the BOR feature (if en-
This device has two options associated with the HALT mode.
abled), plus the 32 kHz oscillator current, plus any current
The first option enables the HALT mode feature, while the
necessary for driving the outputs. Since total power con-
second option disables HALT mode operation. Selecting the
sumption is affected by the amount of current required to
disable HALT mode option will cause the microcontroller to
drive the outputs, all I/Os should be configured to draw
ignore any attempts to HALT the device under software
minimal current prior to entering the HALT mode, if possible.
control. See 10.5 OPTION REGISTER for more details on
this option bit.
13.4.1.1 Entering The Dual Clock Halt Mode
The device enters the HALT mode under software control 13.4.2 Dual Clock Idle Mode
when the Port G data register bit 7 is set to 1. All processor
In the IDLE mode, program execution stops and power
action stops in the middle of the next instruction cycle, and
consumption is reduced to a very low level as with the HALT
power consumption is reduced to a very low level. In order to
mode. However, both oscillators, IDLE Timer (Timer T0), and
expedite exit from HALT, the low speed oscillator is left
Clock Monitor continue to operate, allowing real time to be
running when the device is Halted in the Dual Clock mode.
maintained. The Idle Timer is clocked by the low speed
However, the Idle Timer will not be clocked.
clock. The device remains idle for a selected amount of time
up to 1 second, and then automatically exits the IDLE mode
13.4.1.2 Exiting The Dual Clock Halt Mode
and returns to normal program execution using the high
When the HALT mode is entered by setting bit 7 of the Port speed clock.
G data register, there is a choice of methods for exiting the
The device is placed in the IDLE mode under software
HALT mode: a chip Reset using the RESET pin or a Multi-
control by setting the IDLE bit (bit 6 of the Port G data
Input Wake-up. The Reset method and Multi-Input Wake-up
register).
method can be used with any clock option.
The IDLE Timer window is selectable from one of five values,
0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second and
2 seconds. Selection of this value is made through the ITMR
register.
www.national.com 42
13.0 Power Saving Features 13.5.1 Low Speed HALT Mode
(Continued) The fully static architecture of this device allows the state of
the microcontroller to be frozen. Because the low speed
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to oscillator draws very minimal operating current, it will be left
keep track of elapsed time in the IDLE state. The IDLE Timer running in the low speed halt mode. However, the Idle Timer
runs continuously at the low speed clock rate, whether or not will not be running. This also allows for a faster exit from
the device is in the IDLE mode. Each time the bit of the timer HALT. The processor can be forced to exit the HALT mode
associated with the selected window toggles, the T0PND bit and resume normal operation at any time.
is set, an interrupt is generated (if enabled), and the device During normal operation, the actual power consumption de-
exits the IDLE mode if in that mode. If the IDLE Timer pends heavily on the clock speed and operating voltage
interrupt is enabled, the interrupt is serviced before execu- used in an application and is shown in the Electrical Speci-
tion of the main program resumes. (However, the instruction fications. In the HALT mode, the device only draws a small
which was started as the part entered the IDLE mode is leakage current, plus current for the BOR feature (if en-
completed before the interrupt is serviced. This instruction abled), plus the 32 kHz oscillator current, plus any current
should be a NOP which should follow the enter IDLE instruc- necessary for driving the outputs. Since total power con-
tion.) The user must reset the IDLE Timer pending flag sumption is affected by the amount of current required to
(T0PND) before entering the IDLE mode. drive the outputs, all I/Os should be configured to draw
As with the HALT mode, this device can also be returned to minimal current prior to entering the HALT mode, if possible.
normal operation with a Multi-Input Wake-up input.
The IDLE Timer cannot be started or stopped under software 13.5.1.1 Entering The Low Speed Halt Mode
control, and it is not memory mapped, so it cannot be read or The device enters the HALT mode under software control
written by the software. Its state upon Reset is unknown. when the Port G data register bit 7 is set to 1. All processor
Therefore, if the device is put into the IDLE mode at an action stops in the middle of the next instruction cycle, and
arbitrary time, it will stay in the IDLE mode for somewhere power consumption is reduced to a very low level. In order to
between 30 µs and the selected time period. expedite exit from HALT, the low speed oscillator is left
In order to precisely time the duration of the IDLE state, entry running when the device is Halted in the Low Speed mode.
into the IDLE mode must be ”synchronized to the state of the However, the Idle Timer will not be clocked.
IDLE Timer. The best way to do this is to use the IDLE Timer
interrupt, which occurs on every underflow of the bit of the 13.5.1.2 Exiting The Low Speed Halt Mode
IDLE Timer which is associated with the selected window. When the HALT mode is entered by setting bit 7 of the Port
Another method is to poll the state of the IDLE Timer pending G data register, there is a choice of methods for exiting the
bit T0PND, which is set on the same occurrence. The Idle HALT mode: a chip Reset using the RESET pin or a Multi-
Timer interrupt is enabled by setting bit T0EN in the ICNTRL Input Wake-up. The Reset method and Multi-Input Wake-up
register. method can be used with any clock option, but the availabil-
Any time the IDLE Timer window length is changed there is ity of the G7 input is dependent on the clock option.
the possibility of generating a spurious IDLE Timer interrupt
by setting the T0PND bit. The user is advised to disable 13.5.1.3 HALT Exit Using Reset
IDLE Timer interrupts prior to changing the value of the A device Reset, which is invoked by a low-level signal on the
ITSEL bits of the ITMR Register and then clear the T0PND RESET input pin, takes the device out of the Low Speed
bit before attempting to synchronize operation to the IDLE mode and puts it into the High Speed mode.
Timer.
Note: As with the HALT mode, it is necessary to program two 13.5.1.4 HALT Exit Using Multi-Input Wake-up
NOP’s to allow clock resynchronization upon return from the The device can be brought out of the HALT mode by a
IDLE mode. The NOP’s are placed either at the beginning of transition received on one of the available Wake-up pins.
the IDLE Timer interrupt routine or immediately following the The pins used and the types of transitions sensed on the
“enter IDLE mode” instruction. Multi-input pins are software programmable. For information
For more information on the IDLE Timer and its associated on programming and using the Multi-Input Wake-up feature,
interrupt, see the description in the Timers section. refer to the Multi-Input Wake-up section.
As the low speed oscillator is left running, there is no start up
13.5 LOW SPEED MODE OPERATION delay when exiting the low speed halt mode, regardless of
This mode of operation allows for low speed operation of the the state of the CLKDLY bit.
core clock and low speed operation of the Idle Timer. Be- Note: To ensure accurate operation upon start-up of the
cause the low speed oscillator draws very little operating device using Multi-input Wake-up, the instruction in the ap-
current, and also to expedite restarting from HALT mode, the plication program used for entering the HALT mode should
low speed oscillator is left on at all times in this mode, be followed by two consecutive NOP (no-operation) instruc-
including HALT mode. This is the lowest power mode of tions.
operation on the device. This mode can only be entered from
the Dual Clock mode. 13.5.1.5 Options
To enter the Low Speed mode, the following sequence must This device has two options associated with the HALT mode.
be followed using two separate instructions: The first option enables the HALT mode feature, while the
1. Software sets the CCKSEL bit to 1. second option disables HALT mode operation. Selecting the
disable HALT mode option will cause the microcontroller to
2. Software clears the HSON bit to 0. ignore any attempts to HALT the device under software
Since the low speed oscillator is already running, there is no control. See the Option section for more details on this
clock startup delay. option bit.
43 www.national.com
13.0 Power Saving Features As with the HALT mode, this device can also be returned to
normal operation with a Multi-Input Wake-up input.
(Continued)
The IDLE Timer cannot be started or stopped under software
13.5.2 Low Speed Idle Mode control, and it is not memory mapped, so it cannot be read or
In the IDLE mode, program execution stops and power written by the software. Its state upon Reset is unknown.
consumption is reduced to a very low level as with the HALT Therefore, if the device is put into the IDLE mode at an
mode. However, the low speed oscillator, IDLE Timer (Timer arbitrary time, it will stay in the IDLE mode for somewhere
T0), and Clock Monitor continue to operate, allowing real between 30 µs and the selected time period.
time to be maintained. The device remains idle for a selected In order to precisely time the duration of the IDLE state, entry
amount of time up to 2 seconds, and then automatically exits into the IDLE mode must be synchronized to the state of the
the IDLE mode and returns to normal program execution IDLE Timer. The best way to do this is to use the IDLE Timer
using the low speed clock. interrupt, which occurs on every underflow of the bit of the
The device is placed in the IDLE mode under software IDLE Timer which is associated with the selected window.
control by setting the IDLE bit (bit 6 of the Port G data Another method is to poll the state of the IDLE Timer pending
register). bit T0PND, which is set on the same occurrence. The Idle
The IDLE Timer window is selectable from one of five values, Timer interrupt is enabled by setting bit T0EN in the ICNTRL
0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second, and register.
2 seconds. Selection of this value is made through the ITMR Any time the IDLE Timer window length is changed there is
register. the possibility of generating a spurious IDLE Timer interrupt
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to by setting the T0PND bit. The user is advised to disable
keep track of elapsed time in the IDLE state. The IDLE Timer IDLE Timer interrupts prior to changing the value of the
runs continuously at the low speed clock rate, whether or not ITSEL bits of the ITMR Register and then clear the T0PND
the device is in the IDLE mode. Each time the bit of the timer bit before attempting to synchronize operation to the IDLE
associated with the selected window toggles, the T0PND bit Timer.
is set, an interrupt is generated (if enabled), and the device As with the HALT mode, it is necessary to program two
exits the IDLE mode if in that mode. If the IDLE Timer NOP’s to allow clock resynchronization upon return from the
interrupt is enabled, the interrupt is serviced before execu- IDLE mode. The NOP’s are placed either at the beginning of
tion of the main program resumes. (However, the instruction the IDLE Timer interrupt routine or immediately following the
which was started as the part entered the IDLE mode is “enter IDLE mode” instruction.
completed before the interrupt is serviced. This instruction For more information on the IDLE Timer and its associated
should be a NOP which should follow the enter IDLE instruc- interrupt, see the description in the Section 6.1, Timer T0
tion.) The user must reset the IDLE Timer pending flag (IDLE Timer).
(T0PND) before entering the IDLE mode.
10137424
FIGURE 21. Multi-Input Wake-Up Logic
www.national.com 44
13.0 Power Saving Features be set or reset for the desired edge selects, followed by the
associated WKPND bits being cleared.
(Continued)
This same procedure should be used following reset, since
13.6 MULTI-INPUT WAKE-UP the L port inputs are left floating as a result of reset.
The Multi-Input Wake-up feature is used to return (wake-up) The occurrence of the selected trigger condition for Multi-
the device from either the HALT or IDLE modes. Alternately Input Wake-up is latched into a pending register called
Multi-Input Wake-up/Interrupt feature may also be used to WKPND. The respective bits of the WKPND register will be
generate up to 8 edge selectable external interrupts. set on the occurrence of the selected trigger edge on the
Figure 21 shows the Multi-Input Wake-up logic. corresponding Port L pin. The user has the responsibility of
The Multi-Input Wake-up feature utilizes the L Port. The user clearing these pending flags. Since WKPND is a pending
selects which particular L port bit (or combination of L Port register for the occurrence of selected wake-up conditions,
bits) will cause the device to exit the HALT or IDLE modes. the device will not enter the HALT mode if any Wake-up bit is
The selection is done through the register WKEN. The reg- both enabled and pending. Consequently, the user must
ister WKEN is an 8-bit read/write register, which contains a clear the pending flags before attempting to enter the HALT
control bit for every L port bit. Setting a particular WKEN bit mode.
enables a Wake-up from the associated L port pin. WKEN and WKEDG are all read/write registers, and are
The user can select whether the trigger condition on the cleared at reset. WKPND register contains random value
selected L Port pin is going to be either a positive edge (low after reset.
to high transition) or a negative edge (high to low transition).
This selection is made via the register WKEDG, which is an 14.0 USART
8-bit control register with a bit assigned to each L Port pin. The device contains a full-duplex software programmable
Setting the control bit will select the trigger condition to be a USART. The USART (Figure 22) consists of a transmit shift
negative edge on that particular L Port pin. Resetting the bit register, a receive shift register and seven addressable reg-
selects the trigger condition to be a positive edge. Changing isters, as follows: a transmit buffer register (TBUF), a re-
an edge select entails several steps in order to avoid a ceiver buffer register (RBUF), a USART control and status
Wake-up condition as a result of the edge change. First, the register (ENU), a USART receive control and status register
associated WKEN bit should be reset, followed by the edge (ENUR), a USART interrupt and clock source register
select change in WKEDG. Next, the associated WKPND bit (ENUI), a prescaler select register (PSR) and baud (BAUD)
should be cleared, followed by the associated WKEN bit register. The ENU register contains flags for transmit and
being re-enabled. receive functions; this register also determines the length of
An example may serve to clarify this procedure. Suppose we the data frame (7, 8 or 9 bits), the value of the ninth bit in
wish to change the edge select from positive (low going high) transmission, and parity selection bits. The ENUR register
to negative (high going low) for L Port bit 5, where bit 5 has flags framing, data overrun, parity errors and line breaks
previously been enabled for an input interrupt. The program while the USART is receiving.
would be as follows: Other functions of the ENUR register include saving the
RBIT 5, WKEN ; Disable MIWU ninth bit received in the data frame, enabling or disabling the
SBIT 5, WKEDG ; Change edge polarity USART’s attention mode of operation and providing addi-
RBIT 5, WKPND ; Reset pending flag tional receiver/transmitter status information via RCVG and
SBIT 5, WKEN ; Enable MIWU XMTG bits. The determination of an internal or external clock
If the L port bits have been used as outputs and then source is done by the ENUI register, as well as selecting the
changed to inputs with Multi-Input Wake-up/Interrupt, a number of stop bits and enabling or disabling transmit and
safety procedure should also be followed to avoid wake-up receive interrupts. A control flag in this register can also
conditions. After the selected L port bits have been changed select the USART mode of operation: asynchronous or
from output to input but before the associated WKEN bits are synchronous.
enabled, the associated edge select bits in WKEDG should
45 www.national.com
14.0 USART (Continued)
10137425
FIGURE 22. USART Block Diagram
14.1 USART CONTROL AND STATUS REGISTERS PEN: This bit enables/disables Parity (7- and 8-bit modes
The operation of the USART is programmed through three only). Read/Write, cleared on reset.
registers: ENU, ENUR and ENUI. PEN = 0 Parity disabled.
PEN = 1 Parity enabled.
14.2 DESCRIPTION OF USART REGISTER BITS
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on
ENU — USART CONTROL AND STATUS REGISTER (Ad- reset.
dress at 0BA)
PSEL1 = 0, PSEL0 = 0 Odd Parity (if Parity enabled)
PEN PSEL1 XBIT9/ CHL1 CHL0 ERR RBFL TBMT PSEL1 = 0, PSEL1 = 1 Even Parity (if Parity enabled)
PSEL0 PSEL1 = 1, PSEL0 = 0 Mark(1) (if Parity enabled)
Bit 7 Bit 0 PSEL1 = 1, PSEL1 = 1 Space(0) (if Parity enabled)
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14.0 USART (Continued) XMTG: This bit is set to indicate that the USART is transmit-
ting. It gets reset at the end of the last frame (end of last Stop
XBIT9/PSEL0: Programs the ninth bit for transmission when bit). Read only, cleared on reset.
the USART is operating with nine data bits per frame. For RCVG: This bit is set high whenever a framing error or a
seven or eight data bits per frame, this bit in conjunction with break detect occurs and goes low when RDX goes high.
PSEL1 selects parity. Read/Write, cleared on reset. Read only, cleared on reset.
CHL1, CHL0: These bits select the character frame format. ENUI — USART INTERRUPT AND CLOCK SOURCE REG-
Parity is not included and is generated/verified by hardware. ISTER (Address at 0BC)
Read/Write, cleared on reset.
STP2 BRK ETDX SSEL XRCLK XTCLK ERI ETI
CHL1 = 0, CHL0 = 0 The frame contains eight data bits.
Bit 7 Bit 0
CHL1 = 0, CHL0 = 1 The frame contains seven data bits.
CHL1 = 1, CHL0 = 0 The frame contains nine data bits. STP2: This bit programs the number of Stop bits to be
CHL1 = 1, CHL0 = 1 Loopback Mode selected. Trans- transmitted. Read/Write, cleared on reset.
mitter output internally looped back STP2 = 0 One Stop bit transmitted.
to receiver input. Nine bit framing STP2 = 1 Two Stop bits transmitted.
format is used.
BRK: Holds TDX (USART Transmit Pin) low to generate a
ERR: This bit is a global USART error flag which gets set if Line Break. Timing of the Line Break is under software
any or a combination of the errors (DOE, FE, PE, BD) occur. control.
Read only; it cannot be written by software, cleared on reset.
ETDX: TDX (USART Transmit Pin) is the alternate function
RBFL: This bit is set when the USART has received a assigned to Port L pin L2; it is selected by setting ETDX bit.
complete character and has copied it into the RBUF register.
SSEL: USART mode select. Read only, cleared on reset.
It is automatically reset when software reads the character
from RBUF. Read only; it cannot be written by software, SSEL = 0 Asynchronous Mode.
cleared on reset. SSEL = 1 Synchronous Mode.
TBMT: This bit is set when the USART transfers a byte of XRCLK: This bit selects the clock source for the receiver
data from the TBUF register into the TSFT register for trans- section. Read/Write, cleared on reset.
mission. It is automatically reset when software writes into XRCLK = 0 The clock source is selected through the
the TBUF register. Read only, bit is set to “one” on reset; it PSR and BAUD registers.
cannot be written by software.
XRCLK = 1 Signal on CKX (L1) pin is used as the clock.
ENUR — USART RECEIVE CONTROL AND STATUS REG-
XTCLK: This bit selects the clock source for the transmitter
ISTER (Address at 0BB)
section. Read/Write, cleared on reset.
DOE FE PE BD RBIT9 ATTN XMTG RCVG XTCLK = 0 The clock source is selected through the PSR
Bit 7 Bit 0 and BAUD registers.
XTCLK = 1 Signal on CKX (L1) pin is used as the clock.
DOE: Flags a Data Overrun Error. Read only, cleared on
read, cleared on reset. ERI: This bit enables/disables interrupt from the receiver
section. Read/Write, cleared on reset.
DOE = 0 Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register ERI = 0 Interrupt from the receiver is disabled.
was read. ERI = 1 Interrupt from the receiver is enabled.
DOE = 1 Indicates the occurrence of a Data Overrun ETI: This bit enables/disables interrupt from the transmitter
Error. section. Read/Write, cleared on reset.
FE: Flags a Framing Error. Read only, cleared on read, ETI = 0 Interrupt from the transmitter is disabled.
cleared on reset. ETI = 1 Interrupt from the transmitter is enabled.
FE = 0 Indicates no Framing Error has been detected
since the last time the ENUR register was read. 14.3 ASSOCIATED I/O PINS
FE = 1 Indicates the occurrence of a Framing Error. Data is transmitted on the TDX pin and received on the RDX
PE: Flags a Parity Error. Read only, cleared on read, cleared pin. TDX is the alternate function assigned to Port L pin L2;
on reset. it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function Port L pin L3, requiring no setup.
PE = 0 Indicates no Parity Error has been detected since Port L pin L2 must be configured as an output in the Port L
the last time the ENUR register was read. Configuration Register in order to be used as the TDX pin.
PE = 1 Indicates the occurrence of a Parity Error. The baud rate clock for the USART can be generated on-
BD: Flags a line break. chip, or can be taken from an external source. Port L pin L1
BD = 0 Indicates no Line Break has been detected since (CKX) is the external clock I/O pin. The CKX pin can be
the last time the ENUR register was read. either an input or an output, as determined by Port L Con-
BD = 1 Indicates the occurrence of a Line Break. figuration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter
RBIT9: Contains the ninth data bit received when the
and/or receiver. As an output, it presents the internal Baud
USART is operating with nine data bits per frame. Read only,
Rate Generator output.
cleared on reset.
Note: The CKX pin is unavailable if Port L1 is used for the
ATTN: ATTENTION Mode is enabled while this bit is set.
Low Speed Oscillator.
This bit is cleared automatically on receiving a character with
data bit nine set. Read/Write, cleared on reset.
47 www.national.com
14.0 USART (Continued) If data transmit and receive are selected with the CKX pin as
clock output, the device generates the synchronous clock
14.4 USART OPERATION output at the CKX pin. The internal baud rate generator is
The USART has two modes of operation: asynchronous used to produce the synchronous clock. Data transmit and
mode and synchronous mode. receive are performed synchronously with this clock.
14.4.1 Asynchronous Mode 14.5 FRAMING FORMATS

This mode is selected by resetting the SSEL (in the ENUI The USART supports several serial framing formats (Figure
register) bit to zero. The input frequency to the USART is 23). The format is selected using control bits in the ENU,
16 times the baud rate. ENUR and ENUI registers.
The TSFT and TBUF registers double-buffer data for trans- The first format (1, 1a, 1b, 1c) for data transmission (CHL0 =
mission. While TSFT is shifting out the current character on 1, CHL1 = 0) consists of Start bit, seven Data bits (excluding
the TDX pin, the TBUF register may be loaded by software parity) and one or two Stop bits. In applications using parity,
with the next byte to be transmitted. When TSFT finishes the parity bit is generated and verified by hardware.
transmitting the current character the contents of TBUF are The second format (CHL0 = 0, CHL1 = 0) consists of one
transferred to the TSFT register and the Transmit Buffer Start bit, eight Data bits (excluding parity) and 7/8, one or
Empty Flag (TBMT in the ENU register) is set. The TBMT two Stop bits. Parity bit is generated and verified by hard-
flag is automatically reset by the USART when software ware.
loads a new character into the TBUF register. There is also The third format for transmission (CHL0 = 0, CHL1 = 1)
the XMTG bit which is set to indicate that the USART is consists of one Start bit, nine Data bits and one or two Stop
transmitting. This bit gets reset at the end of the last frame bits. This format also supports the USART “ATTENTION”
(end of last Stop bit). TBUF is a read/write register. feature. When operating in this format, all eight bits of TBUF
The RSFT and RBUF registers double-buffer data being and RBUF are used for data. The ninth data bit is transmitted
received. The USART receiver continually monitors the sig- and received using two bits in the ENU and ENUR registers,
nal on the RDX pin for a low level to detect the beginning of called XBIT9 and RBIT9. RBIT9 is a read only bit. Parity is
a Start bit. Upon sensing this low level, it waits for half a bit not generated or verified in this mode.
time and samples again. If the RDX pin is still low, the The parity is enabled/disabled by PEN bit located in the ENU
receiver considers this to be a valid Start bit, and the remain- register. Parity is selected for 7- and 8-bit modes only. If
ing bits in the character frame are each sampled a three parity is enabled (PEN = 1), the parity selection is then
times around the center of the bit time. Serial data input on performed by PSEL0 and PSEL1 bits located in the ENU
the RDX pin is shifted into the RSFT register. Upon receiving register.
the complete character, the contents of the RSFT register
Note that the XBIT9/PSEL0 bit located in the ENU register
are copied into the RBUF register and the Received Buffer
serves two mutually exclusive functions. This bit programs
Full Flag (RBFL) is set. RBFL is automatically reset when
the ninth bit for transmission when the USART is operating
software reads the character from the RBUF register. RBUF
with nine data bits per frame. There is no parity selection in
is a read only register. There is also the RCVG bit which is
this framing format. For other framing formats XBIT9 is not
set high when a framing error or a break detect occurs and
needed and the bit is PSEL0 used in conjunction with PSEL1
goes low once RDX goes high.
to select parity.
14.4.2 Synchronous Mode The frame formats for the receiver differ from the transmitter
in the number of Stop bits required. The receiver only re-
In this mode data is transferred synchronously with the
quires one Stop bit in a frame, regardless of the setting of the
clock. Data is transmitted on the rising edge and received on
Stop bit selection bits in the control register. Note that an
the falling edge of the synchronous clock.
implicit assumption is made for full duplex USART operation
This mode is selected by setting SSEL bit in the ENUI that the framing formats are the same for the transmitter and
register. The input frequency to the USART is the same as receiver.
the baud rate.
When an external clock input is selected at the CKX pin, data
transmit and receive are performed synchronously with this
clock through TDX/RDX pins.
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14.0 USART (Continued)
10137426
FIGURE 23. Framing Formats
14.6 USART INTERRUPTS 14.7 BAUD CLOCK GENERATION

The USART is capable of generating interrupts. Interrupts The clock inputs to the transmitter and receiver sections of
are generated on Receive Buffer Full and Transmit Buffer the USART can be individually selected to come either from
Empty. Both interrupts have individual interrupt vectors. Two an external source at the CKX pin (port L, pin L1) or from a
bytes of program memory space are reserved for each in- source selected in the PSR and BAUD registers. Internally,
terrupt vector. The two vectors are located at addresses the basic baud clock is created from the MCLK through a
0xEC to 0xEF Hex in the program memory space. The two-stage divider chain consisting of a 1-16 (increments of
interrupts can be individually enabled or disabled using En- 0.5) prescaler and an 11-bit binary counter (Figure 24). The
able Transmit Interrupt (ETI) and Enable Receive Interrupt divide factors are specified through two read/write registers
(ERI) bits in the ENUI register. shown in Figure 25. Note that the 11-bit Baud Rate Divisor
The interrupt from the Transmitter is set pending, and re- spills over into the Prescaler Select Register (PSR). PSR is
mains pending, as long as both the TBMT and ETI bits are cleared upon reset.
set. To remove this interrupt, software must either clear the As shown in Table 18, a Prescaler Factor of 0 corresponds to
ETI bit or write to the TBUF register (thus clearing the TBMT NO CLOCK. This condition is the USART power down mode
bit). where the USART clock is turned off for power saving pur-
The interrupt from the receiver is set pending, and remains pose. The user must also turn the USART clock off when a
pending, as long as both the RBFL and ERI bits are set. To different baud rate is chosen.
remove this interrupt, software must either clear the ERI bit The correspondences between the 5-bit Prescaler Select
or read from the RBUF register (thus clearing the RBFL bit). and Prescaler factors are shown in Table 18. There are
49 www.national.com
14.0 USART (Continued) Prescaler Prescaler
many ways to calculate the two divisor factors, but one Select Factor
particularly effective method would be to achieve a 1.8432 01000 4.5
MHz frequency coming out of the first stage. The 1.8432 01001 5
MHz prescaler output is then used to drive the software
programmable baud rate counter to create a 16x clock for 01010 5.5
the following baud rates: 110, 134.5, 150, 300, 600, 1200, 01011 6
1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 01100 6.5
(Table 17). Other baud rates may be created by using ap-
01101 7
propriate divisors. The 16x clock is then divided by 16 to
provide the rate for the serial shift registers of the transmitter 01110 7.5
and receiver. 01111 8
10000 8.5
TABLE 17. Baud Rate Divisors 10001 9
(1.8432 MHz Prescaler Output)
10010 9.5
Baud Rate 10011 10
Baud Rate
Divisor − 1 (N-1) 10100 10.5
110 (110.03) 1046 10101 11
134.5 (134.58) 855 10110 11.5
150 767 10111 12
300 383 11000 12.5
600 191 11001 13
1200 95 11010 13.5
1800 63 11011 14
2400 47 11100 14.5
3600 31 11101 15
4800 23 11110 15.5
7200 15 11111 16
9600 11
As an example, considering Asynchronous Mode and a crys-
19200 5
tal frequency of 4.608 MHz, the prescaler factor selected is:
38400 2 (4.608 x 2)/1.8432 = 5
Note: The entries in Table 17 assume a prescaler output of 1.8432 MHz. In The 5 entry is available in Table 18. The 1.8432 MHz pres-
asynchronous mode the baud rate could be as high as 1250k. caler output is then used with proper Baud Rate Divisor
(Table 17) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table 17 is 5.
N − 1 = 5 (N − 1 is the value from Table 17)
N = 6 (N is the Baud Rate Divisor)
Baud Rate = 1.8432 MHz/(16 x 6) = 19200
The divide by 16 is performed because in the asynchronous
10137427
mode, the input frequency to the USART is 16 times the
baud rate. The equation to calculate baud rates is given
FIGURE 24. USART BAUD Clock Generation below.
The actual Baud Rate may be found from:
BR = (FC x 2)/(16 x N x P)
TABLE 18. Prescaler Factors
Where:
Prescaler Prescaler BR is the Baud Rate
Select Factor FC is the crystal frequency
00000 NO CLOCK N is the Baud Rate Divisor (Table 17)
00001 1 P is the Prescaler Divide Factor selected by the value in the
00010 1.5 Prescaler Select Register (Table 18)
00011 2 Note: In the Synchronous Mode, the divisor 16 is replaced
by two.
00100 2.5
Example:
00101 3
Asynchronous Mode:
00110 3.5
Crystal Frequency = 5 MHz
00111 4
Desired baud rate = 19200
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14.0 USART (Continued) N = 32.552/6.5 = 5.008 (N = 5)
The programmed value (from Table 17) should be 4 (N - 1).
Using the above equation N x P can be calculated first.
Using the above values calculated for N and P:
N x P = (5 x 106 x 2)/(16 x 19200) = 32.552
BR = (5 x 106 x 2)/(16 x 5 x 6.5) = 19230.769
Now 32.552 is divided by each Prescaler Factor (Table 18) to
error = (19230.769 - 19200) x 100/19200 = 0.16%
obtain a value closest to an integer. This factor happens to
be 6.5 (P = 6.5).
10137428
FIGURE 25. USART BAUD Clock Divisor Registers
14.8 EFFECT OF HALT/IDLE 14.10 ATTENTION MODE

The USART logic is reinitialized when either the HALT or The USART Receiver section supports an alternate mode of
IDLE modes are entered. This reinitialization sets the TBMT operation, referred to as ATTENTION Mode. This mode of
flag and resets all read only bits in the USART control and operation is selected by the ATTN bit in the ENUR register.
status registers. Read/Write bits remain unchanged. The The data format for transmission must also be selected as
Transmit Buffer (TBUF) is not affected, but the Transmit Shift having nine Data bits and either one or two Stop bits.
register (TSFT) bits are set to one. The receiver registers The ATTENTION mode of operation is intended for use in
RBUF and RSFT are not affected. networking the device with other processors. Typically in
The device will exit from the HALT/IDLE modes when the such environments the messages consists of device ad-
Start bit of a character is detected at the RDX (L3) pin. This dresses, indicating which of several destinations should re-
feature is obtained by using the Multi-Input Wake-up scheme ceive them, and the actual data. This Mode supports a
provided on the device. scheme in which addresses are flagged by having the ninth
Before entering the HALT or IDLE modes the user program bit of the data field set to a 1. If the ninth bit is reset to a zero
must select the Wake-up source to be on the RDX pin. This the byte is a Data byte.
selection is done by setting bit 3 of WKEN (Wake-up Enable) While in ATTENTION mode, the USART monitors the com-
register. The Wake-up trigger condition is then selected to be munication flow, but ignores all characters until an address
high to low transition. This is done via the WKEDG register character is received. Upon receiving an address character,
(Bit 3 is one). the USART signals that the character is ready by setting the
If the device is halted and crystal oscillator is used, the RBFL flag, which in turn interrupts the processor if USART
Wake-up signal will not start the chip running immediately Receiver interrupts are enabled. The ATTN bit is also cleared
because of the finite start up time requirement of the crystal automatically at this point, so that data characters as well as
oscillator. The idle timer (T0) generates a fixed (256 tC) delay address characters are recognized. Software examines the
to ensure that the oscillator has indeed stabilized before contents of the RBUF and responds by deciding either to
allowing the device to execute code. The user has to con- accept the subsequent data stream (by leaving the ATTN bit
sider this delay when data transfer is expected immediately reset) or to wait until the next address character is seen (by
after exiting the HALT mode. setting the ATTN bit again).
Operation of the USART Transmitter is not affected by se-
14.9 DIAGNOSTIC lection of this Mode. The value of the ninth bit to be trans-
Bits CHL0 and CHL1 in the ENU register provide a loopback mitted is programmed by setting XBIT9 appropriately. The
feature for diagnostic testing of the USART. When both bits value of the ninth bit received is obtained by reading RBIT9.
are set to one, the following occurs: The receiver input pin Since this bit is located in ENUR register where the error
(RDX) is internally connected to the transmitter output pin flags reside, a bit operation on it will reset the error flags.
(TDX); the output of the Transmitter Shift Register is “looped
back” into the Receive Shift Register input. In this mode, 14.11 BREAK GENERATION
data that is transmitted is immediately received. This feature To generate a line break, the user software should set the
allows the processor to verify the transmit and receive data BRK bit in the ENUI register. This will force the TDX pin to 0
paths of the USART. and hold it there until the BRK bit is reset.
Note that the framing format for this mode is the nine bit
format; one Start bit, nine data bits, and one or two Stop bits. 15.0 A/D Converter
Parity is not generated or verified in this mode. This device contains a 16-channel, multiplexed input, suc-
cessive approximation, 10 bit Analog-to-Digital Converter.
Pins AVCC and AGND are used for the voltage reference.
51 www.national.com
15.0 A/D Converter (Continued) An A/D conversion is initiated by setting the ADBSY bit in the
ENAD control register. The result of the conversion is avail-
15.1 OPERATING MODES able to the user in the A/D result registers, ADRSTH and
It supports both Single Ended and Differential modes of ADRSTL, when ADBSY is cleared by the hardware on
operation. completion of the conversion.
Two specific analog channel selection modes are supported.
These are as follows: TABLE 19. ENAD
1. Allow any specific channel to be selected at one time. Bit 7 Bit 0
The A/D Converter performs the specific conversion re- Channel Select Mode Select Mux/Out Prescale Busy
quested and stops. ADCH3 ADCH2 ADCH1 ADCH0 ADMOD MUX PSC ADBSY
2. Allow any differential channel pair to be selected at one
time. The A/D Converter performs the specific differen-
tial conversion requested and stops. 15.1.1.1 Channel Select
In both Single Ended and Differential modes, there is the This 4-bit field selects one of sixteen channels to be the VIN+.
capability to connect the analog multiplexor output and A/D The mode selection and the mux output determine the VIN-
converter input to external pins. This provides the ability to input. When MUX = 0, all sixteen channels are available, as
externally connect a common filter/signal conditioning circuit shown in Table 20. When MUX = 1, only fourteen channels
for the A/D Converter. are available, as shown in Table 21.
The A/D Converter is supported by three memory mapped All port pins which are used, in the application, in A/D opera-
registers: two result registers and the control register. When tions must be configured as high-impedance inputs. If the
the device is reset, the mode control register (ENAD) is ports are configured as outputs or inputs with weak pull-up
cleared, the A/D is powered down and the A/D result regis- there will be a conflict between the analog signal and the
ters have unknown data. digitally driven output.
15.1.1 A/D Control Register

The control register, ENAD, contains 4 bits for channel se-
lection, 1 bit for mode selection, 1 bit for the multiplexor
output selection, 1 bit for prescaler selection, and a Busy bit.
TABLE 20. A/D Converter Channel Selection when the Multiplexor Output is Disabled
Mode Select Mode Select
ADMOD = 0 ADMOD = 1 Mux Output
Select Bits
Single Ended Differential Disabled
Mode Mode
ADCH3 ADCH2 ADCH1 ADCH0 Channel No. Channel Pairs MUX
(+, −)
0 0 0 0 0 0, 1 0
0 0 0 1 1 1, 0 0
0 0 1 0 2 2, 3 0
0 0 1 1 3 3, 2 0
0 1 0 0 4 4, 5 0
0 1 0 1 5 5, 4 0
0 1 1 0 6 6, 7 0
0 1 1 1 7 7, 6 0
1 0 0 0 8 8, 9 0
1 0 0 1 9 9, 8 0
1 0 1 0 10 10, 11 0
1 0 1 1 11 11, 10 0
1 1 0 0 12 12, 13 0
1 1 0 1 13 13, 12 0
1 1 1 0 14 14, 15 0
1 1 1 1 15 15, 14 0
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15.0 A/D Converter (Continued)
TABLE 21. A/D Converter Channel Selection when the Multiplexor Output is Enabled
Mode Select Mode Select
ADMOD = 0 ADMOD = 1 Mux Output
Select Bits
Single Ended Differential Enabled
Mode Mode
ADCH3 ADCH2 ADCH1 ADCH0 Channel No. Channel Pairs MUX
(+, −)
0 0 0 0 0 0, 1 1
0 0 0 1 1 1, 0 1
0 0 1 0 2 2, 3 1
0 0 1 1 3 3, 2 1
0 1 0 0 4 4, 5 1
0 1 0 1 5 5, 4 1
0 1 1 0 6 6, 7 1
0 1 1 1 7 7, 6 1
1 0 0 0 8 8, 9 1
1 0 0 1 9 9, 8 1
1 0 1 0 10 10, 11 1
1 0 1 1 11 11, 10 1
1 1 0 0 12 Not Used (Note 1
19)
1 1 0 1 13 ADC13 is 1
Mux Output −
(Note 19)
1 1 1 0 ADCH14 is ADCH14 is 1
Mux Output Mux Output +
(Note 18) (Note 18)
1 1 1 1 ADCH15 is ADCH15 is 1
A/D Input (Note A/D Input (Note
18) 18)
Note 18: This Input Channel Selection should not be used when the Multiplexor Output is enabled.
Note 19: This Input Channel Selection should not be used in Differential Mode when the Multiplexor Output is enabled.
15.1.1.2 Multiplexor Output Select allows the input channel to be selected and settled before
This 1-bit field allows the output of the A/D multiplexor and starting a conversion. The sequence to perform conversions
the input to the A/D to be connected directly to external pins. using the Mux Out feature is a multistep process and is listed
This allows for an external, common filter/signal conditioning below.
circuit to be applied to all channels. The output of the exter- 1. Select the desired channel and operating modes and
nal conditioning circuit can then be connected directly to the load them into ENAD without setting ADBSY.
input of the Sample and Hold input on the A/D Converter. 2. Wait the appropriate time until the analog input has
See Figure 26 for the single ended mode diagram. The settled. This will depend on the application and the
Multiplexor output is connected to ADCH14 and the A/D response of the external circuit.
input is connected to ADCH15. For Differential mode, the
3. Select the same desired channel and operating modes
differential multiplexor outputs are available and should be
used in step 1 and load them into ENAD and also set
converted to a single ended voltage for connection to the A/D
ADBSY or set ADBSY by using the SBIT instruction.
Converter Input. See Figure 27.
This will start the conversion.
The channel assignments for this mode are shown in Table
4. Poll ADBSY until it is cleared by the hardware. This
22.
indicates the completion of the conversion.
When using the Mux Output feature, the delay though the
5. Obtain the results from the result registers.
internal multiplexor to the pin, plus the delay of the external
filter circuit, plus the internal delay to the Sample and Hold The port pins used for the multiplexor output must be con-
will exceed the three clock cycles that’s allowed in the configured as high impedance inputs. If the port pins are con-
version. This adds the requirement that, whenever the MUX figured as outputs, or as inputs with weak pull-up, there will
bit = 1, that the channel selected by ADCH3:0 bits be en- be a conflict between the analog signal output and the
abled, even when ADBSY = 0, and gated to the mux output digitally driven output.
pin. The input path to the A/D converter is also enabled. This
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15.0 A/D Converter (Continued)
10137429
FIGURE 26. A/D with Single Ended Mux Output Feature Enabled
10137430
FIGURE 27. A/D with Differential Mux Output Feature Enabled
15.1.1.3 Mode Select values currently in the ENAD register. Normal completion of
This 1-bit field is used to select the mode of operation (single an A/D conversion clears the ADBSY bit and turns off the A/D
ended or differential) as shown in the following Table 22. Converter.
If the user wishes to restart a conversion which is already in
progress, this can be accomplished only by writing a zero to
TABLE 22. A/D Conversion Mode Selection
the ADBSY bit to stop the current conversion and then by
ADMOD Mode writing a one to ADBSY to start a new conversion. This can
0 Single Ended Mode be done in two consecutive instructions.
1 Differential Mode 15.1.2 A/D Result Registers
There are two result registers for the A/D converter: the high
15.1.1.4 Prescaler Select 8 bits of the result and the low 2-bits of the result. The format
This 1-bit field is used to select one of two prescaler clocks of these registers is shown in Figures 27, 28. Both registers
for the A/D Converter. The following Table 23 shows the are read/write registers, but in normal operation, the hard-
various prescaler options. Care must be taken, when select- ware writes the value into the register when the conversion is
ing this bit, to keep the A/D clock frequency within the complete and the software reads the value. Both registers
specified range. are undefined upon Reset. They hold the previous value until
a new conversion overwrites them. When reading ADRSTL,
bits 5-0 will read as 0.
TABLE 23. A/D Converter Clock Prescale
PSC Clock Select TABLE 24. ADRSTH
0 MCLK Divide by 1 Bit 7 Bit 0
1 MCLK Divide by 16 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
15.1.1.5 Busy Bit TABLE 25. ADRSTL

The ADBSY bit of the ENAD register is used to control Bit 7 Bit 0
starting and stopping of the A/D conversion. When ADBSY is
Bit 1 Bit 0 0 0 0 0 0 0
cleared, the prescale logic is disabled and the A/D clock is
turned off, drawing minimal power. Setting the ADBSY bit
starts the A/D clock and initiates a conversion based on the
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15.0 A/D Converter (Continued) auto-zeroing the comparator, 10 cycles for converting, 1
cycle for loading the result into the result registers, for stop-
15.2 A/D OPERATION ping and for re-initializing. The ADBSY flag provides an A/D
The A/D conversion is completed within fifteen A/D converter clock inhibit function, which saves power by powering down
clocks. The A/D Converter interface works as follows. Setting the A/D when it is not in use.
the ADBSY bit in the A/D control register ENAD initiates an Note: The A/D Converter is also powered down when the
A/D conversion. The conversion sequence starts at the be- device is in either the HALT or IDLE modes. If the A/D is
ginning of the write to ENAD operation which sets ADBSY, running when the device enters the HALT or IDLE modes,
thus powering up the A/D. At the first edge of the Converter the A/D powers down and then restarts the conversion from
clock following the write operation, the sample signal turns the beginning with a corrupted sampled voltage (and thus an
on for three clock cycles. At the end of the conversion, the invalid result) when the device comes out of the HALT or
internal conversion complete signal will clear the ADBSY bit IDLE modes.
and power down the A/D. The A/D 10-bit result is immedi-
ately loaded into the A/D result registers (ADRSTH and 15.3 ANALOG INPUT AND SOURCE RESISTANCE
ADRSTL) upon completion. CONSIDERATIONS
Inadvertent changes to the ENAD register during conversion Figure 28 shows the A/D pin model in single ended mode.
are prevented by the control logic of the A/D. Any attempt to The differential mode has a similar A/D pin model. The leads
write any bit of the ENAD Register except ADBSY, while to the analog inputs should be kept as short as possible.
ADBSY is a one, is ignored. ADBSY must be cleared either Both noise and digital clock coupling to an A/D input can
by completion of an A/D conversion or by the user before the cause conversion errors. The clock lead should be kept
prescaler, conversion mode or channel select values can be away from the analog input line to reduce coupling.
changed. After stopping the current conversion, the user can Source impedances greater than 3 kΩ on the analog input
load different values for the prescaler, conversion mode or lines will adversely affect the internal RC charging time
channel select and start a new conversion in one instruction. during input sampling. As shown in Figure 28, the analog
switch to the DAC array is closed only during the 3 A/D cycle
15.2.1 Prescaler sample time. Large source impedances on the analog inputs
The A/D Converter (A/D) contains a prescaler option that may result in the DAC array not being charged to the correct
allows two different clock speed selections as shown in voltage levels, causing scale errors.
Table 23. The A/D clock frequency is equal to MCLK divided If large source resistance is necessary, the recommended
by the prescaler value. Note that the prescaler value must be solution is to slow down the A/D clock speed in proportion to
chosen such that the A/D clock falls within the specified the source resistance. The A/D Converter may be operated
range. The maximum A/D frequency is 1.25 MHz. This at the maximum speed for RS less than 3 kΩ. For RS greater
equates to a 800 ns A/D clock cycle. than 3 kΩ, A/D clock speed needs to be reduced. For ex-
The A/D Converter takes 15 A/D clock cycles to complete a ample, with RS = 6 kΩ, the A/D Converter may be operated
conversion. Thus the minimum A/D conversion time is 12.0 at half the maximum speed. A/D Converter clock speed may
µs when a prescaler of 16 has been selected with be slowed down by either increasing the A/D prescaler
MCLK = 20 MHz. The 15 A/D clock cycles needed for divide-by or decreasing the CKI clock frequency. The A/D
conversion consist of 3 cycles for sampling, 1 cycle for minimum clock speed is 65.536 kHz.
10137453
*The analog switch is closed only during the sample time.
FIGURE 28. A/D Pin Model (Single Ended Mode)
55 www.national.com
16.0 Interrupts The Software trap has the highest priority while the default
VIS has the lowest priority.
16.1 INTRODUCTION Each of the 13 maskable inputs has a fixed arbitration rank-
The device supports fourteen vectored interrupts. Interrupt ing and vector.
sources include Timer 1, Timer 2, Timer 3, Timer T0, Port L Figure 29 shows the Interrupt block diagram.
Wake-up, Software Trap, MICROWIRE/PLUS, USART and
External Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
10137432
FIGURE 29. Interrupt Block Diagram
16.2 MASKABLE INTERRUPTS maskable interrupt must wait until that service routine is
All interrupts other than the Software Trap are maskable. completed.)
Each maskable interrupt has an associated enable bit and An interrupt is triggered only when all of these conditions are
pending flag bit. The pending bit is set to 1 when the interrupt met at the beginning of an instruction. If different maskable
condition occurs. The state of the interrupt enable bit, com- interrupts meet these conditions simultaneously, the highest-
bined with the GIE bit determines whether an active pending priority interrupt will be serviced first, and the other pending
flag actually triggers an interrupt. All of the maskable inter- interrupts must wait.
rupt pending and enable bits are contained in mapped con- Upon Reset, all pending bits, individual enable bits, and the
trol registers, and thus can be controlled by the software. GIE bit are reset to zero. Thus, a maskable interrupt condi-
A maskable interrupt condition triggers an interrupt under the tion cannot trigger an interrupt until the program enables it by
following conditions: setting both the GIE bit and the individual enable bit. When
1. The enable bit associated with that interrupt is set. enabling an interrupt, the user should consider whether or
not a previously activated (set) pending bit should be ac-
2. The GIE bit is set.
knowledged. If, at the time an interrupt is enabled, any
3. The device is not processing a non-maskable interrupt. previous occurrences of the interrupt should be ignored, the
(If a non-maskable interrupt is being serviced, a associated pending bit must be reset to zero prior to en-
abling the interrupt. Otherwise, the interrupt may be simply
www.national.com 56
16.0 Interrupts (Continued) 16.3 VIS INSTRUCTION
The general interrupt service routine, which starts at address
enabled; if the pending bit is already set, it will immediately 00FF Hex, must be capable of handling all types of inter-
trigger an interrupt. A maskable interrupt is active if its asso- rupts. The VIS instruction, together with an interrupt vector
ciated enable and pending bits are set. table, directs the device to the specific interrupt handling
An interrupt is an asychronous event which may occur be- routine based on the cause of the interrupt.
fore, during, or after an instruction cycle. Any interrupt which VIS is a single-byte instruction, typically used at the very
occurs during the execution of an instruction is not acknowl- beginning of the general interrupt service routine at address
edged until the start of the next normally executed instruc- 00FF Hex, or shortly after that point, just after the code used
tion. If the next normally executed instruction is to be for context switching. The VIS instruction determines which
skipped, the skip is performed before the pending interrupt is enabled and pending interrupt has the highest priority, and
acknowledged. causes an indirect jump to the address corresponding to that
At the start of interrupt acknowledgment, the following ac- interrupt source. The jump addresses (vectors) for all pos-
tions occur: sible interrupts sources are stored in a vector table.
1. The GIE bit is automatically reset to zero, preventing any The vector table may be as long as 32 bytes (maximum of 16
subsequent maskable interrupt from interrupting the cur- vectors) and resides at the top of the 256-byte block con-
rent service routine. This feature prevents one maskable taining the VIS instruction. However, if the VIS instruction is
interrupt from interrupting another one being serviced. at the very top of a 256-byte block (such as at 00FF Hex),
2. The address of the instruction about to be executed is the vector table resides at the top of the next 256-byte block.
pushed onto the stack. Thus, if the VIS instruction is located somewhere between
00FF and 01DF Hex (the usual case), the vector table is
3. The program counter (PC) is loaded with 00FF Hex,
located between addresses 01E0 and 01FF Hex. If the VIS
causing a jump to that program memory location.
instruction is located between 01FF and 02DF Hex, then the
The device requires seven instruction cycles to perform the vector table is located between addresses 02E0 and 02FF
actions listed above. Hex, and so on.
If the user wishes to allow nested interrupts, the interrupts Each vector is 15 bits long and points to the beginning of a
service routine may set the GIE bit to 1 by writing to the PSW specific interrupt service routine somewhere in the 32-kbyte
register, and thus allow other maskable interrupts to interrupt memory space. Each vector occupies two bytes of the vector
the current service routine. If nested interrupts are allowed, table, with the higher-order byte at the lower address. The
caution must be exercised. The user must write the program vectors are arranged in order of interrupt priority. The vector
in such a way as to prevent stack overflow, loss of saved of the maskable interrupt with the lowest rank is located to
context information, and other unwanted conditions. 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The
The interrupt service routine stored at location 00FF Hex next priority interrupt is located at 0yE2 and 0yE3, and so
should use the VIS instruction to determine the cause of the forth in increasing rank. The Software Trap has the highest
interrupt, and jump to the interrupt handling routine corre- rand and its vector is always located at 0yFE and 0yFF. The
sponding to the highest priority enabled and active interrupt. number of interrupts which can become active defines the
Alternately, the user may choose to poll all interrupt pending size of the table.
and enable bits to determine the source(s) of the interrupt. If Table 28 shows the types of interrupts, the interrupt arbitra-
more than one interrupt is active, the user’s program must tion ranking, and the locations of the corresponding vectors
decide which interrupt to service. in the vector table.
Within a specific interrupt service routine, the associated The vector table should be filled by the user with the memory
pending bit should be cleared. This is typically done as early locations of the specific interrupt service routines. For ex-
as possible in the service routine in order to avoid missing ample, if the Software Trap routine is located at 0310 Hex,
the next occurrence of the same type of interrupt event. then the vector location 0yFE and -0yFF should contain the
Thus, if the same event occurs a second time, even while the data 03 and 10 Hex, respectively. When a Software Trap
first occurrence is still being serviced, the second occur- interrupt occurs and the VIS instruction is executed, the
rence will be serviced immediately upon return from the program jumps to the address specified in the vector table.
current interrupt routine.
The interrupt sources in the vector table are listed in order of
An interrupt service routine typically ends with an RETI rank, from highest to lowest priority. If two or more enabled
instruction. This instruction set the GIE bit back to 1, pops and pending interrupts are detected at the same time, the
the address stored on the stack, and restores that address to one with the highest priority is serviced first. Upon return
the program counter. Program execution then proceeds with from the interrupt service routine, the next highest-level
the next instruction that would have been executed had pending interrupt is serviced.
there been no interrupt. If there are any valid interrupts
If the VIS instruction is executed, but no interrupts are en-
pending, the highest-priority interrupt is serviced immedi-
abled and pending, the lowest-priority interrupt vector is
ately upon return from the previous interrupt.
used, and a jump is made to the corresponding address in
Note: While executing from the Boot ROM for ISP or virtual the vector table. This is an unusual occurrence and may be
E2 operations, the hardware will disable interrupts from oc- the result of an error. It can legitimately result from a change
curring. The hardware will leave the GIE bit in its current in the enable bits or pending flags prior to the execution of
state, and if set, the hardware interrupts will occur when the VIS instruction, such as executing a single cycle instruc-
execution is returned to Flash Memory. Subsequent inter- tion which clears an enable flag at the same time that the
rupts, during ISP operation, from the same interrupt source pending flag is set. It can also result, however, from inad-
will be lost. vertent execution of the VIS command outside of the context
of an interrupt.
57 www.national.com
16.0 Interrupts (Continued) To ensure reliable operation, the user should always use the
VIS instruction to determine the source of an interrupt. Al-
The default VIS interrupt vector can be useful for applica- though it is possible to poll the pending bits to detect the
tions in which time critical interrupts can occur during the source of an interrupt, this practice is not recommended. The
servicing of another interrupt. Rather than restoring the pro- use of polling allows the standard arbitration ranking to be
gram context (A, B, X, etc.) and executing the RETI instruc- altered, but the reliability of the interrupt system is compro-
tion, an interrupt service routine can be terminated by return- mised. The polling routine must individually test the enable
ing to the VIS instruction. In this case, interrupts will be and pending bits of each maskable interrupt. If a Software
serviced in turn until no further interrupts are pending and Trap interrupt should occur, it will be serviced last, even
the default VIS routine is started. After testing the GIE bit to though it should have the highest priority. Under certain
ensure that execution is not erroneous, the routine should conditions, a Software Trap could be triggered but not ser-
restore the program context and execute the RETI to return viced, resulting in an inadvertent “locking out” of all
to the interrupted program. maskable interrupts by the Software Trap pending flag.
This technique can save up to fifty instruction cycles (tC), or Problems such as this can be avoided by using VIS
more, (25 µs at 10 MHz oscillator) of latency for pending instruction.
interrupts with a penalty of fewer than ten instruction cycles
if no further interrupts are pending.
TABLE 26. Interrupt Vector Table

Vector Address (Note 20)
Arbitration Ranking Source Description
(Hi-Low Byte)
(1) Highest Software INTR Instruction 0yFE–0yFF
(2) Reserved for NMI 0yFC–0yFD
(3) External G0 0yFA–0yFB
(4) Timer T0 Underflow 0yF8–0yF9
(5) Timer T1 T1A/Underflow 0yF6–0yF7
(6) Timer T1 T1B 0yF4–0yF5
(7) MICROWIRE/PLUS BUSY Low 0yF2–0yF3
(8) Reserved 0yF0–0yF1
(9) USART Receive 0yEE–0yEF
(10) USART Transmit 0yEC–0yED
(11) Timer T2 T2A/Underflow 0yEA–0yEB
(12) Timer T2 T2B 0yE8–0yE9
(13) Timer T3 T3A/Underflow 0yE6–0yE7
(14) Timer T3 T3B 0yE4–0yE5
(15) Port L/Wake-up Port L Edge 0yE2–0yE3
(16) Lowest Default VIS Reserved 0yE0–0yE1
Note 20: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last
address of a block. In this case, the table must be in the next block.
16.3.1 VIS Execution the active interrupt with the highest arbitration ranking. This
When the VIS instruction is executed it activates the arbitra- vector is read from program memory and placed into the PC
tion logic. The arbitration logic generates an even number which is now pointed to the 1st instruction of the service
between E0 and FE (E0, E2, E4, E6 etc....) depending on routine of the active interrupt with the highest arbitration
which active interrupt has the highest arbitration ranking at ranking.
the time of the 1st cycle of VIS is executed. For example, if Figure 30 illustrates the different steps performed by the VIS
the software trap interrupt is active, FE is generated. If the instruction. Figure 31 shows a flowchart for the VIS instruc-
external interrupt is active and the software trap interrupt is tion.
not, then FA is generated and so forth. If no active interrupt The non-maskable interrupt pending flag is cleared by the
is pending, than E0 is generated. This number replaces the RPND (Reset Non-Maskable Pending Bit) instruction (under
lower byte of the PC. The upper byte of the PC remains certain conditions) and upon RESET.
unchanged. The new PC is therefore pointing to the vector of
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16.0 Interrupts (Continued)
10137433
FIGURE 30. VIS Operation
16.4 NON-MASKABLE INTERRUPT The Software Trap has the highest priority of all interrupts.
When a Software Trap occurs, the STPND bit is set. The GIE
16.4.1 Pending Flag bit is not affected and the pending bit (not accessible by the
There is a pending flag bit associated with the non-maskable user) is used to inhibit other interrupts and to direct the
Software Trap interrupt, called STPND. This pending flag is program to the ST service routine with the VIS instruction.
not memory-mapped and cannot be accessed directly by the Nothing can interrupt a Software Trap service routine except
software. for another Software Trap. The STPND can be reset only by
The pending flag is reset to zero when a device Reset the RPND instruction or a chip Reset.
occurs. When the non-maskable interrupt occurs, the asso- The Software Trap indicates an unusual or unknown error
ciated pending bit is set to 1. The interrupt service routine condition. Generally, returning to normal execution at the
should contain an RPND instruction to reset the pending flag point where the Software Trap occurred cannot be done
to zero. The RPND instruction always resets the STPND reliably. Therefore, the Software Trap service routine should
flag. re-initialize the stack pointer and perform a recovery proce-
dure that re-starts the software at some known point, similar
16.4.2 Software Trap to a device Reset, but not necessarily performing all the
The Software Trap is a special kind of non-maskable inter- same functions as a device Reset. The routine must also
rupt which occurs when the INTR instruction (used to ac- execute the RPND instruction to reset the STPND flag.
knowledge interrupts) is fetched from program memory and Otherwise, all other interrupts will be locked out. To the
placed in the instruction register. This can happen in a extent possible, the interrupt routine should record or indi-
variety of ways, usually because of an error condition. Some cate the context of the device so that the cause of the
examples of causes are listed below. Software Trap can be determined.
If the program counter incorrectly points to a memory loca- If the user wishes to return to normal execution from the
tion beyond the programmed Flash memory space, the un- point at which the Software Trap was triggered, the user
used memory location returns zeros which is interpreted as must first execute RPND, followed by RETSK rather than
the INTR instruction. RETI or RET. This is because the return address stored on
the stack is the address of the INTR instruction that triggered
If the stack is popped beyond the allowed limit (address 06F
the interrupt. The program must skip that instruction in order
Hex), a 7FFF will be loaded into the PC. Since the Option
to proceed with the next one. Otherwise, an infinite loop of
Register resides at this location, and to maintain the integrity
Software Traps and returns will occur.
of the stack overpop protection, the Flash memory will return
a zero on an instruction fetch and a software trap will be Programming a return to normal execution requires careful
triggered. consideration. If the Software Trap routine is interrupted by
another Software Trap, the RPND instruction in the service
A Software Trap can be triggered by a temporary hardware
routine for the second Software Trap will reset the STPND
condition such as a brownout or power supply glitch.
flag; upon return to the first Software Trap routine, the
59 www.national.com
16.0 Interrupts (Continued) programming error or hardware condition (brownout, power
supply glitch, etc.) sets the STPND flag without providing a
STPND flag will have the wrong state. This will allow way for it to be cleared, all other interrupts will be locked out.
maskable interrupts to be acknowledged during the servicing To alleviate this condition, the user can use extra RPND
of the first Software Trap. To avoid problems such as this, the instructions in the main program and in the Watchdog ser-
user program should contain the Software Trap routine to vice routine (if present). There is no harm in executing extra
perform a recovery procedure rather than a return to normal RPND instructions in these parts of the program.
execution.
Under normal conditions, the STPND flag is reset by a
RPND instruction in the Software Trap service routine. If a
10137434
FIGURE 31. VIS Flow Chart
16.4.2.1 Programming Example: External Interrupt

PSW =00EF
CNTRL =00EE
RBIT 0,PORTGC
RBIT 0,PORTGD ; G0 pin configured Hi-Z
SBIT IEDG, CNTRL ; Ext interrupt polarity; falling edge
SBIT GIE, PSW ; Set the GIE bit
SBIT EXEN, PSW ; Enable the external interrupt
WAIT: JP WAIT ; Wait for external interrupt
.
.
.
.=0FF ; The interrupt causes a
VIS ; branch to address 0FF
; The VIS causes a branch to
; interrupt vector table
.
.
.
.=01FA ; Vector table (within 256 byte
.ADDRW SERVICE ; of VIS inst.) containing the ext
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16.0 Interrupts (Continued)
; interrupt service routine

.
.
.
SERVICE: ; Interrupt Service Routine
RBIT,EXPND,PSW ; Reset ext interrupt pend. bit
.
.
.
RET I ; Return, set the GIE bit
16.5 PORT L INTERRUPTS state, and if set, the hardware interrupts will occur when
Port L provides the user with an additional eight fully select- execution is returned to Flash Memory. Subsequent in-
able, edge sensitive interrupts which are all vectored into the terrupts, during ISP operation, from the same interrupt
same service subroutine. source will be lost.
The interrupt from Port L shares logic with the wake-up
circuitry. The register WKEN allows interrupts from Port L to 17.0 WATCHDOG/Clock Monitor
be individually enabled or disabled. The register WKEDG The devices contain a user selectable WATCHDOG and
specifies the trigger condition to be either a positive or a clock monitor. The following section is applicable only if the
negative edge. Finally, the register WKPND latches in the WATCHDOG feature has been selected in the Option regis-
pending trigger conditions. ter. The WATCHDOG is designed to detect the user program
The GIE (Global Interrupt Enable) bit enables the interrupt getting stuck in infinite loops resulting in loss of program
function. control or “runaway” programs.
A control flag, LPEN, functions as a global interrupt enable The WATCHDOG logic contains two separate service win-
for Port L interrupts. Setting the LPEN flag will enable inter- dows. While the user programmable upper window selects
rupts and vice versa. A separate global pending flag is not the WATCHDOG service time, the lower window provides
needed since the register WKPND is adequate. protection against an infinite program loop that contains the
Since Port L is also used for waking the device out of the WATCHDOG service instruction. The WATCHDOG uses the
HALT or IDLE modes, the user can elect to exit the HALT or Idle Timer (T0) and thus all times are measured in Idle Timer
IDLE modes either with or without the interrupt enabled. If he Clocks.
elects to disable the interrupt, then the device will restart The Clock Monitor is used to detect the absence of a clock or
execution from the instruction immediately following the in- a very slow clock below a specified rate on tC.
struction that placed the microcontroller in the HALT or IDLE The WATCHDOG consists of two independent logic blocks:
modes. In the other case, the device will first execute the WD UPPER and WD LOWER. WD UPPER establishes the
interrupt service routine and then revert to normal operation. upper limit on the service window and WD LOWER defines
(See HALT MODE for clock option wake-up information.) the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
16.6 INTERRUPT SUMMARY
value to a WATCHDOG Service Register named WDSVR
The device uses the following types of interrupts, listed which is memory mapped in the RAM. This value is com-
below in order of priority: posed of three fields, consisting of a 2-bit Window Select, a
1. The Software Trap non-maskable interrupt, triggered by 5-bit Key Data field, and the 1-bit Clock Monitor Select field.
the INTR (00 opcode) instruction. The Software Trap is Table 27 shows the WDSVR register.
acknowledged immediately. This interrupt service rou-
tine can be interrupted only by another Software Trap.
TABLE 27. WATCHDOG Service Register (WDSVR)
The Software Trap should end with two RPND instruc-
tions followed by a re-start procedure. Window Clock
Key Data
2. Maskable interrupts, triggered by an on-chip peripheral Select Monitor
block or an external device connected to the device. X X 0 1 1 0 0 Y
Under ordinary conditions, a maskable interrupt will not
7 6 5 4 3 2 1 0
interrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be inter-
The lower limit of the service window is fixed at 2048 Idle
rupted by the non-maskable interrupt request. A
Timer Clocks. Bits 7 and 6 of the WDSVR register allow the
maskable interrupt routine should end with an RETI
user to pick an upper limit of the service window.
instruction or, prior to restoring context, should return to
execute the VIS instruction. This is particularly useful Table 28 shows the four possible combinations of lower and
when exiting long interrupt service routines if the time upper limits for the WATCHDOG service window. This flex-
between interrupts is short. In this case the RETI instruc- ibility in choosing the WATCHDOG service window prevents
tion would only be executed when the default VIS rou- any undue burden on the user software.
tine is reached. Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
3. While executing from the Boot ROM for ISP or virtual E2 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
operations, the hardware will disable interrupts from oc- the WDSVR Register is the Clock Monitor Select bit.
curring. The hardware will leave the GIE bit in its current
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17.0 WATCHDOG/Clock Monitor (Continued)
TABLE 28. WATCHDOG Service Window Select

Clock Service Window Service Window
WDSVR WDSVR
Monitor for High Speed Mode for Dual Clock & Low Speed Modes
Bit 7 Bit 6
Bit 0 (Lower-Upper Limits) (Lower-Upper Limits)
0 0 X 2048-8k tC Cycles 2048-8k Cycles of 32 kHz Clk
0 1 X 2048-16k tC Cycles 2048-16k Cycles of LS 32 kHz Clk
X X 0 Clock Monitor Disabled Clock Monitor Disabled
X X 1 Clock Monitor Enabled Clock Monitor Enabled
17.1 CLOCK MONITOR When jumping to the boot ROM for ISP and virtual E2
The Clock Monitor aboard the device can be selected or operations, the hardware will disable the lower window error
deselected under program control. The Clock Monitor is and perform an immediate WATCHDOG service. The ISP
guaranteed not to reject the clock if the instruction cycle routines will service the WATCHDOG within the selected
clock (1/tC) is greater or equal to 5 kHz. This equates to a upper window. The ISP routines will service the WATCH-
clock input rate on the selected oscillator of greater or equal DOG immediately prior to returning execution back to the
to 25 kHz. user’s code in flash. Therefore, after returning to flash
memory, the user can service the WATCHDOG anytime
17.2 WATCHDOG/CLOCK MONITOR OPERATION following the return from boot ROM, but must service it within
The WATCHDOG is enabled by bit 2 of the Option register. the selected upper window to avoid a WATCHDOG error.
When this Option bit is 0, the WATCHDOG is enabled and The WATCHDOG has an output pin associated with it. This
pin G1 becomes the WATCHDOG output with a weak pull- is the WDOUT pin, on pin 1 of the port G. WDOUT is active
up. low. The WDOUT pin has a weak pull-up in the inactive
The WATCHDOG and Clock Monitor are disabled during state. Upon triggering the WATCHDOG, the logic will pull the
reset. The device comes out of reset with the WATCHDOG WDOUT (G1) pin low for an additional 16–32 cycles after the
armed, the WATCHDOG Window Select bits (bits 6, 7 of the signal level on WDOUT pin goes below the lower Schmitt
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the trigger threshold. After this delay, the device will stop forcing
WDSVR Register) enabled. Thus, a Clock Monitor error will the WDOUT output low. The WATCHDOG service window
occur after coming out of reset, if the instruction cycle clock will restart when the WDOUT pin goes high.
frequency has not reached a minimum specified value, in- A WATCHDOG service while the WDOUT signal is active will
cluding the case where the oscillator fails to start. be ignored. The state of the WDOUT pin is not guaranteed
The WDSVR register can be written to only once after reset on reset, but if it powers up low then the WATCHDOG will
and the key data (bits 5 through 1 of the WDSVR Register) time out and WDOUT will go high.
must match to be a valid write. This write to the WDSVR The Clock Monitor forces the G1 pin low upon detecting a
register involves two irrevocable choices: (i) the selection of clock frequency error. The Clock Monitor error will continue
the WATCHDOG service window (ii) enabling or disabling of until the clock frequency has reached the minimum specified
the Clock Monitor. Hence, the first write to WDSVR Register value, after which the G1 output will go high following 16–32
involves selecting or deselecting the Clock Monitor, select clock cycles. The Clock Monitor generates a continual Clock
the WATCHDOG service window and match the WATCH- Monitor error if the oscillator fails to start, or fails to reach the
DOG key data. Subsequent writes to the WDSVR register minimum specified frequency. The specification for the Clock
will compare the value being written by the user to the Monitor is as follows:
WATCHDOG service window value, the key data and the 1/tC > 5 kHz — No clock rejection.
Clock Monitor Enable (all bits) in the WDSVR Register. Table 1/tC < 10 Hz — Guaranteed clock rejection.
29 shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before
the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window.
TABLE 29. WATCHDOG Service Actions
Key Window Clock
Action
Data Data Monitor
Match Match Match Valid Service: Restart Service Window
Don’t Care Mismatch Don’t Care Error: Generate WATCHDOG Output
Mismatch Don’t Care Don’t Care Error: Generate WATCHDOG Output
Don’t Care Don’t Care Mismatch Error: Generate WATCHDOG Output
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17.0 WATCHDOG/Clock Monitor lected upper window. Upon return to flash memory, the
WATCHDOG is serviced, the lower window is enabled,
(Continued)
and the user can service the WATCHDOG anytime fol-
17.3 WATCHDOG AND CLOCK MONITOR SUMMARY lowing exit from Boot ROM, but must service it within the
The following salient points regarding the WATCHDOG and selected upper window to avoid a WATCHDOG error.
CLOCK MONITOR should be noted:
17.4 DETECTION OF ILLEGAL CONDITIONS
• Both the WATCHDOG and CLOCK MONITOR detector
The device can detect various illegal conditions resulting
circuits are inhibited during RESET.
from coding errors, transient noise, power supply voltage
• Following RESET, the WATCHDOG and CLOCK MONI- drops, runaway programs, etc.
TOR are both enabled, with the WATCHDOG having the
Reading of unprogrammed ROM gets zeros. The opcode for
maximum service window selected.
software interrupt is 00. If the program fetches instructions
• The WATCHDOG service window and CLOCK MONI- from unprogrammed ROM, this will force a software inter-
TOR enable/disable option can only be changed once, rupt, thus signaling that an illegal condition has occurred.
during the initial WATCHDOG service following RESET.
The subroutine stack grows down for each call (jump to
• The initial WATCHDOG service must match the key data subroutine), interrupt, or PUSH, and grows up for each
value in the WATCHDOG Service register WDSVR in return or POP. The stack pointer is initialized to RAM location
order to avoid a WATCHDOG error. 06F Hex during reset. Consequently, if there are more re-
• Subsequent WATCHDOG services must match all three turns than calls, the stack pointer will point to addresses 070
data fields in WDSVR in order to avoid WATCHDOG and 071 Hex (which are undefined RAM). Undefined RAM
errors. from addresses 070 to 07F (Segment 0), and all other seg-
• The correct key data value cannot be read from the ments (i.e., Segments 4... etc.) is read as all 1’s, which in
WATCHDOG Service register WDSVR. Any attempt to turn will cause the program to return to address 7FFF Hex.
read this key data value of 01100 from WDSVR will read The Option Register is located at this location and, when
as key data value of all 0’s. accessed by an instruction fetch, will respond with an INTR
• The WATCHDOG detector circuit is inhibited during both instruction (all 0’s) to generate a software interrupt, signalling
the HALT and IDLE modes. an illegal condition on overpop of the stack.
• The CLOCK MONITOR detector circuit is active during Thus, the chip can detect the following illegal conditions:
both the HALT and IDLE modes. Consequently, the de- 1. Executing from undefined Program Memory
vice inadvertently entering the HALT mode will be de- 2. Over “POP”ing the stack by having more returns than
tected as a CLOCK MONITOR error (provided that the calls.
CLOCK MONITOR enable option has been selected by When the software interrupt occurs, the user can re-initialize
the program). Likewise, a device with WATCHDOG en- the stack pointer and do a recovery procedure before restart-
abled in the Option but with the WATCHDOG output not ing (this recovery program is probably similar to that follow-
connected to RESET, will draw excessive HALT current if ing reset, but might not contain the same program initializa-
placed in the HALT mode. The clock Monitor will pull the tion procedures). The recovery program should reset the
WATCHDOG output low and sink current through the software interrupt pending bit using the RPND instruction.
on-chip pull-up resistor.
• The WATCHDOG service window will be set to its se- 18.0 MICROWIRE/PLUS
lected value from WDSVR following HALT. Consequently,
the WATCHDOG should not be serviced for at least 2048 MICROWIRE/PLUS is a serial SPI compatible synchronous
Idle Timer clocks following HALT, but must be serviced communications interface. The MICROWIRE/PLUS capabil-
within the selected window to avoid a WATCHDOG error. ity enables the device to interface with MICROWIRE/PLUS
or SPI peripherals (i.e. A/D converters, display drivers,
• The IDLE timer T0 is not initialized with external RESET.
EEPROMs etc.) and with other microcontrollers which sup-
• The user can sync in to the IDLE counter cycle with an port the MICROWIRE/PLUS or SPI interface. It consists of
IDLE counter (T0) interrupt or by monitoring the T0PND an 8-bit serial shift register (SIO) with serial data input (SI),
flag. The T0PND flag is set whenever the selected bit of serial data output (SO) and serial shift clock (SK). Figure 32
the IDLE counter toggles (every 4, 8, 16, 32 or 64k Idle shows a block diagram of the MICROWIRE/PLUS logic.
Timer clocks). The user is responsible for resetting the
The shift clock can be selected from either an internal source
T0PND flag.
or an external source. Operating the MICROWIRE/PLUS
• A hardware WATCHDOG service occurs just as the de- arrangement with the internal clock source is called the
vice exits the IDLE mode. Consequently, the Master mode of operation. Similarly, operating the
WATCHDOG should not be serviced for at least 2048 Idle MICROWIRE/PLUS arrangement with an external shift clock
Timer clocks following IDLE, but must be serviced within is called the Slave mode of operation.
the selected window to avoid a WATCHDOG error.
The CNTRL register is used to configure and control the
• Following RESET, the initial WATCHDOG service (where MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the service window and the CLOCK MONITOR enable/ the MSEL bit in the CNTRL register is set to one. In the
disable must be selected) may be programmed any- master mode, the SK clock rate is selected by the two bits,
where within the maximum service window (65,536 in- SL0 and SL1, in the CNTRL register. Table 30 details the
struction cycles) initialized by RESET. Note that this initial different clock rates that may be selected.
WATCHDOG service may be programmed within the ini-
tial 2048 instruction cycles without causing a
WATCHDOG error.
• When using any of the ISP functions in Boot ROM, the
ISP routines will service the WATCHDOG within the se-
63 www.national.com
18.0 MICROWIRE/PLUS (Continued) SK functions onto the G Port. The SO and SK pins must also
be selected as outputs by setting appropriate bits in the Port
TABLE 30. MICROWIRE/PLUS G configuration register. In the slave mode, the shift clock
Master Mode Clock Select stops after 8 clock pulses. Table 31 summarizes the bit
settings required for Master mode of operation.
SL1 SL0 SK Period
0 0 2 x tC 18.1.2 MICROWIRE/PLUS Slave Mode Operation
0 1 4 x tC In the MICROWIRE/PLUS Slave mode of operation the SK
1 x 8 x tC clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
Where tC is the instruction cycle clock
onto the G Port. The SK pin must be selected as an input
18.1 MICROWIRE/PLUS OPERATION and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
Setting the BUSY bit in the PSW register causes the register. Table 31 summarizes the settings required to enter
MICROWIRE/PLUS to start shifting the data. It gets reset the Slave mode of operation.
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have TABLE 31. MICROWIRE/PLUS Mode Settings
been shifted. The device may enter the MICROWIRE/PLUS This table assumes that the control flag MSEL is set.
mode either as a Master or as a Slave. Figure 32 shows how G4 (SO) G5 (SK) G4 G5
two microcontroller devices and several peripherals may be Operation
Config. Bit Config. Bit Fun. Fun.
interconnected using the MICROWIRE/PLUS arrangements.
1 1 SO Int. MICROWIRE/PLUS
Warning:
SK Master
The SIO register should only be loaded when the SK clock is
0 1 TRI- Int. MICROWIRE/PLUS
in the idle phase. Loading the SIO register while the SK clock
is in the active phase, will result in undefined data in the SIO STATE SK Master
register. 1 0 SO Ext. MICROWIRE/PLUS
Setting the BUSY flag when the input SK clock is in the SK Slave
active phase while in the MICROWIRE/PLUS is in the slave 0 0 TRI- Ext. MICROWIRE/PLUS
mode may cause the current SK clock for the SIO shift STATE SK Slave
register to be narrow. For safety, the BUSY flag should only
be set when the input SK clock is in the idle phase. The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
18.1.1 MICROWIRE/PLUS Master Mode Operation Master is shifted properly. After eight clock pulses the BUSY
In the MICROWIRE/PLUS Master mode of operation the flag is clear, the shift clock is stopped, and the sequence
shift clock (SK) is generated internally. The MICROWIRE/ may be repeated.
PLUS Master always initiates all data exchanges. The MSEL
bit in the CNTRL register must be set to enable the SO and
10137435
FIGURE 32. MICROWIRE/PLUS Application
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18.0 MICROWIRE/PLUS (Continued) SK clock. In the alternate SK phase operation, data is shifted
in on the falling edge of the SK clock and shifted out on the
18.1.2.1 Alternate SK Phase Operation and SK Idle rising edge of the SK clock. Bit 6 of Port G configuration
Polarity register selects the SK edge.
The device allows either the normal SK clock or an alternate A control flag, SKSEL, allows either the normal SK clock or
phase SK clock to shift data in and out of the SIO register. In the alternate SK clock to be selected. Refer to Table 32 for
both the modes the SK idle polarity can be either high or low. the appropriate setting of the SKSEL bit. The SKSEL is
The polarity is selected by bit 5 of Port G data register. In the mapped into the G6 configuration bit. The SKSEL flag will
normal mode data is shifted in on the rising edge of the SK power up in the reset condition, selecting the normal SK
clock and the data is shifted out on the falling edge of the SK signal provided the SK Idle Polarity remains LOW.
clock. The SIO register is shifted on each falling edge of the
TABLE 32. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase

Port G
SK Idle
SK Phase G6 (SKSEL) G5 Data SO Clocked Out On: SI Sampled On:
Phase
Config. Bit Bit
Normal 0 0 SK Falling Edge SK Rising Edge Low
Alternate 1 0 SK Rising Edge SK Falling Edge Low
Alternate 0 1 SK Rising Edge SK Falling Edge High
Normal 1 1 SK Falling Edge SK Rising Edge High
10137436
FIGURE 33. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
10137437
FIGURE 34. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
65 www.national.com
18.0 MICROWIRE/PLUS (Continued)
10137438
FIGURE 35. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High
10137439
FIGURE 36. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High
19.0 Memory Map Address

Contents
All RAM, ports and registers (except A and PC) are mapped S/ADD REG
into data memory address space. xxA7 Reserved for Port B
Address xxA8 ISP Address Register Low Byte
Contents
S/ADD REG (ISPADLO)
0000 to 006F On-Chip RAM bytes (112 bytes) xxA9 ISP Address Register High Byte
0070 to 007F Unused RAM Address Space (Reads As (ISPADHI)
All Ones) xxAA ISP Read Data Register (ISPRD)
xx80 to xx90 Unused RAM Address Space (Reads xxAB ISP Write Data Register (ISPWR)
Undefined Data) xxAC Reserved
xx90 Port E Data Register xxAD Reserved
xx91 Port E Configuration Register xxAE Reserved
xx92 Port E Input Pins (Read Only) xxAF High Speed Timers Control Register
xx93 Reserved for Port E (HSTCR)
xx94 Port F Data Register xxB0 Timer T3 Lower Byte
xx95 Port F Configuration Register xxB1 Timer T3 Upper Byte
xx96 Port F Input Pins (Read Only) xxB2 Timer T3 Autoload Register T3RA Lower
xx97 Reserved for Port F Byte
xx98 to xx9F Reserved xxB3 Timer T3 Autoload Register T3RA Upper
xxA0 Port A Data Register Byte
xxA1 Port A Configuration Register xxB4 Timer T3 Autoload Register T3RB Lower
Byte
xxA2 Port A Input Pins (Read Only)
xxB5 Timer T3 Autoload Register T3RB Upper
xxA3 Reserved for Port A
Byte
xxA4 Port B Data Register
xxB6 Timer T3 Control Register
xxA5 Port B Configuration Register
xxB7 Reserved
xxA6 Port B Input Pins (Read Only)
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19.0 Memory Map (Continued) Address
Contents
S/ADD REG
Address
Contents xxE0 Reserved
S/ADD REG
xxE1 Flash Memory Write Timing Register
xxB8 USART Transmit Buffer (TBUF)
(PGMTIM)
xxB9 USART Receive Buffer (RBUF)
xxE2 ISP Key Register (ISPKEY)
xxBA USART Control and Status Register
xxE3 to xxE5 Reserved
(ENU)
xxE6 Timer T1 Autoload Register T1RB Lower
xxBB USART Receive Control and Status
Byte
Register (ENUR)
xxE7 Timer T1 Autoload Register T1RB Upper
xxBC USART Interrupt and Clock Source
Byte
Register (ENUI)
xxE8 ICNTRL Register
xxBD USART Baud Register (BAUD)
xxE9 MICROWIRE/PLUS Shift Register
xxBE USART Prescale Select Register (PSR)
xxEA Timer T1 Lower Byte
xxBF Reserved for USART
xxEB Timer T1 Upper Byte
xxC0 Timer T2 Lower Byte
xxEC Timer T1 Autoload Register T1RA Lower
xxC1 Timer T2 Upper Byte
Byte
xxC2 Timer T2 Autoload Register T2RA Lower
xxED Timer T1 Autoload Register T1RA Upper
Byte
Byte
xxC3 Timer T2 Autoload Register T2RA Upper
xxEE CNTRL Control Register
Byte
xxEF PSW Register
xxC4 Timer T2 Autoload Register T2RB Lower
xxF0 to FB On-Chip RAM Mapped as Registers
Byte
xxFC X Register
xxC5 Timer T2 Autoload Register T2RB Upper
xxFD SP Register
Byte
xxFE B Register
xxC6 Timer T2 Control Register
xxFF S Register
xxC7 WATCHDOG Service Register
(Reg:WDSVR) 0100 to 017F On-Chip 128 RAM Bytes
xxC8 MIWU Edge Select Register 0200 to 027F On-Chip 128 RAM Bytes
(Reg:WKEDG) 0300 to 037F On-Chip 128 RAM Bytes
xxC9 MIWU Enable Register (Reg:WKEN) 0400 to 0047F On-Chip 128 RAM Bytes
xxCA MIWU Pending Register (Reg:WKPND) 0500 to 057F On-Chip 128 RAM Bytes
xxCB A/D Converter Control Register (ENAD) 0600 to 067F On-Chip 128 RAM Bytes
xxCC A/D Converter Result Register High Byte 0700 to 077F On-Chip 128 RAM Bytes
(ADRSTH) Note: Reading memory locations 0070H–007FH (Segment 0) will return all
xxCD A/D Converter Result Register Low Byte ones. Reading unused memory locations 0080H–0093H (Segment 0)
will return undefined data. Reading memory locations from other Seg-
(ADRSTL) ments (i.e., Segment 8, Segment 9, … etc.) will return undefined data.
xxCE Reserved
xxCF Idle Timer Control Register (ITMR) 20.0 Instruction Set
xxD0 Port L Data Register
20.1 INTRODUCTION
xxD1 Port L Configuration Register
This section defines the instruction set of the COP8 Family
xxD2 Port L Input Pins (Read Only) members. It contains information about the instruction set
xxD3 Reserved for Port L features, addressing modes and types.
xxD4 Port G Data Register
20.2 INSTRUCTION FEATURES
xxD5 Port G Configuration Register
The strength of the instruction set is based on the following
xxD6 Port G Input Pins (Read Only) features:
xxD7 Reserved • Mostly single-byte opcode instructions minimize program
xxD8 Port C Data Register size.
xxD9 Port C Configuration Register • One instruction cycle for the majority of single-byte in-
xxDA Port C Input Pins (Read Only) structions to minimize program execution time.
xxDB Reserved for Port C • Many single-byte, multiple function instructions such as
DRSZ.
xxDC Port D
• Three memory mapped pointers: two for register indirect
xxDD to xxDF Reserved for Port D addressing, and one for the software stack.
67 www.national.com
20.0 Instruction Set (Continued) Reg/Data Contents Contents
• Sixteen memory mapped registers that allow an opti- Memory Before After
mized implementation of certain instructions. Accumulator XX Hex A6 Hex
• Ability to set, reset, and test any individual bit in data Memory Location
memory address space, including the memory-mapped A6 Hex A6 Hex
0005 Hex
I/O ports and registers.
• Register-Indirect LOAD and EXCHANGE instructions Register B or X Indirect. The memory address is specified
with optional automatic post-incrementing or decrement- by the contents of the B Register or X register (pointer
ing of the register pointer. This allows for greater effi- register). In assembly language, the notation [B] or [X] speci-
ciency (both in cycle time and program code) in loading, fies which register serves as the pointer.
walking across and processing fields in data memory. Example: Exchange Memory with Accumulator, B Indirect
• Unique instructions to optimize program size and X A,[B]
throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC. Reg/Data Contents Contents
Memory Before After
20.3 ADDRESSING MODES Accumulator 01 Hex 87 Hex
The instruction set offers a variety of methods for specifying Memory Location
memory addresses. Each method is called an addressing 87 Hex 01 Hex
mode. These modes are classified into two categories: op- 0005 Hex
erand addressing modes and transfer-of-control addressing B Pointer 05 Hex 05 Hex
modes. Operand addressing modes are the various meth-
ods of specifying an address for accessing (reading or writ- Register B or X Indirect with Post-Incrementing/
ing) data. Transfer-of-control addressing modes are used in Decrementing. The relevant memory address is specified
conjunction with jump instructions to control the execution by the contents of the B Register or X register (pointer
sequence of the software program. register). The pointer register is automatically incremented
or decremented after execution, allowing easy manipulation
20.3.1 Operand Addressing Modes of memory blocks with software loops. In assembly lan-
The operand of an instruction specifies what memory loca- guage, the notation [B+], [B−], [X+], or [X−] specifies which
tion is to be affected by that instruction. Several different register serves as the pointer, and whether the pointer is to
operand addressing modes are available, allowing memory be incremented or decremented.
locations to be specified in a variety of ways. An instruction Example: Exchange Memory with Accumulator, B Indirect
can specify an address directly by supplying the specific with Post-Increment
address, or indirectly by specifying a register pointer. The X A,[B+]
contents of the register (or in some cases, two registers)
point to the desired memory location. In the immediate Reg/Data Contents Contents
mode, the data byte to be used is contained in the instruction Memory Before After
itself. Accumulator 03 Hex 62 Hex
Each addressing mode has its own advantages and disad- Memory Location
vantages with respect to flexibility, execution speed, and 62 Hex 03 Hex
program compactness. Not all modes are available with all 0005 Hex
instructions. The Load (LD) instruction offers the largest B Pointer 05 Hex 06 Hex
number of addressing modes.
Intermediate. The data for the operation follows the instruc-
The available addressing modes are:
tion opcode in program memory. In assembly language, the
• Direct number sign character (#) indicates an immediate operand.
• Register B or X Indirect Example: Load Accumulator Immediate
• Register B or X Indirect with Post-Incrementing/ LD A,#05
Decrementing
Reg/Data Contents Contents
• Immediate
• Immediate Short Memory Before After
• Indirect from Program Memory Accumulator XX Hex 05 Hex
The addressing modes are described below. Each descrip- Immediate Short. This is a special case of an immediate
tion includes an example of an assembly language instruc- instruction. In the “Load B immediate” instruction, the 4-bit
tion using the described addressing mode. immediate value in the instruction is loaded into the lower
Direct. The memory address is specified directly as a byte in nibble of the B register. The upper nibble of the B register is
the instruction. In assembly language, the direct address is reset to 0000 binary.
written as a numerical value (or a label that has been defined Example: Load B Register Immediate Short
elsewhere in the program as a numerical value).
LD B,#7
Example: Load Accumulator Memory Direct
LD A,05 Reg/Data Contents Contents
Memory Before After
B Pointer 12 Hex 07 Hex
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20.0 Instruction Set (Continued) Jump Absolute. In this 2-byte instruction, 12 bits of the
instruction opcode specify the new contents of the Program
Indirect from Program Memory. This is a special case of Counter. The upper three bits of the Program Counter re-
an indirect instruction that allows access to data tables main unchanged, restricting the new Program Counter ad-
stored in program memory. In the “Load Accumulator Indi- dress to the same 4-kbyte address space as the current
rect” (LAID) instruction, the upper and lower bytes of the instruction. (This restriction is relevant only in devices using
Program Counter (PCU and PCL) are used temporarily as a more than one 4-kbyte program memory space.)
pointer to program memory. For purposes of accessing pro- Example: Jump Absolute
gram memory, the contents of the Accumulator and PCL are
JMP 0125
exchanged. The data pointed to by the Program Counter is
loaded into the Accumulator, and simultaneously, the original Contents Contents
contents of PCL are restored so that the program can re- Reg
Before After
sume normal execution.
PCU 0C Hex 01 Hex
Example: Load Accumulator Indirect
PCL 77 Hex 25 Hex
LAID
Reg/Data Contents Contents Jump Absolute Long. In this 3-byte instruction, 15 bits of
the instruction opcode specify the new contents of the Pro-
Memory Before After gram Counter.
PCU 04 Hex 04 Hex Example: Jump Absolute Long
PCL 35 Hex 36 Hex JMP 03625
Accumulator 1F Hex 25 Hex
Reg/ Contents Contents
Memory Location
25 Hex 25 Hex Memory Before After
041F Hex
PCU 42 Hex 36 Hex
PCL 36 Hex 25 Hex
20.3.2 Tranfer-of-Control Addressing Modes
Program instructions are usually executed in sequential or- Jump Indirect. In this 1-byte instruction, the lower byte of
der. However, Jump instructions can be used to change the the jump address is obtained from a table stored in program
normal execution sequence. Several transfer-of-control ad- memory, with the Accumulator serving as the low order byte
dressing modes are available to specify jump addresses. of a pointer into program memory. For purposes of access-
A change in program flow requires a non-incremental ing program memory, the contents of the Accumulator are
change in the Program Counter contents. The Program written to PCL (temporarily). The data pointed to by the
Counter consists of two bytes, designated the upper byte Program Counter (PCH/PCL) is loaded into PCL, while PCH
(PCU) and lower byte (PCL). The most significant bit of PCU remains unchanged.
is not used, leaving 15 bits to address the program memory. Example: Jump Indirect
Different addressing modes are used to specify the new JID
address for the Program Counter. The choice of addressing
Reg/ Contents Contents
mode depends primarily on the distance of the jump. Farther
jumps sometimes require more instruction bytes in order to Memory Before After
completely specify the new Program Counter contents. PCU 01 Hex 01 Hex
The available transfer-of-control addressing modes are: PCL C4 Hex 32 Hex
• Jump Relative Accumulator 26 Hex 26 Hex
• Jump Absolute Memory
• Jump Absolute Long Location 32 Hex 32 Hex
• Jump Indirect 0126 Hex
The transfer-of-control addressing modes are described be-
low. Each description includes an example of a Jump in- The VIS instruction is a special case of the Indirect Transfer
struction using a particular addressing mode, and the effect of Control addressing mode, where the double-byte vector
on the Program Counter bytes of executing that instruction. associated with the interrupt is transferred from adjacent
Jump Relative. In this 1-byte instruction, six bits of the addresses in program memory into the Program Counter in
instruction opcode specify the distance of the jump from the order to jump to the associated interrupt service routine.
current program memory location. The distance of the jump
can range from −31 to +32. A JP+1 instruction is not allowed. 20.4 INSTRUCTION TYPES
The programmer should use a NOP instead. The instruction set contains a wide variety of instructions.
Example: Jump Relative The available instructions are listed below, organized into
related groups.
JP 0A
Some instructions test a condition and skip the next instruc-
Contents Contents tion if the condition is not true. Skipped instructions are
Reg
Before After executed as no-operation (NOP) instructions.
PCU 02 Hex 02 Hex
PCL 05 Hex 0F Hex
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20.0 Instruction Set (Continued) 20.4.6 Stack Control Instructions
Push Data onto Stack (PUSH)
20.4.1 Arithmetic Instructions
Pop Data off of Stack (POP)
The arithmetic instructions perform binary arithmetic such as
addition and subtraction, with or without the Carry bit. 20.4.7 Memory Bit Manipulation Instructions
Add (ADD) The memory bit manipulation instructions allow the user to
Add with Carry (ADC) set and reset individual bits in memory.
Subtract with Carry (SUBC) Set Bit (SBIT)
Increment (INC) Reset Bit (RBIT)
Decrement (DEC) Reset Pending Bit (RPND)
Decimal Correct (DCOR)
20.4.8 Conditional Instructions
Clear Accumulator (CLR)
The conditional instruction test a condition. If the condition is
Set Carry (SC)
true, the next instruction is executed in the normal manner; if
Reset Carry (RC) the condition is false, the next instruction is skipped.
If Equal (IFEQ)
20.4.2 Transfer-of-Control Instructions
If Not Equal (IFNE)
The transfer-of-control instructions change the usual se-
quential program flow by altering the contents of the Pro- If Greater Than (IFGT)
gram Counter. The Jump to Subroutine instructions save the If Carry (IFC)
Program Counter contents on the stack before jumping; the If Not Carry (IFNC)
Return instructions pop the top of the stack back into the
If Bit (IFBIT)
Program Counter.
If B Pointer Not Equal (IFBNE)
Jump Relative (JP)
And Skip if Zero (ANDSZ)
Jump Absolute (JMP)
Decrement Register and Skip if Zero (DRSZ)
Jump Absolute Long (JMPL)
Jump Indirect (JID) 20.4.9 No-Operation Instruction
Jump to Subroutine (JSR) The no-operation instruction does nothing, except to occupy
Jump to Subroutine Long (JSRL) space in the program memory and time in execution.
Jump to Boot ROM Subroutine (JSRB) No-Operation (NOP)
Return from Subroutine (RET) Note: The VIS is a special case of the Indirect Transfer of
Return from Subroutine and Skip (RETSK) Control addressing mode, where the double byte vector
associated with the interrupt is transferred from adjacent
Return from Interrupt (RETI)
addresses in the program memory into the program counter
Software Trap Interrupt (INTR) (PC) in order to jump to the associated interrupt service
Vector Interrupt Select (VIS) routine.
20.4.3 Load and Exchange Instructions 20.5 REGISTER AND SYMBOL DEFINITION
The load and exchange instructions write byte values in The following abbreviations represent the nomenclature
registers or memory. The addressing mode determines the used in the instruction description and the COP8 cross-
source of the data. assembler.
Load (LD) Registers
Load Accumulator Indirect (LAID)
A 8-Bit Accumulator Register
Exchange (X)
B 8-Bit Address Register
20.4.4 Logical Instructions X 8-Bit Address Register
The logical instructions perform the operations AND, OR, S 8-Bit Segment Register
and XOR (Exclusive OR). Other logical operations can be SP 8-Bit Stack Pointer Register
performed by combining these basic operations. For ex-
PC 15-Bit Program Counter Register
ample, complementing is accomplished by exclusive-ORing
the Accumulator with FF Hex. PU Upper 7 Bits of PC
Logical AND (AND) PL Lower 8 Bits of PC
Logical OR (OR) C 1 Bit of PSW Register for Carry
Exclusive OR (XOR) HC 1 Bit of PSW Register for Half Carry
GIE 1 Bit of PSW Register for Global Interrupt
20.4.5 Accumulator Bit Manipulation Instructions
Enable
The Accumulator bit manipulation instructions allow the user
VU Interrupt Vector Upper Byte
to shift the Accumulator bits and to swap its two nibbles.
Rotate Right Through Carry (RRC) VL Interrupt Vector Lower Byte
Rotate Left Through Carry (RLC)
Swap Nibbles of Accumulator (SWAP)
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20.0 Instruction Set (Continued) Symbols
Imm 8-Bit Immediate Data
Symbols
Reg Register Memory: Addresses F0 to FF
[B] Memory Indirectly Addressed by B Register
(Includes B, X and SP)
[X] Memory Indirectly Addressed by X Register
Bit Bit Number (0 to 7)
MD Direct Addressed Memory
← Loaded with
Mem Direct Addressed Memory or [B] ↔ Exchanged with
Meml Direct Addressed Memory or [B] or
Immediate Data
71 www.national.com
20.0 Instruction Set (Continued)
20.6 INSTRUCTION SET SUMMARY
ADD A,Meml ADD A←A + Meml

ADC A,Meml ADD with Carry A←A + Meml + C, C←Carry,
HC←Half Carry
SUBC A,Meml Subtract with Carry A←A − MemI + C, C←Carry,
HC←Half Carry
AND A,Meml Logical AND A←A and Meml
ANDSZ A,Imm Logical AND Immed., Skip if Zero Skip next if (A and Imm) = 0
OR A,Meml Logical OR A←A or Meml
XOR A,Meml Logical EXclusive OR A←A xor Meml
IFEQ MD,Imm IF EQual Compare MD and Imm, Do next if MD = Imm
IFEQ A,Meml IF EQual Compare A and Meml, Do next if A = Meml
IFNE A,Meml IF Not Equal Compare A and Meml, Do next if A ≠ Meml
IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A > Meml
IFBNE # If B Not Equal Do next if lower 4 bits of B ≠ Imm
DRSZ Reg Decrement Reg., Skip if Zero Reg←Reg − 1, Skip if Reg = 0
SBIT #,Mem Set BIT 1 to bit, Mem (bit = 0 to 7 immediate)
RBIT #,Mem Reset BIT 0 to bit, Mem
IFBIT #,Mem IF BIT If bit #,A or Mem is true do next instruction
RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag
X A,Mem EXchange A with Memory A↔Mem
X A,[X] EXchange A with Memory [X] A↔[X]
LD A,Meml LoaD A with Memory A←Meml
LD A,[X] LoaD A with Memory [X] A←[X]
LD B,Imm LoaD B with Immed. B←Imm
LD Mem,Imm LoaD Memory Immed. Mem←Imm
LD Reg,Imm LoaD Register Memory Immed. Reg←Imm
X A, [B ± ] EXchange A with Memory [B] A↔[B], (B←B ± 1)
X A, [X ± ] EXchange A with Memory [X] A↔[X], (X←X ± 1)
LD A, [B ± ] LoaD A with Memory [B] A←[B], (B←B ± 1)
LD A, [X ± ] LoaD A with Memory [X] A←[X], (X←X ± 1)
LD [B ± ],Imm LoaD Memory [B] Immed. [B]←Imm, (B←B ± 1)
CLR A CLeaR A A←0
INC A INCrement A A←A + 1
DEC A DECrement A A←A − 1
LAID Load A InDirect from ROM A←ROM (PU,A)
DCOR A Decimal CORrect A A←BCD correction of A (follows ADC, SUBC)
RRC A Rotate A Right thru C C→A7→…→A0→C
RLC A Rotate A Left thru C C←A7←…←A0←C, HC←A0
SWAP A SWAP nibbles of A A7…A4↔A3…A0
SC Set C C←1, HC←1
RC Reset C C←0, HC←0
IFC IF C IF C is true, do next instruction
IFNC IF Not C If C is not true, do next instruction
POP A POP the stack into A SP←SP + 1, A←[SP]
PUSH A PUSH A onto the stack [SP]←A, SP←SP − 1
VIS Vector to Interrupt Service Routine PU←[VU], PL←[VL]
JMPL Addr. Jump absolute Long PC←ii (ii = 15 bits, 0 to 32k)
JMP Addr. Jump absolute PC9…0←i (i = 12 bits)
JP Disp. Jump relative short PC←PC + r (r is −31 to +32, except 1)
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JSRL Addr. Jump SubRoutine Long [SP] ←PL, [SP−1]←PU,SP−2, PC←ii

JSR Addr. Jump SubRoutine [SP]←PL, [SP−1]←PU,SP−2, PC9…0←i
JSRB Addr Jump SubRoutine Boot ROM [SP]←PL, [SP−1]←PU,SP−2,
PL←Addr,PU←00, switch to flash
JID Jump InDirect PL←ROM (PU,A)
RET RETurn from subroutine SP + 2, PL←[SP], PU←[SP−1]
RETSK RETurn and SKip SP + 2, PL←[SP],PU←[SP−1],
skip next instruction
RETI RETurn from Interrupt SP + 2, PL←[SP],PU←[SP−1],GIE←1
INTR Generate an Interrupt [SP]←PL, [SP−1]←PU, SP−2, PC←0FF
NOP No OPeration PC←PC + 1
20.7 INSTRUCTION EXECUTION TIME Instructions Using A & C

Most instructions are single byte (with immediate addressing
CLRA 1/1
mode instructions taking two bytes).
INCA 1/1
Most single byte instructions take one cycle time to execute.
DECA 1/1
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped LAID 1/3
instruction opcode. DCORA 1/1
See the BYTES and CYCLES per INSTRUCTION table for RRCA 1/1
details.
RLCA 1/1
Bytes and Cycles per Instruction
SWAPA 1/1
The following table shows the number of bytes and cycles for
SC 1/1
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions RC 1/1
IFC 1/1
[B] Direct Immed.
IFNC 1/1
ADD 1/1 3/4 2/2
PUSHA 1/3
ADC 1/1 3/4 2/2
POPA 1/3
SUBC 1/1 3/4 2/2
ANDSZ 2/2
AND 1/1 3/4 2/2
Transfer of Control Instructions
OR 1/1 3/4 2/2
XOR 1/1 3/4 2/2 JMPL 3/4
IFEQ 1/1 3/4 2/2 JMP 2/3
IFGT 1/1 3/4 2/2 JP 1/3
IFBNE 1/1 JSRL 3/5
DRSZ 1/3 JSR 2/5
SBIT 1/1 3/4 JSRB 2/5
RBIT 1/1 3/4 JID 1/3
IFBIT 1/1 3/4 VIS 1/5

RET 1/5
RPND 1/1
RETSK 1/5
RETI 1/5
INTR 1/7
NOP 1/1
73 www.national.com
Memory Transfer Instructions

Register Register Indirect
Indirect Direct Immed. Auto Incr. & Decr.
[B] [X] [B+, B−] [X+, X−]
X A, (Note 21) 1/1 1/3 2/3 1/2 1/3
LD A, (Note 21) 1/1 1/3 2/3 2/2 1/2 1/3
LD B,Imm 1/1 (If B < 16)
LD B,Imm 2/2 (If B > 15)
LD Mem,Imm 2/2 3/3 2/2
LD Reg,Imm 2/3
IFEQ MD,Imm 3/3
Note 21: = > Memory location addressed by B or X or directly.
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OPCODE TABLE
Upper Nibble
F E D C B A 9 8 7 6 5 4 3 2 1 0
JP−15 JP−31 LD 0F0,#i DRSZ RRCA RC ADC ADC IFBIT ANDSZ LD IFBNE 0 JSR JMP JP+17 INTR 0
0F0 A,#i A,[B] 0,[B] A,#i B,#0F x000–x0FF x000–x0FF
JP−14 JP−30 LD 0F1,#i DRSZ * SC SUBC SUBC IFBIT JSRB LD IFBNE 1 JSR JMP JP+18 JP+2 1
0F1 A,#i A,[B] 1,[B] B,#0E x100–x1FF x100–x1FF
JP−13 JP−29 LD 0F2,#i DRSZ X A,[X+] X IFEQ IFEQ IFBIT Re- LD IFBNE 2 JSR JMP JP+19 JP+3 2
0F2 A,[B+] A,#i A,[B] 2,[B] served B,#0D x200–x2FF x200–x2FF
JP−12 JP−28 LD 0F3,#i DRSZ X A,[X−] X IFGT IFGT IFBIT Re- LD IFBNE 3 JSR JMP JP+20 JP+4 3
0F3 A,[B−] A,#i A,[B] 3,[B] served B,#0C x300–x3FF x300–x3FF
JP−11 JP−27 LD 0F4,#i DRSZ VIS LAID ADD ADD IFBIT CLRA LD IFBNE 4 JSR JMP JP+21 JP+5 4
0F4 A,#i A,[B] 4,[B] B,#0B x400–x4FF x400–x4FF
JP−10 JP−26 LD 0F5,#i DRSZ RPND JID AND AND IFBIT SWAPA LD IFBNE 5 JSR JMP JP+22 JP+6 5
0F5 A,#i A,[B] 5,[B] B,#0A x500–x5FF x500–x5FF
JP−9 JP−25 LD 0F6,#i DRSZ X A,[X] X A,[B] XOR XOR IFBIT DCORA LD IFBNE 6 JSR JMP JP+23 JP+7 6
0F6 A,#i A,[B] 6,[B] B,#09 x600–x6FF x600–x6FF
75
JP−8 JP−24 LD 0F7,#i DRSZ * * OR A,#i OR IFBIT PUSHA LD IFBNE 7 JSR JMP JP+24 JP+8 7
0F7 A,[B] 7,[B] B,#08 x700–x7FF x700–x7FF
JP−7 JP−23 LD 0F8,#i DRSZ NOP RLCA LD A,#i IFC SBIT RBIT LD IFBNE 8 JSR JMP JP+25 JP+9 8
0F8 0,[B] 0,[B] B,#07 x800–x8FF x800–x8FF
JP−6 JP−22 LD 0F9,#i DRSZ IFNE IFEQ IFNE IFNC SBIT RBIT LD IFBNE 9 JSR JMP JP+26 JP+10 9
Lower Nibble
0F9 A,[B] Md,#i A,#i 1,[B] 1,[B] B,#06 x900–x9FF x900–x9FF

JP−5 JP−21 LD 0FA,#i DRSZ LD LD LD INCA SBIT RBIT LD IFBNE 0A JSR JMP JP+27 JP+11 A
0FA A,[X+] A,[B+] [B+],#i 2,[B] 2,[B] B,#05 xA00–xAFF xA00–xAFF
JP−4 JP−20 LD 0FB,#i DRSZ LD LD LD DECA SBIT RBIT LD IFBNE 0B JSR JMP JP+28 JP+12 B
0FB A,[X−] A,[B−] [B−],#i 3,[B] 3,[B] B,#04 xB00–xBFF xB00–xBFF
JP−3 JP−19 LD 0FC,#i DRSZ LD Md,#i JMPL X A,Md POPA SBIT RBIT LD IFBNE 0C JSR JMP JP+29 JP+13 C
0FC 4,[B] 4,[B] B,#03 xC00–xCFF xC00–xCFF
JP−2 JP−18 LD 0FD,#i DRSZ DIR JSRL LD A,Md RETSK SBIT RBIT LD IFBNE 0D JSR JMP JP+30 JP+14 D
0FD 5,[B] 5,[B] B,#02 xD00–xDFF xD00–xDFF
JP−1 JP−17 LD 0FE,#i DRSZ LD A,[X] LD LD [B],#i RET SBIT RBIT LD IFBNE 0E JSR JMP JP+31 JP+15 E
0FE A,[B] 6,[B] 6,[B] B,#01 xE00–xEFF xE00–xEFF
JP−0 JP−16 LD 0FF,#i DRSZ * * LD B,#i RETI SBIT RBIT LD IFBNE 0F JSR JMP JP+32 JP+16 F
0FF 7,[B] 7,[B] B,#00 xF00–xFFF xF00–xFFF
* is an unused opcode i is the immediate data Md is a directly addressed memory location The opcode 60 Hex is also the opcode for IFBIT #i,A
www.national.com
21.0 Development Support
21.1 TOOLS ORDERING NUMBERS FOR THE COP8 FLASH FAMILY DEVICES
This section provides specific tools ordering information for the devices in this datasheet, followed by a summary of the tools and
development kits available at print time. Up-to-date information, device selection guides, demos, updates, and purchase
information can be obtained at our web site at: www.national.com/cop8.
Unless otherwise noted, tools can be purchased for worldwide delivery from National’s e-store: http://www.national.com/
store/
Tool Order Number Cost* Notes/Includes
Evaluation Software and Reference Designs
Software and Web Downloads: Free Assembler/ Linker/ Simulators/ Library Manager/
Utilities www.national.com/cop8 Compiler Demos/ Flash ISP and NiceMon Debugger
Utilities/ Example Code/ etc.
(Flash Emulator support requires licensed COP8-NSDEV
CD-ROM).
Hardware COP8-REF-FL1 VL For COP8Flash Sx/Cx - Demo Board and Software;
Reference Designs 44PLCC Socket; Stand-alone, or use as development target
board with Flash ISP and/or COP8Flash Emulator. Does not
include COP8 development software.
COP8-REF-AM VL For COP8Flash Ax - Demo Board and Software; 28DIP
Socket. Stand alone, or use as development target board
with Flash ISP and/or COP8Flash Emulator. Does not
include COP8 development software.
Starter Kits and Hardware Target Boards
Starter COP8-SKFLASH-01 VL Supports COP8Sx/Cx/Ax - Target board with 68PLCC
Development Kits COP8CDR9, 44PLCC and 28DIP sockets, LEDs, Test
Points, and Breadboard Area. Development CD, ISP Cable,
Debug Software and Source Code. No p/s. Also supports
COP8Flash Emulators and Kanda ISP Tool.
COP8-REF-FL1 or VL COP8Flash Hardware Reference Design boards can also be
COP8-REF-AM used as Development Target boards, with ISP and Emulator
onboard connectors.
Software Development Languages, and Integrated Development Environments
National’s WCOP8 COP8-NSDEV $3 Fully Licensed IDE with Assembler and
IDE and Assembler Emulator/Debugger Support. Assembler/ Linker/ Simulator/
on CD Utilities/ Documentation. Updates from web. Included with
SKFlash, COP8 Emulators, COP8-PM.
COP8 Library www.kkd.dk/libman.htm Eval The ultimate information source for COP8 developers -
Manager from KKD Integrates with WCOP8 IDE. Organize and manage code,
notes, datasheets, etc.
WEBENCH Online www.national.com Free Online Graphical IDE, featuring UNIS Processor Expert(
Graphical /webench Code Development Tool with Simulator - Develop
Application Builder applications, simulate and debug, download working code.
With Unis Online project manager.
Processor Expert COP8-SW-PE2 L Graphical IDE and Code Development Tool with
Simulator - Stand-alone, enhanced PC version of our
WEBENCH tools on CD.
Byte Craft C COP8-SW-COP8C M DOS/16bit Version - No IDE.
Compiler COP8-SW-COP8CW H Win 32 Version with IDE.
IAR Embedded COP8-SW-EWCOP8 H Complete tool set, with COP8 Emulator/Debugger support.
Workbench Tool EWCOP8-BL M Baseline version - Purchase from IAR only.
Set. Assembler-Only Version Free Assembler only; No COP8 Emulator/Debugger support.
www.national.com 76
21.0 Development Support (Continued)
Hardware Emulation and Debug Tools

Hardware COP8-EMFlash-00 L Includes 110v/220v p/s, target cable with 2x7 connector, 68
Emulators COP8-DMFlash-00 M pin COP8CDR9 Null Target, manuals and software on CD.
COP8-IMFlash-00 H - COP8AME/ANE9 uses optional 28 pin Null Target
(COP8-EMFA-28N).
- Add PLCC Target Package Adapter if needed.
Emulator Null COP8-EMFA-68N VL 68 pin PLCC COP8CDR9; Included in COP8-EM/DM/IM
Target COP8-EMFA-28N VL Flash.
28pin DIP COP8AME9; Must order seperately.
Emulator Target COP8-EMFA-44P VL 44 pin PLCC target package adapter. (Use instead of 2x7
Package Adapters emulator header)
COP8-EMFA-68P VL 68 pin PLCC target package adapter. (Use instead of 2x7
emulator header)
NiceMon Debug COP8-SW-NMON Free Download code and Monitor S/W for single-step debugging
Monitor Utility via Microwire. Includes PC control/debugger software and
monitor program.
Development and Production Programming Tools
National’s COP8-PM-02 L Board with 40DIP ZIF base socket for optional COP8FLASH
Engineering (Available late 2004) programming adapters; Includes 110v/220v p/s, manuals
Programmer and software on CD; (Requires optional -PGMA
programming adapters for flash)
Programming COP8-PGMA-28DF1 L For programming 28DIP COP8AM/AN only.
Adapters COP8-PGMA-28SF1 L For programming 28SOIC COP8AM/AN only.
(For any COP8-PGMA-44PF1 L For programming all 44PLCC COP8FLASH.
programmer COP8-PGMA-44CSF L For programming all 44LLP COP8FLASH.
supporting flash
COP8-PGMA-48TF1 L For programming all 48TSSOP COP8 FLASH.
adapter base
COP8-PGMA-68PF1 L For programming all 68PLCC COP8FLASH
pinout)
COP8-PGMA-56TF1 L For programming all 56TSSOP COP8FLASH.
KANDA’s Flash COP8ISP L Parallel/Serial connected Dongle, with target cable and
ISP Programmer www.kanda.com Control Software; Updateable from the web; Purchase from
www.kanda.com
Softec Flash ISP www.softecmicro.com L Serial connected cable, with control software; Purchase
Programmer from www.softecmicro.com
Development COP8CBR9/CCR9/CDR9 Free All packages. Obtain samples from: www.national.com
Devices COP8CBE9/CCE9
COP8SBR9/SCR9/SDR9
COP8SBE9/SCE9
COP8AME9/ANE9
*Cost: Free; VL= < $100; L=$100-$300; M=$300-$1k; H=$1k-$3k; VH=$3k-$5k
77 www.national.com
21.2 COP8 TOOLS OVERVIEW
COP8 Evaluation Software and Reference Designs -

Software and Hardware for: Evaluation of COP8 Development Environments; Learning about COP8 Architecture and
Features; Demonstrating Application Specific Capabilities.
Product Description Source
WCOP8 IDE and Software Evaluation downloads for Windows. Includes WCOP8 IDE evaluation www.cop8.com
Software version, Full COP8 Assembler/Linker, COP8-SIM Instruction Level Simulator or Unis FREE Download
Downloads Simulator, Byte Craft COP8C Compiler Demo, IAR Embedded Workbench
(Assembler version), Manuals, Applications Software, and other COP8 technical
information.
COP8 Hardware Reference Designs for COP8 Families. Realtime hardware environments with a NSC Distributor,
Reference variety of functions for demonstrating the various capabilities and features of specific or Order from:
Designs COP8 device families. Run Windows demo reference software, and exercise www.cop8.com
specific device capabilities. Also can be used as a realtime target board for code
development, with our flash development tools.
(Add our COP8Flash Emulator, or our COP8-NSDEV CD with your ISP cable for a
complete low-cost development system.)
COP8 Starter Kits and Hardware Target Solutions -

Hardware Kits for: In-depth Evaluation and Testing of COP8 capabilities; Developing and Testing Code; Implementing
Target Design.
COP8 Flash Flash Starter Kit - A complete Code Development Tool for COP8Flash Families. A NSC Distributor,
Starter Kits Windows IDE with Assembler, Simulator, and Debug Monitor, combined with a or Order from:
simple realtime target environment. Quickly design and simulate your code, then www.cop8.com
download to the target COP8flash device for execution and simple debugging.
Includes a library of software routines, and source code. No power supply.
(Add a COP8-EMFlash Emulator for advanced emulation and debugging)
COP8 Hardware Preconfigured realtime hardware environments with a variety of onboard I/O and NSC Distributor,
Reference display functions. Modify the reference software, or develop your own code. Boards or Order from:
Designs support our COP8 ISP Utility, NiceMon Flash Debug Monitor, and our COP8Flash www.cop8.com
Emulators.
COP8 Software Development Languages and Integrated Environments -

Integrated Software for: Project Management; Code Development; Simulation and Debug.
WCOP8 IDE National’s COP8 Software Development package for Windows on CD. Fully licensed NSC Distributor,
from National on versions of our WCOP8 IDE and Emulator Debugger, with Assembler/ Linker/ or Order from:
CD-ROM Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger www.cop8.com
Utilities/ Example Code/ etc. Includes all COP8 datasheets and documentation.
Included with most tools from National.
Unis Processor Processor Expert( from Unis Corporation - COP8 Code Generation and Simulation Unis, or Order
Expert tool with Graphical and Traditional user interfaces. Automatically generates from:
customized source code "Beans" (modules) containing working code for all on-chip www.cop8.com
features and peripherals, then integrates them into a fully functional application code
design, with all documentation.
Byte Craft ByteCraft COP8C- C Cross-Compiler and Code Development System. Includes ByteCraft
COP8C Compiler BCLIDE (Integrated Development Environment) for Win32, editor, optimizing C Distributor,
Cross-Compiler, macro cross assembler, BC-Linker, and MetaLinktools support. or Order from:
(DOS/SUN versions available; Compiler is linkable under WCOP8 IDE) www.cop8.com
IAR Embedded IAR EWCOP8 - ANSI C-Compiler and Embedded Workbench. A fully integrated IAR Distributor,
Workbench Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy or Order from:
high-level simulator/debugger. (EWCOP8-M version includes COP8Flash Emulator www.cop8.com
support) (EWCOP8-BL version is limited to 4k code limit; no FP).
www.national.com 78
COP8 Hardware Emulation/Debug Tools -

Hardware Tools for: Real-time Emulation; Target Hardware Debug; Target Design Test.
COP8Flash COP8 In-Circuit Emulator for Flash Families. Windows based development and NSC Distributor,
Emulators - real-time in-circuit emulation tool, with trace (EM=None; DM/IM=32k), s/w or Order from:
COP8-EMFlash breakpoints (DM=16, EM/IM=32K), source/symbolic debugger, and device www.cop8.com
COP8-DMFlash programming. Includes COP8-NDEV CD, 68pin Null Target, emulation cable with
COP8-IMFlash 2x7 connector, and power supply.
NiceMon Debug A simple, single-step debug monitor with one breadpoint. MICROWIRE interface. Download from:
Monitor Utility www.cop8.com
Development and Production Programming Tools -

Programmers for: Design Development; Hardware Test; Pre-Production; Full Production.
COP8 Flash COP8 Flash Emulators include in-circuit device programming capability during NSC Distributor, or
Emulators development. Order from:
www.cop8.com
NiceMon National’s software Utilities "KANDAFlash" and "NiceMon" provide development Download from:
Debugger, In-System-Programming for our Flash Starter Kit, our Prototype Development www.cop8.com
KANDAFlash Board, or any other target board with appropriate connectors.
KANDA The COP8-ISP programmer from KANDA is available for engineering, and small www.kanda.com
COP8-ISP volume production use. PC parallel or serial interface.
SofTec Micro The inDart COP8 programmer from KANDA is available for engineering and www.softecmicro.com
inDart COP8 small volume production use. PC serial interface only.
COP8 COP8-PM Development Programming Module. Windows programming tool for NSC Distributor, or
Programming COP8 OTP and Flash Families. Includes on-board 40 DIP programming socket, Order from web.
Module control software, RS232 cable, and power supply. (Requires optional
COP8-PGMA programming adapters for COP8FLASH devices)
Third-Party A variety of third-party programmers and automatic handling equipment are Various Vendors
Programmers approved for non-ISP engineering and production use.
Factory Factory programming available for high-volume requirements. National
Programming Representative
21.3 WHERE TO GET TOOLS

Tools can be ordered directly from National, National’s e-store (Worldwide delivery: http://www.national.com/store/) , a National
Distributor, or from the tool vendor. Go to the vendor’s web site for current listings of distributors.
Vendor Home Office Electronic Sites Other Main Offices
Byte Craft Limited 421 King Street North www.bytecraft.com Distributors Worldwide
Waterloo, Ontario [email protected]
Canada N2J 4E4
Tel: 1-(519) 888-6911
Fax: (519) 746-6751
IAR Systems AB PO Box 23051 www.iar.se USA:: San Francisco
S-750 23 Uppsala [email protected] Tel: +1-415-765-5500
Sweden [email protected] Fax: +1-415-765-5503
Tel: +46 18 16 78 00 [email protected] UK: London
Fax +46 18 16 78 38 [email protected] Tel: +44 171 924 33 34
Fax: +44 171 924 53 41
Germany: Munich
Tel: +49 89 470 6022
Fax: +49 89 470 956
79 www.national.com
Vendor Home Office Electronic Sites Other Main Offices

KANDA Systems Unit 17 -18 www.kanda.com USA:
LTD. Glanyrafon Enterprise Park, [email protected] Tel: 303-456-2060
Aberystwyth, Ceredigion, Fax: 303-456-2404
SY23 3JQ, UK [email protected]
Tel: +44 1970 621041 www.logicaldevices.net
Fax: +44 1970 621040
K and K Kaergaardsvej 42 DK-8355 www.kkd.dk [email protected]
Development ApS Solbjerg Denmark
Fax: +45-8692-8500
National 2900 Semiconductor Dr. www.national.com/cop8 Europe:
Semiconductor Santa Clara, CA 95051 support @nsc.com Tel: 49(0) 180 530 8585
USA [email protected] Fax: 49(0) 180 530 8586
Tel: 1-800-272-9959 Hong Kong:
Fax: 1-800-737-7018 Distributors Worldwide
SofTec Microsystems Via Roma, 1 [email protected] Germany:
33082 Azzano Decimo (PN) www.softecmicro.com Tel.:+49 (0) 8761 63705
Italy [email protected] France:
Tel: +39 0434 640113 Tel: +33 (0) 562 072 954
Fax: +39 0434 631598 UK:
Tel: +44 (0) 1970 621033
The following companies have approved COP8 programmers in a variety of configurations. Contact your vendor’s local office
or distributor and request a COP8FLASH update. You can link to their web sites and get the latest listing of approved
programmers at: www.national.com/cop8.
Advantech; BP Microsystems; Data I/O; Dataman; Hi-Lo Systems; KANDA, Lloyd Research; MQP; Needhams; Phyton; SofTec
Microsystems; System General; and Tribal Microsystems.
22.0 Revision History

Date Section Summary of Changes
October 2000 Base revision for this history.
April 2001 Throughout Various typographical errors.
Electrical Specifications Reduced dynamic supply current specification.
Reduced input leakage current.
Added general statement regarding specification limits.
Added temp range 7 (−40˚C to +125˚C)
In-System Programming Clarified use of high voltage on G6 pin to force execution from Boot ROM.
May 2001 Added LLP and TSSOP Packages
Sept., 2001 Development Support Updated with the latest support information.
January 2002 Forced Execution from Added Figure.
Boot ROM
April 2002 Pin Descriptions Caution on GND connection on LLP package.
Timers Clarification on high speed PWM Timer use.
Development Support Updated with the latest support information.
August 2003 Pin Descriptions Clarification of the functions of L4 and L6 for T2 and T3 PWM Output.
Reset Addition of caution regarding rising edge on RESET with low VCC.
Power Saving Features Description of modified function of ITMR Register.
A/D Converter Updated specifications to reflect final product and test specifications.
Specifications
Development Support Updated with the latest support information.
Released as final.
www.national.com 80
23.0 Physical Dimensions inches (millimeters) unless otherwise noted
LLP Package (LQA)

Order Number COP8CBR9HLQ8 or COP8CCR9HLQ7 or COP8CDR9HLQ7
or COP8CCR9HLQ8 or COP8CDR9HLQ8
NS Package Number LQA44A
81 www.national.com
23.0 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
TSSOP Package (MTD)

Order Number COP8CBR9IMT8 or COP8CCR9IMT7 or COP8CDR9IMT7
or COP8CCR9IMT8 or COP8CDR9IMTA8
NS Package Number MTD48
TSSOP Package (MTD)

Order Number COP8CBR9KMT8 or COP8CCR9KMT7 or COP8CCR9KMT8
or COP8CDR9KMT7 or COP8CDR9KMTA8
NS Package Number MTD56
www.national.com 82
23.0 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier (VA)

Order Number COP8CBR9HVA8 or COP8CCR9HVA7 or COP8CCR9HVA8
or COP8CDR9HVA7 or COP8CDR9HVA8
NS Package Number V44A
Plastic Leaded Chip Carrier (VA)

Order Number COP8CBR9LVA8 or COP8CCR9LVA7 or COP8CCR9LVA8
or COP8CDR9LVA7 or COP8CDR9LVA8
NS Package Number V68A
83 www.national.com
COP8CBR9/COP8CCR9/COP8CDR9 8-Bit CMOS Flash Based Microcontroller with 32k Memory,
Notes
LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform
into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of
whose failure to perform when properly used in the life support device or system, or to affect its
accordance with instructions for use provided in the safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center
Support Center Fax: +49 (0) 180-530 85 86 Support Center Fax: 81-3-5639-7507
Email: [email protected] Email: [email protected] Email: [email protected] Email: [email protected]
Tel: 1-800-272-9959 Deutsch Tel: +49 (0) 69 9508 6208 Tel: 81-3-5639-7560
English Tel: +44 (0) 870 24 0 2171
www.national.com Français Tel: +33 (0) 1 41 91 8790
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Cop8Cbr9/Cop8Ccr9/Cop8Cdr9 8-Bit CMOS Flash Microcontroller With 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout

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Cop8Cbr9/Cop8Ccr9/Cop8Cdr9 8-Bit CMOS Flash Microcontroller With 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout

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Virtual EEPROM, 10-Bit A/D and Brownout

COP8CBR9/COP8CCR9/COP8CDR9 8-Bit CMOS Flash Based Microcontroller with 32k Memory,

2.0 Features n MICROWIRE/PLUS (Serial Peripheral Interface

COP8™ is a trademark of National Semiconductor Corporation.

© 2003 National Semiconductor Corporation DS101374 www.national.com

4.0 Ordering Information

12.1 TIMER T0 (IDLE TIMER) ...................................................................................................................... 35

15.3 ANALOG INPUT AND SOURCE RESISTANCE CONSIDERATIONS .................................................. 55

TABLE 1. Pinouts for All Packages

TABLE 1. Pinouts for All Packages (Continued)

8.0 Electrical Characteristics

DC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)

AC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C)

AC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)

Note 2: Maximum rate of voltage change must be < 0.5 V/ms.

A/D Converter Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C unless

A/D Converter Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C unless

DC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C)

DC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C) (Continued)

AC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C)

AC Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C) (Continued)

A/D Converter Electrical Characteristics (−40˚C ≤ TA ≤ +125˚C)

FIGURE 1. MICROWIRE/PLUS Timing

Port G has the following alternate features:

10.1 CPU REGISTERS

10.3 DATA MEMORY

FIGURE 7. RAM Organization

10.4.1 Virtual EEPROM 10.5 OPTION REGISTER

FIGURE 10. Brownout Reset Operation

10.8 OSCILLATOR CIRCUITS

High Speed Oscillator Low Speed Oscillator

FIGURE 12. Crystal Oscillator

LSON HSON DCEN CCKS

The ENAD register contains the following bits:

FIGURE 13. Block Diagram of ISP

TABLE 8. PGMTIM Register Format

TABLE 10. MICROWIRE/PLUS ISP Commands

TABLE 11. User ISP/Virtual E2 Entry Points

TABLE 12. Register and Bit Name Definitions

FIGURE 15. Functional Block Diagram for Idle Timer T0

TABLE 14. Idle Timer Window Length Idle Timer Period

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit

12.2.2 Mode 1. Processor Independent PWM Mode

FIGURE 17. Timer in External Event Counter Mode

TABLE 15. Timer Operating Modes

FIGURE 19. Diagram of Power Save Modes

FIGURE 20. Wake-up from HALT

FIGURE 21. Multi-Input Wake-Up Logic

FIGURE 22. USART Block Diagram

14.4.1 Asynchronous Mode 14.5 FRAMING FORMATS

FIGURE 23. Framing Formats

14.6 USART INTERRUPTS 14.7 BAUD CLOCK GENERATION

FIGURE 25. USART BAUD Clock Divisor Registers

14.8 EFFECT OF HALT/IDLE 14.10 ATTENTION MODE

15.1.1 A/D Control Register

FIGURE 27. A/D with Differential Mux Output Feature Enabled

15.1.1.5 Busy Bit TABLE 25. ADRSTL

FIGURE 28. A/D Pin Model (Single Ended Mode)

FIGURE 29. Interrupt Block Diagram