COA Assignment: This Assignment Consists of 10 Questions. Each Question Is of 5 Marks
COA Assignment: This Assignment Consists of 10 Questions. Each Question Is of 5 Marks
1. Design a digital circuit that perform four logic operations of exclusive-OR, exclusive-NOR, NOR
and NAND. Use two selection variables. Show logic diagram of one typical stage?
2. An 8-bit register contains the binary value 10011100. What is the register value after arithmetic
shift right? Starting from the initial number 10011100, determine the register value after an
arithmetic shift left, and state whether there is an overflow.
3. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed
with multiplexers.
i. How many selection inputs are there in each multiplexer?
ii. What size of multiplexers is needed?
iii. How many multiplexers are there in the bus?
4. What are the basic differences between a branch instruction, a call subroutine instruction, and
program interrupt?
5. Given the 16-bit value 1001101011001 101. What operation must be performed in order to:
i. clear to 0 the first eight bits?
ii. set to 1 the last eight bits?
iii. complement the middle eight bits?
6. A relative mode branch type of instruction is stored in memory at an address equivalent to decimal
750. The branch is made to an address equivalent to decimal 500.
a. What should be the value of the relative address field of the instruction (in decimal)?
b. Determine the relative address value in binary using 12 bits. (Why must the number be in
2's complement?)
c. Determine the binary value in PC after the fetch phase and calculate the binary value of
500. Then show that the binary value in PC plus the relative address calculated in part (b)
is equal to the binary value of 500.
7. Write a program to evaluate the arithmetic statement:
𝐴 − 𝐵 + 𝐶 ∗ (𝐷 ∗ 𝐸 − 𝐹)
𝑋=
𝐺+𝐻∗𝐾
a. Using a general register computer with three address instructions.
b. Using a general register computer with two address instructions.
c. Using an accumulator type computer with one address instructions.
d. Using a stack organized computer with zero-address operation instructions.
8. A bus-organized CPU similar to Fig. 8-2 has 16 registers with 32 bits in each, an ALU, and
a destination decoder.
a. How many multiplexers are there in the A bus, and what is the size of each multiplexer?
b. How many selection Inputs are needed for MUX A and MUX 8?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU for data, including input and output
carries?
e. Formulate a control word for the system assuming that the ALU has 35 operations.
9. Let SP = 000000 in the stack of Fig. 8-3.
10. A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer system
needs 2K bytes of RAM, 4K bytes of ROM, and four interface units, each with four registers. A
memory-mapped 1/0 configuration is used. The two highest-order bits of the address bus are
assigned 00 for RAM, 01 for ROM, and 10 for interface registers.
a. How many RAM and ROM chips are needed?
b. Draw a memory-address map for the system.
c. Give the address range in hexadecimal for RAM, ROM, and interface.