Lecture 8 Example: BCD increment-by-1

I8 I4 I2 I1 O8 O4 O2 O1
0 0 0 0 0 0 0 1

K-map minimization examples 0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1

POS minimization with K-map I1
I2
O1
O2
0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
1
I4 O4 0 1 0 1 0 1 1 0

Design example I8 O8 0
0
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1 0 0 0 1 0 0 1

"Switching network" logic blocks 1
1
0
0
0
1
1
0
0
X
0
X
0
X
0
X
(multiplexers/demultiplexers) block diagram 1
1
0
1
1
0
1
0
X
X
X
X
X
X
X
X
1 1 0 1 X X X X
truth table 1 1 1 0 X X X X
1 1 1 1 X X X X

Need a 4-variable Karnaugh map

for each of the 4 output functions
1 2

BCD increment-by-1: K-maps Example: Two-bit multiplier

I8 I8
A2 A1 B2 B1 P8 P4 P2 P1
O8 0 0 X 1 O4 0 1 X 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0
O8 = I4I2I1 + I8I1' 1 0 0 0 0 0
0 0 X 0 0 1 X 0
I1 I1 A1 P1 1 1 0 0 0 0
O4 = I4I2' + I4I1' + I4'I2I1 A2 0 1 0 0 0 0 0 0
P2
0 1 X X 1 0 X X 0 1 0 0 0 1
I2 I2 B1 P4
B2 P8
1 0 0 0 1 0
0 0 X X 0 1 X X 1 1 0 0 1 1
I4 1 0 0 0 0 0 0 0
I4 0 1 0 0 1 0
I8 I8 1 0 0 1 0 0
O2 = I8'I2'I1 + I2I1' 1 1 0 1 1 0
O2 0 0 X 0 O1 1 1 X 1 block diagram 1 1 0 0 0 0 0 0
O1 = I1' 0 1 0 0 1 1
1 1 X 0 0 0 X 0 truth table 1 0 0 1 1 0
I1 I1 1 1 1 0 0 1
We greatly simplify
0 0 X X 0 0 X X
the logic by using I2 I2
the don’t cares 1 1 X X Need a 4-variable Karnaugh map
1 1 X X
for each of the 4 output functions
I4 I4
3 4

A2A1 A2 A2A1 A2
B2B1 00 01 11 10 B2B1 00 01 11 10
P8=A2A1B2B1
00 0 0 0 0 00 0 0 0 0
P4=A2B2B1'
+A2A1'B2
POS minimization with K-maps
01 0 0 0 0 01 0 0 0 0
B1 B1
B2
11 0 0 1 0
B2
11 0 0 0 1
Encircle the zeros in the map
10 0 0 0 0 10 0 0 1 1
Interpret indices complementary to SOP
A1 A1 form
A2 A2 A
A2A1 A2A1 AB
B2B1 00 01 11 10 B2B1 00 01 11 10 CD 00 01 11 10 F = (B’+C+D)(B+C+D’)(A’+B’+C)
P1=A1B1
P2=A2'A1B2 00 0 0 0 0 00 0 0 0 0 00 1 0 0 1
+A1B2B1'
01 0 0 1 1 01 0 01
Same idea as with truth tables
+A2B2'B1 1 1 0 0 1 0 0
B1 B1 D
+A2A1'B1 11 0 1 0 1 11 0 1 1 0 11 1 1 1 1
B2 B2 C
10 0 1 1 0 10 0 0 0 0 10 1 1 1 1
A1 A1 B
6
 Design example: Comparator Comparator: K-maps
A B C D LT EQ GT K-map for LT K-map for EQ K-map for GT
0 0 0 0 0 1 0
A 0 1 1 0 0 A A A
LT
AB < CD 1 0 1 0 0 AB AB AB
B CD 00 01 11 10 CD 00 01 11 10
AB = CD 1 1 1 0 0 CD 00 01 11 10
EQ 0 1 0 0 0 0 1
C GT
AB > CD 0 1 0 1 0 00 0 0 0 0 00 1 0 0 0 00 0 1 1 1
D 1 0 1 0 0
1 1 1 0 0 01 1 0 0 0 01 0 1 0 0 01 0 0 1 1
1 0 0 0 0 0 1 D D D
0 1 0 0 1 11 1 1 0 1 11 0 0 1 0 11 0 0 0 0
1 0 0 1 0 C C C
1 1 1 0 0 10 1 1 0 0 10 0 0 0 1 10 0 0 1 0
block diagram 1 1 0 0 0 0 1
0 1 0 0 1
truth table 1 0 0 0 1 B B B
1 1 0 1 0
LT = A'B'D+A'C+B'CD GT = BC'D'+AC'+ABD'
Need a 4-variable Karnaugh map
for each of the 3 output functions EQ = A'B'C'D'+A'BC'D+ABCD+AB'CD'
= (A xnor C)•(B xnor D)
7 8

Comparator: Implementing EQ Comparator: Circuit schematics

Option 1:
A B C D
EQ = A'B'C'D'+A'BC'D+ABCD+AB'CD'

5 gates but they require lots of inputs

EQ Option 2
EQ = (A xnor C) •(B xnor D)

XNOR is constructed from 3 simple gates

EQ

7 gates but they all have 2 inputs each

9 10

Switching networks logic blocks Multiplexers

Multiplexer (MUX)
Basic concept
 Routes one of many inputs
to a single output  2n data inputs; n control inputs ("selects");
 Also called a selector
control
1 output
 Connects one of 2n inputs to the output
 “Selects” decide which input connects to

Demultiplexer (DEMUX)
output
 Routes a single input to one
of many outputs
 Also called a decoder
control

11 12
 Multiplexers: Truth tables Multiplexers

Two alternative truth-tables: Functional
2:1 mux: Z = S0'In0 + S0In1

4:1 mux: Z = S1'S0'In0 + S1'S0In1 + S1S0'In2 + S1S0In3
and Logical

8:1 mux: Z = S2'S1'S0'In0 + S2'S1'S0In1 + ...
Example: A 2:1 Mux Functional truth table Logical truth table
I0 2:1 I0 I0
Z = SIn1 + S'Ino S Z In1 In0 S Z I1 Z I1 I1
mux 4:1
0 In0 0 0 0 0 I2 mux Z I2
1 In1 0 0 1 0 I3 I3 8:1
I0 S0 Z
0 1 0 1 I4 mux
Z 0 1 1 0 I5
S1 S0 I6
S 1 0 0 0
I7
I1 1 0 1 1
1 1 0 1
1 1 1 1 S2 S1 S0
13 14

Multiplexers: Implementation Cascading multiplexers

2:1 mux 4:1 mux
I0 I0

Can form large multiplexers from smaller
S
Z ones (many implementation options)
I1 8:1 mux 8:1 mux
I1
Z
I0 I0 2:1
I2 I1 4:1 I1 mux
I2 mux
I3 I2 2:1
I3 2:1 Z I3
mux mux 4:1
I4 mux Z
I5 4:1 I4 2:1
I6 mux I5 mux
I7
I6 2:1
I7 mux
S1 S0 S2
S1 S0
15 S0 S2 S1 16

Multiplexer as logic block Multiplexer as logic block

A 2n:1 mux can implement any function of n
Can also use a 2n-1:1 mux to implement a
variables as a lookup table function of n variables
 (n-1) mux control variables S0 – Sn–2
F(A,B,C) = m0 + m2 + m6 + m7  One data variable Sn-1
= A'B'C' + A'BC' + ABC' + ABC  Four possible values for each data input: 0, 1,
A B C F
1 0
Sn-1, Sn-1'
0 0 0 1
0 0 1 0 0 1 A B C F
0 1 0 1 1 2 0 0 0 1 C'
0 1 1 0 0 3 F 0 0 1 0 C' 0
1 0 0 0 0 4 8:1 MUX 0 1 0 1 C' C' 1 F
1 0 1 0 0 5 0 1 1 0 0 2 4:1 MUX
1 1 0 1 1 6 1 0 0 0 0 1 3
1 1 1 1 1 7 1 0 1 0 S1 S0
S2 S1 S0 1 1 0 1 1
1 1 1 1 A B
17 18
A B C
 Multiplexer as logic block

F(A,B,C,D) implemented using an 8:1 mux

AB A
CD 00 01 11 10 1 0
00 1 0 1 1
Choose A,B,C as D 1
control variables 0 2
1 3 8:1 F
01 1 0 0 0 MUX
D Choose D as a D' 4
D 5
11 1 1 0 1 data variable 6
C D'
D' 7
10 0 1 1 0 S2 S1 S0

B A B C

19