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Digital Design 2 LAB: Objective

1. The document describes an experiment involving designing and implementing various digital counters on a ZedBoard including an asynchronous ripple counter, synchronous up/down counter, push button counter, and two-digit BCD counter. 2. The counters were designed using VHDL, simulated, and synthesized for implementation on the ZedBoard. 3. Additional components like a clock divider and debouncer were used to improve the design functionality and operation.

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عمر مجدي انيس سلعوس
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25 views25 pages

Digital Design 2 LAB: Objective

1. The document describes an experiment involving designing and implementing various digital counters on a ZedBoard including an asynchronous ripple counter, synchronous up/down counter, push button counter, and two-digit BCD counter. 2. The counters were designed using VHDL, simulated, and synthesized for implementation on the ZedBoard. 3. Additional components like a clock divider and debouncer were used to improve the design functionality and operation.

Uploaded by

عمر مجدي انيس سلعوس
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Digital design 2 LAB

Experiment 3:
Instructor Name: Dr.Ashraf Armoush
Names: Omar Salous Ahmad Nabhan

Objective:
1. Synthesize.
2. Implement the design using the ZedBoard.
Tools:
1. Xilinx Design Tools-Vivado 2020.1
2. ZedBoard
Part1: Asynchronous Ripple Counter
Introduction:
In this part, we will build a 4-bit Asynchronous ripple
counter using T flip-flops.
Procedure:
1. T Flip-Flops (TFF):
Digital design 2 LAB

Pins:
T: Synchronous Input (0: No change, 1: Toggle)
CLK: positive edge trigger clock.
Clear: Asynchronous active low clear.
Q: output
QBAR: output.
Digital design 2 LAB
I written VHDL code for the T Flip-Flop

Then written the following simulation code for the T Flip-Flop


Digital design 2 LAB

And the result of applying the previous simulation for T Flip-Flop

2. 4-bit Asynchronous Counter:


I will design a 4 bit asynchronous ripple counter using the
previous T flip-flop as a component.
Ports:
CLK
Enable: Active High Enable
Reset: Active Low Reset
Q: (4-bit output)
Digital design 2 LAB

I written VHDL code for the 4-bit Asynchronous Counter


Digital design 2 LAB
Then written the following simulation code for 4-bit Asynchronous
Counter

And the result of applying the previous simulation for 4-bit


Asynchronous Counter
Digital design 2 LAB
3. Clock Divider:
Since the system is running at 100MHz, I'm going to divide the input clock to generate a
1Hz output clock, so I can see the change in the results and notice the change in LED’s
counting.

I written VHDL code for the Clock Divider

4. Top-Level Entity:
Here we will use Divider and Asynchronous Counter as
a component to build Asynchronous Ripple Counter
that a higher level entity, as you can see below:
Digital design 2 LAB
I written VHDL code for the Top-Level Entity

We now synthesize our simulation on ZedBoard and check


results to Asynchronous Ripple Counter, but first must
create constraint file, we wrote the following code to set
the pin and the voltage level for each port as following:
Digital design 2 LAB

Part2: Auto Up Down Synchronous Counter


Introduction:
In this part, I will build Synchronous Auto Counter and will use
Divider to divide the clock so we can notice the change in LED’s
counting.
Procedure:
1. Synchronous Auto Counter:
This is a 4-bit counter that increment/decrement automatically using
the system clock.

When upDown equal:


1  the 4-bit counter that decrement
0  the 4-bit counter that increment

I written VHDL code for Synchronous Auto Counter


Digital design 2 LAB
Then written the following simulation code for Synchronous Auto
Counter

And the result of applying the previous simulation for Synchronous


Auto Counter

2. Clock Divider:
Since the system is running at 100MHz, I'm going to divide the input clock to generate a
1Hz output clock, so I can see the change in the results and notice the change in LED’s
counting.
Digital design 2 LAB
I written VHDL code for the Clock Divider

3. Top-Level Entity:
Here we will use Divider and Synchronous Auto
Counter as a component to build Auto Up Down
Synchronous Counter that a higher level entity, as you
can see below:
Digital design 2 LAB
I written VHDL code for the Top-Level Entity

We now synthesize our simulation on ZedBoard and check


results to Auto up down Synchronous Counter, but first
must create constraint file, we wrote the following code to
set the pin and the voltage level for each port as following:
Digital design 2 LAB

Part 3: Push Button Up Down Counter.

A: Synchronous Counter VHDL code:


Digital design 2 LAB

B: simulation for Synchronous Counter:

Problem:
There is will be a problem when we push on the button.
Unwanted signals due to trembling in the finger pressing the
button. But the system understand these Signals as inputs.
Digital design 2 LAB

Solution:
We used Push Button Debouncer in order to bypass the signals
generated by the vibrations in order to enter the correct inputs
into the system.

C: PBDebouncer: vhdl code (software solution).


Digital design 2 LAB

D: Top level
Digital design 2 LAB

E: In the constraint file, we wrote the following code to set


the pin and the voltage level for each port as following:
Digital design 2 LAB

Part 4: Two-Digit BCD Counter

A: BCD Counter vhdl code.


Digital design 2 LAB

B. Testbench & Simulation for BCD Counter .


Digital design 2 LAB

C: Time multiplexer:
We used this component to display a number on a seven
segment in one time then display on the second .
This operation happens in very very short time . So , our eyes see
that two seven segment operate at the same time (Optical
illusions).

vhdl code :
Digital design 2 LAB

D: BCD to Seven segment :


Digital design 2 LAB

E: divider: We discussed it at the beginning of the


report.

F: the Top Component.


Digital design 2 LAB
Digital design 2 LAB
Digital design 2 LAB
G: In the constraint file , we wrote the following code to
set the pin and the voltage level for each port as
following :

Conclusion:
In this experiment we learned to build synchronous and
asynchronous counters, and then use them for something
bigger (structural components).
In addition, We also learned how to bypass the vibrations
in the input signals by using a software solution (Push
Putton Debouncer).
Finally, we show the results on seven segment display.

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