CAD Lab Manual KEC 653B (4mail)
CAD Lab Manual KEC 653B (4mail)
CAD Lab Manual KEC 653B (4mail)
LAB MANUAL
CAD FOR ELECTRONICS LAB [KEC-653B]
B.Tech. 3rd Year VIth Semester
(Branch: ECE)
PSPICE Experiments
(b) Transient Analysis of CMOS inverter using step input with parameters.
(d) Transient Analysis of CMOS inverter using pulse input with parameters.
Part ‘B’-
VHDL PROGRAMS
2. Design, Simulation and Analysis of NMOS and CMOS Inverter using net listing.
Experiment No. 1
Aim- (a) Transient Analysis of BJT inverter using pulse input.
(b)DC Analysis (VTC) of BJT inverter with and without parameters
Theory- The BJT circuit shown in Fig. 1 acts as an inverter: When the input voltage is low, the
transistor does not conduct, there is no current through RC, and the collector voltage (output) is
pulled up to VCC. When the input voltage is increased, the transistor begins to conduct, the
voltage drop across RC starts increasing, and the output voltage falls. Finally, when the input
voltage is high enough to drive the transistor into saturation, there is a fixed small drop
(VCE=0.1 to 0.2 V) across the transistor, and the output voltage saturates to this low value. The
transfer characteristic is shown in Fig. 2
Circuit Diagram-
Result- Thus the BJT Inverter circuit was simulated using ORCAD capture and its output
waveform was obtained.
DC Analysis: DC analysis of BJT inverter using dc voltage source .From the graph we can
analysis that the transistor is entering in to the active region at the input voltage of 0.7V.
V1
R1 15v
1k
Q1 V
V2
.7 QbreakN
V
0
0
Fig: 2 VTC (voltage transfer characteristic curve)
DC analysis of BJT inverter with parameters: For parametric sweep initial value of resistor R1 is 500
ohm.
V1
R1 15v
{rval}
0 PARAMETERS:
Color = Def ault
rval = 500
Q1 V
V2
.7 Qbreakn
V
0
0
15V
r=1k
10V
r=100k
5V
0V
0V 0.1V 0.2V 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V
... V(R1:1) ... V(Q1:b)
V_V2
Transient Analysis – Transient analysis of BJT inverter-
Questions:
1). How can a BJT inverter circuit be used as a switch in practical applications? Take an LED
and glow it using BJT as a switch and verify your result.
2). Design an AND gate using this basic concept of BJT inverter logic.
3). Design an OR gate using this basic concept of BJT inverter logic.
4). Can you drive motor using BJT? Design a circuit to do the same and verify your results using
spice simulation.
5). How can you design an oscillator by modifying the BJT inverter concept. Design an oscillator
circuit and show results using spice simulation.
Experiment No. 2
Theory- An inverter circuit outputs a voltage representing the opposite logic-level to its input.
Inverters can be constructed using a single NMOS transistor coupled with a resistor. Since this
'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost.
However, because current flows through the resistor in one of the two states, the resistive-drain
configuration is disadvantaged for power consumption and processing speed.
Circuit Diagram-
Result- Thus the nMOS Inverter circuit was simulated using ORCAD capture and its output
Waveform was obtained.
Transient Analysis – Transient analysis of nMOS inverter using pulse input.
R1 V2
5k 5v
V
M1
V1 = 0 V3
V2 = 5 MbreakN V
0
TD = 0n
TR = 0n
TF = 0n 0
PW = 50n 0
PER = 100n
5.0V
2.5V
0V
V(M1:g)
5.0V
4.5V
4.0V
SEL>>
3.5V
0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us
V(R1:1)
Time
---V(M1:g)= input
---V(R1:1) = output
DC Analysis – DC analysis of nMOS using dc
R1 V2
5k 5v
V
M1
V1
0V dc
MbreakN V
0
0
0
input.
5.0V
4.0V
3.0V
2.0V
1.0V
0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(R1:1) V(M1:g)
V_V1
---V(M1:g)= input
---V(R1:1) = output
DC analysis of nMOS inverter using parametric sweep: From the parametric sweep we can
analyze that if we increase the value of resistor R1 switching voltage decreases.
6.0V
4.0V
2.0V
0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M1:d) V(V1:+)
V_V1
Transient analysis of nMOS inverter using Step Input: step input has been applied for 10ms. From the
graph we can see that for input voltage of 0v output output obtain is equal to Vdd ie 5V.
R1 V2
5k 5v
V
M1
V1
0V dc
MbreakN V
0
0
0
5.0V
4.0V
3.0V
2.0V
1.0V
0V
0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms
V(R1:1) V(M1:g)
Time
---V(M1:g)= input
---V(R1:1) = output
Questions:
1). How can a NMOS inverter circuit be used as a switch in practical applications? Take an LED
and glow it using BJT as a switch and verify your result.
2). Design an AND gate using this basic concept of NMOS inverter logic.
3). Design an OR gate using this basic concept of NMOS inverter logic.
4). Can you drive motor using NMOS transistor? Design a circuit to do the same and verify your
results using spice simulation.
5). How can you design an oscillator by modifying the NMOS inverter concept. Design an
oscillator circuit and show results using spice simulation.
Experiment No. 3
Theory -CMOS circuits are constructed in such a way that all PMOS transistors must have either
an input from the voltage source or from another PMOS transistor. Similarly,
all NMOS transistors must have either an input from ground or from another NMOS transistor.
The composition of a PMOS transistor creates low resistance between its source and drain
contacts when a low gate voltage is applied and high resistance when a high gate voltage is
applied. On the other hand, the composition of an NMOS transistor creates high resistance
between source and drain when a low gate voltage is applied and low resistance when a high gate
voltage is applied. CMOS accomplishes current reduction by complementing every n MOSFET
with a p MOSFET and connecting both gates and both drains together. A high voltage on the
gates will cause the n MOSFET to conduct and the p MOSFET to not conduct while a low
voltage on the gates causes the reverse. This arrangement greatly reduces power consumption
and heat generation.
Circuit Diagram-
Result- Thus the CMOS Inverter circuit was simulated using ORCAD capture and its output
Waveform was obtained.
Transient Analysis : Transient analysis of CMOS inverter has been done and rise time and fall
time has been
calculated.
5.0V
2.5V
0V
V(M1:g)
5.0V
2.5V
SEL>>
0V
0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us
V(M2:d)
Time
DC Analysis: Dc sweep of CMOS inverter has been done by sweeping input voltage from 0-5V with an
increment of 0.1V. From the DC analysis switching voltage has been calculated and is found to be Vdd/2.
6.0V
4.0V
2.0V
0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M2:d) V(M1:g)
V_V1
Questions:
1). Design a CMOS inverter with taking the W/L ratio of PMOS vs NMOS as 4:1 and give a
comparison of its characteristics curve with respect to the inverter designed by you.
2). What will happen if a capacitive load will be connected to the output terminal. Apply 10 pf
capacitor at output terminal and check the response.
3). How this CMOS inverter will behave with different load conditions? Apply some load, vary
it and verify your answer.
4). At which value of input signal this CMOS inverter will dissipate maximum power? Verify
your answer using PSPICE simulation.
5). In the last experiments, you designed BJT inverter and then NMOS inverter. Now compare
the performance of these with this CMOS inverter from the VTC curve you obtained after
simulation of the same.
6). State the applications of CMOS?
Experiment No. 4
Theory- The design and analysis of CMOS logic circuits are based on the principles developed
for the nMOS depletion-load logic circuits. Figure 1.8 shows the circuit diagram of a two-input
CMOS NOR gate. When either one or both inputs are high, there is a conducting path between
the output node and the ground created by n-net and the p-net is cut-off. If both the input
voltages are low, the n-net is cut-off, then the p-net creates a conducting path between the output
node and supply voltage VDD. Thus the dual the circuit structure allows that for any given input
combination, the output is either to VDD or ground via a low-resistance path. The DC current
path is not established between VDD and ground for any input combinations.
Circuit Diagram
Result- Thus the CMOS NOR circuit was simulated using ORCAD capture and its output
Waveform was obtained.
Transient Analysis- Transient analysis of NOR Gate has been done and rise time and fall time
has been calculated.
V1
MbreakP 5v
M1
0
MbreakP
M2
M3 V
M4
V1 = 0 V4
V2 = 5 MbreakN VV 1 =0 V3
TD = 0 V2 = 5 V
TR = 0 TD = 0n
TF = 0 TR = 0n
PW = 50n TF = 0 0
PER = 120n 0 PW = 50n 0
PER = 120n
1.0V
0.5V
SEL>>
0V
V(M3:d)
5.0V
2.5V
0V
0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us
V(V4:+)
Time
---V(M3:d)= output
---V(V4:+)=input
Falltime_NoOvershoot(V(M3:d)) 368.32780ps
Risetime_NoOvershoot(V(M3:d)) 959.98552ps
DC Analysis: From the DC analysis switching voltage has been calculated and is found to be
approximately equal to Vdd/2.
6.0V
4.0V
2.0V
0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M3:d) V(V2:+)
V_V2
---V(M3:d)= output
---V(V4:+)=input
Questions:
1). Design a four- input NOR gate and verify the results using PSPICE simulation.
2). What will happen if a capacitive load will be connected to the output terminal. Apply 10 pf
capacitor at output terminal and check the response.
3). How this NOR gate will behave with different load conditions? Apply some load, vary it and
verify your answer.
4). At what values of input signals this NOR gate will dissipate maximum power? Verify your
answer using PSPICE simulations.
5). Design two input XOR gates using universal NOR gates only, simulate and verify your result.
Experiment No. 5
Theory-The design and analysis of CMOS logic circuits are based on the principles developed
for the nMOS depletion-load logic circuits. Figure mentioned below shows the circuit diagram of
a two-input CMOS NAND gate. When both inputs are low, there is a conducting path between
the output node and the p net and the n-net is cut-off. If both the input voltages are high, then
there is conducting path between n net and ground and n-net is cut-off. Thus the dual the circuit
structure allows that for any given input combination, the output is either to VDD or ground via a
low-resistance path. The DC current path is not established between VDD and ground for any
input combinations.
Circuit Diagram
Result- Thus the CMOS NAND circuit was simulated using ORCAD capture and its output
waveform was obtained.
Transient Analysis -
V1
5v
0
MbreakP MbreakP
M3 M4
V2 V
5v
M2
0
MbreakN
M1
MbreakN V
V1 = 0 V3
V2 = 5
TD = 0
TR = 0
TF = 0
PW = 50n 0
PER = 100n
5.0V
2.5V
SEL>>
0V
V(M1:g)
5.0V
2.5V
0V
0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us
V(M2:d)
Time
---V(m1:g)= input
---V(m2:d)= output
Falltime_NoOvershoot(V(M2:d))= 1.91495n
Risetime_NoOvershoot(V(M2:d))= 1.66493n
DC Anlaysis - From the DC analysis switching voltage has been calculated and is found to be 2.6V.
V1
5v
0
MbreakP MbreakP
M3 M4
V2 V
5v
M2
0
MbreakN
M1
MbreakN V
V3
0V dc
0
5.0V
4.0V
3.0V
2.0V
1.0V
0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M2:d) V(M1:g)
V_V3
---V(m1:g)= input
---V(m2:d)= output
Questions:
1). Design a four- input NAND gate and verify the results using PSPICE simulation.
2). What will happen if a capacitive load will be connected to the output terminal. Apply 10 pf
capacitor at output terminal and check the response.
3). How this NAND gate will behave with different load conditions? Apply some load, vary it
and verify your answer.
4). At what values of input signals this NAND gate will dissipate maximum power? Verify your
answer using PSPICE simulations.
5). Design a two input MUX using universal NAND gates only, simulate and verify your result.
Experiment No.6
Aim- Analysis of frequency response of Common Source amplifiers.
The bandwidth of single stage MOSFET amplifier is determined by speed limitations of the
transistor itself. In simple terms, this means that it takes certain time for charge carriers to move
from source to drain and device cannot work faster than that.
The unity-gain frequency (fT) is the frequency at which short-circuit current gain of the common-
source configuration becomes unity. The value of unity-gain frequency can be estimated as:
gm
fT
2 (CGS CGD)
where gm is gate trans conductance and CGS and CGD are net equivalent MOSFET capacitances.
The MOSFET capacitances have both internal and external contributions. Of course, much more
detailed modeling is required to predict the unity-gain bandwidth accurately but the equation (1)
is OK as an estimate in many cases.
The bandwidth (BW) of MOSFET amplifiers rarely can approach fT due to additional limitations
caused by particular circuit layout. Usually, BW << fT.
Figure below shows the generic form of the CS amplifier with resistive load-
Circuit Diagram-
Result-
Design of Common Source amplifier has been done successfully and measured values of Gain
and Bandwidth is…………….
Questions:
1). In practical applications, can we use this CS amplifier without having resistors R3 and R4 in the
circuit? Find out the way to do the same.
2). What is the practical utility of CS amplifier? State applications where it can be used.
3). How will u relate the effect of coupling capacitance to 3db frequency? What will happen if you
remove CC from the circuit from input stage?
4). Analyze the effect of input coupling capacitor by varying its value from low to high and check the
frequency response.
5). How does a common source amplifier behaves under varying load conditions?
Experiment No.7
Aim- Analysis of frequency response of Source Follower amplifiers.
Software required- ORCAD PSPICE tool (17.2)
Theory –
Common Drain Amplifier or Source Follower is a voltage follower, its gain is less than 1.
Figure below shows the generic form of the Source Follower amplifier with resistive load-
PSPICE Code:
V_V1 4 0 15Vdc
V_V2 5 0 AC 1 SIN 0 1 10k 0 0 0
R_R5 2 5 100
R_R1 1 4 1k
R_R2 0 3 2000k
M_M1 1 2 3 3 MbreakN
C_C4 3 0 500f
C_C5 2 1 2p
C_C6 0 2 1p
.MODEL MbreakN NMOS VTO=0.8063 TOX=2.1500E-08
.AC DEC 10 1 1000G
.plot ac VDB(3)
.OP
.PROBE
.END
Result-
Design of Common Source amplifier has been done successfully and measured values of Gain
and Bandwidth is…………….
Fig.: Frequency response of Source Follower Amplifier circuit
Precautions:
Questions:
1). In practical applications, can we use this source follower amplifier without having resistors
R5 in the circuit? Find out the way to do the same.
2). What is the practical utility of source follower amplifier? State applications where it can be
used.
3). How will u relate the effect of output capacitance to 3db frequency? What will happen if you
remove C4 from the circuit from output stage?
4). Analyze the effect of input coupling capacitor by varying its value from low to high and
check the frequency response.
5). How does a source follower amplifier behaves under varying load conditions?
Experiment No.08
Aim- Design and Simulation of Full Adder using VHDL program module
Theory- A full adder adds binary numbers and accounts for values carried in as well as out. A
one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the
operands, and Cin is a bit carried in from the previous less significant stage. The full adder is
usually a component in a cascade of adders which add 8, 16, 32 etc. bit binary numbers. The
circuit produces a two-bit output, output carry and sum typically represented by the
signals Cout and S.
Circuit Diagram-
Truth Table-
VHDL Code -
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity full_adder is
port (A: in STD_LOGIC;
B: in STD_LOGIC;
Cin: in STD_LOGIC;
S: out STD_LOGIC;
Cout: out STD_LOGIC;
end full_adder;
Result- Thus the Full adder was simulated using Xilinx and its output waveform was obtained.
Questions:
1). Implement a four bit FA using designed one bit full adder and verify results in XILINX.
2). Design the same one bit FA as above using component description.
3). Design the same one bit FA as above by describing the behavior of the same.
4). Design a half adder cell and then design one bit full adder using such two half adders in
cascade.
Experiment No.09
Aim- Design and Simulation of 8x1 MUX using VHDL program module
Theory - A multiplexer (or mux) is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select
lines, which are used to select which input line to send to the output. Multiplexers are mainly
used to increase the amount of data that can be sent over the network within a certain amount of
time and bandwidth. A multiplexer is also called a data selector.
Block Diagram-
Truth Table-
VHDL Code
library IEEE;
use IEEE.std_logic_1164.all;
entity mux151 is
port (
I :in STD_LOGIC_VECTOR (7 downto 0); --8 i/p lines
S :in STD_LOGIC_VECTOR (2 downto 0); --3 data select lines
en_l:in STD_LOGIC; --active low enable i/p
y :out STD_LOGIC --output line );
end mux151;
Result- Thus the 8X1 Multiplexer was simulated using Xilinx and its output waveform was
obtained
Questions:
1). Implement a 32:1 MUX using designed 8:1 MUX and verify results in XILINX.
2). Design the same 32:1 MUX as above using component description.
3). Design the same 32:1 MUX as above by using dataflow modelling style.
4). Design a 4:1 MUX and then design 8:1 MUX using such MUX’s in cascade.
Experiment No.10
Theory- A decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-
to-2n. The example decoder circuit would be an AND gate because the output of an AND gate is
"High" (1) only when all its inputs are "High." Such output is called as "active High output". If
instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its
inputs are "High". Such output is called as "active low output. The input to a decoder is parallel
binary number and it is used to detect the presence of a particular binary number at the input.
The output indicates presence or absence of specific number at the decoder input.
Block Diagram-
Y0
X2 Y1
3x8
X1 Decoder Y2
Y3
X0
Y4
Y5
Y6
Y7
Truth Table
Input Output
X2 X1 X0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_3_to_8 is
port (X : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_3_to_8;
VCC1 3 0 DC 15V
VCC2 0 5 DC 15V
R1 1 0 50
R2 6 0 50
R3 3 2 1K
R4 3 7 1K
R5 4 5 9K
Q1 2 1 4 q1
Q2 7 6 4 q2
VIN1 1 0 DC 4
VIN2 6 0 DC 3
.MODEL q1 NPN(IS=2.10E-016)
.MODEL q2 NPN(IS=2.10E-016)
.TRAN 1US 500US
.PLOT TRAN V(2) V(7)
.OP
.PROBE
.END
Procedure:
1. Open the spice window on spice software.
2. Write the spice code of the circuit in text file.
3. Now save the file in cir format, reopen it and then simulate.
4. Carry out required analysis of the above circuit.
Result:
Plot the required graph.
Precautions:
1. Do not insert pen drive.
2. Do the required analysis & plot it properly.
Conclusion:
Now vary some parameters and see different results and then conclude about the
designed circuit on the basis of same analysis.
CIRCUIT DIAGRAM:
Experiment No. 12
Object: Design, Simulation and Analysis of NMOS and CMOS Inverter using
netlisting.
vdd 2 0 5v
vin 1 0 dc 5v pulse(0 5v 0 1ns 1ns 20us 40us)
m1 3 1 2 2 pmod l=1u w =200u
.model pmod pmos (vto=-2)
m2 3 1 0 0 nmod l=1u w=5u
.model nmod nmos (vto=2)
. dc vin 0 5 0.1v
. plot dc v(3)
.probe
.op
.end
vdd 2 0 5v
vin 1 0 dc 5v pulse(0 5v 0 1ns 1ns 20us 40us)
m1 3 1 2 2 nmod1 (l=1u w =200u)
.model nmod1 nmos (vto=2)
m2 3 1 0 0 nmod2 (l=1u w=5u)
.model nmod2 nmos (vto=2)
. dc vin 0 5 0.1v
. plot dc v(3)
.probe
.op
.end
Procedure:
1. Open the spice window on spice software.
2. Write the spice code of the circuit in text file.
3. Now save the file in cir format, reopen it and then simulate.
4. Carry out required analysis of the above circuit.
Result:
Plot the required graph.
Precautions:
1. Do not insert pen drive.
2. Do the required analysis & plot it properly.
Conclusion:
Now vary some parameters and see different results and then conclude about the
designed circuit on the basis of same analysis.
CIRCUIT DIAGRAM:
W=22u
L=2u
Vin Vout
W=22u
L=2u
OUTPUT WAVEFORM: