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Zybo & Zynq Intro: Esdc Lab 1

This document provides an overview of the Zybo development board and its Zynq chip. The Zynq is a dual-core ARM processor with an FPGA. The Zybo board allows designing the programmable logic through IP integration using AXI interfaces. The design flow involves using Vivado tools to generate a bitstream to program the FPGA logic and export the design to SDK to build a software application to run on the ARM processor. Additional resources for learning about the Zybo and Zynq are available.

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Miguel Fuentes
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123 views16 pages

Zybo & Zynq Intro: Esdc Lab 1

This document provides an overview of the Zybo development board and its Zynq chip. The Zynq is a dual-core ARM processor with an FPGA. The Zybo board allows designing the programmable logic through IP integration using AXI interfaces. The design flow involves using Vivado tools to generate a bitstream to program the FPGA logic and export the design to SDK to build a software application to run on the ARM processor. Additional resources for learning about the Zybo and Zynq are available.

Uploaded by

Miguel Fuentes
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ZYBO & ZYNQ INTRO

ESDC Lab 1
Outline
•  Development board: Zybo
•  Zynq overview
•  IP-based design
•  AXI interface
•  Hardware-Software co-design
•  Available resources

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Zynq development boards
•  Zybo (14 units)

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Zybo

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Zynq overview
•  PS: dual-core ARM Cortex 9 processor
•  Executes program stored in memory (written in C or binary libraries)
•  Hardware is fixed, optimum design
•  Several clock cycles per instruction
•  PL: Virtex-7 family FPGA
•  Custom logic configured by interconnection (written in VHDL or Verilog)
•  Completely versatile in hardware structure
•  Very fast (one cycle per operation)
•  Both parts needed in typical design
•  PL acting as peripheral to PS
•  PS acting as slave for PL hardware (less frequent)

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Zynq overview

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Zybo components

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Board power supply jumper (JP7)
•  Three ways to power the Zybo: USB, Power adapter and Battery
•  Preferred method: USB
•  Important: note the position of jumper JP7

Desired position of JP7

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Zynq programming method (JP5)
•  Zynq PS acts as a master to the PL
•  PS loads and executes a Zynq Boot Image, which includes a First Stage
Bootloader (FSBL), a bitstream for configuring the PL (optional), and a user
application.
•  Three methods to boot: MicroSD, QSPI, and JTAG. Preferred method: JTAG
or MicroSD. Note that your application will not run in the QSPI position.
•  Important: note the position of jumper JP5

Desired position of JP5

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Board peripheral connections to the Zynq
•  Zynq is a dual device: ARM processor (PS) and FGPA (PL)
•  Some board resources are connected to the PL, some to the PS
•  Most devices need to use PL to connect to PS
•  Peripherals in PL using AXI bus

Resources in PS Resources in PL
•  DDR3 •  Audio
•  Ethernet PHY •  VGA
•  2 buttons (BTN4-BTN5) •  HDMI
•  1 LED (LD12) •  4 switches (SW0-SW3)
•  4 leds (LD0-LD3)
•  4 buttons (BTN0-BTN3)

Need to use PL fabric


(VHDL) to use any of
these resources
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IP-based design
•  ARM APU communicates with peripherals inside the PS, or inside the
PL
•  PL peripherals are custom logic designed to do specific task and
communicate with PS
•  Communication with special bus interface: AXI

11
IP design Summary
•  PS functionality can be extended by instantiating peripherals in PL
•  Adding IP in PL involves
•  Enabling interface(s) in PS
•  Selecting IP from the IP Catalog and configuring IP for desired functionality
•  Assigning address
•  Connecting IP ports to ports of other peripherals and/or to external pins
•  HDL Wrapper is needed for IP Integrator Block
•  Bitstream must be generated when PL has any IP
•  The FPGA must be programmed with the generated hardware
bitstream before an application can be run

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AXI Interface
•  Part of ARM standard bus interface AMBA

AMBA

APB AHB AXI ATB

AXI-4 AXI-4 AXI-4


Memory Map Stream Lite

Interface Features
Memory Map / Full Traditional Address/Data Burst
(AXI4) (single address, multiple data –up to 256)
Streaming Data-Only, Unlimited burst
(AXI4-Stream)
Lite Traditional Address/Data—No Burst
(AXI4-Lite) (single address, single data)

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Vivado-SDK design flow

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Vivado-SDK design flow
1. Launch Vivado

2. Invoke IP Integrator to
create Block Diagram
5. Generate Top-Level HDL 9. Specify hardware
6. Add Constraints description from Vivado
7. Generate Bitstream => .bit 10. Add Software
8. Export hardware to SDK Project & Build => .elf

Vivado SDK
11. Program bitstream & .elf into Zynq

ZedBoard

15
Additional resources in Atenea and others
•  Xilinx presentations
•  Datasheets and manuals
•  Books
•  Videos
•  Google.....

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