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Module 3 (Mixed Language Description)

Mixed-language description allows HDL code to contain both VHDL and Verilog extracts in the same module. To do this, the simulator must support a mixed-language environment where both VHDL and Verilog modules and libraries are visible. Currently there are some limitations, such as only entire modules/entities can invoke each other, but simulators are working to reduce restrictions. Mixed-language description combines advantages of VHDL and Verilog, for example using VHDL file operations in Verilog modules.

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195 views

Module 3 (Mixed Language Description)

Mixed-language description allows HDL code to contain both VHDL and Verilog extracts in the same module. To do this, the simulator must support a mixed-language environment where both VHDL and Verilog modules and libraries are visible. Currently there are some limitations, such as only entire modules/entities can invoke each other, but simulators are working to reduce restrictions. Mixed-language description combines advantages of VHDL and Verilog, for example using VHDL file operations in Verilog modules.

Uploaded by

Yash
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Module-3

MIXED-LANGUAGE DESCRIPTION

Highlights of Mixed-Language Description

Mixed-Language Description is a powerful tool in writing HDL code. The mixing


here is referring to an HDL code with VHDL and Veilog extracts in the same
module.

Facts

• To write HDL code in mixed language, the simulator used with the HDL
package should be able to handle a mixed-language environment.

• In the mixed-language environment, both VHDL and Verilog module files


are made visible to the simulator.

• In the mixed-language environment , both VHDL and Verilog libraries are


made visible to the simulator.

• At the present time, the mixed-language environment has some


limitations, but the development of simulators that can handle mixed-
language environments with minimal constraints is underway. One of
these major constraints is that a VHDL module can only invoke the entire
Verilog module, and a Verilog module can only invoke a VHDL entity. For
example, we cannot invoke a VHDL procedure from a Verilog module.
Check your simulator to see if it has recent updates that may not have
such restrictions.

• Mixed-language description can combine the advantages of both VHDL


and Verilog in one module. For example, VHDL has more extensive file
operations than Verilog including write and read. By writing mixed
language, the VHDL file operations can be incorporated in Verilog
modules.

How to Invoke One Language From the Other


• When writing VHDL code you can invoke (import) a Verilog module.

• If you are writing Verilog code, you can invoke (import) a VHDL entity.
• By instantiating a VHDL package in a Verilog module, the contents of this
package are made visible to the module.

• Similarly, by invoking a Verilog module in a VHDL module, all information


in the Verilog module is made visible to the VHDL module

How to Invoke a VHDL Entity From a Verilog Module

• In Verilog, invoke a VHDL entity by entering its name (identifier)


and its ports in the Verilog module.
• The parameters of the module should match the type and port
directions of the entity.
• VHDL ports that can be mapped to Verilog modules are: in, out,
and inout; buffer, in some simulators, is not allowed.
• Only the entire VHDL entity can be made visible to the Verilog
module.
Example of how to invoke a VHDL entity from a Verilog
module
Invoking a VHDL Entity From a Verilog Module
Example explanation

• The simulator looks first in the Verilog module to see if there


are any Verilog modules by the name of VHD_enty.

• If it could not find one, the simulator looks in the VHDL entities.
When the simulator finds an entity with the name VHD_enty, it
binds this entity to the Verilog module.

• In above example input a is passed to input port x; input b is


passed to input y.

• The VHDL entity calculates the outputs O1 and O2; these two
outputs are passed to the Verilog outputs c and d, respectively.

• Invoking a VHDL module is very similar to invoking a function or


a task.
Invoking a VHDL Entity From a Verilog Module
MIXED-LANGUAGE DESCRIPTION OF A FULL ADDER
• A full adder is constructed from two half adders, as was
done in previous module. The logic diagramis shown
below.
• The code of the half adder is written in VHDL.
• A Verilog module is written to describe a full adder using
the VHDL code of the half adder.

Mixed-Language Description of a Full Adder


Half Adder code in VHDL
Verilog code for Full Adder invoke VHDL Half Adder

• The Verilog statement

HA H1 (y, cin, s0, c0);

• invokes a module by the name of HA. Because there is no


Verilog module by this name, the simulator looks at the VHDL
modules attached to the Verilog modules.

• The simulator finds an entity by the name of HA; accordingly,


this entity and its bound architecture(s) are made visible to the
Verilog module.

• The architecture here is a data-flow description of a half adder.

• The inputs y and cin are passed to the input ports of HA, a and
b.

• The VHDL entity calculates the outputs s and c as:

s <= a xor b; c <= a and b;

• The outputs of the entity s and c are passed to the outputs of


the module HA, s0 and c0.
MIXED-LANGUAGE DESCRIPTION OF A MASTER-SLAVE D FLIP-FLOP

• VHDL data-flow description is used to simulate the D-latch (see Chapter


2).

• The master-slave flip-flop is described in a Verilog module.

• The VHDL entity is invoked to import the description of a D-latch.

VHDL code for D-Latch


Verilog module for master-slave D Flip-flop

Simulation waveform of master-slave D Flip-flop


MIXED-LANGUAGE DESCRIPTION OF A NINE-BIT ADDER

• A nine-bit adder consisting of three adder slices is described.

• Each adder slice is a three-bit carry-look ahead adder.

• The three-bit carry-lookahead is described by a VHDL module.

• The Verilog module invokes the VHDL entity three times.

• The VHDL entity adders_RL is a data-flow description of a three-bit


lookahead adder

• The delay-propagation time is taken as 0.

• the VHDL entity is invoked by the statement:

adders_RL A1 (a [2:0], b [2:0], c0, sum_total [2:0], cr0);

Mixed-Language Description of a Nine-Bit Adder

VHDL code of 3-bit carry-look ahead adder


Verilog module for Nine-Bit Adder
How to Invoke a Verilog Module From a VHDL Entity
• In the VHDL module, declare a component with the same name as the
Verilog module to be invoked (see structural description).
• The name and port modes of the component should be identical to the
name and input/output modesof the Verilog module.
• Remember that Verilog is case sensitive, so be sure to match the case.
• Below shown an example of how to invoke a Verilog module from a
VHDL module.
Invoking a Verilog Module From a VHDL Module for AND gate
Invoking a Verilog Module From a VHDL Module for
Full Adder.

MIXED-LANGUAGE DESCRIPTION OF A FULL ADDER

• A full adder is constructed from two half adders, as was done in previous
module. The logic diagram is shown below.
• The code of the half adder is written in verilog.
• A VHDL module is written to describe a full adder using the verilog code
of the half adder.

VHDL Module for FULL ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder is
port (x, y, cin: in std_logic; sum, carry: out std_logic);
end Full_Adder;
architecture Full_MXD of Full_Adder is
component HA_verilog
port (I1, I2: in std_logic; O1, O2 : std_logic);
end component;
component and2
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
signal s0, c0, c1: std_logic;
begin
HA1 : HA_verilog port map (y, cin, s0, c0);
HA2 : HA_verilog port map (x, s0, sum, c1);
A1 : and2 port map (co, c1, carry);
end Full_MXD;

Verilog module for Half Adder and AND gate

module HA_verilog (I1,I2,O1,O2);


input I1, I2;
output O1, O2;
assign O1 = I1 ^ I2;
assign O2 = I1 & I2;
endmodule

module and2 (I1,I2,O1);


input I1, I2;
output O1;
assign O1 = I1 & I2;
endmodule
MIXED-LANGUAGE DESCRIPTION OF A JK FLIP-FLOP WITH A
CLEAR SIGNAL
• In this example, a mixed-language description of a JK flip-flop is written.
• JK flip-flops were covered in Chapters 3 and 4.
• The excitation table of a JK flip-flop with a clear signal is shown in Table.

• The flip-flop is declared as a VHDL component, and a Verilog behavioral


description of the flip-flop based on Table as written.

• The Verilog is linked to the VHDL component by giving the Verilog


module the same name as the VHDL component.

• The ports of the component should also be the same as those of the
Verilog module.

• Below shows the mixed language description of the flip-flop. The JK flip-
flop is declared as a component with the statement:

• The above component is linked to a Verilog module by the statement:


module jk_verilog (j, k, ck, clear, q, qb);
• The above module has the same name and ports as the VHDL
component jk_verilog. Accordingly, the relationship between the input
and output ports described in the Verilog module is visible to the VHDL
component.
• The Verilog module describes, in behavioral style, a JK flip-flop with an
active high clear.

• Hence, the VHDL component jk_verilog is also a JK flip-flop with an


active high clear.

Mixed-Language Description of a JK FlipFlop (invoking Verilog module


from VHDL Module)
Verilog Module for JK flip flop
Limitations of Mixed-Language Description
As previously mentioned, mixed-language description is somehow limited at
present time. These limitations can be summarized as follows:

• Not all VHDL data types are supported in mixed-language description.


Only bit, bit_vector, std_logic, std_ulogic, std_logic_vector, and
std_ulogic_vector are supported.

• The VHDL port type buffer is not supported.

• Only a VHDL component construct can invoke a Verilog module. We


cannot invoke a Verilog module from any other construct in the VHDL
module.

• A Verilog module can only invoke a VHDL entity. It cannot invoke any
other construct in the VHDL module such as a procedure or function.

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