A 10-Megasample-per-Second

Analog-to-Digital Converter with

Filter and Memory
In addition to analog-to-digital conversion, the HP E1430A addresses
the problems of gain ranging, anti-aliasing protection, frequency band
selection, triggering, data buffering, and multichannel synchronization.

by Howard E. Hilton

The Hewlett-Packard E1430A is a VXIbus-based analog-to- Module Description

digital converter (ADC) module containing a high- The HP E1430A is implemented as a single-slot, C-size
dynamic-range, 23-bit-resolution, 10-MSa/s (megasample- VXIbus module,1,2 as shown in Fig. 1. The primary analog
per-second) ADC, a family of octave-spaced anti-aliasing connections are the three BNC connectors on the front panel,
filters, a complex frequency shifter, and a 8-Mbyte FIFO which are for the analog input signal, an external clock, and an
buffer memory. It is designed to provide maximum external trigger. The four SMB connectors on the front panel
performance and flexibility for capturing a bandlimited provide the capability of sending synchronizing signals from
continuous analog signal in a format compatible with one VXIbus mainframe to another mainframe containing
digital computers. additional HP E1430A modules.

According to Nyquist’s sampling theorem, any signal con-

fined to a finite frequency bandwidth can be completely
represented by a sequence of discrete samples taken at a
rate of at least twice the signal bandwidth. If we are
interested only in a finite time segment of the analog
signal, all the necessary information is contained in a
finite number of these samples taken from the appropriate
segment of the sequence. In the absence of additive
measurement noise we could theoretically represent the
signal with infinite precision, although this would require
infinite precision for each discrete sample. However, all
analog measurements have some level of additive noise,
which limits the amount of signal information available.
Therefore, it is only necessary to store each sample with
sufficient finite precision to retain the available signal
information in the presence of the additive noise.

In other words, it is theoretically possible to completely

determine a finite time segment of a bandlimited analog
signal, to the extent allowed by additive measurement
noise, by collecting a finite number of finite-precision
samples of the signal. To maintain complete generality in
capturing such a signal, the signal bandwidth, center
frequency, start time, and time duration should all be
independently specifiable. The HP E1430A offers a wide
range of independent choices of all of these parameters
while guaranteeing that the sample rate and data precision
are sufficient to characterize the signal. The HP E1430A
also minimizes the amount of additive measurement noise
to preserve as much signal information as possible.

The HP E1430A is much more than an analog-to-digital

converter. It also addresses the problems of gain ranging,
anti-aliasing protection, frequency band selection, trigger-
ing, data buffering, and multichannel synchronization. Fig. 1. HP E1430A analog-to-digital converter module.

October 1993 Hewlett-Packard Journal

Fig. 2. Block diagram of the HP E1430A ADC module.

The rear panel contains the standard VXIbus connectors, resonances of the input cable inductance with the cable-
which are used for programming and reading data from to-chassis capacitance.
the module. The HP E1430A complies with the VXIbus
register-based protocol. Status lights are provided to Diodes are placed between the grounds to protect against
indicate when the module is being accessed via the damage and to satisfy safety concerns arising from high
VXIbus backplane or when the input range is exceeded, common-mode voltages. The result is an input termination
producing an overload in the ADC. that maintains good flatness to 4 MHz, suppresses low-
frequency ground loop pickup, reduces high-frequency
Fig. 2 shows a functional block diagram of the HP E1430A common-mode feedthrough, and eliminates unsafe high
module. common-mode voltages.

Analog Signal Conditioning Opening S1 under program control causes the input signal
It is common practice at audio frequencies to provide to be ac coupled through a 0.2-µF capacitor. This makes
high-impedance balanced differential inputs for ADC possible the measurement of low-level ac signals in the
modules. However, maintaining good frequency response presence of a large dc offset. Programming S2 to the
to a band-width of 4 MHz requires the use of a terminated grounded position provides a 0-volt reference so that the
transmission line to drive the input. The HP E1430A offset DAC can be programmed to eliminate any dc offset
implements a 50-ohm pseudofloating input as shown in in the input amplifier.
Fig. 3. The cable ground is isolated from chassis ground
by 50 ohms in parallel with a 0.04-µF capacitor. This is The gain or attenuation of the input amplifier is program-
sufficient impedance to break up low-frequency ground mable in 6-dB steps so that sinusoidal input signals
loops, maintaining the key benefit of a differential input. ranging from −32 dBm to +28 dBm can be scaled to
At high frequencies where ground loops are no longer a produce a full-scale sine wave at the ADC. The noise
problem, the 0.04-µF capacitor shorts out the common- added to the signal by the HP E1430A is −136 dB/Hz
mode signal, reducing the impact of common-mode relative to full scale (dBfs/Hz) for the −14-dBm and higher
feedthrough at high frequencies. The resistor damps out ranges. It is −128 dBfs/Hz for the −20-dBm and lower
ranges. This represents a 14-dB noise figure in the
−32-dBm range. Most ADC modules have fixed, high-level
input ranges requiring the user to provide low-noise
external amplification.

Anti-Aliasing Filter
Since the normal ADC sample rate is 10 MHz, a complete
representation of the input signal can be achieved only for
bandwidths up to 5 MHz. To eliminate the possibility of
higher-frequency components causing ambiguous results
as a result of aliasing, all signal components above 5 MHz
need to be removed before sampling occurs. The analog
anti-aliasing filter in the HP E1430A is flat to 4 MHz and
rejects signals above 6 MHz by at least 110 dB. Thus the
0-to-4-MHz frequency range of the sampled signal will be
Fig. 3. Analog signal conditioning equivalent circuit. alias-free. The analog filter transition band from 4 MHz to

October 1993 Hewlett-Packard Journal

6 MHz affects the flatness and allows some aliasing in the
sampled signal frequency range of 4 MHz to 5 MHz. In
some applications a complete, unambiguous representa-
tion of a continuous signal may not be necessary, or the
user may have additional information about the signal to
allow a valid interpretation of the aliased components. In
those cases anti-aliasing filtering may not be necessary,
and the analog filter may be bypassed. This programmable
mode allows the user to take advantage of the full 20-MHz
sampler bandwidth. The anti-aliasing filter bypass mode
should be used with caution and is not recommended for
normal operation.

Sampling ADC
The heart of the HP E1430A is a precision ADC that
generates 23-bit outputs at sample rates up to 10.24 MHz.
The amplitude resolution is far in excess of the converter’s
analog noise. Thus, the effects of finite quantization levels Fig. 4. Harmonic distortion as a function of input level
can be completely ignored, leaving the main error mecha-
nisms, which are random white noise and linearity errors.
For each sample the random error has a Gaussian ampli- Zoom and Decimation Filtering
tude distribution with an rms level of −70 dB relative to a For changing the signal bandwidth and center frequency,
full-scale sine wave. The random error for each sample is the HP E1430A provides a complex frequency shifter
essentially uncorrelated with previous samples, meaning (zoom) and a complex low-pass filter. Both functions are
that the spectral energy of the noise is uniformly distrib- implemented digitally with proprietary Hewlett-Packard
uted across the 5-MHz Nyquist band. Therefore, the noise high-speed ICs to achieve real-time operation. A Block
can be expressed as −137 dBfs/Hz. With the input amplifier diagram of the digital signal processing is shown in Fig. 5.
noise included, the overall HP E1430A noise level is
−136 dBfs/Hz (−128 dBfs/Hz for input ranges < −20 dBm). The local oscillator generates cosine and sine waves with
This low noise density is comparable to the best available spurious components smaller than -110 dBc and frequency
ADCs at any sample rate. resolution better than 10 µHz. These are then multiplied
by the incoming signal to produce the real and imaginary
In many applications, random errors can be filtered, components of the down-converted complex baseband
averaged, or otherwise processed to reduce their impact signal. The complex baseband signal is then filtered to the
on the final result. In these applications the deterministic desired bandwidth by separately filtering the real and
signal-related errors—that is, distortion components— imaginary components.
may limit the resulting accuracy unless they are signifi-
cantly lower than the −70 dB broadband noise level. The Bandwidth choices are provided with a cascaded chain of
HP E1430A achieves distortion errors of −80 dBfs to digital low-pass filters, each of which reduces the band-
−110 dBfs depending on the level and dynamics of the width by a factor of two. With the ADC sample rate, Fs,
applied signal. The graph shown in Fig. 4 shows the worst- set to the standard internal 10-MHz rate, the available
case harmonic level for sinusoidal inputs of various levels. bandwidth choices are ±5 MHz, ±2.5 MHz, ..., ±0.149 Hz
This distortion performance is considerably better than around the programmed LO frequency. Each of the filters
traditional ADCs in the 10-MSa/s class. has ±0.35-dB amplitude flatness to 75% of its indicated
corner frequency and has >105-dB rejection for signals
A more complete discussion of ADC errors and how the above 125% of its indicated corner frequency. Because of
HP E1430A minimizes them is given in the October 1993 the sharp cutoff, the time-domain step response of the
Hewlett-Packard Journal article titled “A 10-MHz Analog- filters has approximately 20% overshoot. Also, since the
to-Digital Converter with 110-dB Linearity,” publication filters are not linear-phase, the time-domain impulse
number 5962-9494E. response is not symmetric. In time-domain applications

Fig. 5. Zoom and decimation filtering

October 1993 Hewlett-Packard Journal

where overshoot and/or impulse response symmetry data is sufficiently fast then the memory will never
are important the user can apply additional signal overflow and the measurement will continue indefinitely.
processing to achieve the desired filter response. If the memory should ever overflow then the measure-
Although the HP E1430A does not include this compen- ment will stop and wait until data is read out, the mea-
sation filtering, all the necessary signal information is surement is rearmed, and a new trigger occurs. This mode
preserved to accomplish it within a host computer or of operation is useful for real-time applications that
signal processing module. employ a high-speed signal processor to read and operate
on each sample of data. The deep FIFO memory allows
Once the signal bandwidth is reduced below ±fs/4 the the consumer to read the data in bursts to accommodate
sample rate is also reduced by a factor of two in each pauses for such things as disk access times or block mode
filter stage. Thus, each filter output is generated with a computations.
sample rate of four times the nominal cutoff frequency.
This is sufficient to avoid any aliasing within the filter The effective trigger time can be offset from the actual
passband and transition band. The user can program an trigger event by programming a trigger timing offset. The
additional factor-of-two sample rate reduction to get an pretrigger offset is limited to the physical depth of the
output sample rate of only two times the nominal filter FIFO memory. The post-trigger offset is limited to
cutoff. This is still sufficient to avoid aliasing within 226 samples.
the passband, but the transition band will not be fully
alias-free. This additional decimation is useful in Data Output
applications such as FFT-based spectrum analysis, The output data from the FIFO memory can be directed to
where the lower sample rate is beneficial but transition a VXIbus register or a high-speed local bus. The VXIbus
band aliasing is not of concern. register can be read by any controller compatible with the
VMEbus standard. The memory is unpacked from the 64-
The data multiplexing block can be programmed to bit memory and sent to the 16-bit register as four separate
output only samples from a particular filter or to words. Although this mode provides compatibility with a
multiplex the outputs of all of the filters beyond a broad range of controllers, it limits the data flow to
selected one. In the multiplexed filter mode each approximately 4 Mbytes/s. The local bus mode supports
output sample is tagged with a number to indicate from data transfers over a high-speed 8-bit ECL bus to an
which filter it came. This mode is useful in the imple- adjacent module (to the right) in the VXIbus mainframe.
mentation of 1/N-octave analysis algorithms. The HP E1430A can output data over the local bus at rates
up to 80 Mbytes/s. This mode requires the use of a
The real and imaginary components are each computed consumer module that supports Hewlett-Packard’s ECL
to 32-bit precision to preserve the processing gain local bus protocol. The protocol accommodates multiple
provided in the narrowband filters. Thus, each complex adjacent HP E1430A modules sending data to a single
output sample contains 64 bits. Whether or not all signal processor module such as the HP E1485A. In
these bits are stored in memory can be programmed in addition to the increased data rates, the local bus mode
the data formatting block. allows output data to flow concurrently with control
traffic over the standard VMEbus backplane. This can
Data Formatting and FIFO Memory simplify the design of real-time signal processing systems
The HP E1430A can be programmed to save only the that require interactive control. In both of the data output
real component of the signal or to save the complete modes the samples must be read out sequentially,
complex signal. The data precision can be set to 16 bits beginning with the sample following the effective trigger.
or 32 bits. Thus, each sample occupies from two to The HP E1430A does not support random access or
eight bytes of memory. The data formatting block memory-mapped access to the data.
packs the selected data into 64-bit words, which are
stored in the FIFO memory. Since the standard FIFO Clock and Trigger Generation
depth is 1 Mwords (8 Mbytes), it is possible to hold up Normally the ADC clock is produced by a 10-MHz crystal
to 4 Msamples in memory at one time. oscillator inside the clock generation block. However, for
applications requiring a customer-supplied sample clock,
The memory can be configured either in block mode or the HP E1430A can accept an external TTL clock signal at
in continuous mode. In block mode, data collection a front-panel connector. The ADCs of multiple HP E1430A
initiated by a trigger proceeds until a specified block modules can be synchronized by programming them to
length is captured. The measurement is then paused so use a common ECL clock line on the backplane. One of
that the data can be read out. Before a new block can the modules can then be programmed as the clock master
be collected, the module must be rearmed and trig- that drives this line. For systems involving more than one
gered again. This mode is useful in capturing single VXIbus mainframe, the backplane clock line can be
transient events or whenever the output data rate is too extended to another mainframe by using the SMB connec-
high to be read and processed in real time. tor on the front panel.

In the continuous mode, data collection is initiated by a The trigger event used to start a measurement can be
trigger and continues as long as the FIFO memory does generated in four different ways: software trigger,
not overflow. Data can be read out of the memory external TTL, ADC threshold, and log magnitude. Any
while the measurement is in progress. If the reading of HP E1430A module can synchronously trigger multiple

October 1993 Hewlett-Packard Journal

HP E1430A modules via a shared sync line on the VXIbus (Standard Commands for Programmable Instruments)
backplane. This line can be extended between mainframes protocol. The HP E1405B interprets each SCPI command
in the same manner as the ADC clock described above. All and performs the appropriate register read/write opera-
modules in a synchronous system are triggered on exactly tions on the HP E1430A. A driver is provided to support
the same ADC sample. All triggering modes support slope the HP ITG (Interactive Test Generator) and HP VEE-Test
selection. The ADC and log magnitude modes also allow interactive environments. Either of these environments
user selection of a trigger threshold, with hysteresis to can use this driver and SCPI commands to provide a
prevent noise-generated false triggers on the wrong slope. virtual front panel on the computer screen for control of
The log magnitude triggering is based on the magnitude of the HP E1430A. The ITG and VEE software environments
the complex signal after zooming and filtering. The are sold separately.
frequency selectivity of this mode is ideally suited to
capturing low-level burst communication signals in the Summary
presence of larger interfering signals. The primary features that set the HP E1430A module apart
from a typical ADC module are its high accuracy, high
Control sample rate, selectable anti-aliasing filters, selectable
All control of the HP E1430A module is accomplished by center frequency, deep FIFO memory, analog signal
means of twenty-four writable and eighteen readable conditioning, triggering, and fast data transfers. These are
16-bit registers mapped into the 16-bit VXIbus address important considerations in modern communications
space. The operating and service manual documents the receivers, radar and sonar processors, and transient
function of each of these registers in detail. The module capture equipment. Before digital signal processing
can be programmed from any VXIbus or VMEbus control- algorithms can be applied effectively to signals, those
ler. The registers allow direct, high-speed access to all of signals must first be captured accurately in digital form.
the functions of the module. The HP E1430A provides all the necessary capabilities to
perform this function with a high degree of flexibility.
To assist a programmer in using the HP E1430A effec-
tively, the operating and service manual also includes Acknowledgments
documentation and a distribution disk or tape for a library The key contributions to the HP E1430A were made by
of functions to facilitate programming the registers. These several people at the Lake Stevens Instrument Division.
functions provide a C-language interface for setting up Dean Payne designed the analog portions of the module
single modules and synchronous groups of modules and managed schematic capture and printed circuit layout
spanning multiple VXIbus mainframes. Along with the for the entire product. The digital design was done by
low-level control functions, the library provides setup Jerry Ringel with help from Hoang Nu. Software support
save and recall, autorange, auto-zero, and diagnostics. included a function library provided by Doug Passey and
Also included are filter correction coefficients and a test software written by Chris Sutton. The challenging
resampling algorithm to facilitate high-resolution, printed circuit layout was accomplished by Lavonne Fogel
time-domain sampling. Because source code is included, and Allyson Riley. Rene Slocumb was the project coordi-
the functions can be modified or translated to other nator. Marketing support and assistance in product
languages. An executable program that invokes the definition came from Lee Meyer. As the first application
diagnostic functions is included so that users with a programmer to use the HP E1430A, Mike Gribler provided
supported controller can test the HP E1430A without valuable QA and definition feedback to the project.
writing any code. Ed Guppy generated the product documentation.

For users who are accustomed to a high-level ASCII References

control interface, the distribution disk or tape includes 1. VMEbus Extensions for Instrumentation System Specification,
software that will configure an HP E1405B command Revision 1.3, July 14, 1989.
2. L.A. DesJardin, “VXIbus: A Standard for Test and Measurement
module to respond to ASCII commands from a supported System Architecture,” Hewlett-Packard Journal, Vol. 43, no. 2,
external controller. The commands conform to the SCPI April 1992, pp. 6-14.

Copyright © 1993 Hewlett-Packard Co.

Printed in U.S.A. 4/94
5962-9497E

October 1993 Hewlett-Packard Journal