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8085 Time-Delay-And-Counter

This document discusses time delay and counters in microprocessors. It defines time delay as using a number of instructions to keep track of a time interval. There are three main types of time delay: using NOP instructions, using a counter, and using nested loops with internal and external counters. The document also defines a counter program as one that can design different types of counters like up/down counters with time delays between states. It provides an example program for a down counter that displays each state on an output port with a 1ms delay between each state.

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7K views6 pages

8085 Time-Delay-And-Counter

This document discusses time delay and counters in microprocessors. It defines time delay as using a number of instructions to keep track of a time interval. There are three main types of time delay: using NOP instructions, using a counter, and using nested loops with internal and external counters. The document also defines a counter program as one that can design different types of counters like up/down counters with time delays between states. It provides an example program for a down counter that displays each state on an output port with a 1ms delay between each state.

Uploaded by

M jhansi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Microprocessor Lectures Time Delay and Counter 6th lecture

Time Delay and Counter

Lecture objectives: at the end of this lecture the student will able to:
1- Define the time delay.
2- Study types of time delay.
3- Design all types of counters.

6.1 Time Delay:


6.1.1 Definition of time delay: it is number of instructions that written to keep a track for
certain interval. Time delay or (software delay) can be designed through executing group of
instruction number of times. Flow chart as an example of time delay is shown in Fig. (6-1)
below.

Loading delay
in register

Exe. some of
instructions

Decrement
delay register

No Is
Register
=0

Yes
End

Figure (6-1): Example of time delay.

1 | Page Al-Najaf Technical College Communications Techniques Eng. Dep.


Microprocessor Lectures Time Delay and Counter 6th lecture
6.1.2 Types of time delay: there are three types of time delay as shown below:
A. Time Delay using NOP instruction: NOP instruction does nothing but take 4 T-states of
processor time to execute. So by executing NOP instruction between two instructions we can
get delay of 4 T-state where:

6.1

B. Time Delay Using Counter: Time delay can be created using counting process which means
executing number of instructions many times where the initial value of counter required to get
specific time delay can be determined. there are two types of delay using counter as below:
B.1 time delay using one register (8-bit counter): in this type of time delay the register
delay is one register loaded with 8-bit number in one loop as shown in program 6.1below :

Program 6.1

MVI C,37 (delay reg.)


LOOP1 MVI A, 33
RAR (some ins.)
DCR C (decrement delay reg.)
JNZ LOOP1 (condition)
HLT

B. 2 time delay using register pair: in this type of time delay the register delay is register
pair loaded with 16-bit number in one loop as shown in program 6.2 below:

Program 6.2

LXI B,234B (delay reg.)


LOOP1 MVI A, 33
RAR (some ins.)
DCX B (decrement delay reg.)
MOV A,C
ORA B
JNZ LOOP1 (condition)
HLT

C. time delay using loop with in loop: this time delay is used two loop one internal and the
other loop is external, these two loops can be designed by using one register or register pair
as shown in program 6.3 below:

2 | Page Al-Najaf Technical College Communications Techniques Eng. Dep.


Microprocessor Lectures Time Delay and Counter 6th lecture
Program 6.3

MVI B,37 (delay reg. external loop)


LOOP 2 MVID,FF (delay reg. internal loop)
LOOP1 MVI A, 33
RAR (some ins.)
DCR D (decrement delay reg. int. loop)
JNZ LOOP1 (condition)
DCR B (decrement delay reg. ext. loop)
JNZ LOOP2 (condition)
HLT
6.1.3 Calculation of time delay: the interval of any program can be calculated by using the equation
below:

6.2

Where Tt is total time interval. To is the out loop instructions time. Ti is in loop instructions time.

6.3

6.4

Where N10 is the number that loaded in delay register in decimal. t is the processor time clock.

Example 6.1: Calculate the time delay to programs (6.4, 6.5 and 6.6) below, (let the microprocessor
frequency is 1MHz)
Solution:
First t=1/F=1/1*106 =1µS

Program 6.4

MVI C,37 (delay reg.) 7Tstate


LOOP1 MVI A, 33 7Tstate
RAR (some ins.) 4Tstate
DCR C (decr. delay reg.) 4Tstate
JNZ LOOP1 (condition) 10/7Tstate
HLT 6Tstate

Tt =To + Ti
To = [7Tstate (MVI C,37) + 7Tstate (JNZ loop1) + 6Tstate (HLT)]*t
=20 Tstate*1 µS =20 µS
Ti=[7Tstate (MVI A,33) + 4Tstate (RAR) + 4Tstate (DCR C) + 10Tstate (JNZ loop1)]*t*55
=[25Tstate]*t*55
=[25 µS]*55=1375 µS
Tt=20 µS+1375 µS=1395 µS =1.395 mS

3 | Page Al-Najaf Technical College Communications Techniques Eng. Dep.


Microprocessor Lectures Time Delay and Counter 6th lecture
Program 6.6
Program 6.5
MVI B,37 (delay reg. external loop) 7Tstate
LXI B,234B (delay reg.) 10Tstate LOOP 2 MVI D,FF (delay reg. internal loop) 7Tstate
LOOP1 MVI A, 33 7Tstate LOOP1 MVI A, 33 7Tstate
RAR (some ins.) 6Tstate RAR (some ins.) 6Tstate
DCX B (decr. delay reg.) 4Tstate DCR D (decr. delay reg. int. loop) 4Tstate
MOV A,C 4Tstate JNZ LOOP1 10/7Tstate
ORA B 4Tstate DCR B (decr. delay reg. ext. loop) 4Tstate
JNZ LOOP1 (condition) 10/7Tstate JNZ LOOP2 (condition) 10/7Tstate
HLT 6Tstate HLT 6Tstate

For program 6.5

To=[10Tstate (LXI B,234B) + 7Tstate (JNZ loop) + 6Tstate (HLT)] = 23 µS


Ti=[7Tstate (MVI A,33) +4Tstate (RAR) + 4Tstate (DCX B) + 4Tstate (MOV A,C) +4Tstate (ORA B) +
10Tstate (JNZ loop1)]*9035 = (33 Tstate)*9035=(33 µS)*9035=298155 µS
Tt=23 µS+298155 µS=298178 µS=298.178ms

For program 6.6

To=[7Tstate (MVI B,37) + 7Tstate (JNZ loop2) + 6Tstate (HLT)]


=20 Tstate=20 µS
Ti=[7Tstate (MVI D,FF) + {7Tstate (MVI A,33) + 4Tstate (RAR) + 4Tstate (DCR D)} * 255 + {10Tstate (JNZ Comment [DS1]: Internal loop

loop1) * 254}+ 7Tstate (JNZ loop1) +4Tstate (DCR B)] * 55 +10Tstate (JNZ loop2)*54 Comment [DS2]: External loop

=[7Tstate (MVI D,FF) + {3825 Tstate }+{2450 Tstate}+7Tstate (JNZ loop1) +4Tstate (DCR B)]*55 + 540
= [18 + 3825 + 2450] * 55 + 540
= 346,115 + 540
=346500 Tstate=346,655 µS
Tt=To + Ti =20 µS+346,655 µS=346,675 µS=346.68ms

6.2 Counters:

6.2.1 Definition of counter: A counter program is an program written to design a counter (all
types of counter such as up, down, Johnson, serial, parallel, decimal, etc.) with flexibility in
controlling of time interval between counting states.
Example 6.2: write ALP (Assembly Language Program) to design down counter mod (255) and
display the counting states on out port with time delay (1ms) for each counting
state. Let the processor operate with frequency 2MHz.
Solution: Fig. (6.2) show the flow chat of the counter program

4 | Page Al-Najaf Technical College Communications Techniques Eng. Dep.


Microprocessor Lectures Time Delay and Counter 6th lecture
Initialize
counter

Counting state
display

Time delay
1ms

Update count

No

Is count
complete

Yes
End

Figure (6.2): flow chart of Ex.6.2

MVI A,FF 7Tstate


A1: OUT 02 10Tstate
MVI D, XX 7Tstate
A2: DCR D 4Tstate
Now, must loading register D with certain number
JNZ A2(delay) 10/7Tstate
to get the time delay 1ms, this number calculated as below:
DCR A 4Tstate
First Tstate = 1/F = 1/2*106 = 0.5µS
JNZ A1(Count display)
10/7Tstate
Tt=To + Ti
HLT 6Tstate
Where Tt=1ms
To=[10Tstate (OUT 02) + 7Tstate (MVI DXX) + 7Tstate (JNZ A2)+ 4Tstate (DCR A) +10Tstate (JNZ A1)]*
0.5µS
=[38 Tstate] * 0.5µS=19 µS
Ti=[(4Tstate (DCR D) * N10)+ (10Tstate (JNZ A2) * (N10-1))]*0.5 µS
=(2* N10)+5* (N10-1)
=(7 N10-5) µS
By return to initial equation
Tt=To + Ti
1000 µS=19 µS+ (7 N10-5) µS
1000 µS=19 µS+7 N10 µS-5 µS

5 | Page Al-Najaf Technical College Communications Techniques Eng. Dep.


Microprocessor Lectures Time Delay and Counter 6th lecture
1000 µS=14 µS+7 N10 µS
N10=(1000-14)/7=140.857=141
Therefore must loading equivalent to 141 in hexadecimal which equal (8D) in register D.

other solution:
Tt = [10T (OUT 02) + 7T (MVI D, XX) + 4T*N10 (DCR D) + 10T*N10-1 (JNZ A2) + 7T (JNZ A2) +
4T (DCR A) + 10T (JNZ A1) ] * 0.5S
1000S =[ 38T + 4T*N10 + 10T* (N10-1)] * 0.5S
1000S = 19S + 2*N10 S+ 5*N10 S- 5S
1000S = 14S + 7*N10 S
N10 = (1000 - 14)/7 = 140.857=141
Therefore must loading equivalent to 141 in hexadecimal which equal (8D) in register D.

Home work:
1- Calculate the required time to execute the JPE instruction if the condition is satisfying. Let the
processor operate with 4 MHz frequency.

2- Write ALP to make the microprocessor working as up/down counter mod (32) with time delay
2ms between each two counting states. (let the frequency is 2 MHz)

6 | Page Al-Najaf Technical College Communications Techniques Eng. Dep.

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