Field-Effect Transistors

FET

Junction Field Effect Metal–oxide–semiconductor

Transistor (JFET) field-effect transistor (MOSFET)

n-channel p-channel Depletion Type Enhancement Type

FET
Junction Field-Effect Transistor (JFET)
N-channel JFET
- n-type material forms channel between the
embedded layers of p-type material
- Top of the n-type channel connected through an
ohmic contact to a terminal - drain (D)
- Lower end of the same material connected through
an ohmic contact to a terminal - source (S)
- Two p-type materials connected together and to the
gate (G) terminal
- Drain and source connected to ends of n-type
channel
- Gate connected to the two layers of p-type material
- In the absence of applied potentials - JFET has two
p–n junctions under no-bias conditions
- Depletion region at each junction
- Depletion region void of free carriers - unable to
support conduction
N-channel JFET operation
- VGS =0 V, VDS >0V
- Gate and a source terminal at the same potential

- Depletion region in the low end of each p-material

- VDD (=VDS) is applied -> the electrons drawn to the

drain terminal -> establishment of conventional current
ID with the defined direction
- Drain and source currents are equivalent (ID = IS)

- Flow of charge limited solely by the resistance of the

n-channel between drain and source

- Depletion region wider near the top of both p-type
- materials
 N-channel JFET operation
● ID establishes various voltage levels through the
channel
● The upper region of p-type material will be
reverse-biased by a higher voltage than the lower
region
● Greater the applied reverse bias, wider the depletion
region
● The reverse bias of the p-n junction for the length of the
channel - gate current IG = 0 A
Assuming uniform resistance in
the n-channel ● VDS increased from 0 V to a few volts -> the current
will increase as determined by Ohm’s law
N-channel JFET operation
● The relative straightness of the plot - for low
values of VDS, the resistance is essentially
constant
● As VDS increases and approaches level VP -
widening of depletion regions - a noticeable
reduction in channel width
● Reduced path of conduction causes the
resistance to increase
● The more horizontal the curve, the higher the
resistance -> the resistance approaches
“infinite” ohms in the horizontal region
N-channel JFET operation
● If VDS is increased to a level where it appears that the two
depletion regions would “touch” - pinch-off will result.
● VDS level that establishes this condition - pinch-off voltage (VP)
● ID maintains a saturation level - IDSS
● In reality a very small channel still exists, with a current of very high
density
● The fact that ID does not drop off at pinch-off and maintains the
saturation level
● Absence of a drain current would remove the possibility of different
potential levels through the n-channel material to establish the
varying levels of reverse bias along the p–n junction
● Result would be a loss of the depletion region distribution that
caused pinch-off in the first place
 N-channel JFET operation
● As VDS is increased beyond VP, the region of close encounter
between the two depletion regions increases in length along
the channel, but the level of ID remains essentially the same
● In essence, therefore, once VDS > VP the JFET has the
characteristics of a current source
● the current is fixed at ID = IDSS , voltage VDS (for levels > VP)
is determined by the applied load.
● The choice of notation IDSS is derived from the fact that it is the
drain-to-source current with a short-circuit connection from
gate to source
Current source equivalent
for VGS = 0 V, VDS > VP. ● IDSS is the maximum drain current for a JFET and is defined by
the conditions VGS =0 V and VDS > | VP |
 N-channel JFET operation

Current source equivalent

for VGS = 0 V, VDS > VP.
N-channel JFET operation
VGS < 0 V
● Gate terminal set at lower and lower potential levels as compared to the
source
● Negative voltage of 1 V is applied between the gate and source terminals
for a low level of VDS
● Effect of the negative-bias VGS - to establish depletion regions similar to
those obtained with VGS 0 V, but at lower levels of VDS
● Therefore, the result of applying a negative bias to the gate is to reach the
saturation level at a lower level of VDS,
● The resulting saturation level for ID has been reduced - will continue to
decrease as VGS is made more and more negative.
● Pinch-off voltage continues to drop in a parabolic manner as VGS becomes
more and more negative
● VGS when VGS = -VP will be sufficiently negative to establish a saturation
level that is essentially 0 mA - device has been “turned off”
N-channel JFET operation
VGS < 0 V
● Negative voltage of 1 V is applied between gate and source terminals
● For low level of VDS -> effect of the applied negative-bias VGS to
establish depletion regions similar to those obtained with VGS = 0 V at
lower levels of VDS
● Result of applying a negative bias to the gate - to reach the saturation
level at a lower level of VDS
● Resulting saturation level for ID reduced
● ID will continue to decrease as VGS is made more and more negative
● Pinch-off voltage continues to drop in a parabolic manner as VGS
becomes more and more negative
● VGS = -VP : sufficiently negative to establish a saturation level of 0 mA
- device ‘turned off’
● Level of VGS that results in ID =0 mA is defined by VGS = VP
● VP negative for n-channel devices and positive for p-channel devices
 N-channel JFET operation
● Ohmic/ voltage-controlled
resistance region

● JFET employed as a
variable resistor
resistance is controlled
by the applied
gate-to-source voltage

● Slope of each curve and

therefore the resistance
of the device between
drain and source for VDS Constant-current,saturation
< VP a function of the /linear amplification region
applied voltage VGS

● As VGS becomes more Typically employed in linear

and more negative, the amplifiers (amplifiers with
slope of each curve
becomes more and more minimum distortion of the
horizontal, corresponding applied signal)
to an increasing
resistance level
N-channel JFET operation: Summary
P-channel JFET operation
 JFET Transfer Characteristics

DC analysis - graphical rather than a mathematical approach

Graphical approach - plot of device equation + plot of the network equation
Solution defined by the point of intersection of the two curves
Device characteristics will be unaffected by the network in which the device is employed
JFET Transfer Characteristics
JFET Transfer Characteristics
JFET Transfer Characteristics
JFET Transfer Characteristics
JFET Transfer Characteristics
JFET Transfer Characteristics (P-channel)
JFET Operating Region