ALLEGRO PCB DESIGN

TUTORIAL
(FROM ZERO TO MANUFACTURING)

GÖKÇE KESK N

MARCH 2007

CARNEGIE MELLON UNIVERSITY

This tutorial is intended for beginners in printed circuit board design who wish to complete a board in
Cadence Allegro Tool at Carnegie Mellon ECE Linux Computers.

Allegro is a very comprehensive package program from Cadence that incorporates several sub-tools to
complete the design of a printed circuit board. Unfortunately, I have not been able to locate a complete
tutorial that describes all the steps one should do to complete a PCB design from scratch, so I had to
learn many things through thousands of pages of documentation. The steps below are based on my own
experience as I went through the complicated design process, and this document is open to suggestions
for improvement and/or any corrections. However, I believe it will be useful for people with little or
no experience in the tool. The images in tutorial might seem blurry on printouts, but if you zoom in on
the pdf, you can read a much higher resolution of them.

BASICS

It is assumed that you have access to a Linux platform at the ECE department, and you are at a Linux
station. Alternatively, you can use an X-Win or a VNC session.

The following line should be added to your ~/.cshrc file before running Allegro:

setenv PATH ${PATH}:/usr/cds/spb-15.7/tools/bin:/usr/cds/spb-15.7/tools/pcb/bin:/usr/cds/spb-15.7/tools/specctra/bin

You have to log out and log back in for the change to take effect.

INTRODUCTION

To complete a board design, you need to learn many built-in tools within Allegro. The design process is
as follows:

1) Select the components (capacitors, sockets, etc.) you will be using on your board. Once you have
a list, collect the datasheets and look at the suggested footprints (that is, the hole sizes or pads) in those
documents. I ordered the components from Digikey (www.digikey.com).
2) For each component, you have to create a footprint. Footprint is a physical view of the
component that includes the holes through your board or pads for surface mount components. Footprints
can be reused in the same board several times. For those who are familiar with chip design, this is
similar to creating the layout of a gate in your standard cell library. Footprints are created with Allegro
Package Designer (APD). The size and properties of the pins of the components are completed using
Padstack Editor.
3) Once you have the footprint, you need to create a symbol view of the component to be used in
the schematic view of your board. Symbol creation maps the pins in the footprint to the pins of the
symbol. For chip designers, this is similar to creating the symbol view of a schematic in your standard
cell library. You need to use Allegro Part Developer for this step.
4) You have to create a schematic view of your board. This means adding different components on
your board and connecting them with wires. This is similar to the schematic editor in icfb, but you need
to use a much less user friendly tool called Design Entry HDL.
5) Once you have the schematic, you have to generate the netlist and import it to Allegro PCB
Editor to complete the board layout. You place the physical views of the components, define power and
ground planes, add vias between layers and route physical wires using this tool. It is analogous to the
Virtuoso Layout Editor in icfb.

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6) After you have the board layout, you generate a few files called artwork for manufacturing your
board. I used Sierra Proto Express’ No-Touch option for 4-layer boards (http://www.protoexpress.com).

SETTING UP YOUR PROJECT

To create a project, follow these steps:

• Type “projmgr &” on the xterm and select a new Allegro PCB Librarian XL as the startup tool.
• On the GUI, click on a “Create Design Project” button and follow through the steps. Add all
available libraries to your project.
• Your GUI should look like Fig. 1. If you see a different flow, change your flow from Flows-
>Library Management.

Fig. 1 PCB Librarian

• On an xterm, create two directories under your worklib. Name them as “pads” and “symbols”.
• Click Tools ->Setup on the Librarian GUI. On the pop-up window, click on Tools tab. Click on the
Setup button next to the PCB Editor tool. In the new pop-up window, select “Design_Paths” under
Categories section on the left. On the right, you will see psmpath and padpath lines. For psmpath, click
on the value field marked with “…” button and add the “symbols” directory you just created to the
topmost line. Do the same for padpath, this time with “pads” directory.

DESIGNING THE FOOTPRINT

To create a footprint of a component, type “apd &” and select Allegro Package Designer XL from the
menu.
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• Click on File -> New and select “Package Symbol”.
• Setup the grid desired grid resolution (say, to 10 mils) from Setup ->Grids. The units in PCB design
are in mils. 1 mil is equal to one thousandth of an inch (1mil = 0.001inch = 0.0254mm).
• Define the cross section of your board from Setup->Cross Section. If you are using a 4-layer board
with the middle two layers as Power and Ground, add them as “Plane” layer type and “Negative” Film
Type (Fig. 2). Name them accordingly. Add FR-4 dielectrics in between if that is your dielectric type.

Fig.2 Defining the Cross-Sections.

• Draw a rectangle by Add -> Rectangle or by clicking the icon on the toolbar. There will be a toolbar
on the right side of the screen where you can define the active class and sub-class under the “Options”
tab (Fig. 3). Select “Component Geometry” as Class, “Assembly Top” as Sub-Class and “Static Solid”
as the Shape Fill to draw a rectangular physical outline of your component.
• Create a second rectangle, the same size as the previous one and overlapping it, but this time
Place_Bound_Top as the Sub-Class.
• Add the pins of your component from Layout -> Add Pins. On the right side of the screen, select
the Padstack by clicking on the box with “…” sign on it. Allegro has a list of default padstacks, select
one for the moment (say Pad44cir33). You can modify it later if needed. Add your pins within the
previously defined rectangles.
• Save your footprint. Then go to File->Create Symbol and this will create a “design.psm” file in the
directory of your choice. Put your symbols under a common folder named “symbols” under worklib.

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 Fig. 3 Drawing Rectangles

• For complicated footprints like a QFP or a PGA package, you can use the “Package Symbol
(Wizard)” option when you create a new cell. That will automate many of the steps and create the
package footprint quickly.

DESIGNING PADSTACKS

If you want to design your own padstack (and in many cases, you will), you have to use Padstack Editor.
You can invoke this tool from PCB Librarian GUI as in Fig. 1 (brought up by “projmgr &” command)
after you open a project; just click on the Padstack Editor Button.

• Padstack Editor will open a pop-up window. In the type field, define your pad type. For a hole that
will punch from the top of the the board through all layers to the bottom, you have to select “Through”.
For surface mount components with pads on only one side of the board, you have to select “Single”.
Click “Fixed” for internal layers. In the drill/slot hole type select “circular” for holes (you would most
probably select rectangular for surface mounts). You have to select “Plated” for holes that will have
electrical connection to wires or planes on your board (this is mostly the case, unless you specifically
want unconnected holes for inserting metal legs to keep your board above the table while you are
testing). Drill diameter is the diameter of the hole. Fill in other fields as shown in Fig. 4.
• Click on the “Layers” tab on Padstack Editor. Add the extra layers in your board (GND and VDD) to
the padstack by right-clicking on the arrow button next to the “Default Internal” and selecting “Insert”.
For “Regular Pad”, use a value 10-20 mils larger than the drill hole size defined in the previous screen.
For “Thermal Relief”, “Anti Pad”, “Soldermask Top” and “Soldermask Bottom”, use 10-20 mils larger
than Regular Pad. Fig. 5 explains this step. For surface mount pads, you do not need to define internal
layers, but just the top layer.

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 Fig. 4 Padstack Editor

• Save your padstack into the “pads” directory you created under your worklib. If you want to change
the padstack of any of your components you previously designed, open the footprint of the component
by Allegro Package Developer, and go to Tools -> Padstack -> Replace.

Fig. 5 More Padstack Editor

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Flash Symbols for Thermal Relief

Thermal relief in a padstack is used to reduce heat flow to the copper plane; that allows us to use less
heat at the pins of the component while soldering, preventing any damage to the component. Thermal
relief structure is defined as flash symbols in Allegro. To create a thermal relief, you have to run Allegro
Package Designer (apd&).
• Once APD is open, go to File -> New -> Flash Symbol. Go to Setup -> Cross Section and define
the cross sections in your design as before.
• Go to Add -> Flash and select Inner and Outer Diameters. For Inner diameter, select the same size
as the Regular Pad of the padstack that you are building this Thermal Relief for. The Outer Diameter
should be 10-20 mils larger than the Inner Diameter. For Spoke Width, select 20 mils (for pads that have
large diameters – 90 mils or more -, you can use 30 mils for width). Use 4 Spokes with 45 degree angle.
• Click on OK and create a symbol (.fsm) for this flash. Store it in your symbols directory.
• Open the Padstack Editor for the pad that you would like to add this flash and click on Layers Tab as
in Fig. 5. For Thermal Relief, select Flash as Geometry and add the .fsm symbol you created by clicking
on “…”. Use the Flash symbol for all layers of the board.

Designing Vias

Vias are through holes that connect signal lines on one side of the board to the other side for routing.
The only difference between them and padstacks is that no components will be inserted into vias, and
that’s why they can be of smaller size (less than 20 mils in diameter). Design a via -similar to a
padstack- in allowable dimensions from your manufacturer and save it in your pads directory. You will
need that while doing board layout in later stages.

CREATING SYMBOLS FOR SCHEMATIC EDITOR

After you design the footprint for the component, you have to map the physical pin information of the
component to pins in the symbol view in schematic. Part Developer is the tool to use to do this.

• Open the PCB Librarian and click on the “Part Developer” button on the GUI. On the new window,
open the cell for which you would like to create the schematic symbol by File -> Open -> Cell.
• Setup the Part Developer. Click on Tools -> Setup. Follow the steps in the Allegro Part Developer
Tutorial pages 21-26. You can reach this tutorial at /usr/cds/spb-15.7/doc/pdv_tut/pdv_tut.pdf. I have
also pasted those instructions below, directly from Cadence’s documentation:

Start: Part Developer Tutorial from Cadence Documentation

• Click on the Package node in the Setup Options tree. The Package options appear in the Setup
dialog box.
• Type LIBRARY_NAME and my_library [your library name, Gökçe’s note] in the Name and Value
columns, respectively.
• Press Ctrl + I to create a blank row in the Additional Package Properties grid.
• Type PACKAGE_CREATOR and ? in the Name and Value columns, respectively. The Package
panel should appear as in Fig. 6:

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 Fig. 6 Part Developer Setup

• Next, you need to add the LIBRARY_NAME property to the symbols and configure the symbol pin
text to display pin text in 0.6 grid size. Click on the Symbol node in the Setup Options tree. The Symbol
panel appears in the Setup dialog box.
• Enter LIBRARY_NAME and my_library in the Name and Value columns, respectively, in the
Symbol Properties grid. Next, you need to determine the display parameters.
• Select Both in the Visibility column to ensure that both the property name and its value are visible in
the symbol. Select Mono in the Color field. Select 90 in the Rotation field. This ensures that the property
is displayed at an angle of 90 degrees to the symbol. Select Top-Left in the Location field. This ensures
that the property is displayed at the top-left corner of the symbol. The filled Symbol panel is as in Fig 7:

Fig. 7 Part Developer Setup

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• Next, set up Part Developer so that pin text appears in 0.6 grid size. Click on Symbol Pins in the
Setup Options tree. Change the value in the Pin Text Height column to 0.0600.

End: Part Developer Tutorial from Cadence Documentation

• Click on OK and close the setup dialog box.

• On the left side of the screen of the Part Developer main window, right click on “Packages” and then
“New”. This will create a new package for your component.
• On the right side of the screen, under “General” tab, below the “Associated Footprints” section and
“Jedec Type”, click on the “…” button and select the footprint for the component you created before. To
find the footprint easily, click on one of the rows and right click, select “Filter Rows”, type in the first
few characters of the footprint followed by a star and click OK (Fig. 8). Do the same for “Alt Symbols”,
just below Jedec Type (select the same footprint).

Fig. 8 Part Developer: Adding the Footprint

• Click on “Package Pin” tab. Click Pins - > Add. Enter a pin of your component under Scalar
section. Select the Type as Power for Vdd/Gnd (Fig. 9). For signal pins; select input, output or bidir.
Click on Add, and repeat the process for all pins. Click on OK.

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• Click on Footprint->Extract From Footprint (labeled as 1 in Fig. 10). Click on the “Number”
field under “Package Pins” for the pin you want to map, click on S1 field under “Logical Pins” you want
to map this pin to, and click “Map” (labeled as 2). For logical pins you want to turn into global pins (for
example, Vdd/Gnd), click on the logical pin, then Move -> Logical Pins to Global (labeled as 3). You
can assign several Physical Pins to Global Pins (e.g., you can have several Gnd connections in your
package). Repeat the procedure for all Package Pins.
• After mapping is finished, click on Generate Symbol(s). This will create a symbol view for use
under schematic editor. You can see the view by selecting sym_1 on the left panel of Part Developer,
and you can modify it as you like. Global pins will not be displayed on the symbol.
• Generate symbols for all of the components you have created the footprints for.

Fig.9 Part Developer: Adding Pins

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 Fig. 10 Part Developer: Mapping Pins

DESIGNING THE SCHEMATIC

Once you have all the symbols of the components in your library, you are ready to start your schematic
design. For schematic entry of your board, you have to close the PCB Librarian and start PCB Design
Expert. You can do this by typing “projmgr &” on xterm and choosing that tool. After you open your
project, you have to change the tool flow from Flows -> Board Design. You should see a window as in
Fig. 11.
• Click on “Design Entry” button. This will open up a schematic window. Go to Component -> Add
and under “Library”, select “standard”. Select “d size page” under “Cells” (Fig. 12). Later, add the
components you wish to place on your board (you can find the symbols you created under your defined
library name) within page borders. Connect them with wires. You can see the shortcut locations for
these steps in Fig. 12 labeled as 2.
• As far as I have seen, Design Entry HDL schematic editor is a much less user-friendly tool than the
one under icfb, but nevertheless it works. I will not elaborate on the different difficulties of the tool, but
mention a couple of things you might find useful. To select the components in a given area, use “Group”
tab in the toolbar. To move a component, use the “Edit” tab. To name nets (I highly recommend), use
Wire -> Signal Name. Naming will be useful during layout.

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 Fig.11 PCB Design Expert Flow

Fig. 12 Design Entry HDL: Adding Components

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• Once you are done with your schematic, you have to export the netlist so that the PCB Editor can
read it and place the components on your board. To do that, go to File -> Export Physical. Select the
options as shown in Fig. 13. With this step, you are done with your schematic editor.

Fig. 13 Design Entry HDL: Exporting the Netlist

BOARD LAYOUT

You are now finally ready to design the layout of your board, the eagerly waited moment of this tutorial.

• First, open PCB Design Expert (if you don’t have it open already), and click on Layout button on
Fig. 11.
• Draw an unfilled rectangle with class Manufacturing and Subclass Photoplot_Outline. Draw a
second rectangle the same size as this one, and overlapping it, but this time class Board Geometry and
Subclass Outline.
• Draw a third rectangle enclosed by the Board Outline. The class for this rectangle should be Route
Keepin, and Subclass All. Draw a fourth rectangle, the same size as the third one and overlapping it, with
Class Package Keepin, subclass All.
• Setup your Cross Section similar to the padstack. From Setup -> Cross Section.
• Setup your Constraints (DRC Rules) from Setup -> Constraints. Always have On-Line DRC on.
Set Standard Values according to the data provided by the manufacturer. Under Physical Rules Set
section, click on “Set values”, scroll down on the pop-up window and select the via you previously
defined, and click on “Add”. Close the Constraints Window.

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• Go to File -> Import and select the netlist directory where you have exported your schematic design
(this is most probably under somewhere similar to worklib/design_name/packaged). Select the
options as shown in Fig 14 and click on “Import Cadence”.
• Go to Place -> QuickPlace. Fill in the fields as shown in Fig. 14. Click on “Place”. Move the placed
components within the keeping areas with Edit -> Move.
• Go to Add -> Rectangle and add a filled rectangle within the previously defined keepins; the class
should be Etch and the Subclass Vdd. Repeat the same with Subclass Gnd.
• On the right side of the screen, go to Visibility (marked 2 in Fig. 15) and unselect all layers except
for Gnd.
• Go to Shape -> Select Shape or Void and click on the Gnd rectangle you drew. Select the signal
name “Gnd” from the list of imported nets on the right side of the screen, labeled 1 in Fig. 15.
Similarly, assign the Vdd net by setting visibility.
• If you want automatic routing of your components, you can go to Route -> Automatic. Specctra is
the router tool for Allegro. I have not gone through auto routing since I did not have many routes.
For manual routing, go to Add -> Line and route the wire between the two pins you would like to
connect (these will be connected with thin blue lines before you actually connect). On the right side
of the screen, you can adjust the width and the layer of the line. If you double click while you are
drawing, your route will go from the Act (Active Layer) to the Alt (Alternative Layer) with the via
type that you have defined previously. If you have defined more than one via, you can select the one
that you would like. If not critical, use wider lines than the minimum design rule.

Fig. 14 Importing Logic and Placing Components

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 Fig. 15 Assigning Vdd/Gnd Planes

• After you have finished the routing, add four big holes (diameter ~ 120-150mils) in the corners of
your board. You can use those to connect metal legs (as in a dining table) to your design while you
are testing the chips. You should also name the routes/important points on your board using
silkscreen. Silkscreen is a white (mostly) coating that is applied on or below the board for
component names, routes, test points, etc; and it helps identify the various points while you are
actually testing. You can add text from Add -> Text, and be sure to select Class as Board Geometry
and Sub-Class as Silkscreen_Top or Silkscreen_Bottom, depending on where you would like to add
the text.
• Make sure you have no errors by Tools -> Update DRC. You can see the result in the bottom of
PCB Editor Window. You can also go to Tools -> Reports. Double click on Design Rules Check
Report and then click on Report. Correct any errors you might have.

MANUFACTURING DATA

The last step in the tutorial is to create your manufacturing data.

• Go to Display -> Visibility on the PCB Editor Main Window. Select Global Visibility to All
Invisible, an option on the top-right of the pop-up window that opens. Then select Group ->
Geometry on the top-left, and turn on Board Geometry -> Outline. Click OK.
• Go to Manufacture -> Artwork. Artwork Control Form opens. On the bottom, click on Apertures,
then Edit, then Auto -> Without Rotation. Click on OK and go back to the Artwork Control Form.
• Under General Parameters tab, select the output format (Gerber RS274X for Sierra Proto). If you got
any errors about precision, set the appropriate values under Format.

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• Right click on the Available Films Window and select Add. Name the new film as BoardOutline.
Click on OK.
• Go to Display -> Visibility and turn off all layers except Soldermask_Top. Go to Manufacture ->
Artwork and create a film layer with that name, similar to what you did for BoardOutline. Repeat the
steps for Soldermask_Bottom, Silkscreen_Top and Silkscreen_Bottom.
• On the right side of the Artwork Control Form, set undefined line width to 10 mils for all film layers.
For negative layers (Vdd and Gnd), set the Plot mode to Negative. Fig. 16 has a snapshot of this
window.

Fig. 16 Creating Artwork

• Select all Positive layers, and click on Create Artwork. Click on Viewlog to see if there are any
errors or warnings, correct them if there are any. Repeat the same for all negative layers.
• Close the Artwork Control Form and go to Manufacture -> NC -> NC Drill. Set the Scale Factor to
1, unselect all options (including Repeat Codes), and click on Drill. See the Viewlog for any
errors/warnings.
• At the end of this step, you have created all the necessary files for manufacturing (.art files and .drl
file). You can find them under a directory similar to /worklib/design_name/physical. To be sure,
create a new board in PCB Editor window and import all artwork layers from File -> Import ->
Artwork and check if they look good (negative layers will look “inverted”).
• Submit the files to the manufacturer. Well done!

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