CHAPTER 2

INTRODUCTION T O MICROCONTROLLERS
2.1 MICROPROCESSOR S AND M ICROCONTROLLERS

Since the invention of microprocessors, different companies has started manufacturing

more and more sophisticated processors with improved features such as large data bus, large
address bus, sophisticated memory management techniques and instruction set, capability of handling
a wide range of integer and floating point data, parallel processing of instructions, etc. But these
sophisticated processors are not necessary for small applications such as controlling a motor,
monitoring/controlling temperature, switching ON/OFF traffic lights, etc. In the 1980s the
manufacturers of microprocessors realized that there is a need for low cost, compact, single-chip
programmable systems for small dedicated applications and so started manufacturing another class
of programmable ICs called microcontrollers.

Microcontrollers are similar to microprocessors, but they are designed to work as a true
single-chip system by integrating all the devices needed for a system on a single-chip. The basic
functional units of a microprocessor will be ALU, a set of registers, timing and control unit. The
microcontroller will have these functional blocks and in addition may have IO ports, a programmable
timer, RAM memory and EPROM/EEPROM memory. Some microcontrollers may even have internal
ADC and/or DAC.

Basic Functional Blocks of a Microcontroller

The microcontroller is a programmable IC manufactured by VLSI (Very Large Scale

Integration) technique, and capable of performing arithmetic and logical operations. The various
functional blocks of a typical microcontroller is shown in Fig. 2.1. The basic functional blocks of
a microcontroller are the ALU, Flag register, Register array, Program Counter (PC), Instruction

RAM EPROM Parallel Serial

Timer ADC DAC
Memory Memory IO Port IO Port

Internal Bus

Instruction Program
Register ALU Timing & Decoding
Control Counter
Array Unit
Unit
Flag Register

Fig. 2.1 : Functional block diagram of a microcontroller.

2. 2 MICROPROCESSORS AND MICROCONTROLLERS

decoding Unit, Timing and control unit, RAM memory, EPROM/EEPROM memory, Parallel IO
port, Serial IO port, Programmable timer, ADC and DAC. All microcontrollers may not have all the
blocks shown in Fig. 2.1. Some of the functional blocks shown in Fig. 2.1, may not be available in
certain microcontrollers.
The ALU is the computational unit of the microcontroller which performs arithmetic and
logical operations. The various conditions of the result are stored as status bits called flags in the
flag register. The register array and internal RAM memory are used as a temporary storage device
for storing temporary data during execution of a program.
The program codes and permanent data are stored in EPROM/EEPROM. In microcontroller-
based systems, an external memory is provided only when the internal memory is not sufficient
and so in most of the microcontroller-based systems, the program and data are stored in the
internal memory of the microcontroller itself.
The program counter generates the address of the instructions to be fetched from the memory
and sends it through the internal bus to the memory. (If the instruction to be fetched is stored in the
external memory then the address is send through IO ports to the external memory. Because the
microcontrollers communicate with the external world only through IO ports.) The memory will
send the instruction codes, which are decoded by the instruction decoding unit and send the
information to the timing and control unit. The timing and control unit will generate the necessary
control signals for internal and external operation of the microcontroller.
The parallel and serial IO ports are used for interfacing IO devices like switches, keyboard,
LCD/LED, ADC, DAC, etc., and also for any other input/output operations.
Microcontrollers do not have a dedicated external address and data bus. Therefore for
interfacing any additional peripheral devices, the external address and data buses are formed only
by using port lines.
Microcontrollers with internal ADC can directly accept analog signals for processing. Likewise,
microcontrollers with internal DAC can directly generate analog signals for controlling analog devices.
A programmable timer can be used for time-based operations and it can also be used as a counter.
TABLE - 2.1 : COMPARISON OF MICROPROCESSOR AND MICROCONTROLLER

Microprocessor Microcontroller
1. The functional blocks of a microprocessor are 1. The microcontroller includes the functional blocks
the ALU, registers, and timing and control unit. of a microprocessor and in addition has a timer,
a parallel IO port, a serial IO port, internal RAM
and EPROM/EEPROM memory. Some
controllers even have ADC and/or DAC.
2. A microprocessor is concerned with rapid 2. A microcontroller is concerned with rapid
movement of code and data between the movement of code and data within the
external memory and the microprocessor. microcontroller. Hence it has few instructions for
Hence it has a large number of instructions for data transfer between the external memory and
moving data between the external memory and the microcontroller.
the microprocessor.
3. Microprocessors mostly operate on byte/word 3. Microcontrollers often manipulate with bits and
data and so have very few bit manipulating so have a large number of bit manipulating
instructions. instructions.
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 3

Table - 2.1 continued...

Microprocessor Microcontroller
4. Microprocessors usually require interfacing of 4. Microcontrollers can be used to form a
a large number of additional ICs to form a single chip microcomputer-based system
microcomputer-based system. Hence the PCB without any additional ICs. Hence the PCB of a
of a microprocessor-based system will be large microcontroller-based system will be small
and so the system will be costly. and so the system will be cheap.
5. The microprocessors are used for designing 5. Microcontrollers are used for designing
general purpose digital computing system (or application specific dedicated systems.
computers).
2.2 INTEL 8031/8051 MICROCONTROLLER
The 8051 family of microcontrollers was originally released by INTEL and later on licensed
to many semiconductor companies like PHILIPS, ATMEL, SIEMENS, HARRIS, etc. These
companies have developed a family of 8X5X microcontrollers with the same base architecture but
with different internal memory capacity and internal devices. Some of the popular members of
8X5X family of microcontrollers are listed in Table-2.2.
2.2.1 Pins and Signals of 8031/8051

The INTEL 8051 is an 8-bit microcontroller with 128 byte internal RAM and 4 kb internal
ROM. The INTEL 8031 is same as 8051 except that it does not have an internal ROM (i.e., the
8031 has all features of 8051 except the internal ROM). The 8051 is a 40-pin IC available in Dual
In-line Package (DIP) and it requires a single power supply of +5-V. Its maximum internal clock
frequency rating is 12 MHz. The 8031 is pin to pin compatible with 8051. The 8X5X family
members listed in Table-2.2 are also pin-to-pin compatible with 8051. The pin configuration of
8031/8051 microcontroller is shown in Fig. 2.3 and the signals of the controller are listed in
Table-2.3. Some of the port pins of a 8031/8051 microcontroller have alternate functions and they
are listed in Table-2.4.
TABLE- 2.2 : SOME MEMBERS OF THE 8X5X FAMILY OF MICROCONTROLLERS

Microcontroller Internal memory capacity Number of Timers

RAM ROM EPROM FLASH EPROM
8031 128 bytes - - - 2
8032 256 bytes - - - 3
8051 128 bytes 4 kb - - 2
8052 256 bytes 8 kb - - 3
8751 128 bytes - 4 kb - 2
8752 256 bytes - 8 kb - 3
8951 128 bytes - - 4 kb 2
8952 256 bytes - - 8 kb 3
2. 4 MICROPROCESSORS AND MICROCONTROLLERS

8 8
P1.0 ¬
®1 40 ¬ VCC P1.7 - P1.0 P0.7 - P0.0
P1.1 ¬
®2 39 ¬
® P0.0(AD0) (AD7 - AD0)
®3
P1.2 ¬ ® P0.1(AD1)
38 ¬
8
P1.3 ¬
®4 37 ¬
® P0.2(AD2) P2.7 - P2.0
P1.4 ¬
®5 36 ¬
® P0.3(AD3) ® (A15 - A8)
(RD) P3.7 ¬
P1.5 ¬
®6 35 ¬
® P0.4(AD4) (WR) P3.6 ¬ ®
®7
P1.6 ¬ 34 ¬
® P0.5(AD5) (T1) P3.5 ¬
®
P1.7 ¬
®8 33 ¬
® P0.6(AD6) ®
(T0) P3.4 ¬
8031/8051

8031/8051
RST ® 9 ® P0.7(AD7)
32 ¬ (INT1) P3.3 ¬ ®
(RXD) P3.0 ¬ ® 10 31 ¬ EA/VPP (INT0) P3.2 ¬ ® ¬ EA/V PP

(TXD) P3.1 ¬ ® 11 30 ® ALE/PROG (TXD) P3.1 ¬ ® ® ALE/PROG

(INT0) P3.2 ¬ ® 12 29 ® PSEN (RXD) P3.0 ¬ ® ® PSEN
(INT1) P3.3 ¬ ® 13 28 ¬
® P2.7(A15)
(T0) P3.4 ¬
® 14 ® P2.6(A14)
27 ¬ ¬ VCC
(T1) P3.5 ¬
® 15 26 ¬
® P2.5(A13)
(WR) P3.6 ¬ ® 16 25 ¬
® P2.4(A12) RST® ®V SS

(RD) P3.7 ¬® 17 24 ¬
® P2.3(A11) XTAL2 ¬
®
XTAL2 ¬ ® 18 ® P2.2(A10)
23 ¬
XTAL1 ® 19 XTAL1 ®
® P2.1(A9)
22 ¬
VSS ¬ 20 ® P2.0(A8)
21 ¬

Note : The signals shown within brackets are alternate functions of port pins.

Fig. 2.2 : Pin configuration of an INTEL 8031/8051 microcontroller.

TABLE - 2.3 : SIGNALS OF A 8031/8051 MICROCONTROLLER

Pins/Signal Description

P0.7 - P0.0 Port-0 input/output pins.

P1.7 - P1.0 Port-1 input/output pins.
P2.7 - P2.0 Port-2 input/output pins.
P3.7 - P3.0 Port-3 input/output pins.
RST Reset input
XTAL1, XTAL2 Pins for crystal connection. The signal at XTAL2 can be used
as clock signal for peripherals.

PSEN Program store enable. Used as read control or enable for external
program memory.
ALE/PROG Address Latch Enable or program pulse input during EPROM/
ROM programming.

EA/VPP External Access or Programming voltage.

VCC Power supply (+5-V)
VSS Power supply ground (0-V)
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 5

TABLE - 2.4 : ALTERNATE FUNCTIONS OF PORT PINS

Port pins Alternate signal Description

P0.7 - P0.0 AD7 - AD0 Multiplexed low byte address/data.

P2.7 - P2.0 A15 - A8 High byte address
P3.7 RD External memory read control signal
P3.6 WR External memory write control signal
P3.5 T1 External input to timer 1
P3.4 T0 External input to timer 0
P3.3 INT1 External interrupt 1
P3.2 INT0 External interrupt 0
P3.1 TxD Serial data output
P3.0 RxD Serial data input

The 8031/8051 microcontroller has 32 IO pins and they are organized as four numbers of an
8-bit parallel port. The ports are denoted as port-0, port-1, port-2 and port-3. Each port can be
used either as an 8-bit parallel port or 8 numbers of 1-bit port (i.e., individual pins of each port can
be used as 1-bit IO line independently). When used as 1-bit port, the port pins are denoted as PX.Y,
where X can take values 0 to 3 and Y can take values 0 to 7. For example, the bit-0 of
port-1 is denoted as P1.0. The ports behave as latches during output operation and as buffers
during input operation. Except port-0 all other ports are provided with internal pull up. Hence, while
using port-0 for IO operation, external pull up should be provided.
Except port-1 all other ports have alternate functions. (Port-1 can be used only for IO
operation.) When external memory is employed, port-0 functions as multiplexed low byte address
or data lines, and port-2 functions as high byte address lines. Therefore, for accessing external
memory the microcontroller uses a 16-bit address and accesses the memory in bytes. Hence the
addressable memory space is 64 kb (216 = 64 k). The 8031/8051 allows the external memory to be
organized as two banks of 64 kb, one for the program/code and the other for the data. The signal
PSEN is used as read control/enable for program memory. The port pin P3.7 functions as read
control (RD) and the port pin P3.6 functions as write control (WR) for data memory. When two
external memory banks are not desirable, the PSEN and RD should be externally ANDed to provided
a single read control signal. In such cases the controller will access a common memory space (of
maximum capacity 64 kb) for program and data.

In systems with external memory, the signal ALE is used to demultiplex the low byte address
or data using an external latch. The output signal on the ALE pin is the clock signal with a frequency
one-sixth of a crystal or internal clock frequency. The controller will output the ALE signal at a
constant rate (i.e., at one-sixth of internal clock) even when there is no external memory. Therefore
the ALE can also be used for external timing and clock source for peripherals or IO devices. In
EPROM/ROM version of 8051 family controllers, the programming pulse can be input through
ALE during programming of EPROM/ROM.
2. 6 MICROPROCESSORS AND MICROCONTROLLERS

Signal EA is used as an external program memory access control. The microcontroller will
access the program from external memory if EA pin is grounded. During programming mode of
internal EPROM/ROM, this pin is used to supply the programming voltage (+12-V).
Note : For programming the internal EPROM/ROM of 8051 family of microcontroller, a
separate programmer should be employed. The controllers listed in Table-2.2, does not have
ISP (In-system programmable) facility.
The XTAL1 and XTAL2 pins are provided for external quartz crystal connection, in order
to generate the required clock for the microcontroller. The maximum frequency of a quartz crystal
that can be connected to an 8031/8051 microcontroller is 12 MHz. (There are higher clock versions
of the 8051 family of microcontrollers. For details please refer to manufacturers data sheet.)
Alternatively the external clock can be supplied through an XTAL1 pin. The internal clock frequency
of an 8031/8051 microcontroller is same as a crystal frequency or externally supplied clock
frequency. When a crystal is connected between XTAL1 and XTAL2, the controller will output a
clock signal through XTAL2 whose frequency is same as crystal frequency and this clock signal
can be used for peripheral or IO devices.
The RST signal is used to reset the microcontroller in order to bring the controller to a
known state. For proper reset the RST pin should be held low for at least two machine cycles.
When the 8031/8051 controller is reset, all the internal registers are cleared except the port latches,
stack pointer and SBUF register. The internal RAM is not affected by reset. The content of the
various registers of 8031/8051 after a reset are listed in Table-2.5.

TABLE - 2.5 : CONTENTS OF REGISTERS AFTER A RESET

Register Content after reset Register Content after reset

PC 00H SP 07 H
ACC 00 H TCON 00 H
B 00H TH0 00 H
PSW 00H TL0 00 H
DPTR 0000 H TH1 00 H
P0-P3 FFH TL1 00 H
IP xxx00000B SCON 00 H
IE 0xx00000B SBUF Indeterminate
TMOD 00H PCON 0xxx00000B

The 8031/8051 has five interrupts. In this two interrupts are external interrupts and the
remaining three are internal interrupts. The two external interrupts are interrupts initiated by applying
appropriate signals through the pins INT0 and INT1, and they are called external interrupt-0 and
external interrupt-1 respectively. The internal interrupts are initiated by timer-0, timer-1 and the
serial port. All the interrupts of 8031/8051 are maskable and vectored interrupts. The vector address
and the priorities of the interrupts of 8031/8051 are listed in Table-2.6. (The priorities of the
interrupts can also be altered by programming the IP register.)
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 7

TABLE - 2.6 : VECTOR ADDRESS AND PRIORITY OF AN 8031/8051

Interrupt Vector address Normal priority

External interrupt-0 0003 H highest
Timer-0 interrupt 000BH
External interrupt-1 0013 H
Timer-1 interrupt 001BH
Serial port interrupt 0023 H lowest

2.2.2 Architecture of 8031/8051

The architecture of 8031/8051 is shown in Fig. 2.3. The various functional blocks of 8051
are the ALU, Special Function Registers (SFRs) listed in Table-2.7, Instruction Register (IR),
Program Counter (PC), 128 bytes RAM, 4 kb ROM, Port latches and drivers, Oscillator, Timing
and Control Unit.

The 8031/8051 has Harvard architecture in which the same address in different memory
devices or banks is used for program (or code) and data. Therefore the architecture has two
dedicated 16-bit address pointers, namely, Program Counter (PC) and Data Pointer (DPTR). The
PC is used as the address pointer to access program instructions and it is automatically incremented
after every byte of instruction fetch. The DPTR is used as address pointers to read/write data in
data memory and it is programmable using instructions.
Since the size of the address pointers are 16-bit they can address up to 216 = 64 k memory
locations. Hence 8031/8051 supports two memory banks of 64 kb each, one for program and the other
for data. In 8051, when the EA pin is tied to the VCC (logic-1), the first 4 kb of program memory address
space refers to 4 kb internal ROM and the remaining 60 kb refer to external (EPROM/RAM) memory.
In 8051, when the EA pin is tied to the ground (logic-0), the entire 64 kb of program address space
refers to external (EPROM/RAM) memory. In 8031 there is no internal ROM and so EA pin is always
grounded and in this case the entire program memory is external.
The 8031/8051 has separate 256 bytes internal RAM accessed by using an 8-bit address. In
this 256 bytes address space, the first 128 addresses are allotted to internal RAM and the next 128
bytes are allotted to SFR. The internal RAM/SFR can be accessed by using MOV instructions and
external data memory (RAM) can be accessed by using MOVX instruction.
The 8051 has four numbers of 8-bit ports, namely, port-0, port-1, port-2 and port-3. Each
port has a latch and driver (or buffer). When external memory is employed the port-0 lines will
function as multiplexed low byte address/data lines and port-2 lines will function as high byte
address lines. Also, the port pins P3.7 and P3.6 are used to output read and write control signals
respectively. In fact, each pin of port-3 has an alternate function which are listed in Table-2.4.
Port-1 is a dedicated IO port and does not have any alternate function. The ports are also
mapped as internal memory in the controller and so they can be addressed as memory locations for
8-bit operation.
2. 8 MICROPROCESSORS AND MICROCONTROLLERS

P0.7

P0.5
P0.4
P0.3
P0.6

P0.2
P0.1

P2.7
P0.0

P2.5
P2.4
P2.3
P2.6

P2.2
P2.1
P2.0
­
¯­¯­
¯­ ¯­
¯­ ¯­
¯­¯ ­
¯­¯­
¯­ ¯­
¯­ ­¯
¯¯ ­
Port-0 Port-2
Drivers Drivers

­ ­ ­ ­
¯ ¯ ­
RAM Address RAM Port-0
Port-2 ¯
Register Memory Latch ROM Memory
Latch
­ ­ ­ ­ ­
¯ ¯ ¯ ¯
­ ­ ­
¯ ¯
Program
Address Register
¬
A-Register SP
(Stack Pointer)
¯ ¯
TEMP1 TMP1 ¨ Buffer ¨
¯ PCON SCON TMOD TCON
B-Register ¯ ¯ T2C0N Th0 TL0 Th1
TL1
PC
Incrementer
¨
ALU
SBUF IE IP
¯ Interrupt, Serial Port
PSW and Timer Blocks PC
(Program Counter)
¨
PSEN ¬ ­ ­ ­
Timing
ALE ¬ Instruction ¯ ¯ ¯
and ¬ ® DPTR
¨
EA ® Control Register
­ ­ (Data Pointer)
RST ® Unit
¯
¯
Port-3
­
PD
Port-1
Latch Latch
­ ­
¯ ¯ ¯
Port-1 Port-3
Oscillator Drivers Drivers

­ ­­
¯­ ¯­
¯­ ¯­
¯­
­¯ ­ ­ ­
¯­ ¯­
¯­ ¯­
¯­ ­¯
¯¯ ­ ¯¯ ¯
P3.7
P1.7

P3.5
P3.4
P3.3
P1.5
P1.4
P1.3

P3.6

P3.2
P3.1
P1.6

P1.2
P1.1

P3.0
P1.0

VCC VSS
¯
XTAL1 XTAL2

Note : The 8031 microcontroller will not have ROM memory.

Fig. 2.3 : Architecture of a 8031/8051 microcontroller.

The SFRs include 21 internal registers listed in Table-2.7. (A detailed explanation of SFRs is
presented in the next section.) The SFRs are mapped as internal data memory. The data memory
address space 80H to FFH are reserved for SFRs. Each register of SFR has one-byte address. Some
of the registers are both byte and bit-addressable. (The registers whose address ends with 0H or 8H
are bit-addressable.)
The 8051 has an 8-bit ALU which performs arithmetic and logical operations on binary data.
The A and B registers are used to hold the input data and the result of the ALU operation. Starting
from the address stored in the PC, the controller will fetch the instructions one by one, and store in
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 9

IR, which decodes the instructions and give information to the timing and control unit. Using the
information supplied by the IR unit, the control signals necessary for internal and external operations
are generated by the timing and control unit. The 8031/8051 has an internal oscillator and so it is
sufficient if an external quartz crystal is connected for clock generation.
The 8031/8051 has two 16-bit programmable timers/counters namely, timer-1 and timer-0.
In the counter mode of operation they can count the number of high to low transitions of the signal
applied to the timer pins. In timer mode of operation they can be independently programmed to
work in any one of the four operating modes. The timer operating modes are called mode-0,
mode-1, mode-2 and mode-3.
The 8051 family of microcontrollers has a full duplex serial port which can be programmed to
work in any one of the four operating modes, namely, mode-0, mode-1, mode-2 and mode-3. In
mode-0 the serial port can either receive or transmit at a fixed baud rate. In mode-2 it can simultaneously
transmit and receive at any one of the two selectable baud rates. In mode-1 and mode-3 it can work
as a full duplex serial port with variable baud rates which is programmed using timer-1.
TABLE - 2.7 : SPECIAL FUNCTION REGISTER (SFR)

Special function register Byte address

in hexa
Symbol Name
A or ACC A-register or accumulator E0
B B-register F0
DPH Data pointer higher order register 83
DPL Data pointer lower order register 82
IE Interrupt enable register A8
IP Interrupt priority register B8
P0 Port-0 80
P1 Port-1 90
P2 Port-2 A0
P3 Port-3 B0
PCON Power control register 87
PSW Program status word D0
SCON Serial port control register 98
SBUF Serial port data buffer 99
SP Stack pointer 81
TMOD Timer/Counter mode control register 89
TCON Timer/Counter control register 88
TL0 Timer-0 low order register 8A
TH0 Timer-0 high order register 8C
TL1 Timer-1 low order register 8B
TH1 Timer-1 high order register 8D
2. 10 MICROPROCESSORS AND MICROCONTROLLERS

2.2.3 Programming Model of an 8031/8051

The programming model of the 8031/8051 microcontroller is shown in Fig. 2.4. The model
will show the programmable internal devices of a processor or controller. During execution of a
program the contents of the registers and RAM memory locations shown in the programming
model are altered.

7 Internal RAM 0 7 0 7 Internal ROM 0

QPI
7FH F0H* B-Register 0FFFH
Math Registers
7EH E0H* A-Register 0FFEH
7DH 7 0

QPI
D0H* PSW Flags
7 0

QPI QPI QPI QPI

B8H* IP Register Interrupt
A8H* IE Register Registers
7 0
99H SBUF Register Serial Port
98H* SCON Register Registers
7 0
8DH TH1 Counter
31H 8CH TH0 Counter Timer/Counter
30H 8BH TL1 Counter Data Registers
2FH* 8AH Tl0 Counter
Bit 7 0
Addressable 89H TMOD Register Timer Control
RAM 88H* TCON Register Registers
7 0
20H*
87H PCON Register
1FH
Register Bank-3 7 0
QPI

R7 - R0 83H DPH
18H Data Pointers
82H DPL
17H
Register Bank-2 7 0
R7 - R0 81H SP Stack Pointer
10H 7 0
0FH
QPI

Register Bank-1 B0H* Port-3

R7 - R0 A0H* Port-2 IO Port
08H Port-1 Latches
90H*
07H
Register Bank-0 80H* Port-0
R7 - R0 0001H
00H 15 87 0 0000H
Program Counter (PC)

Note : The hexa addresses marked with symbol * are bit - addressable.
In an 8031 microcontroller there is no internal ROM.

Fig. 2.4 : Programming model of a 8031/8051 microcontroller.

The programming model of an 8031/8051 microcontroller includes a 128 byte internal

RAM and all the Special Function Registers (SFRs). In addition, the programming model of an
8051 includes a 4 kb internal ROM. The internal RAM locations are separate data memory address
space and accessed either by direct or indirect addressing using an 8-bit address. The SFRs are
also separate data memory address spaces and are accessed by direct addressing using an 8-bit
address. The 4 kb internal ROM in an 8051 controller is mapped as program memory and accessed
using a 16-bit address.
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 11

The first 32 bytes of internal RAM are organized as four groups of eight registers. Each group
is called a register bank and denoted as bank-0, bank-1, bank-2 and bank-3. The eight registers of a
bank are denoted as Rn where n takes values from 0 to 7. At any one time the controller can use any
one of the register bank as general purpose registers (or scratch pad registers). The selection of the
register bank depends on the value of bits RS0 and RS1 in the PSW register. After a reset the PSW
register is cleared and so the controller works with register bank-0.
The internal RAM locations in the address range 20H to 2FH are bit-addressable. The internal
RAM locations in the address range 2F H to 7FH can be used as general purpose RAM. The hexa
address of the bit-addressable RAM are listed in Table-2.8. The 16 RAM locations in the address
range 20H to 2FH has a capacity of 128 bits (16 × 8 = 128). Each bit in this RAM area can be
addressed by an 8-bit address in the range 00H to 7FH, as shown in Table-2.8.

TABLE- 2.8: BYTE ADDRESS OF BIT-ADDRESSABLE RAM

Byte Hexa address of bit position

address B7 B6 B5 B4 B3 B2 B1 B0

20 07 06 05 04 03 02 01 00
21 0F 0E 0D 0C 0B 0A 09 08
22 17 16 15 14 13 12 11 10
23 1F 1E 1D 1C 1B 1A 19 18
24 27 26 25 24 23 22 21 20
25 2F 2E 2D 2C 2B 2A 29 28
26 37 36 35 34 33 32 31 30
27 3F 3E 3D 3C 3B 3A 39 38
28 47 46 45 44 43 42 41 40
29 4F 4E 4D 4C 4B 4A 49 48
2A 57 56 55 54 53 52 51 50
2B 5F 5E 5D 5C 5B 5A 59 58
2C 67 66 65 64 63 62 61 60
2D 6F 6E 6D 6C 6B 6A 69 68
2E 77 76 75 74 73 72 71 70
2F 7F 7E 7D 7C 7B 7A 79 78

2.2.4 Special Function Register (SFR)

The 8031/8051 is provided with 21 special function registers and they are used for selecting
various programmable features of the microcontroller. The special functions of most of the SFR
are distinguishable. Each SFR has an internal one-byte address assigned to it. Some of the registers
are both byte and bit-addressable. The SFR along with their byte address are listed in Table-2.7.
The bit-addressable register along with address for each bit are listed in Table-2.9.
2. 12 MICROPROCESSORS AND MICROCONTROLLERS

TABLE- 2.9 : BIT ADDRESS OF SFR

Hexa address of bit position

SFR
B7 B6 B5 B4 B3 B2 B1 B0
B F7 F6 F5 F4 F3 F2 F1 F0
A or ACC E7 E6 E5 E4 E3 E2 E1 E0
PSW D7 D6 D5 D4 D3 D2 D1 D0
IP BF BE BD BC BB BA B9 B8
P3 B7 B6 B5 B4 B3 B2 B1 B0
IE AF AE AD AC AB AA A9 A8
P2 A7 A6 A5 A4 A3 A2 A1 A0
SCON 9F 9E 9D 9C 9B 9A 99 98
P1 97 96 95 94 93 92 91 90
TCON 8F 8E 8D 8C 8B 8A 89 88
P0 87 86 85 84 83 82 81 80

A and B Registers
The A and B registers are called CPU registers. They are used to hold the data for most of the
CPU (ALU) operations. The size of A and B registers are 8-bit and they are mapped as on-chip data
memory with byte address E0H and F0H respectively. These registers are also bit-addressable.
In most of the ALU operations, the result is stored in the A-register and so, it is also known
as the accumulator.
Data Pointer (DPTR)
The data pointer is a 16-bit register used to hold the 16-bit address of data memory. The
16-bit data pointer can also be used as two numbers of 8-bit data pointer, namely, DPH and DPL.
The 8-bit data pointers are used for accessing internal RAM and SFR. The 16-bit data pointer is
used for accessing external data memory.
The 8-bit data pointer DPH and DPL are mapped as internal memory with byte address 83H
and 82H respectively. The contents of the data pointer are programmable using instructions.
Program Status Word (PSW)
The program status word store the status of the result of the ALU operations and some of the
status of the processor by means of a 1-bit status called flags. The PSW is also known as a flag
register. The flags are useful for the programmer to test the condition of the result and make decisions.
The format of the PSW of an 8031/8051 microcontroller is shown in Fig. 2.5. The PSW
consists of four math flags and two register bank select bits. The math flags are carry, auxiliary
carry, overflow and parity flags. These flags are altered after arithmetic and logical operations
depending on the result. The carry flag is set when the result has a carry. When there is a carry
from the lower nibble to the upper nibble, the auxiliary carry is set. When the result has even parity,
the parity flag is set. In certain mathematical operations if the size of the result exceeds the size of
the destination register then the overflow flag is set.
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 13

B7 B6 B5 B4 B3 B2 B1 B0

CF AF - RS1 RS0 OF - PF

® Parity Flag
® Overflow Flag
® Register Bank Select Bit 0
® Register Bank Select Bit 1
® Auxiliary Carry Flag
® Carry Flag
Fig. 2.5 : Format of PSW of an 8051 family of microcontrollers.

The register bank select bits RS1

TABLE - 2.10: SELECTION OF A REGISTER BANK
and RS0 are used to select any one of
the four register banks of the internal Bank select bits Selected Range of hexa
RAM. At any one time the microcontroller register bank address of the
RS1 RS0 selected bank
can work with (or access) only one
register bank selected by these bits. The
0 0 Bank-0 00H - 07 H
bank select bits are programmable and
0 1 Bank-1 08H - AFH`
after reset the controller defaults to
1 0 Bank-2 10H - 17 H
bank-0. The selection of a register bank
1 1 Bank-3 08H - 1F H
using the RS1 and RS0 bits are listed in
Table-2.10.
Stack Point er (SP)
The stack pointer always holds the 8-bit address at the top of the stack. The 8031/8051
microcontroller supports the LIFO (Last-In-First-Out) stack, and the stack may reside anywhere
in on-chip RAM (i.e., the programmer can reserve any portion of on-chip RAM as stack.) After a
reset the stack pointer is initialized to 07H. The stack can be accessed using PUSH and POP
instructions. During PUSH operation, the stack pointer is automatically incremented by one and
during POP operation the stack pointer is automatically decremented by one.
Power Control Register (PCON)
The PCON register is used for power control and baud rate selection. It also consists of
general purpose user flags. The format of a PCON register is shown in Fig. 2.6.
The controller can be driven to the idle mode by setting the IDL bit of the PCON register.
When the idle mode is activated the clock signal is stopped to CPU(ALU), but the clock signal is
supplied to interrupt, timer and serial port blocks. The idle mode can be terminated either by an
interrupt or by hardware reset.
The controller can be driven to power down mode by setting the PD bit of a PCON register.
During power down mode the internal oscillator is stopped, and the content of SFR and internal
RAM are preserved. When the controller remains in the power down mode, the VCC (power supply
2. 14 MICROPROCESSORS AND MICROCONTROLLERS

voltage) can be reduced to 2-V. The power down mode can be terminated only by a hardware reset
and during hardware reset the content of SFR are altered but the content of internal RAM are
preserved.
B7 B6 B5 B4 B3 B2 B1 B0

SMOD - - - GF1 GF0 PD IDL

® Idle Mode bit 1 = Idle Mode

® Power Down Bit, 1 = Power Down Mode
® General Purpose Flag Bit-0
® General Purpose Flag Bit-1
® Serial Mode Baud Rate Selection
Fig. 2.6 : Format of a PCON register of 8051 family of microcontrollers.

Note : The idle and power down mode are not available in NMOS version of 8031/8051.

The SMOD bit is used to decide the baud rate in serial port operating modes 1, 2 or 3. In
mode 2, if SMOD = 0, then the baud rate is 1/64 of oscillator frequency and if SMOD = 1, then the
baud rate is 1/32 of oscillator frequency. (In 8031/8051 the oscillator frequency and microcontroller
internal frequency are same.) In mode 1 and 3, the baud rate depends on the SMOD and timer-1
overflow rate.
SMOD
The baud rate in mode 1 or 3 = 2 32 × (Timer-1 overflow rate).

When timer-1 is configured for auto reload mode then,

Oscillator frequency
Timer-1 overflow rate = 12 × 256 − (TH1)

where, TH1 = Reload count value (8-bit) in higher order timer-1 count register.
The general purpose flag bits GF1 and GF0 can be used by the programmer to indicate the
status of certain events during program execution.
Serial Data Buffer (SBUF) Register
The SBUF register is used to hold the parallel data during transmission and reception. During
serial reception, the serial data is received via RxD pin and converted to parallel data and stored in
the receive buffer. During serial transmission, the parallel data is stored in the transmit buffer and
then converted to serial data to transmit via TxD pin.
The transmit and receive buffers are assigned the same internal address 99H but the transmit
buffer can be accessed only for write operation and the receive buffer can be accessed only for
read operation. When data is written to SBUF it goes to transmit buffer and when data is read from
SBUF it comes from the receive buffer.
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 15

Serial Port Control Register (SCON)

The format of a SCON register is shown in Fig. 2.7. The SCON register consists of mode
selection bits, the 9th data bit (bit-B8) for transmit and receive, and the serial port interrupt bits TI and RI.
The bits SM0 and SM1 are used to select any one of the four operating modes for serial transmission
and reception. The four modes of a serial port are mode-0, mode-1, mode-2 and mode-3.
B7 B6 B5 B4 B3 B2 B1 B0
SM0 SM1 SM1 SM2 TB8 RB8 TI RI

® Receive Interrupt Flag

¯ ¯ ® Transmit Interrupt Flag
0 0 - Mode-0
0 1 - Mode-1 ® Received 9 Bit (i.e., Bit B of Received Data)
th
8

1
1
0 - Mode-2
1 - Mode-3
® Transmitted 9 Bit (i.e., Bit B of Transmitted Data)
th
8

® Receive Enable
®Serial Mode Bit-2
Fig. 2.7 : Format of a SCON register of the 8051 family of microcontrollers.

Serial port mode-0:

In this mode, the serial port functions as a half duplex serial port with a fixed baud rate.
The 8-bit serial data is received and transmitted through the RxD pin and the controller
outputs the shift clock through the TxD pin during reception and transmission. The
baud rate is fixed at 1/12 of the oscillator frequency.
Serial port mode-1:
In this mode, the serial port functions as a full duplex serial port with variable baud rates. In
this mode, one data consists of 10 bits which includes one start bit, eight data bit and one
stop bit. During reception the stop bit is stored as RB8 in the SCON register. The baud rate
in mode-1 depends on the value of the SMOD bit in the PCON register and the timer-1
overflow rate.
Serial port mode-2:
In this mode, the serial port functions as a full duplex serial port with a baud rate of
either 1/32 or 1/64 of the oscillator frequency. In this mode, one data consists of 11 bits
which includes one start bit, eight data bit, a programmable 9th data bit and one stop bit.
During transmission the TB8 of the SCON register is added as the 9th data bit and during
reception the 9th data bit is stored as RB8 in the SCON register. (This 9th data bit can be used
as parity bit.) The baud rate depends on the value of the SMOD bit in the PCON register.
Serial port mode-3:
Mode-3 is same as mode-2, except the baud rate. In mode-3, the baud rate is variable.
The baud rate depends on the value of the SMOD bit in the PCON register and the timer-1
overflow rate.
2. 16 MICROPROCESSORS AND MICROCONTROLLERS

The serial mode bit-2 (SM2) has no effect in mode-0 and when programmed for mode-0,
the SM2 should be equal to zero. In mode-1, SM2 is used to check a valid stop bit during reception.
In mode-1, if SM2 = 0, then Receive Interrupt (RI) is activated only when a valid stop bit is
received.
In mode-2 and mode-3 the SM2 bit is used to enable multiprocessor communication. In
multiprocessor communication, the serial port of a number of microcontrollers can be connected
to a common serial bus. One controller will act as a master and all other controllers will act as
slaves. A unique 8-bit address is assigned to each slave and the SM2 bit in all the slaves is set to 1.
When the SM2 bit is one, the slaves will consider the received byte as address and when the SM2
bit is zero, the slaves will consider the received byte as data. For communication with a slave the
master will first send an address byte and then a data byte.

The master initiates communication with a slave by sending the address of the slave on the
bus. The address byte will be received by all the slaves. Since SM2 = 1 initially in all the slaves, the
received byte will be considered as the address and the slaves will verify whether the received
address matches with the assigned address. The slave whose assigned address matches with the
received address will clear its SM2 bit. Now SM2 bit of only one of the slave will be zero. Next, the
master will send a data byte which is also received by all the slaves, but the data byte is accepted by
the slave whose SM2 = 0 and so the receive interrupt is activated only in one of the slaves whose
SM2 = 0. After reading the received data from the SBUF register, the SM2 bit of the slave should
be set to one again to receive the next data.
The REN bit of the SCON register can be used to enable or disable the serial reception.
When REN is set to one, the serial reception is enabled and when REN is cleared to zero, the serial
reception is disabled.
The bits TI and RI of the SCON register are a transmit interrupt flag and a receive interrupt flag
respectively. They are also called serial data interrupt flags. The controller will set the TI bit during the
transmission of stop bit of a data character in modes 1 to 3 and during the transmission of the 8th bit of
a data character in mode-0. Similarly, the controller will set the RI bit during the reception of stop bit of
a data character in modes 1 to 3 and during the reception of the 8th bit of a data character is mode-0.
These two flags are logically ORed internally and used as an internal interrupt signal (called serial port
interrupt) to interrupt the current program being executed by the controller. On receiving the serial port
interrupt the controller has to suspend the current program execution and begins to execute a subroutine
program to check the value of bits TI and RI of the SCON register. If TI is one, then the controller can
understand that the previous character has been transmitted and so the controller can execute another
subroutine to clear TI flag and load the next data in the SBUF register. If RI is one, the controller can
understand that a character has been received and so the controller can execute another subroutine to
clear the RI flag and read the data from the SBUF register.
Timer Mode Control (TMOD) Register
The TMOD register is used to select the operating mode and the timer/counter operation of
the timers. The format of a TMOD register is shown in Fig. 2.8. The lower four bits of the TMOD
register is used to control timer-0 and the upper four bits are used to control timer-1.
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 17

The two timers can be independently programmed to operate in various modes. The TMOD
register has two separate two bit field M0 and M1 to program the operating mode of timers. The
operating modes of timers are mode-0, mode-1, mode-2 and mode-3. In all these operating modes
the oscillator clock is divided by 12 and applied as the input clock to the timer.

Timer-1 Control Timer-0 Control

IPQ IPQ
B7 B6 B5 B4 B3 B2 B1 B0

Gate C/T M1 M0 Gate C/T M1 M0

QPI QPI
Gate Control for Timer-1¬
® Mode Selection
Timer/Counter Selection ¬ for Timer-0
for Timer-1
® Timer/Counter Selection
for Timer-0
Mode Selection for Timer-1 ¬ ® Gate Control for Timer-0
M1 M0 Operating mode C/T Operation Gate Clock
0 0 Mode-0 0 Timer 0 Internal clock
0 1 Mode-1 1 Counter 1 External clock
1 0 Mode-2
1 1 Mode-3

Fig. 2.8 : Format of the TMOD register of the 8051 family of microcontroller.
Timer port mode-0:

In mode-0, the timer register is configured as a 13-bit register. For timer-1 the 8 bits of TH1
and lower 5 bits of TL1 are used to form the 13-bit register. For timer-0 the 8-bit of TH0
and lower 5 bits of TL0 are used to form the 13-bit register. (The upper three bits of the
TL registers are ignored.) For every clock input to timer the 13-bit timer register is incremented
by one. When the timer count rolls over from all 1s to all 0s, (i.e., 11111 1111 1111 to 00000
0000 0000) the timer interrupt flag in the TCON register is set to one.
Timer port mode-1:

Mode-1 is same as mode-0 except the size of the timer register. In mode-1, the TH and
TL registers are cascaded to form a 16-bit timer register.
Timer port mode-2:

In mode-2, the timers function as 8-bit timers with automatic reload feature. The
TL-register will function as an 8-bit timer count register and the TH-register will hold
an initial count value. When the timer is started, the initial value in TH is loaded to TL and
for each clock input to timer the 8-bit timer count register is incremented by one. When the
timer count rolls over from all 1s to all 0s (i.e., 1111 1111 to 0000 0000), the timer interrupt
flag in the TCON register is set to one and the content of the TH-register is reloaded in the
TL-register and the count process starts again from this initial value.
2. 18 MICROPROCESSORS AND MICROCONTROLLERS

Timer port mode-3:

In mode-3, the timer-0 is configured as two separate 8-bit timers and timer-1 is stopped.
In mode-3, the TL0 will function as an 8-bit timer controlled by standard timer-0 control
bits and the TH0 will function as an 8-bit timer controlled by timer-1 control bits. While
timer-0 is programmed in mode-3, timer-1 can be programmed in mode-0, 1 or 2 and can be
used for applications that do not require an interrupt.

The C/Tbit of the TMOD register is used to program the counter or timer operation of the
timer. When C/T bit is set to one, the timer will function as an event counter. The C/T bit
is programmed to zero for timer operation.

Normally the TR (Timer Run) bit in the TCON register is used to control the clock input to
the timer. In order to allow the clock input (Note : the timer will run only if the clock input is allowed),
the TR bit should be set to one. In addition, the GATE bit in the TMOD register will facilitate the
external signal applied to the INTpin to act as an additional control signal to allow or disallow the
clock input to the timer. When GATE = 1, the clock input to the timer is allowed only if the signal
at the INT pin is high (as well as TR should be set to one.) When GATE = 0, the signal at the INT
pin is ignored (but the TR should be set to one.)
Timer Control (TCON) Register
The TCON register consists of timer overflow flags, timer run control bits, external interrupt
flags and external interrupt type control bits. The format of a TCON register is shown in Fig. 2.9.
B7 B6 B5 B4 B3 B2 B1 B0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timer-1 Overflow Flag ¬ ® Interrupt-0 Type Control Bit

Timer-1 Run Control Bit ¬ ® Interrupt-0 Edge Flag
Timer-0 Overflow Flag ¬ ® Interrupt-1 Type Control Bit
Timer-0 Run Control Bit ¬ ® Interrupt-1 Edge Flag
Fig. 2.9 : Format of a TCON register of the 8051 family of microcontroller.

The timers in a 8031/8051 microcontroller are upcounters and keep on incrementing as long
as the clock is applied. Therefore, when the clock is applied after reaching the maximum value
(i.e., the content of the counter is all 1s), the content of the counter will become zero (i.e., all 0 s).
This condition is called timer overflow and it is also the end of timing which a program wants to
maintain by using the timer. The TCON register has a 1-bit flag, TF for each timer to indicate the
timer overflow or end of timing. Whenever the timer/counter overflows, the TF flag is set to one.
The TF flag is also used as an interrupt signal to initiate the execution of a subroutine. When the
controller vectors to subroutine, the TF flag is cleared.
The TR bit is used to start/stop the timer/counter. When the TR bit is set to one, the timer/
counter will start counting and continue the counting as long as the TR bit is one. The timer/
counter will stop counting when the TR bit is cleared to zero.
C HAPTER 2 I NTRODUCTION T O M ICROCONTROLLERS 2. 19

When a valid external interrupt signal is detected, the IE flag is set to one. When the controller
accepts the external interrupt and starts processing it, the IE flag is cleared to zero. The IT bit is
used to program the type of external interrupt signal to be recognized by the controller. The IT bit
is programmed as one to recognize the falling edge triggered external interrupt and it is programmed
as zero to recognize logic low level external interrupt.
Interrupt Enable (IE) Register
The IE-register is used to enable/disable the interrupts of an 8051. The interrupts are recognized
(or accepted) by the controller only if they are enabled. The IE-register can be programmed to
enable/disable all the five interrupts of an 8051 totally or individually. The format of an IE-register
is shown in Fig. 2.10. The EA bit of the IE-register can be programmed as zero, to disable all the
five interrupts of 8051. When EA bit is programmed as one, the interrupts are enabled provided
their individual enable bits are programmed as one. (The EA bit is also called global enable.)
B7 B6 B5 B4 B3 B2 B1 B0
EA X X ES ET1 EX1 ET0 EX0
QPI
Don’t Care
(Programmed
® Enable External Interrupt-0
as Zero) ® Enable Timer-0 Interrupt
® Enable External Interrupt-1
® Enable Timer-1 Interrupt
® Enable All ® Enable Serial Port Interrupt
Interrupts
Note : 1 -Enable ; 0 - Disable.

Fig. 2.10 : Format of the IE register of the 8051 family of microcontrollers.

Each interrupt has one-bit field to enable or disable it individually. When EA = 1, if the enable
bit of a particular interrupt is programmed as one, then it is enabled and if the enable bit is programmed
as zero, then it is disabled.
Interrupt Priority (IP) Register
The 8051 has five interrupts and the normal priority of these interrupts from highest to lowest are
external interrupt-0, Timer-0 interrupt, External interrupt-1, Timer-1 interrupt and serial port interrupt.
The IP-register can be programmed to make the priority of any of the interrupt as highest.
The format of an IP-register is shown in Fig. 2.11. The IP-register has one-bit field for the priority
of each interrupt. When the priority bit of a particular bit is programmed as one, then its priority
will be highest. In 8051, while servicing a lower priority interrupt a higher priority interrupt will be
recognized but another lower priority interrupt will not be recognized.
B7 B6 B5 B4 B3 B2 B1 B0
X X X PS PT1 PX1 PT0 PX0

1 = Highest Priority
® Priority of External Interrupt-0
0 = Normal Priority
® Priority of Timer-0 Interrupt
® Priority of External Interrupt-1
Note : 1 - Enable ; 0 - Disable.
® Priority of Timer-1 Interrupt
® Priority of Serial Port Interrupt
Fig. 2.11 : Format of the IP-register of an 8051 family of microcontrollers.