International University
School of Electrical Engineering
Digital Logic Design Lab
EE054IU
MSI COMBINATIONAL LOGIC
Submitted by
Nguyễn Nhất Duy – EEEEIU18025
Phạm Vĩnh Phú – EEEEIU18085
Date Performed: 19/04/2021
Date Submitted: 21/04/2021
Lab Section: Lab 2
Course Instructor: M. Eng Trang Kien
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GRADING GUIDELINE FOR LAB REPORT
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Contents
MSI COMBINATIONAL LOGIC 1
Theoretical Background 7
Experimental Procedure 8
1. 4-BIT MAGNITUDE COMPARATOR – IC 74LS85 8
2. DESIGN 8-BIT MAGNITUDE COMPARATOR USING IC 74LS85 9
3. DESIGN 4-BIT PARITY GENERATOR/CHECKER USING 74LS86 11
Discussion of Results 13
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List of Figures
Figure 1 ___________________________________________________________ 9
Figure 2 __________________________________________________________ 12
Figure 3 __________________________________________________________ 12
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List of Tables
Table 1 ................................................................................................................... 8
Table 2 ................................................................................................................. 10
Table 3 ................................................................................................................. 11
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Theoretical Background
We need to understand the operation of logic gates:
- NOT gate expression: X = 𝐴
o X = HIGH when 𝐴 = LOW.
o NOT gate can also be made from NAND and NOR gate:
NAND gate: 𝐴. 𝐴 = 𝐴
NOR gate: 𝐴 + 𝐴 = 𝐴
- NOR gate expression: X = 𝐴 + 𝐵
o X = HIGH only when both A and B are LOW and X = LOW, otherwise.
o NOR gate can also be made from NAND gate:
NAND gate:
- NAND gate expression: X = 𝐴. 𝐵
o X = HIGH only when both A and B are LOW and X = LOW, otherwise.
o NAND gate can also be made from NOR gate:
NOR gate:
- OR gate expression: X = A + B
o X = LOW only when both A and B are LOW, X = HIGH
otherwise.
o OR gate can also be made from NAND and NOR gate:
NAND gate:
NOR gate:
- AND gate expression: X = A.B
o X = HIGH only when both A and B are HIGH, X = LOW, otherwise.
o AND gate can also be made from NAND and NOR gate:
NAND gate:
NOR gate:
- XOR gate expression: X = A ⊕ B
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o X = HIGH only if A and B are in different levels, i.e. A: LOW B: HIGH,
which also yields that X = LOW when A and B are in the
same level.
Experimental Procedure
1. 4-BIT MAGNITUDE COMPARATOR – IC 74LS85
Comparing Input Cascading Input Output
A3,B3 A2,B2 A1,B1 A0,B0 A>B A<B A=B A>B A<B A=B
A3>B3 x x x x x x H L L
A3<B3 x x x x x x L H L
A3=B3 A2>B2 x x x x x H L L
A3=B3 A2<B2 x x x x x L H L
A3=B3 A2=B2 A1>B1 x x x x H L L
A3=B3 A2=B2 A1<B1 x x x x L H L
A3=B3 A2=B2 A1=B1 A0>B0 x x x H L L
A3=B3 A2=B2 A1=B1 A0<B0 x x x L H L
A3=B3 A2=B2 A1=B1 A0=B0 1 0 0 H L L
A3=B3 A2=B2 A1=B1 A0=B0 0 1 0 L H L
A3=B3 A2=B2 A1=B1 A0=B0 x x 1 L L H
A3=B3 A2=B2 A1=B1 A0=B0 0 0 0 H H L
A3=B3 A2=B2 A1=B1 A0=B0 1 1 0 L L L
Table 1
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Comment:
Cascading input: We set it to the first case A = B without considering the MSB
of A and B, it will give the result is A = B.
Compare the MSB of A3 and B3 first if A3 > B3 then it will ignore all the following
conditions and give the result A3 > B3, likewise for the case A3 < B3. If A3 = B3
then it will consider each corresponding case in turn.
2. DESIGN 8-BIT MAGNITUDE COMPARATOR USING IC 74LS85
Figure 1
The following steps can be used to build an 8-bit magnitude comparator.
Before we begin, we find that the number of switches required to create the
desired IC is insufficient, so we connect U1's A=B input to a 5V voltage
source, the remained cascading input will be left connecting to nothing. Let's
begin with U1 by connecting inputs A0, A1, A2, and A3 to SW1, SW2, SW3,
and SW4, respectively. Connect B0, B1, B2, and B3 to SW5, SW6, SW7,
and SW8, respectively. Connect U1's Cascading Input to U2's Cascading
Input. Connect inputs A0, A1, A2 and A3 to SW9, SW10, SW11, and SW12
in U2. Connect B0, B1, B2, and B3 to SW13, SW14, SW15, and SW16,
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respectively. Finally, connect QA<B to LED1, QA=B to LED2 and QA>B to
LED3.
X Y Result
LED1 LED2 LED3
0101 0101 0101 0111 1 0 0
1111 0101 0101 0111 0 0 1
1111 0101 1111 0100 0 0 1
1001 0110 0101 1000 0 0 1
Table 2
What is the purpose of cascading inputs of 74LS85(II)?
When you’re cascading multiple devices and the inputs are identical, the result
depends on the other devices processing the least significant bits. The output of
the comparator processing lower order bits have to be connected to the cascading
inputs. If the inputs are not equal, the LSB bits don’t care, the cascading inputs are
ignored.
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3. DESIGN 4-BIT PARITY GENERATOR/CHECKER USING 74LS86
A B C D Even Output Odd Output
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 1
Table 3
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Expression of even and odd when using XOR gate:
Even: C ⊕ D ⊕ B ⊕ A
Odd: ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
C ⊕ D ⊕ B ⊕ A
Circuit diagram:
Even:
Figure 2
Odd:
Figure 3
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Discussion of Results
- All the experiments work well based on the theoretical background
- Through all the experiments, we know how to build the real circuit diagram based
on theory.
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