EE331L

Experiment #4

Flip Flops

Written by: Shehab alaa ramadan Group: C

Instructor: Dr.Ahmed Adwaib

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 1-Objectives:
• To design a sequential logic circuit using JK-Flip-Flop and d flip flop.
• To implement the designed circuit.

2-Introduction:

In this lab we will explore some digital electronics focusing especially on flip-flop circuits. A
flipflop circuit is a binary memory element and forms the basic building block for many memory
systems, counters, and other sequential logic circuits, i.e. circuits that respond to a series of
inputs rather than merely the present input. A flip-flop has two output terminals and two stable
voltage states. When operating correctly, if one of the output terminals is in a high voltage
state the other output terminal is in a low voltage state. The output voltages of the two
terminals can be flipped (exchanged) very quickly by applying a single input pulse to an
appropriate input terminal. The new ”flipped” state of the output terminals is then stable, i.e. it
persists even after the input pulse has ended.

3-Equipments:
-ICs 7400,7404,7410,7474,7476
-a surface mount dip switch
-D C Power Supply.
-Red Green LEDs
-Connecting Wires
-BreadBoard

4-Experimental procedure:

D flip flop

State 1:

Clock – LOW; D – 0 ; PR – 0 ; CL – 1 ; Q – 0 ; Q’ – 1

For the State 1 inputs the RED led glows indicating the Q’ to be HIGH and GREEN led shows Q to
be LOW. As discussed above when CLEAR is set to HIGH, Q is reset to 0 and can be seen above.

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 State 2:

Clock – LOW ; D – 0 ; PR – 1 ; CL – 0 ; Q – 1 ; Q’ – 0

For the State 2 inputs the GREEN led glows indicating the Q to be HIGH and RED led shows Q’ to
be LOW. As discussed above when PRESET is set to HIGH, Q is set to 1 and can be seen above.

State 3: Clock – LOW ; D – 0 ; PR – 1 ; CL – 1 ; Q – 1 ; Q’ – 1

For the State 3 inputs the RED and GREEN led glows indicating the Q and Q’ to be HIGH initially.
When the PR and CL are pulled down on releasing the buttons, the state goes to clear.

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 State 4: Clock – HIGH ; D – 0 ; PR – 0 ; CL – 0 ; Q – 0 ; Q’ – 1

For the State 4 inputs the RED led glows indicating the Q’ to be HIGH and GREEN led shows Q to
be LOW. This state is stable and stays there until the next clock and input. Since the CLOCK is
LOW to HIGH edge triggered, D input button should be pressed before pressing the CLOCK
button.

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 State 5: Clock – HIGH ; D – 1 ; PR – 0 ; CL – 0 ; Q – 1 ; Q’ – 0

For the State 5 inputs the GREEN led glows indicating the Q to be HIGH and RED led shows Q’ to
be LOW. This state is also stable and stays there until the next clock and input. Since the
CLOCK is LOW to HIGH edge triggered, D input button should be pressed before pressing the
CLOCK button.

JK Flip Flop :

State 1:

Clock– HIGH ; J – 0 ; K – 1 ; R – 1 ; Q – 0 ; Q’ – 1

For the State 1 inputs the RED led glows indicating the Q’ to be HIGH and GREEN led shows Q to
be LOW. The working can be verified with the truth table.

Note: R is already Pulled up so no need to press the button to make it 1.

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 State 2: Clock– HIGH ; J – 1 ; K – 0 ; R – 1 ; Q – 1 ; Q’ – 0

For the State 2 inputs the GREEN led glows indicating the Q to be HIGH and RED led shows Q’ to
be LOW. The same can be verified with the truth table.

State 3: Clock– HIGH ; J – 1 ; K – 1 ; R – 1 ; Q/Q’ – Toggle between two states

For the State 3 inputs the RED and GREEN leds glows alternatively for each clock pulse (HIGH to
LOW edge) indicating the toggling action. The output toggle from the previous state to another
state and this process continues for each clock pulse.

For first clock pulse with J=K=1

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 For second clock pulse with J=K=1

State 4: Clock– LOW ; J – 0 ; K – 0 ; R – 0 ; Q – 0 ; Q’ – 1

Note: R is already Pulled up so we need to press the button to make it 0.

The State 4 output shows that the input changes does not affect under this state. The output
RED led glows indicating the Q’ to be HIGH and GREEN led shows Q to be LOW. This state is
stable and stays there until the next clock and input is applied with RESET as HIGH pulse.

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 State 5: The remaining states are No change states during which the output will similar to
previous output state. The changes do not affect the output states, you can verify with the
Truth Table above.

5-Results:
D Flip-flop:

D Flip-flops are used as a part of memory storage elements and data processors as well. D flip-
flop can be built using NAND gate or with NOR gate. Due to its versatility they are available as IC
packages. The major applications of D flip-flop are to introduce delay in timing circuit, as a
buffer, sampling data at specific intervals. D flip-flop is simpler in terms of wiring connection
compared to JK flip-flop. Here we are using NAND gates for demonstrating the D flip flop.

Whenever the clock signal is LOW, the input is never going to affect the output state. The
clock has to be high for the inputs to get active. Thus, D flip-flop is a controlled Bi-stable latch
where the clock signal is the control signal. Again, this gets divided into positive edge triggered
D flip flop and negative edge triggered D flip-flop. Thus, the output has two stable states based
on the inputs which have been discussed below.

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 Truth table of D Flip-Flop:

INPUT OUTPUT
Clock
D Q Q’

LOW x 0 1

HIGH 0 0 1

HIGH 1 1 0

The D(Data) is the input state for the D flip-flop. The Q and Q’ represents the output states of
the flip-flop. According to the table, based on the inputs the output changes its state. But, the
important thing to consider is all these can occur only in the presence of the clock signal. This,
works exactly like SR flip-flop for the complimentary inputs alone.

Representation of D Flip-Flop using Logic Gates:

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 Representation of D Flip-Flop using NAND Gates

INPUT OUTPUT

Input 1 Input 2 Output 3

0 0 1

0 1 1

1 0 1

1 1 0

Thus, comparing the NAND gate truth table and applying the inputs as given in D flip-flop truth
table the output can be analysed. Analysing the above assembly as a three stage structure
considering previous state(Q’) to be 0

when D = 1 and CLOCK = HIGH

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 Output : Q = 1, Q’ = 0. Working is correct.

PRESET and CLEAR:

D flip flop has another two inputs namely PRESET and CLEAR. A HIGH signal to CLEAR pin will
make the Q output to reset that is 0. Similarly a HIGH signal to PRESET pin will make the Q
output to set that is 1. Hence the name itself explain the description of the pins.

INPUT OUTPUT
Clock
PRESET CLEAR D Q Q’

X HIGH LOW X 1 0

X LOW HIGH X 0 1

X HIGH HIGH X 1 1

HIGH LOW LOW 0 0 1

HIGH LOW LOW 1 1 0

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 JK Flip-flop:

The name JK flip-flop is termed from the inventor Jack Kilby from texas instruments. Due to its
versatility they are available as IC packages. The major applications of JK flip-flop are Shift
registers, storage registers, counters and control circuits. Inspite of the simple wiring of D type
flip-flop, JK flip-flop has a toggling nature. This has been an added advantage. Hence they are
mostly used in counters and PWM generation, etc. Here we are using NAND gates for
demonstrating the JK flip flop

Whenever the clock signal is LOW, the input is never going to affect the output state. The
clock has to be high for the inputs to get active. Thus, JK flip-flop is a controlled Bi-stable
latch where the clock signal is the control signal. Thus, the output has two stable states based
on the inputs which have been discussed below.

Truth table of JK Flip Flop:

INPUT OUTPUT
Clock
RESET J K Q Q’

X LOW X X 0 1

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 HIGH HIGH 0 0 No Change

HIGH HIGH 0 1 0 1

HIGH HIGH 1 0 1 0

HIGH HIGH 1 1 Toggle

LOW HIGH X X No Change

HIGH HIGH X X No Change

HIGH HIGH X X No Change

The J (Jack) and K (Kilby) are the input states for the JK flip-flop. The Q and Q’ represents the
output states of the flip-flop. According to the table, based on the inputs, the output changes
its state. But, the important thing to consider is all these can occur only in the presence of the
clock signal. This, works like SR flip-flop for the complimentary inputs and the advantage is that
this has toggling function.

Representation of JK Flip-Flop using Logic Gates:

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 Representation of JK Flip-Flop using NAND Gates

Thus, comparing the three input and two input NAND gate truth table and applying the inputs
as given in JK flip-flop truth table the output can be analysed. Analysing the above assembly as
a two stage structure considering previous state (Q’) to be 0

When J = 1, K = 0 and CLOCK = HIGH

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 Output: Q = 1, Q’ = 0. Working is correct.

RESET:

The RESET pin has to be active HIGH. All the pins will become inactive upon LOW at RESET pin.
Hence, this pin always pulled up and can be pulled down only when needed.

6-Questions:
1-
the sound or motion of something flapping loosely

2a: a backward handspring

3: a usually electronic device or a circuit (as in a computer) capable of assuming either of

4: a rubber sandal loosely fastened to the foot by a thong

2-

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 3-

JK Flip Flop is a universal flip-flop that makes the circuit toggle between two states and is
widely used in shift registers, counters, PWM and computer applications
Typical applications of the D type flip flop are: Latches, Counters, Memory Devices, Shift
Registers.

4-

Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q) regardless of
clock input status. These inputs are called the preset (PRE) and clear (CLR). The preset input
drives the flip-flop to a set state while the clear input drives it to a reset state
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless
of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D)
input meeting the setup time requirements is transferred to the outputs on the positive-going
edge of the clock pulse.

5-

Conversion of J-K Flip-Flop into D Flip-Flop:

 Step-1:
We construct the characteristic table of D flip-flop and excitation table of JK flip-flop.

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  Step-2:
Using the K-map we find the boolean expression of J and K in terms of D.

J=D
K = D'

 Step-3:

We construct the circuit diagram of the conversion of JK flip-flop into D flip-flop.

6-

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  Synchronous circuits:

In synchronous circuits the input are pulses (or levels and pulses) with certain restrictions
on pulse width and circuit propagation delay. Therefore synchronous circuits can be divided
into clocked sequential circuits and uncklocked or pulsed sequential circuits.

In a clocked sequential circuit which has flip-flops or, in some instances, gated latches, for its
memory elements there is a (synchronizing) periodic clock connected to the clock inputs of all
the memory elements of the circuit, to synchronize all internal changes of state.

Hence the operation of the entire circuit is controlled and synchronized by the periodic pulses
of the clock.

On the other hand in an unclocked or pulsed sequential circuit, such a clock is not present.
Pulse mode circuits require two consecutive transitions between 0 and 1 - that is a 0-pulseor a
1 pulse to alter the circuit’s state. A pulse -mode circuit is designed to respond to pulses of
certain duration; the constant signals between the pulses are “null” or “spacer” signals, which
do not affect the circuit’s behavior

From the above block diagrams we can note the following:

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 1) Pulse outputs: For pulsed sequential circuits these occur only for the duration of the
respective input pulse and in some cases for duration considerably less. For clocked
sequential circuits these outputs occur for the duration of the clock pulse.

2) Level outputs: These change state at the start of the respective input or clock pulse and
remain in that state until the next state of output is required.

A requirement of synchronous sequential circuits is that the duration of the activating pulse or
clock pulse should be sufficiently low in value that the pulse (or clock) has disappeared by the
time the secondaries (the flip-flops outputs) have taken on their new value; otherwise the
circuit will change state again. This means that the storage elements (flip-flops) should be edge-
triggered devices (for example: D-type flip-flop, the JK flip-flop and their derivatives).

 Asynchronous circuits:

The circuit is considered to be asynchronous if it does not employ a periodic clock signal C
to synchronize its internal changes of state. Therefore the state changes occur in direct
response to signal changes on primary (data) input lines, and different memory elements can
change state at different times.

In asynchronous sequential circuits the inputs are levels and there are no clock pulses; the
inputs events drive the circuit.

In general, an asynchronous circuit does not need the precise timing control supported by flip-
flops. It may therefore contain latches rather than flip-flops. In many cases, an asynchronous
circuit simply relies on the propagation delays of its component gates and connections,
combined with the circuit’s feedback structure, to implement its memory functions.

7-Refrence:

[1] CD4051B datasheet, Texas Instruments Incorporated, 2000. (Available, for example, from
www. ee.washington.edu/stores/DataSheets/cd4000/cd4051.pdf.)

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