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Assignment #02: Name: - Ahmad Raza 20-ARID-1665 Section: - BSCS 2 (A) Course: - Digital Logic & Design

1. The document describes the design and implementation of an OR gate circuit using an IC. It provides the pin configurations and internal design of IC chips for OR gates, including the 7432 TTL chip and 4081 CMOS chip. 2. Components needed include the OR gate IC, wires, LED, power supply, resistors, and breadboard. An OR gate produces a high output if one or both inputs are high. Truth tables and symbol are also provided. 3. The procedure connects the inputs and outputs of the OR gates to the corresponding pins of the IC chip based on the pin configurations. The power supply is connected to activate the IC.

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0% found this document useful (0 votes)
82 views

Assignment #02: Name: - Ahmad Raza 20-ARID-1665 Section: - BSCS 2 (A) Course: - Digital Logic & Design

1. The document describes the design and implementation of an OR gate circuit using an IC. It provides the pin configurations and internal design of IC chips for OR gates, including the 7432 TTL chip and 4081 CMOS chip. 2. Components needed include the OR gate IC, wires, LED, power supply, resistors, and breadboard. An OR gate produces a high output if one or both inputs are high. Truth tables and symbol are also provided. 3. The procedure connects the inputs and outputs of the OR gates to the corresponding pins of the IC chip based on the pin configurations. The power supply is connected to activate the IC.

Uploaded by

Ahmad Raza
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Assignment #02

Name: - Ahmad Raza 20-ARID-1665


Section: - BSCS 2nd (A)
Course: - Digital Logic & Design.

Date: - June 26, 2021.

1. Practical Title

OR Gate
2. Required Components
IC Number of OR Gate:
7432.
Wires
LED
Power Supply
Resistors
Bread Board.
OR Gate:
An OR gate is a logic gate that performs logical OR operation. A logical OR operation has a high output (1) if
one or both the inputs to the gate are high (1). If neither input is high, a low output (0) result. Just like an AND
gate, an OR gate may have any number of input probes but only one output probe.

Symbol:

OR Gate Truth Table


2 Input OR Gate
Truth tables list the output of a particular digital logic circuit for all the possible combinations of its inputs. The
truth table of a 2 input OR gate can be represented as:

OR Gate Circuit Diagram:


OR Gate IC 4071
4071 is a 14 pin 1C as you can see where four or gates are fixed together having two inputs. Pin number 14 is
tvcc where maximum SV DC supply is given which activates the IC. Pin number 7 is grounded.

3. Procedure:
Pin 1 and 2 are the input for the first gate and 3 is the respective output for the first gate. Pin numbers 5 and 6
are inputs for the second gate whose output is pin number 4. For the third gate pin number 8 and 9 are the inputs
whose output is pin number 10 for the last gate pin number 12 and 13 are the inputs whose respective output is
at pin number 11. Thus how the IC looks internally for CMOS.
OR Gate IC 7432
In TTL logic the internal arrangement differs from that incase of CMOS logics. In TTL logic 2- input OR gate
IC number is 74LS32. popularly known as 7432. LS stands for a low power Schottky version.

Again one more type of IC number is also available in the market which is 74HC32 where HC stands for high-
speed CMOS version i.e. it has lower current consumption and wider voltage range. 74LVC32 is another low
voltage CMOS version of the same. Let us have a discussion on 74LS32 which is a TTL IC. In this IC there are
fourteen pins. The internal gate diagram of 7432 can make your idea clear.

In this IC, pin 1 and 2 are the inputs of the first gate where the output is from pin number 3. Again pin numbers
4 and 5 are the inputs of the second gate whose output is in pin 6. Pin 10 and 9 are the inputs of the fourth gate
whose output is at pin 8. The input of the last gate or fourth gate is pin 13 and 12 and pin 11 is its output.
Pin 7 is ground and pin 14 is +vcc supply where again +Vcc supply where again +SVdC is the normal and
maximum supply. One thing must be maintained at +SVDC. If the i/p voltage would be more than this it may
cause damage to the IC.

4. Application.
OR gates are used in automatic digital control circuits. There are many sensors are used to detect faults in an
industry. The sensor creates a signal if any fault occurs. Then OR gates give command signals to the main
processor for the shutdown. OR gates are used in Door Bell Switches.

1. Practical Title:

AND Gate:

2. Required Components:
 IC Number is 7408.
 Power supply (5v)
 1K (2 pieces), 220Ω resistors.
 4LS09 QUAD AND GATE IC.
 1 LED.
 Buttons (2 pieces)
 100nF capacitor (2 pieces)
 Breadboard and Connecting wires.
AND Gate:
An AND gate is a logic gate having two or more inputs and a single output. An AND gate operates on logical
multiplication rules. In this gate, if either of the inputs is low (0), then the output is also low. If all of the inputs
are high (1), then the output will also be high. An AND gate can have any number of inputs, although 2 input
and 3 input AND gates are the most common.

Symbol:

Truth Table
AND Gate Circuit Diagram:

AND Gate IC 7408:

For AND Gate IC number in TTL is 7408. 7408 is Quad 2- input IC where four gates are present together. Let
us have a look at the internal diagram of 7408.
3. Procedure:
Here pins 1, 2 are the inputs of the first gate whose respective output is 3. Again 4 and 5 are the inputs of the
second gate whose output is at pin 6. The inputs of the fourth are pin 12 and 13 and pin 11 is its output.

Pin 14 is the supply input which can be a maximum of 5.2 volt D.C. if input voltage be more than this it may
cause damage to the IC.

AND Gate IC 4081

In CMOS logic i.e. complimentary MOSFET logic I.C number of AND Gate is 4081. This IC also has two
inputs and one respective output. In this IC there are also 4 gates together. Now see the below internal diagram
of this circuit to make it clearer.
Pin 1 and 2 are the inputs of the first gate whose output is in number 3. Again Pin 5 and 6 are the inputs of the
second gate whose output is at Pin 4. pi number 7 is grounded. Pin 8 and 9 are the inputs of the third gate whose
output is at pin 10.

Again pin 13 and 12 are the inputs of the fourth AND gate whose output is at pin number 11. Pin 13 and 12 are
the inputs of fourth AND Gate whose output is at pin number 11. Pin number 14 is a power supply where a
maximum 5.2-volt direct current supply can be given to activate the IC.

Here too if more voltage is given if may damage the IC. Inter circuit of CMOS and TTL differs from each other
which must be noticed carefully.

4. Application.

The AND gate is used for data transmission control in digital electronics. AND gate allows or
disallows the transmission of data through a channel. AND Gates are used in digital measuring
instruments. AND gates are also used in alarm circuits.

1. Practical Title:

NAND Gate.

2. Required Components:
 Power supply (5v)
 1K and 220Ω resistors.
 74LS00 QUAD NAND GATE IC.
 1 LED.
 Buttons.
 100nF capacitor.
 Connecting wires.
 Breadboard.

NAND Gate:

In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output which is false only if
all its inputs are true; thus its output is complement to that of an AND gate. A LOW (0) output results only if all
the inputs to the gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results.

Symbol:

Truth Table:

NAND Gate Circuit Diagram:


NAND Gate IC 7400:

The first part number in the series, the 7400, is a 14-pin IC containing four two-input NAND gates. Each gate uses two
input pins and one output pin, with the remaining two pins being power (+5 V) and ground.

3. Procedure:

4. Application.

There are many applications of NAND gate available. NAND gates are used in Alarm circuit using LDR,
Freezer warning buzzer circuits, automatic temperature control circuits.

1. Practical Title:

Nor Gate.
2. Required Components:
 Operating voltage range: +4.75 to +5.25V
 Maximum supply voltage:7V
 Maximum current allowed to draw through each gate output: 8mA
 TTL outputs
 Low power consumption
 Maximum ESD: 3.5KV
 Typical Rise Time: 15ns
 Typical Fall Time: 15ns
 Operating temperature:0°C  to 70°C
 Storage Temperature: -65°C  to 150°C
NOR Gate:

The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the
right. A HIGH output (1) results if both the inputs.

Symbol:

Truth Table:

NOR Gate Circuit Diagram:


NOR Gate IC Number:

7402.

3. Procedure:
Pin configuration

74LS02 is a 14 PIN IC as shown in the pinout diagram. The chip is available in different packages and is chosen
depending on requirement. The description for each pin is given below.

Pin Number Description


NORGATE 1
2 1A-INPUT1 of GATE 1
3 1B-INPUT2 of GATE 1
1 1Y-OUTPUT of GATE1
NORGATE 2
5 2A-INPUT1 of GATE 2
6 2B-INPUT2 of GATE 2
4 2Y-OUTPUT of GATE2
NORGATE 3
8 3A-INPUT1 of GATE 3
9 3B-INPUT2 of GATE 3
10 3Y-OUTPUT of GATE3
NORGATE 4
11 4A-INPUT1 of GATE 4
12 4B-INPUT2 of GATE 4
13 4Y-OUTPUT of GATE4
SHARED TERMINALS
7 GND- Connected to ground
14 VCC-Connected to positive voltage to provide power to all four gates

There are many reasons for using 74LS02. Here are a few cases why it is used.

1. The chips basically used when (NOR) logic function is required. The chip has four (NOR) gates in it. We can
use one or all gates.

2. When you want logic inverter. NOR gates in this chip can be reconnected to make them NOT gates. Each
NOR gate can form a single NOT gate. So we can make 74LS02 chip a four NOT gate chip if necessary.

3. Where high speed NOR operation is necessary. As mentioned earlier the gates in the chip are designed by
SCHOTTKY TRANSISTORS. With them the switching delays of gates are minimized. Because of this the chip
can be used high speed applications.

4. 74LS02 is one of cheapest IC. It is really popular and is available everywhere.

5. The chip also provides TTL outputs which are a must in some systems.

4. Application.
 General purpose NOR logic operation
 Digital Electronics
 Servers
 ALUs
 Memory units
 Networking
 Digital systems

1. Practical Title

Half Adder:

2. Required Components:

IC 7486 
Bread Board
LED
Push Button
Wires
resistors

Half Adder:

A half adder is a combinational circuit with two binary inputs (augend and addend bits) and two binary outputs
(sum and carry bits). It adds two inputs (A and B) and produces the sum (S) and the carry (C) bits. It is an
arithmetic circuit used to perform the arithmetic operation of addition of two single bit words.

Symbol:

Truth Table:

Inputs Outputs

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

K-Map Simplification
According to rules of binary addition, the sum bit (S) and the carry bit (c) are as follows:
The sum bit (S) is the XOR of A and B. So we have S=AB'+A'B=A⊕B
Again the carry bit (C) is the AND of A and B. So C=AB.

Logic Diagram

Half Adder using NAND Gates

Five NAND gates are required in order to design a half adder. The circuit to realize half adder using NAND
gates is shown below.
Also get an idea about How to Build OR, AND, NOT Gates using NAND Gate

Half Adder using NOR Gates

Five NOR gates are required in order to design a half adder. The circuit to realize half adder using NOR gates is
shown below

Procedure:
We can make the circuit in real on breadboard to understand it clearly. For this we used two widely
used XOR and AND chip from 74 series 74LS86 and 74LS08.

Both are gate ICs. 74LS86 has four XOR gates inside the chip and 74LS08 has four AND gates inside it. These two
ICs are widely available and we will make Half-Adder circuit using this two.
Below is the Pin Diagram for both the ICs:

Circuit Diagram to use these two ICs as a half-adder circuit-


We constructed the circuit in breadboard and observed the output.

In the above circuit diagram one of the XOR gate from 74LS86 is used and also one of the AND gate from
74LS08 is used. Pin 1 and 2 of 74LS86 is the input of the gate and pin 3 is the output of the gate, on the other
side pin 1 and 2 of 74LS08 is the input of the AND gate and pin 3 is the output of the gate. Pin No 7 of both ICs
is connected to GND and 14th pin of the both ICs is connected to VCC. In our case the VCC is 5v. We added
two leds to identify the output.  When the output is 1, the LED will glow.

We added DIP switch in the circuit to provide input on the gates, for the bit 1 we are providing 5V as input and
for 0 we are providing GND through 4.7k resistor. 4.7k resistor is used to provide 0 inputs when the switch is in
off state.

4. Application.
Half adder on its own does not have any useful application. You can use two half adders and an OR gate to
build a full adder. N such full adders can be used to make a word adder. However the component count and
propagation delay will be quite large for a large value of N, say 16 or 32. For long word additions, ALU
designers today make use of carry look ahead adders.

1. Practical Title

Multiplexer

2. Required Components:

IC 74151

Bread Board

LED

Push Button

Wires

The Multiplexer component implements a 2 to 16 input mux providing a single output, based on hardware


control signals. The De-Multiplexer component implements a 2 to 16 output demux from a single input, based
on hardware control signals. Only one input or output connection may be made at a time.

Multiplexer:
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and single output
line. One of these data inputs will be connected to the output based on the values of selection lines.

Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination will select only one data input. Multiplexer is also called as Mux.

4x1 Multiplexer

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The block
diagram of 4x1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on the combination of inputs present at these two
selection lines. Truth table of 4x1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as

Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit diagram of 4x1
multiplexer is shown in the following figure.
We can easily understand the operation of the above circuit. Similarly, you can implement 8x1 Multiplexer and
16x1 multiplexer by following the same procedure.

Implementation of Higher-order Multiplexers.

Now, let us implement the following two higher-order Multiplexers using lower-order Multiplexers.

8x1 Multiplexer

16x1 Multiplexer

8x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We know that
4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1 Multiplexer has 8 data inputs,
3 selection lines and one output.

So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each 4x1 Multiplexer
produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as
inputs and to produce the final output.

Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and one output Y.
The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output


S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table.
The block diagram of 8x1 Multiplexer is shown in the following figure.
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of upper 4x1
Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I3 to I0. Therefore, each 4x1
Multiplexer produces an output based on the values of selection lines, s1 & s0.

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second
stage. The other selection line, s2 is applied to 2x1 Multiplexer.

If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to I0 based on the values of
selection lines s1 & s0.

If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to I4 based on the values of
selection lines s1 & s0.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs as one 8x1
Multiplexer.

16x1 Multiplexer

In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer. We know that
8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. Whereas, 16x1 Multiplexer has 16 data
inputs, 4 selection lines and one output.
So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each 8x1 Multiplexer
produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as
inputs and to produce the final output.

Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s3 to s0 and one output Y.
The Truth table of 16x1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14
1 1 1 1 I15

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the above Truth
table. The block diagram of 16x1 Multiplexer is shown in the following figure.

The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data inputs of upper 8x1
Multiplexer are I15 to I8 and the data inputs of lower 8x1 Multiplexer are I7 to I0. Therefore, each 8x1
Multiplexer produces an output based on the values of selection lines, s2, s1 & s0.
The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second
stage. The other selection line, s3 is applied to 2x1 Multiplexer.

If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is7 to I0 based on the values of
selection lines s2, s1 & s0.

If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I15 to I8 based on the values of
selection lines s2, s1 & s0.

Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs as one 16x1
Multiplexer.

Simplify the logic diagram below.

Solution:

Write the Boolean expression for the original logic diagram shown above

Transfer the product terms to the Karnaugh map.

It is not possible to form groups.

No simplification is possible; leave it as it is.

No logic simplification is possible for the above diagram. This sometimes happens. Neither the methods of
Karnaugh maps nor Boolean algebra can simplify this logic further.

We show an Exclusive-OR schematic symbol above; however, this is not a logical simplification. It just makes
a schematic diagram look nicer.

Since it is not possible to simplify the Exclusive-OR logic and it is widely used, it is provided by manufacturers
as a basic integrated circuit (7486).

Bread Board:
3. Procedure:

Use K-Map to find expression for Sum & Carry and implement using Multiplexer.

Connections are made as per the circuit diagram, for Full Adder.

Give the input digital values as per the truth table and verify the output on the LEDs of the
trainer kit.
Similarly use K-Map to find expression for Difference and Borrow & repeat the steps 2 & 3
for Full Subtraction.

4. Application.
In all types of digital system applications, multiplexers find its immense usage. Since these allows multiple
inputs to be connected independently to a single output, multiplexers are found in variety of applications
including data routing, logic function generators, control sequencers, parallel-to-serial converters, etc. 

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