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2 Exp Nand Gate Implementation 20bce1082

1. The document describes an experiment to verify that all logic gates can be implemented using only NAND gates. 2. It explains how to construct NAND gate implementations of the basic logic gates: NOT using one NAND gate, AND using two NAND gates, OR using three NAND gates, XOR using four NAND gates, and NOR using five NAND gates. 3. The results showed that the behavior of AND, OR, NOT, XOR, and NOR gates can all be replicated using only NAND gates, demonstrating that the NAND gate is a "universal gate" that can be used to construct any other basic logic gate.

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Parimala Ashok
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58 views5 pages

2 Exp Nand Gate Implementation 20bce1082

1. The document describes an experiment to verify that all logic gates can be implemented using only NAND gates. 2. It explains how to construct NAND gate implementations of the basic logic gates: NOT using one NAND gate, AND using two NAND gates, OR using three NAND gates, XOR using four NAND gates, and NOR using five NAND gates. 3. The results showed that the behavior of AND, OR, NOT, XOR, and NOR gates can all be replicated using only NAND gates, demonstrating that the NAND gate is a "universal gate" that can be used to construct any other basic logic gate.

Uploaded by

Parimala Ashok
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Register Number: 20BCE1082 Name: SHRIKUMARAN.

P A

VERIFICATION OF ALL LOGIC GATES USING NAND GATE

Experiment no. 2 Date:1-03-2021

Aim of the Experiment:

To study and verify the all logic gates using UNIVERSAL Gate NAND.

APPARATUS REQUIRED:

EMONA – net Circuit labs:

1. Circuit Implementation of NAND gate as NOT gate – EMONA net CIRCUIT labs:
2. Circuit implementation of NAND gate as AND gate using EMONA net circuit labs:

3. Circuit Implementation of NAND Gate as OR Gate in EMONA – net CIRCUIT labs:


4. Circuit implementation of NAND gate as XOR gate using EMONA net circuit labs:

5. Circuit implementation of NAND Gate as NOR gate using EMONA net circuit labs:
Inference & Result :

1. NAND Gate as NOT Gate:

A NAND Gate will work as a not gate if same input is given to both the terminals of the NAND Gate.

• 𝑌 = ̅̅̅̅̅̅
𝐴. 𝐴 = 𝐴̅ + 𝐴̅ = 𝐴̅ (the input A is given to both the terminals of the NAND gate)

2. NAND Gate as AND gate:

A NAND gate will work as a AND Gate if the output of the NAND Gate is connected to both the input
terminals of another NAND Gate

• Y= ̅̅̅̅̅
𝐴. 𝐵 = A.B

3. NAND Gate as OR Gate:

A NAND Gate will work as a OR Gate if the same input is given to 2 NAND Gates and the output of the
2 NAND Gates is connected to another NAND Gate

• 𝑌 = ̅̅̅̅̅
𝐴̅. 𝐵̅ = ̅̅̅
𝐴 ̅ + 𝐵̅ ̅ = A+B

4. NAND Gate as XOR Gate:

A NAND Gate will work as a XOR Gate if the input A and the output of the first NAND Gate is
Connected to second NAND Gate and the input B and output of first NAND Gate is connected to
Third NAND Gate and the outputs of 2nd and 3rd NAND Gates are connected to another NAND Gate.

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅
• Y= (((𝐴. ( ̅̅̅̅̅
𝐴. 𝐵 )). (𝐵. ̅̅̅̅̅
(𝐴. 𝐵 ))) = ((𝐴. ( ̅̅̅̅̅
𝐴. 𝐵 )) + (𝐵. ̅̅̅̅̅
(𝐴. 𝐵 )) = 𝐴. ( ̅̅̅̅̅
𝐴. 𝐵 ) + 𝐵. ( ̅̅̅̅̅
𝐴. 𝐵 )
= (𝐴. ( 𝐴̅ + 𝐵̅ ) + 𝐵. ( 𝐴̅ + 𝐵̅ )) = (𝐴. 𝐴̅ + 𝐴. 𝐵̅ ) + (𝐵. 𝐴̅ + 𝐵. 𝐵̅ ) = (0 + 𝐴. 𝐵̅ ) + (𝐵. 𝐴̅ + 0)
= 𝐴. 𝐵̅ + 𝐵. 𝐴̅

5. NAND Gate as NOR Gate:

A NAND Gate will work as a NOR Gate if the input A is connected to both the terminals of the 1st
NAND Gate and input B is Connected to both the terminals of the second NAND Gate and the outputs of
1st and 2nd NAND Gate is connected to 3rd NAND Gate and the output of the 3rd NAND Gate is connected
to the first and Second terminals of the 4th NAND Gate.

• ̿̿̿̿̿
Y=𝐴 ̅. 𝐵̅ = 𝐴̅. 𝐵̅ = ̅̅̅̅̅̅̅̅
𝐴+𝐵
RESULT:

From the above experiment it is proven that the working of AND, OR , NOT , XOR and NOR
Gates can be performed using a NAND Gate.
Similarly, any Gate can be replaced by a equivalent network of NAND Gates so it is called as a
UNIVERSAL GATE.

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