Si5429DU

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Vishay Siliconix
P-Channel 30 V (D-S) MOSFET
PowerPAK® ChipFET® Single
FEATURES
D
D • TrenchFET® power MOSFET
D 7 8
S 6 • Thermally enhanced PowerPAK®
5 ChipFET® package
- Small footprint area, thin 0.8 mm profile
1
S 2
3 D D
- Low on-resistance
1.

m 9 4 D
0m
9

1 3. • 100 % Rg tested
m

G
m

Top View Bottom View • Material categorization: for definitions of compliance

Marking code: BH please see www.vishay.com/doc?99912

PRODUCT SUMMARY APPLICATIONS S

VDS (V) -30 • Power management for
RDS(on) max. () at VGS = -10 V 0.015 mobile computing G
RDS(on) max. () at VGS = -4.5 V 0.022 - Adaptor switch
Qg typ. (nC) 20 - Load switch
ID (A) a -12
- DC/DC converter P-Channel
MOSFET
Configuration Single D

ORDERING INFORMATION
Package PowerPak® ChipFet®
Lead (Pb)-free and halogen-free Si5429DU-T1-GE3

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS -30
V
Gate-source voltage VGS ± 20
TC = 25 °C -12 a

TC = 70 °C -12 a
Continuous drain current (TJ = 150 °C) ID
TA = 25 °C -11.8 b, c
TA = 70 °C -9.4 b, c A
Pulsed drain current (t = 300 μs) IDM -50
TC = 25 °C -12 a
Continuous source-drain diode current IS
TA = 25 °C -11.86 b, c
TC = 25 °C 31
TC = 70 °C 20
Maximum power dissipation PD W
TA = 25 °C 3.1 b, c
TA = 70 °C 2 b, c
Operating junction and storage temperature range TJ, Tstg -55 to +150
°C
Soldering recommendations (peak temperature) d, e 260

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum junction-to-ambient b, f t5s RthJA 34 40
°C/W
Maximum junction-to-case (drain) Steady state RthJC 3 4
Notes
a. Package limited
b. Surface mounted on 1" x 1" FR4 board
c. t = 5 s
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum under steady state conditions is 90 °C/W

S12-0804-Rev. A, 16-Apr-12 1 Document Number: 63933

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Si5429DU
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Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = -250 μA -30 - - V
VDS temperature coefficient VDS/TJ - -20 -
ID = -250 μA mV/°C
VGS(th) temperature coefficient VGS(th)/TJ - 4.4 -
Gate-source threshold voltage VGS(th) VDS = VGS , ID = -250 μA -1 - -2.2 V
Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
VDS = -30 V, VGS = 0 V - - -1
VDS = -30 V, VGS = 0 V, TJ = 55 °C - - -5
Zero gate voltage drain current IDSS VDS = -3 V, VGS = 0 V - -0.0001 - μA
VDS = -3 V, VGS = 0 V, TJ = 0 °C - -0.0001 -
VDS = -3 V, VGS = 0 V, TJ = 55 °C - -0.0001 -
On-state drain current a ID(on) VDS  -5 V, VGS = -4.5 V --20 - - A
VGS = -10 V, ID = -7 A - 0.0122 0.0150
Drain-source on-state resistance a RDS(on) 
VGS = -4.5V, ID = -5 A - 0.0178 0.0220
Forward transconductance a gfs VDS = -10V, ID = -7 A - 25 - S
Dynamic b
Input capacitance Ciss - 2320 -
Output capacitance Coss VDS = -15 V, VGS = 0 V, f = 1 MHz - 275 - pF
Reverse transfer capacitance Crss - 235 -
VDS = -15 V, VGS = -10 V, ID = -12 A - 42 63
Total gate charge Qg
- 20 30
nC
Gate-source charge Qgs VDS = -15 V, VGS = -4.5 V, ID = -12 A - 6.3 -
Gate-drain charge Qgd - 6.3 -
Gate resistance Rg f = 1 MHz 0.8 4.2 8.4 
Turn-on delay time td(on) - 35 70
Rise time tr VDD = -15 V, RL = 1.5  - 25 50
Turn-off delay time td(off) ID  -10 A, VGEN = -4.5 V, Rg = 1  - 31 60
Fall time tf - 10 20
ns
Turn-on delay time td(on) - 10 20
Rise time tr VDD = -15 V, RL = 1.5  - 10 20
Turn-off delay time td(off) ID  -10 A, VGEN = -10 V, Rg = 1  - 40 80
Fall time tf - 10 20
Drain-Source Body Diode Characteristics
Continuous source-drain diode current IS TC = 25 °C - - -2
A
Pulse diode forward current ISM - - 50
Body diode voltage VSD IS = -10 A, VGS = 0 V - -0.83 -1.2 V
Body diode reverse recovery rime trr - 10 20 ns
Body diode reverse recovery charge Qrr IF = -10 A, di/dt = 100 A/μs, - 3 10 nC
Reverse recovery fall time ta TJ = 25 °C - 6 -
ns
Reverse recovery rise time tb - 4 -
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %
b. Guaranteed by design, not subject to production testing


Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

S12-0804-Rev. A, 16-Apr-12 2 Document Number: 63933

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Si5429DU
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

50 10
VGS = 10 V thru 5 V
VGS = 4 V

40 8
ID - Drain Current (A)

ID - Drain Current (A)

30 6

20 4 TC = 25 °C

10 VGS = 3 V 2 TC = 125 °C

TC = - 55 °C
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

0.030 3000

Ciss
0.025 2400
RDS(on) - On-Resistance (Ω)

VGS = 4.5 V
C - Capacitance (pF)

0.020
1800

0.015
1200
VGS = 10 V
0.010
Coss
600
0.005
Crss

0.000 0
0 10 20 30 40 50 0 3 6 9 12
ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current Capacitance

10 1.6

VGS = 10 V
RDS(on) - On-Resistance (Normalized)

8 ID = 12 A 1.4
VGS - Gate-to-Source Voltage (V)

VDS = 15 V
VGS = 4.5 V
6 1.2
VDS = 7.5 V VDS = 24 V

4 1.0

2 0.8

0 0.6
0 9 18 27 36 45 - 50 - 25 0 25 50 75 100 125 150
Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

S12-0804-Rev. A, 16-Apr-12 3 Document Number: 63933

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Si5429DU
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

100 0.060

0.050 ID = 7 A

RDS(on) - On-Resistance (Ω)

IS - Source Current (A)

10 TJ = 150 °C 0.040

0.030
TJ = 25 °C

1 0.020 TJ = 125 °C

0.010 TJ = 25 °C

0.1 0.000
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10
VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)

Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

2.0 50

1.8 40

30
Power (W)

1.6
VGS(th) (V)

1.4 20
ID = 250 μA

1.2 10

1.0 0
- 50 - 25 0 25 50 75 100 125 150
0.001 0.01 0.1 1 10 100 1000
TJ - Temperature (°C)
Time (s)

Threshold Voltage Single Pulse Power

100
Limited by RDS(on)*

100 μs
10
ID - Drain Current (A)

1 ms

1 10 ms

100 ms

1s
0.1 10 s
TA = 25 °C DC

BVDSS Limited
0.01
0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified

Safe Operating Area

S12-0804-Rev. A, 16-Apr-12 4 Document Number: 63933

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Si5429DU
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

40 35

30
32

Power Dissipation (W)

25
ID - Drain Current (A)

24 20

15
16
Package Limited
10
8
5

0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TC - Case Temperature (°C) TC - Case Temperature (°C)

Current Derating a Power Derating

Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit

S12-0804-Rev. A, 16-Apr-12 5 Document Number: 63933

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Si5429DU
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance

0.2

0.1 Notes:
0.1
PDM
0.05
t1
t2
t1
0.02 1. Duty Cycle, D =
t2
2. Per Unit Base = RthJA = 90 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse 4. Surface Mounted
0.01
10-4 10-3 10-2 10-1 1 10 100 1000
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Duty Cycle = 0.5

Normalized Effective Transient
Thermal Impedance

0.2

0.1

0.05
0.02
Single Pulse
0.1
10-4 10-3 10-2 10-1 1
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Case

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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63933.

S12-0804-Rev. A, 16-Apr-12 6 Document Number: 63933

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® ChipFET® Case Outline
D
(8) (7) (6) (5)

E
Pin #1
indicator

(1) (2) (3) (4)

Side view of single Side view of dual

Z
A
C

A1
e
b

D2 D2
H D1 K L Detail Z
D(1) D(2) D(3) G(4) SI(1) GI(2) S2(3) G2(4)
K1
L

K2
E1 E3
E2

D3
H

D(8) D(7) D(6) S(5) D1(8) D1(7) D2(6) D2(5)

K3
Backside view of single pad Backside view of dual pad

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.70 0.75 0.85 0.028 0.030 0.033
A1 0 - 0.05 0 - 0.002
b 0.25 0.30 0.35 0.010 0.012 0.014
C 0.15 0.20 0.25 0.006 0.008 0.010
D 2.92 3.00 3.08 0.115 0.118 0.121
D1 1.75 1.87 2.00 0.069 0.074 0.079
D2 1.07 1.20 1.32 0.042 0.047 0.052
D3 0.20 0.25 0.30 0.008 0.010 0.012
E 1.82 1.90 1.98 0.072 0.075 0.078
E1 1.38 1.50 1.63 0.054 0.059 0.064
E2 0.92 1.05 1.17 0.036 0.041 0.046
E3 0.45 0.50 0.55 0.018 0.020 0.022
e 0.65 BSC 0.026 BSC
H 0.15 0.20 0.25 0.006 0.008 0.010
K 0.25 - - 0.010 - -
K1 0.30 - - 0.012 - -
K2 0.20 - - 0.008 - -
K3 0.20 - - 0.008 - -
L 0.30 0.35 0.40 0.012 0.014 0.016
C14-0630-Rev. E, 21-Jul-14
DWG: 5940
Note
• Millimeters will govern

Revision: 21-Jul-14 1 Document Number: 73203

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Single

0.225 0.350
(0.009) (0.014)
0.200 0.650 0.300 0.300
(0.008) (0.026) (0.012) (0.012)

0.100
(0.004)

0.250
(0.010)
(0.075)

(0.059)
1.900

1.500

0.500
(0.020)

0.350
(0.014)

0.350
(0.014)

1.870 0.305
(0.074) (0.012)

2.575
(0.101)

Recommended Minimum Pads

Dimensions in mm/(Inches)

Return to Index
APPLICATION NOTE

Document Number: 69948 www.vishay.com

Revision: 21-Jan-08 9
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Revision: 01-Jan-2021 1 Document Number: 91000