Different Silicon Growth Techniques
Different Silicon Growth Techniques
Different Silicon Growth Techniques
Faculty of Engineering
Submitted By
Pre-Comm.3
Submitted to
Cairo, 2014
ABSTRACT
Single crystal silicon has played the fundamental role in electronic industry since
the second half of the 20th century and still remains the most widely used
material. Electronic devices and integrated circuits are fabricated on single-crystal
silicon wafers which are produced from silicon crystals grown primarily by the
Czochralski (CZ) technique.
Various defects are formed in the growing crystal as well as in the wafers during
their processing. As engineers we deal with crystal defects in the technology of
manufacturing silicon single crystals and silicon wafers for the electronic industry.
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TABLE OF COTENTS
Contents
ABSTRACT...................................................................................................................................................... II
TABLE OF COTENTS ...................................................................................................................................... III
TABLE OF FIGURES ....................................................................................................................................... III
1. INTRODUCTION ..................................................................................................................................... 1
2. Czochralski (CZ) growth of silicon crystals ............................................................................................ 2
2.1 Defects during Czochralski Crystal Growth and Silicon Wafer Manufacturing............................. 3
3. Float zone (FZ) growth of silicon crystals .............................................................................................. 4
4. Manufacturing of silicon wafers ........................................................................................................... 6
TABLE OF FIGURES
III
1. INTRODUCTION
Single crystals of silicon for today´s electronic industry are produced primarily by
the Czochralski (CZ) method (Czochralski, 1918; Teal & Little, 1950). Only
applications with extreme demands on pure bulk material utilize the Float Zone
(FZ) method (Keck & Golay, 1953).
The CZ method is based on crystal pulling from the melt, while the FZ method
utilizes re-crystallization of poly-silicon rod which is locally molten by passage of
the RF coil.
The processes differ mainly in production cost and speed (which favor the CZ
method) and in the purity of produced material (which is higher in case of the FZ
method). The lower purity, which was seemingly unfavorable, helped CZ silicon
become the dominant material as it makes silicon wafers more resistant against
thermal stress and metallic contamination.
Furthermore the FZ process could not follow the continual increase in crystal
diameter. The diameter of 200 mm is the current size limit for FZ crystals while
450 mm capability was demonstrated for CZ process. So we’re going to discuss
the CZ & FZ crystal growth.
2. Czochralski (CZ) growth of silicon crystals
Both chambers are piped to a vacuum system. The puller is typically purged with
inert gas (most commonly argon). In the beginning of the process the quartz
crucible is loaded with a charge of poly-silicon chunks and the single crystalline
seed is fitted into the seed holder. After closing the puller the chambers are
evacuated and re-filled by inert gas to the desired process pressure.
Once the seed touches the melt surface, it is subjected to a huge thermal shock
leading to generation of numerous dislocations. In order to achieve dislocation-
free growth, “necking” is performed. To achieve this condition, the crystal pulling
rate is increased to about 3 to 6 mm per minute, and the crystal diameter is
reduced to about 5 to 2 mm, which allows dislocations to partially freeze in the
neck and partially move to the crystal surface.
As the diameter increases to the desired crystal diameter the pull rate is gradually
increased (which is called “shouldering stage”) until the crystal grows with the
desired diameter and the proper growth rate. Then, the cylindrical portion of the
crystal, the “crystal body”, is grown.
The melt and the crystal are in intimate contact at the solid-liquid interface. The
melt surface forms a meniscus to the crystal which reflects the light from the hot
crucible to the chamber windows. This results in the appearance of a shiny ring on
the melt surface around the crystal. As the meniscus height increases with crystal
radius, changes in the meniscus height can be sensed and used for crystal
diameter control during the growth of the crystal body.
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Solidification heat is conducted to the crystal surface and radiated to the
chamber. For longer ingots the heat conduction is reduced and therefore the
pulling rate has to be reduced. The crystal is rotated to homogenize the
distribution of impurities and to suppress inhomogeneities in the temperature
field. The crucible is rotated in the opposite sense to the crystal to stabilize the
melt flow and control the oxygen concentration in the crystal.
The final stage of the crystal growth is the tail growth where the diameter is
slowly decreased and a conical shape is achieved. The diameter of the
solidification interface is reduced and dislocation formation is suppressed due to
minimization of the thermal shock. Once the crystal has detached from the melt
the power to the puller is decreased and the crystal is cooled down while being
lifted into the upper chamber. At the end of the process, the crystal is removed
from the puller for further processing.
A typical oxygen and carbon concentrations in FZ silicon are below 5*1015 cm-3.
FZ crystals are doped by adding the doping gas phosphine (PH3) or diboron (B2H6)
to the inert gas for n-type and p-type, respectively. Unlike CZ growth, the silicon
molten Zone is not in contact with any substances except ambient gas, which may
only contain doping gas. Therefore FZ silicon can easily achieve much higher
purity and higher resistivity.
Dopants with a small k0 like Sn can be introduced by pill doping - holes are drilled
into the ingot into which the dopant is incorporated - or by evaporating a dopant
layer on the whole ingot before the float zoning process.
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4. Manufacturing of silicon wafers
First, the crystal crown and tail are cut off and the crystal body is divided into
several pieces. Then the crystal quality (resistivity, oxygen and carbon content,
dislocation-free state) is assessed on test wafers. Each section of the crystal is
then surface-ground to the desired diameter, the crystal is oriented, and the flat
is ground onto the cylindrical ingot.
The flat identifies the orientation of the silicon wafers with respect to specific
crystallographic directions; usually it corresponds to the (1 1 0) plane. Silicon
wafers are sliced from the crystal sections using wire-saws or the inner-diameter
(ID) saws.
After edge grinding the wafer is lapped, etched and polished. Finally, the polished
silicon wafer may have an epitaxial layer deposited on the prime surface by silicon
epitaxial methods. Optionally the wafer backside can be coated with a poly silicon
layer or a protective layer of silicon oxide. After final cleaning and inspection the
silicon wafers are suitable for device or integrated circuit (IC) manufacturing.
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CONCLUSION
Crystal defects are formed in silicon during the growth of the single crystals and
processing of the wafers. Depending on their nature, density, and size; these
defects may substantially influence silicon material properties and consequently
strongly impact process of device manufacturing. Crystal defects can be
controlled from the early beginning by influencing their formation during the
crystal growth. We discussed several aspects of controlling oxygen concentration
in CZ silicon crystals, which is the basic method for control of oxygen precipitation
in silicon wafers.
Another reason for treatment of the wafer can be an effort to modify properties
of wafer surface. For example oxygen precipitation and also appearance of the
vacancy-type defects, the COPs, can be controlled by high temperature annealing
of polished silicon wafers in optimized ambient. In this manner a wafer which
contains a defect-free near-surface denuded zone and an optimized defect
density in the bulk of the wafer providing effective no. of metal impurities can be
obtained.
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REFERENCES
[1] http://en.wikipedia.org/wiki/Float-zone_silicon
[2] Michael Riordan & Lillian Hoddeson (1997) Crystal Fire: the birth of the
information age, page 230, W. W. Norton & Company ISBN 0-393-04124-7.
[3] http://www.siliconsultant.com/sicrysgr.htm
[4] https://www.mersen.com/en/products/advanced-materials-and-solutions-
for-high-temperature/high-temperature-thermal-insulation/silicon-wafer-
manufacturing-processes.html
[5] http://www.graphite-eng.com/industries/photovoltaic